Display device

Abstract

A display device is disclosed. The display device includes a first power line, a second power line, a data line, a first scan line, a second scan line, a light emitting element connected between the first power line and a first node, a first transistor connected between the first node and the second power line and including a gate electrode connected to a second node, a second transistor connected between the data line and the second node and including a gate electrode connected to the first scan line, and a fourth transistor connected between the first power line and the first node and including a gate electrode connected to the second scan line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0048141 filed on April 21, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a display device. Background Art

[0004] Display devices can display images by using light-emitting elements such as light-emitting diodes (LEDs) as light sources for pixels. LEDs have relatively good durability even under harsh environmental conditions and offer excellent performance in terms of lifespan and brightness. Research has been conducted on using materials with highly reliable inorganic crystal structures to manufacture LEDs, incorporate them into display device panels, and use them as pixel light sources.

[0005] The display device includes a pixel, and the pixel may include a light-emitting diode, a driving transistor that supplies a driving current to the light-emitting diode, and a storage capacitor that maintains the gate-source voltage of the driving transistor (i.e., the voltage between the gate electrode and the source electrode of the driving transistor) at a specific voltage level. In addition, the pixel may further include a sensing transistor that is connected to a node between the driving transistor and the light-emitting diode to transmit a signal related to the characteristics of the driving transistor (e.g., threshold voltage and mobility) and / or the light-emitting characteristics of the light-emitting diode (e.g., current-voltage characteristics) to the outside.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art. Summary of the Invention

[0007] The light-emitting characteristics (e.g., current-voltage characteristics) of a light-emitting diode may vary depending on the light-emitting conditions. As a result, the gate-source voltage of a driving transistor (i.e., the voltage applied between the gate electrode and the source electrode of the driving transistor) may vary, and the pixel may not emit light at the desired brightness. As a result, brightness deviation (or brightness variation) may occur in the display device.

[0008] Exemplary embodiments of the present disclosure have been made in an effort to provide a display device that can display an image with uniform brightness.

[0009] One or more example embodiments of the present disclosure provide a display device including: a first power line; a second power line; a data line; a first scan line; a second scan line; a light emitting element connected between the first power line and a first node; a first transistor connected between the first node and the second power line, and including a gate electrode connected to a second node; a second transistor connected between the data line and the second node, and including a gate electrode connected to the first scan line; and a fourth transistor connected between the first power line and the first node, and including a gate electrode connected to the second scan line.

[0010] A first power voltage applied to the first power line can be greater than a second power voltage applied to the second power line, and an anode electrode of the light emitting element can be connected to the first power line.

[0011] The display device can further include a third transistor connected to a second electrode of the first transistor and a sensing line, and including a gate electrode connected to the second scan line, wherein a first electrode of the first transistor can be connected to the first node.

[0012] The display device can further include: an emission control line; and a fifth transistor connected between the second electrode of the first transistor and the second power line, and including a gate electrode connected to the emission control line.

[0013] At least one of the first to fifth transistors can include an oxide semiconductor.

[0014] The display device can further include a storage capacitor between the first power line and the second node.

[0015] The display device can further include: a scan driver configured to supply a first scan signal to the first scan line and a second scan signal to the second scan line; an emission driver configured to supply an emission control signal to the emission control line; a data driver configured to supply a data signal to the data line; and a sensing driver configured to receive a sensing signal corresponding to a threshold voltage of the first transistor through the sensing line.

[0016] The emission driver is to supply an emission control signal having a gate cut-off voltage level to the emission control line in a first period in which: the scan driver is to supply a first scan signal having a first gate-on voltage level to the first scan line, and is to supply a second scan signal having a second gate-on voltage level to the second scan line; and the data driver is to supply a data signal to the data line.

[0017] The emission driver provides an emission control signal having a first gate-off voltage level to the emission control line in the first cycle. In the first cycle: the scan driver may provide a first scan signal having a gate-on voltage level to the first scan line, and may provide a second scan signal having a second gate-off voltage level to the second scan line; and the data driver may provide a data signal to the data line.

[0018] The emission driver will provide an emission control signal with a gate-off voltage level to the emission control line in the second cycle, and the scan driver may provide a first scan signal with a first gate-on voltage level to the first scan line and a second scan signal with a second gate-on voltage level to the second scan line in the second cycle; the data driver may provide a reference voltage to the data line in the second cycle; and the sensing driver may apply an initialization voltage to the sensing line in the first sub-cycle of the second cycle and may receive a sensing signal in the second sub-cycle of the second cycle.

[0019] The display device may further include a storage capacitor between the second electrode of the first transistor and the second node.

[0020] The light emitting element may include a plurality of light emitting elements connected in parallel to each other.

[0021] Each of the light emitting elements may include an anode electrode and a cathode electrode, and the anode electrode of at least one of the light emitting elements may be connected to the cathode electrodes of the other light emitting elements.

[0022] Another exemplary embodiment of the present disclosure provides a display device, comprising: a first power line; a second power line; a data line; a sensing line; a first scan line; a second scan line; a light-emitting element connected between the first power line and a first node; a first transistor connected between the first node and the second power line and including a gate electrode connected to the second node; a second transistor connected between the data line and the second node and including a gate electrode connected to the first scan line; and a third transistor connected between the first node and the sensing line and including a gate electrode connected to the second scan line.

[0023] A first power voltage applied to the first power line may be greater than a second power voltage applied to the second power line, and an anode electrode of the light emitting element may be connected to the first power line.

[0024] The display device may further include a storage capacitor between the first power line and the second node.

[0025] The display device may further include a storage capacitor between the second node and the second power line.

[0026] The display apparatus can further include a scan driver configured to provide a first scan signal to the first scan line and a second scan signal to the second scan line, a data driver configured to provide a data signal to the data line, and a sensing driver configured to receive a sensing signal corresponding to a threshold voltage of the first transistor through the sensing line.

[0027] In the first period, the first power voltage applied to the first power line can change to be less than the second power voltage applied to the second power line; in the first period, the scan driver can provide the first scan signal having the first gate-on voltage level to the first scan line and can provide the second scan signal having the second gate-on voltage level to the second scan line; in the first period, the data driver can provide the reference voltage to the data line; and the sensing driver can apply an initialization voltage to the sensing line in a first sub-period of the first period and can receive the sensing signal in a second sub-period of the first period.

[0028] According to one or more exemplary embodiments of the display apparatus of the disclosure, the light emitting element in the pixel can be connected between the first power line (e.g., a high power voltage) and the first electrode of the first transistor. Accordingly, regardless of a change in the characteristics of the light emitting element, the gate-source voltage of the first transistor (i.e., the voltage between the second electrode and the gate electrode of the first transistor) can be controlled only by the data voltage applied to the gate electrode of the first transistor, and the pixel can emit light at a desired brightness, and the display apparatus can have uniform brightness (or substantially uniform brightness).

[0029] In one or more exemplary embodiments, the pixel can include a fourth transistor connected between the first power line and the first electrode of the first transistor, and a third transistor connected to the second electrode of the first transistor. Accordingly, the display apparatus can sense the characteristics (e.g., threshold voltage) of the first transistor T1 and eliminate (or reduce) the brightness deviation (or brightness variation) due to the change in the characteristics of the first transistor. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1A and Figure 1B show a perspective view and a cross-sectional view of a light emitting element according to an exemplary embodiment, respectively.

[0031] Figure 2A and Figure 2B show a perspective view and a cross-sectional view of a light emitting element according to another exemplary embodiment, respectively.

[0032] Figure 3A and Figure 3B show a perspective cross-sectional view and a cross-sectional view of a light emitting element according to another exemplary embodiment, respectively.

[0033] Figure 4 A perspective cross-sectional view of a light emitting element according to another exemplary embodiment is shown.

[0034] Figure 5 A block diagram illustrating a display device according to one or more exemplary embodiments of the present disclosure is shown.

[0035] Figure 6 Shown included in Figure 5 A circuit diagram of an example of a pixel in a display device.

[0036] Figure 7A and Figure 7B Shown for illustration Figure 6 Diagram of the operation of pixels in display mode.

[0037] Figure 7C Shown for illustration Figure 6 FIG. 5 is a diagram of the operation of a pixel in sensing mode.

[0038] Figure 8 Shown included in Figure 5 A circuit diagram of a comparative example of a pixel in a display device of FIG.

[0039] Figure 9 Shown included in Figure 5 A circuit diagram of another example of a pixel in a display device.

[0040] Figure 10 Shown included in Figure 5 A circuit diagram of another example of a pixel in a display device.

[0041] Figure 11 Shown for illustration Figure 10 Graph of pixel operations.

[0042] Figure 12 Shown included in Figure 5 A circuit diagram of another example of a pixel in a display device. DETAILED DESCRIPTION

[0043] With reference to the detailed description and accompanying drawings of the following exemplary embodiments, the aspects and features of the present disclosure and the methods for realizing the same may be more easily understood. However, the present disclosure is not limited to the exemplary embodiments described below and may be implemented in many different forms. The following exemplary embodiments are provided to complete the present disclosure and to allow those skilled in the art to clearly understand the scope of the present disclosure, and the present disclosure is defined by the appended claims and their equivalents.

[0044] It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or there can be intervening elements or layers. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the accompanying drawings for describing the exemplary embodiments of the present disclosure are illustrative, and therefore the present disclosure is not limited to the exemplary embodiments shown. Throughout the specification, the same reference numerals represent the same constituent elements. In addition, in order to make the present disclosure clear, parts that are not related to the description of the present disclosure are omitted or simplified in the accompanying drawings.

[0045] Although the terms "first," "second," and the like are used to describe various constituent elements, these constituent elements are not limited by these terms. These terms are merely used to distinguish one constituent element from another constituent element. Therefore, within the technical spirit of the present disclosure, the first constituent element described below may be the second constituent element. The singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0046] Each of the features of the various exemplary embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may be technically connected and driven differently in a manner that is well understood by those skilled in the art. Each exemplary embodiment may be practiceable independently of one another, and may be practiced together in a relationship to one another.

[0047] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1A and Figure 1B 1 and 2 show a perspective view and a cross-sectional view of a light emitting element according to an exemplary embodiment, respectively. Figure 1A and Figure 1B , a cylindrical rod-shaped light emitting element LD is shown, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0049] refer to Figure 1A and Figure 1B The light emitting element LD according to the exemplary embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be configured as a stacked body in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked in one direction.

[0050] According to one or more exemplary embodiments, the light emitting element LD may have a rod shape extending in one direction. The light emitting element LD may have one end portion and another end portion along the one direction.

[0051] In some embodiments, one of the first and second semiconductor layers 11 and 13 may be disposed at one end portion of the light emitting element LD, and the other may be disposed at the other end portion of the light emitting element LD.

[0052] In some embodiments, the light-emitting element LD may be a rod-shaped light-emitting diode. Here, the rod shape includes a rod or bar shape (such as a cylinder or polygonal column) whose longitudinal length is longer than its width, and the cross-sectional shape of the rod shape is not particularly limited. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its cross-section).

[0053] In some embodiments, the size of the light-emitting element LD is as small as nanometer to micrometer scale, for example, the diameter D and / or the length L are in the range of about 100 nm to about 10 μm. However, the size of the light-emitting element LD is not limited thereto. For example, the size of the light-emitting element LD can be varied according to the design conditions of various devices (e.g., display devices) using the light-emitting device (which uses the light-emitting element LD as a light source).

[0054] The first semiconductor layer 11 may include at least one n-type semiconductor material. For example, the first semiconductor layer 11 may include one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor material doped with a first conductive dopant such as Si, Ge, and Sn. However, the material included in the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be made of a different material.

[0055] The active layer 12 is formed on the first semiconductor layer 11 and may be formed to have a single quantum well structure or a multi-quantum well structure. When the active layer 12 includes a material having a multi-quantum well structure, a plurality of quantum layers and well layers may be alternately stacked.

[0056] When an appropriate voltage (e.g., a set voltage or a predetermined voltage) or more is applied between the terminal portions of the light emitting element LD, the light emitting element LD emits light when electron-hole pairs are combined in the active layer 12. By controlling the emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various light emitting devices in addition to pixels of a display device.

[0057] The active layer 12 may emit light having a wavelength of 400 nm to 900 nm. For example, when the active layer 12 emits light in the blue or green wavelength band, it may include an inorganic material containing nitrogen, such as AlGaN or AlGaInN. For example, when the active layer 12 has a structure in which quantum layers and well layers are alternately stacked in a multi-quantum well structure, the quantum layers may include inorganic materials such as AlGaN or AlGaInN, and the well layers may include inorganic materials such as GaN or AlInN. In one or more exemplary embodiments, the active layer 12 may include AlGaInN as the quantum layers and AlInN as the well layers.

[0058] However, the present disclosure is not limited thereto, and the active layer 12 may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include Group III to Group V semiconductor materials according to the wavelength band of light emitted from the active layer 12. Depending on the materials included therein, the light emitted from the active layer 12 is not limited to light in the blue wavelength band or the green wavelength band, and may be light in the red wavelength band.

[0059] On the other hand, light emitted from the active layer 12 may be emitted from both sides as well as the outer surface in the longitudinal direction of the light emitting element LD. The direction of light emitted from the active layer 12 is not limited to one direction.

[0060] The second semiconductor layer 13 is provided on the active layer 12 and may include a semiconductor material of a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor material doped with a second conductive dopant (such as Mg, Ca, or Ba). However, the material included in the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of a different material.

[0061] In one or more exemplary embodiments, the drawings illustrate that the first semiconductor layer 11 and the second semiconductor layer 13 are each formed as a single layer, but the present disclosure is not limited thereto. For example, depending on the material of the active layer 12, the first semiconductor layer 11 and the second semiconductor layer 13 may include a larger number of layers. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may further include a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0062] In some embodiments, the first length L1 of the first semiconductor layer 11 may be longer than the second length L2 of the second semiconductor layer 13 .

[0063] In some embodiments, the light emitting element LD may further include an insulating film INF disposed on a surface thereof. The insulating film INF may be formed on the surface of the light emitting element LD so as to surround the outer surface (e.g., outer peripheral surface or outer circumferential surface) of the active layer 12 and may also surround the first semiconductor layer 11 and the second semiconductor layer 13.

[0064] In some embodiments, the insulating film INF may expose two end portions of the light emitting element LD having different polarities. For example, the insulating film INF may not cover one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 provided at respective ends in the longitudinal direction of the light emitting element LD (e.g., two planes (e.g., upper and lower surfaces) of a cylinder) and may expose it. In some embodiments, the insulating film INF may expose one of the end portions of the light emitting element LD.

[0065] In some embodiments, the insulating film INF may include a transparent insulating material. For example, the insulating film INF may be made of SiO x or SiN x The insulating film INF is made of SiO2 or Si3N4, which is not particularly determined, but is not limited thereto. The constituent material of the insulating film INF is not particularly limited, and the insulating film INF can be made of various insulating materials currently known to those skilled in the art.

[0066] The insulating film INF can prevent or substantially prevent a short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In one or more exemplary embodiments, by forming the insulating film INF, surface defects of the light-emitting element LD can be reduced or minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. In one or more exemplary embodiments, when a plurality of light-emitting elements LD are closely arranged, the insulating film INF can prevent or substantially prevent an undesirable short circuit that may occur between the corresponding light-emitting elements LD.

[0067] In one or more exemplary embodiments, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF, the light emitting element LD may further include additional constituent elements disposed on the upper portion and / or lower portion of the corresponding layers of the light emitting element LD. For example, the light emitting element LD may further include one or more of a phosphor layer, an active layer, a semiconductor material layer, and an electrode layer disposed on one side of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0068] Figure 2A and Figure 2B A perspective view and a cross-sectional view are respectively shown of a light emitting element according to another exemplary embodiment.

[0069] refer to Figure 2A and Figure 2B According to exemplary embodiments of the present disclosure, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to exemplary embodiments, the first semiconductor layer 11 is disposed in a central region of the light emitting element LD, and the active layer 12 may be disposed on a surface of the first semiconductor layer 11 so as to surround at least one region of the first semiconductor layer 11. For example, the active layer 12 may be disposed along an outer edge or a peripheral region of the first semiconductor layer 11 so as to surround at least one region of the first semiconductor layer 11. In one or more exemplary embodiments, the second semiconductor layer 13 may be disposed on a surface of the active layer 12 so as to surround at least one region of the active layer 12. For example, the second semiconductor layer 13 may be disposed along an outer edge or a peripheral region of the active layer 12 so as to surround at least one region of the active layer 12.

[0070] In addition, the light-emitting element LD may further include an electrode layer 14 and / or an insulating film INF surrounding at least one region of the second semiconductor layer 13. For example, the light-emitting element LD may include an electrode layer 14 disposed on the surface of the second semiconductor layer 13 so as to surround a region of the second semiconductor layer 13, and the insulating film INF may be disposed on the surface of the electrode layer 14 so as to surround at least one region of the electrode layer 14. For example, the electrode layer 14 may be disposed along the outer edge or peripheral region of the second semiconductor layer 13 so as to surround at least one region of the second semiconductor layer 13, and the insulating film INF may be disposed along the outer edge or peripheral region of the electrode layer 14 so as to surround at least one region of the electrode layer 14. For example, the light-emitting element LD may be implemented as a core-shell structure including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the electrode layer 14, and the insulating film INF, sequentially disposed from the center outward. In some embodiments, the electrode layer 14 and / or the insulating film INF may be omitted.

[0071] In some embodiments, the light emitting element LD may be provided to have a polygonal horn shape extending in one direction (e.g., the length L direction). For example, the light emitting element LD may have a hexagonal horn shape. However, the shape of the light emitting element LD is not limited thereto and may be varied.

[0072] In one or more exemplary embodiments, the two end portions of the first semiconductor layer 11 along the length L of the light emitting element LD may have a protruding shape. The shapes of the two end portions of the first semiconductor layer 11 may be different from each other. For example, one of the two end portions of the first semiconductor layer 11, which is located at the upper side, may have a horn-like shape having a single vertex as its width narrows toward the upper portion of the horn. In one or more exemplary embodiments, the other end portion of the two end portions of the first semiconductor layer 11, which is located at the lower side, may have a polygonal column shape having a constant width.

[0073] In some embodiments, the first semiconductor layer 11 may be positioned at the core of the light emitting element LD, for example, at the center (or central region) of the light emitting element LD. In one or more exemplary embodiments, the light emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal shape, the light emitting element LD may have a hexagonal shape.

[0074] Figure 3A and Figure 3B 1 and 2 show a perspective cross-sectional view and a cross-sectional view of a light emitting element according to another embodiment. Figure 3A and Figure 3B , for the convenience of description, a portion of the insulating film INF is omitted.

[0075] refer to Figure 1A 、 Figure 1B 、 Figure 3A and Figure 3B The light emitting element LD may further include an electrode layer 14 disposed on the second semiconductor layer 13 .

[0076] The electrode layer 14 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto. In some embodiments, the electrode layer 14 may be a Schottky contact electrode. The electrode layer 14 may include a metal or metal oxide, such as Cr, Ti, Al, Au, Ni, indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO) and their oxides or alloys, which may be used alone or in combination. In some embodiments, the electrode layer 14 may be substantially transparent or transflective. Therefore, the light generated by the active layer 12 of the light-emitting element LD can be transmitted through the electrode layer 14 and can be emitted to the outside of the light-emitting element LD.

[0077] In some embodiments, the insulating film INF may have a curved shape in at least a portion of an edge region adjacent to the electrode layer 14. In some embodiments, when manufacturing the light emitting element LD, the curved surface shape may be formed by an etching process.

[0078] On the other hand, Figure 1A and Figure 1B In the light emitting element LD shown in , even when the light emitting element LD does not include the electrode layer 14 , the insulating film INF may have a curved shape in at least a portion of the edge region.

[0079] Figure 4 FIG2 shows a perspective cross-sectional view of a light emitting element according to another exemplary embodiment. Figure 4 , for the convenience of description, a portion of the insulating film INF is omitted.

[0080] refer to Figure 1A 、 Figure 1B and Figure 4 The light emitting element LD may further include a third semiconductor layer 15, a fourth semiconductor layer 16, and a fifth semiconductor layer 17. The third semiconductor layer 15 may be disposed between the first semiconductor layer 11 and the active layer 12. The fourth semiconductor layer 16 and the fifth semiconductor layer 17 may be disposed between the active layer 12 and the second semiconductor layer 13. In one or more exemplary embodiments, the light emitting element LD may further include a first electrode layer 14a formed on an upper surface of the second semiconductor layer 13 and a second electrode layer 14b formed on a lower surface of the first semiconductor layer 11.

[0081] Figure 4 The light emitting element LD and Figure 1A The difference between the light emitting element LD is that Figure 4 The light emitting element LD further includes a third semiconductor layer 15, a fourth semiconductor layer 16, and a fifth semiconductor layer 17, as well as a first electrode layer 14a and a second electrode layer 14b, and the active layer 12 includes other elements. The first semiconductor layer 11, the second semiconductor layer 13, and the insulating film INF can be Figure 1A The described first semiconductor layer 11 , second semiconductor layer 13 , and insulating film INF are substantially the same.

[0082] In some embodiments, Figure 4 Each of the active layer 12 and the semiconductor layers 11, 13, 15, 16, and 17 of the light emitting element LD may include at least phosphorus (P). Figure 1A As described above, when the active layer 12 includes nitrogen (N), the light emitting element LD may emit blue light or green light. In one or more exemplary embodiments, when the active layer 12 and each of the semiconductor layers 11, 13, 15, 16, and 17 include at least phosphorus (P), the light emitting element LD may emit red light. For example, the light emitting element LD may emit red light having a central wavelength band of 620 nm to 750 nm.

[0083] As reference Figure 1A and Figure 1BThe first semiconductor layer 11 can include an n-type semiconductor material. When the light emitting element LD emits red light, the first semiconductor layer 11 can include a semiconductor material having In x Al y Ga 1-x-y P (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer 11 can be (or can include) n-AlGaInP doped with an n-type dopant Si.

[0084] As described above with reference to Figure 1A and Figure 1B The second semiconductor layer 13 can include a p-type semiconductor material. When the light emitting element LD emits red light, the second semiconductor layer 13 can include a semiconductor material having In x Al y Ga 1-x-y P (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer 13 can be (or can include) p-GaP doped with a p-type dopant Mg.

[0085] The active layer 12 can be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. As described above with reference to Figure 1A and Figure 1B The active layer 12 can include a material having a single quantum well structure or a multiple quantum well structure, and can emit light having a specific wavelength band. For example, when the active layer 12 emits light in a red wavelength band, the active layer 12 can include a material such as AlGaP or AlGaInP. As another example, when the active layer 12 has a multiple quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layers can include a material such as AlGaP or AlGaInP, and the well layers can include a material such as GaP or AlInP. In one or more exemplary embodiments, the active layer 12 can emit red light having a center wavelength band of 620 nm to 750 nm by including AlGaInP as the quantum layers and AlInP as the well layers.

[0086] The third semiconductor layer 15 and the fourth semiconductor layer 16 can be disposed adjacent to the upper and lower portions of the active layer 12, and can be referred to as cladding layers.

[0087] The third semiconductor layer 15 can be disposed between the first semiconductor layer 11 and the active layer 12. Similar to the first semiconductor layer 11, the third semiconductor layer 15 can include an n-type semiconductor material. For example, the third semiconductor layer 15 can include a semiconductor material having In x Al y Ga 1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1). In an embodiment, the first semiconductor layer 11 may be (or may include) n-AlGaInP, and the third semiconductor layer 15 may be (or may include) n-AlInP. However, it is not limited thereto.

[0088] The fourth semiconductor layer 16 may be provided between the active layer 12 and the second semiconductor layer 13. Similar to the second semiconductor layer 13, the fourth semiconductor layer 16 may be a p-type semiconductor, and for example, the fourth semiconductor layer 16 may include a semiconductor layer having In x Al y Ga 1-x-y In one or more exemplary embodiments, the second semiconductor layer 13 may be (or may include) p-GaP, and the fourth semiconductor layer 16 may be (or may include) p-AlInP.

[0089] The fifth semiconductor layer 17 may be disposed between the fourth semiconductor layer 16 and the second semiconductor layer 13. Similar to the second semiconductor layer 13 and the fourth semiconductor layer 16, the fifth semiconductor layer 17 may be a p-type doped semiconductor. The fifth semiconductor layer 17 may have a function of reducing the difference in lattice constant between the fourth semiconductor layer 16 and the second semiconductor layer 13. For example, the fifth semiconductor layer 17 may be a tensile strain barrier reduction (TSBR) layer. For example, the fifth semiconductor layer 17 may include p-GaInP, p-AlInP, or p-AlGaInP, but is not limited thereto.

[0090] The first electrode layer 14a may be disposed on the upper surface of the second semiconductor layer 13, and the second electrode layer 14b may be disposed on the lower surface of the first semiconductor layer 11. In some embodiments, at least one of the first electrode layer 14a and the second electrode layer 14b may be omitted. The first electrode layer 14a and the second electrode layer 14b may each include a Figure 3A The electrode layer 14 is made of at least one of the materials discussed.

[0091] Figure 5 1 shows a block diagram of a display device according to one or more exemplary embodiments of the present disclosure. In some embodiments, Figure 5 Can be used Figures 1A to 4 The light emitting element LD described in is used as a light source.

[0092] refer to Figure 5The display device 100 may include a display portion 110 (or a display panel), a scan driver 120 (or a gate driver), a light emitting driver 130 (or an emission driver or an emission control driver), a data driver 140 (or a source driver), a sensing portion 150 (or a sensing driver), a timing controller 160, and a power supply 170.

[0093] The display portion 110 may include scan lines SC1 to SCn (or first scan lines) (where n is a positive integer), data lines DL1 to DLm (where m is a positive integer), and a plurality of pixels PXL. In one or more exemplary embodiments, the display portion 110 may further include emission control lines EL1 to ELn, sensing scan lines SS1 to SSn (or second scan lines), and sensing lines RL1 to RLm (or lead lines).

[0094] The pixels PXL among the plurality of pixels may be disposed in a region (eg, a pixel region) divided by the scan lines SC1 to SCn and the data lines DL1 to DLm.

[0095] The pixel PXL may be connected to a corresponding one of the scan lines SC1 to SCn and a corresponding one of the data lines DL1 to DLm. In one or more exemplary embodiments, the pixel PXL may be connected to a corresponding one of the emission control lines EL1 to ELn, a corresponding one of the sensing scan lines SS1 to SSn, and a corresponding one of the sensing lines RL1 to RLm. Hereinafter, "connection" may include not only electrical connection but also physical connection, and may include not only direct connection but also indirect connection through another component.

[0096] The pixel PXL may include a light emitting element and at least one transistor for supplying a driving current to the light emitting element.

[0097] The pixel PXL can emit light with a brightness corresponding to the data voltage (or data signal) provided by the data line (e.g., the jth data line DLj (j is a positive integer less than or equal to m)) in response to a first scan signal provided by the scan line (e.g., the i-th scan line SCi (i is a positive integer less than or equal to n)). The emission period of the pixel PXL can be adjusted based on the emission control signal provided by the emission control line (e.g., the i-th emission control line ELi). In one or more exemplary embodiments, the pixel PXL can output characteristic information of the light-emitting element (e.g., information related to the threshold voltage and / or mobility of the driving transistor, and / or the current-voltage characteristics, sensing voltage or sensing current of the light-emitting device) through the sensing line (e.g., the j-th sensing line RLj) in response to a second scan signal provided by the sensing scan line (e.g., the i-th sensing scan line SSi).

[0098] Will refer to it later Figure 6 as well as 7A to 7C The detailed structure and operation of the pixel PXL are described.

[0099] Refer again Figure 5 , the scan driver 120 may generate a first scan signal based on the scan control signal SCS and sequentially provide the first scan signal to the scan lines SC1 to SCn. Here, the scan control signal SCS may include a scan start signal (or a scan start pulse), a scan clock signal, etc., and may be provided from the timing controller 160. For example, the scan driver 120 may include a shift register (or stage) that sequentially generates and outputs a pulse-type first scan signal corresponding to a pulse-type scan start signal (e.g., a gate-on voltage level pulse) by using a scan clock signal.

[0100] The scan driver 120 may generate a second scan signal (or a sensing control signal) similar to the first scan signal and sequentially provide the second scan signal to the sensing scan lines SS1 to SSn.

[0101] The emission driver 130 may generate an emission control signal based on the emission drive control signal ECS and sequentially provide the emission control signal to the emission control lines EL1 to ELn. Here, the emission drive control signal ECS may include an emission start signal (or emission start pulse), an emission clock signal, etc., and may be provided from the timing controller 160. For example, the emission driver 130 may include a shift register (or stage) that sequentially generates and outputs a pulse-type emission control signal corresponding to a pulse-type emission start signal (e.g., a gate-off voltage level pulse) using the emission clock signal. In some embodiments, the emission driver 130 and the emission control lines EL1 to ELn may be omitted.

[0102] The data driver 140 may generate a data signal (or data voltage) based on the image data DATA2 and the data control signal DCS provided from the timing controller 160, and transmit the data signal to the data lines DL1 to DLm. Here, the data control signal DCS is a signal for controlling the operation of the data driver 140 and may include a load signal (or data enable signal) for instructing output of a valid data voltage.

[0103] In one or more exemplary embodiments, the data driver 140 may generate a data signal (or data voltage) corresponding to a data value (or grayscale value) included in the image data DATA2 by using a gamma voltage. Here, the gamma voltage may be generated by the data driver 140 or may be provided by a separate gamma voltage generating circuit (e.g., a gamma integrated circuit). For example, the data driver 140 may select one of the gamma voltages based on the data value to output as a data signal.

[0104] The sensing driver 150 may provide an initialization voltage to the sensing lines RL1 to RLm based on the compensation control signal CCS in a sensing mode (or sensing period), and may sense emission characteristics of the pixels PXL through the sensing lines RL1 to RLm. Here, the compensation control signal CCS may be provided from the timing controller 160 .

[0105] For reference, the display device 100 can operate in a sensing mode (or sensing period) or a display mode (or display period). In the display mode, the display device 100 can supply a data voltage to the pixel PXL so that the light-emitting element LD in the pixel PXL emits light corresponding to the data voltage, and in the sensing mode, the display device 100 can sense the emission characteristics of the pixel PXL. The sensing time corresponding to the sensing mode can be allocated before or after the display period, and in some cases, the display period and the sensing period can be included in one frame (or frame period).

[0106] The emission characteristics of the pixel PXL may include a threshold voltage and mobility of at least one transistor (e.g., a driving transistor) in the pixel PXL, and characteristic information of the light-emitting element (e.g., current-voltage characteristics). For example, the sense driver 150 may detect a sense value (or sense voltage or sense current) corresponding to the emission characteristics of the pixel PXL through the sense lines RL1 to RLm.

[0107] The sensed value may be provided to the timing controller 160, and the timing controller 160 may compensate the image data DATA2 (or the input image data DATA1) based on the sensed value. However, the present disclosure is not limited thereto, and for example, the sensed value may be provided from the sense driver 150 to the data driver 140, and the data driver 140 may generate a data voltage based on the sensed value. For example, the data driver 140 may change or compensate the data voltage based on the amount of change in the sensed value. For example, the data voltage may be compensated based on the emission characteristics (or changes in the emission characteristics) of the sensed pixel PXL.

[0108] The timing controller 160 may receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor), generate a scan control signal SCS, an emission drive control signal ECS, and a data control signal DCS based on the control signal CS, and convert the input image data DATA1 to generate image data DATA2. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. For example, the timing controller 160 may convert the input image data DATA1 into image data DATA2 in a format usable by the data driver 140.

[0109] In one or more exemplary embodiments, the timing controller 160 may further generate a compensation control signal CCS based on the control signal CS. The compensation control signal CCS may be provided to the sensing driver 150.

[0110] The power supply 170 may provide a first power voltage VDD (or high power voltage) and a second power voltage VSS (or low power voltage) to the display portion 110. The first power voltage VDD and the second power voltage VSS are voltages required for the operation of the pixel PXL, and the first power voltage VDD may have a voltage level higher than the voltage level of the second power voltage VSS. The power supply 170 may provide a driving voltage to at least one of the scan driver 120, the emission driver 130, the data driver 140, and the sensing driver 150.

[0111] In one or more exemplary embodiments, Figure 5 As shown in FIG, the scan driver 120, the emission driver 130, the data driver 140, the sensing driver 150, and the timing controller 160 are shown as being configured independently of each other, but are not limited thereto. For example, at least one of the scan driver 120, the emission driver 130, the data driver 140, the sensing driver 150, and the timing controller 160 may be formed in the display portion 110, or implemented as an integrated circuit (IC) and mounted on a flexible circuit board to be connected to the display portion 110. For example, the scan driver 120 and the emission driver 130 may be formed in the display portion 110. In one or more exemplary embodiments, at least two of the scan driver 120, the emission driver 130, the data driver 140, the sensing driver 150, and the timing controller 160 may be implemented in an IC. For example, the data driver 140 and the sensing driver 150 may be implemented as one integrated circuit.

[0112] Figure 6 Shown included in Figure 5 A circuit diagram of an example of a pixel in a display device.

[0113] refer to Figure 6, the pixel PXL may be connected to the scan line SC, the sensing scan line SS, the emission control line EL, the data line DL, and the sensing line RL. For example, the scan line SC, the sensing scan line SS, the emission control line EL, the data line DL, and the sensing line RL may correspond to the i-th scan line SCi, the i-th sensing scan line SSi, the i-th emission control line ELi, the j-th data line DLj, and the j-th sensing line RLj, respectively. In one or more exemplary embodiments, the pixel PXL may be connected between the first power line PL1 and the second power line PL2. Here, referring to Figure 5 The first power voltage VDD described above may be applied to the first power line PL1, and referring to Figure 5 The described second power voltage VSS may be applied to the second power line PL2 .

[0114] The pixel PXL may include at least one light-emitting element, a first transistor T1 (or a driving transistor), a second transistor T2 (or a first switching transistor), a third transistor T3 (or a sensing transistor), a fourth transistor T4 (or a second switching transistor), a fifth transistor T5 (or an emission control transistor), and a storage capacitor CST. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include an oxide semiconductor and may be, for example, an N-type transistor. However, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are not limited thereto, and at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include a silicon semiconductor or may be implemented as a P-type transistor.

[0115] At least one light emitting element may include a light emitting element LD. An anode electrode of the light emitting element LD may be connected to (or coupled to) the first power line PL1 (or the first pixel electrode connected to the first power line PL1), and a cathode electrode of the light emitting element LD may be connected to the first node N1 (or the second pixel electrode). The light emitting element LD may generate light having a brightness (e.g., a set brightness or a predetermined brightness) corresponding to the amount of current (or drive current) supplied from the first transistor T1. The light emitting element LD may be a reference Figures 1A to 4 However, the present disclosure is not limited thereto, and the light emitting element LD may be an organic light emitting element.

[0116] In some embodiments, the at least one light emitting element may include a plurality of light emitting elements. The plurality of light emitting elements including the light emitting element LD may be connected in parallel to each other between the first power line PL1 and the first node N1.

[0117] In one or more exemplary embodiments, at least one light-emitting element may further include a reverse light-emitting element LDR. The reverse light-emitting element LDR is connected in parallel with the light-emitting element LD, which constitutes the effective light source, between the first power line PL1 and the first node N1 (or between the first pixel electrode and the second pixel electrode). However, the reverse light-emitting element LDR may be connected between the first power line PL1 and the first node N1 in a direction opposite to that of the light-emitting element LD. For example, the anode electrode of the reverse light-emitting element LDR may be connected to the cathode electrode of the light-emitting element LD or the first node N1, and the cathode electrode of the reverse light-emitting element LDR may be connected to the anode electrode of the light-emitting element LD or the first power line PL1. Even when a drive voltage (e.g., a set drive voltage or a predetermined drive voltage, e.g., a drive voltage in the forward direction) is applied between the first power line PL1 and the first node N1, the reverse light-emitting element LDR remains in an inactive state, and thus substantially no current may flow in the reverse light-emitting element LDR.

[0118] The first electrode (or first transistor electrode) of the first transistor T1 may be connected to the first node N1, and the second electrode (or second transistor electrode) of the first transistor T1 may be connected to the third node N3, and the gate electrode of the first transistor T1 may be connected to the second node N2. For example, the first electrode of the first transistor T1 may be a drain electrode, and the second electrode of the first transistor T1 may be a source electrode, but the present disclosure is not limited thereto. The first transistor T1 may control the amount of current flowing through the light-emitting element LD in response to the voltage of the second node N2.

[0119] A first electrode of the second transistor T2 may be connected to the data line DL, a second electrode of the second transistor T2 may be connected to the second node N2, and a gate electrode of the second transistor T2 may be connected to the scan line SC. When a first scan signal having a gate-on voltage level is supplied to the scan line SC, the second transistor T2 may be turned on, and a data signal (or data voltage) may be transmitted from the data line DL to the second node N2.

[0120] The storage capacitor CST may be formed between the first power line PL1 and the second node N2. The storage capacitor CST may store the voltage of the second node N2 (eg, a data signal applied to the second node N2).

[0121] A first electrode of the third transistor T3 may be connected to the sensing line RL, a second electrode of the third transistor T3 may be connected to the third node N3, and a gate electrode of the third transistor T3 may be connected to the sensing scan line SS. When a second scan signal having a gate-on voltage level is supplied to the sensing scan line SS, the third transistor T3 may be turned on, and an initialization voltage may be applied from the sensing line RL to the third node N3, or a sensing signal (e.g., a sensing current) may be transmitted from the third node N3 to the sensing line RL. The sensing signal may be supplied to the reference Figure 5 The sensing driver 150 is described.

[0122] A first electrode of the fourth transistor T4 may be connected to the first power line PL1, a second electrode of the fourth transistor T4 may be connected to the first node N1, and a gate electrode of the fourth transistor T4 may be connected to the sensing scan line SS. When a second scan signal having a gate-on voltage level is supplied to the sensing scan line SS, the fourth transistor T4 may be turned on and may connect the first power line PL1 and the first node N1. In a sensing mode, the fourth transistor T4 may form a current flow path for driving current to flow from the first power line PL1 to the first transistor T1.

[0123] A first electrode of the fifth transistor T5 may be connected to the third node N3, a second electrode of the fifth transistor T5 may be connected to the second power line PL2, and a gate electrode of the fifth transistor T5 may be connected to the emission control line EL. When an emission control signal having a gate-on voltage level is supplied to the emission control line EL, the fifth transistor T5 may be turned on, and the third node N3 and the second power line PL2 may be connected. In the display mode, the fifth transistor T5 may form a current flow path for driving current to flow from the first power line PL1 through the light-emitting element LD, the first transistor T1, and the fifth transistor T5 to the second power line PL2.

[0124] You can refer to Figure 7A 、 Figure 7B and Figure 7C To describe Figure 6 More specific operations of the pixel PXL.

[0125] Figure 7A and Figure 7B Shown for illustration Figure 6 Diagram of the operation of pixels in display mode. Figure 7C Shown for illustration Figure 6 FIG. 5 is a diagram of the operation of a pixel in sensing mode.

[0126] refer to Figure 6 as well as 7A to 7C, the emission control signal EM may be applied to the emission control line EL, the first scan signal SCAN1 may be applied to the scan line SC, the second scan signal SCAN2 may be applied to the sensing scan line SS, and the data voltage VDATA (or data signal) may be applied to the data line DL. The first power voltage VDD may have a constant voltage level (e.g., a high voltage level HIGH), and the second power voltage VSS may have a constant voltage level (e.g., a low voltage level LOW lower than the high voltage level HIGH).

[0127] In the following, we will first refer to Figure 7A and Figure 7B The operation of the pixel PXL in the display mode is described.

[0128] As reference Figure 5 As described, Figure 7A and Figure 7B In the display mode shown in FIG, a valid data voltage is applied to (or written to) the pixel PXL, and the pixel PXL may emit light at a luminance corresponding to the valid data voltage.

[0129] The emission control signal EM may have a gate-off voltage level OFF (or a logic low level) in the first period P1, and may have a gate-on voltage level ON (or a logic high level) in a second period P2 that is different from the first period P1. Therefore, in the first period P1, the fifth transistor T5 may be turned off in response to the emission control signal EM having the gate-off voltage level OFF, and in the second period P2, the fifth transistor T5 may be turned on in response to the emission control signal EM having the gate-on voltage level ON.

[0130] In the first sub-period P_S1 of the first period P1, the pulse of the first scan signal SCAN1 may have a gate-on voltage level ON. The width of the first sub-period P_S1 (or the width of the pulse of the first scan signal SCAN1) is smaller than the width of the first period P1, and for example, the width of the first sub-period P_S1 is 2 horizontal times, and the first period P1 may be greater than 3 horizontal times. Here, the horizontal time may be a period of a substantially horizontal synchronization signal or the display device 100 (see Figure 5 ) is a period in which pixel rows are selected sequentially.

[0131] In this case, in the first sub-period P_S1 , the second transistor T2 is turned on in response to the first scan signal SCAN1 having the gate-on voltage level ON, and the data voltage VDATA of the data line DL may be applied to the second node N2 .

[0132] The data voltage VDATA may have a first data value D1 (or voltage level) in at least a portion of the first sub-period P_S1. For example, when the first scan signal SCAN1 has a pulse of 2 horizontal times, the data voltage VDATA may have the first data value D1 for the pixel PXL 1 horizontal time after the pulse of the first scan signal SCAN1 occurs.

[0133] Therefore, the first data value D1 may be applied to the second node N2 in at least a portion of the first sub-period P_S1 .

[0134] The storage capacitor CST may store the data voltage VDATA (eg, the first data value D1) supplied to the second node N2 in the first sub-period P_S1. For example, the storage capacitor CST may be charged with a voltage corresponding to the difference between the first power voltage VDD and the first data value D1.

[0135] In one or more exemplary embodiments, in the first sub-period P_S1 , the pulse of the second scan signal SCAN2 may have the gate-on voltage level ON. The waveform and phase of the second scan signal SCAN2 may be substantially the same as those of the first scan signal SCAN1 .

[0136] In this case, in the first sub-period P_S1, the third transistor T3 is turned on in response to the second scan signal SCAN2 having the gate-on voltage level ON, and the sensing line RL and the third node N3 may be connected. When an initialization voltage is applied to the sensing line RL from the sensing driver 150, the initialization voltage may be applied to the third node N3. Here, the initialization voltage may be greater than or equal to the second power voltage VSS. In one or more exemplary embodiments, the initialization voltage may be equal to the second power voltage VSS, for example.

[0137] Similarly, in the first sub-period P_S1, the fourth transistor T4 is turned on in response to the second scan signal SCAN2 having the gate-on voltage level ON, and the first power line PL1 and the first node N1 may be connected. Therefore, since the first power line PL1 and the first node N1 have the same voltage level, for example, since no driving voltage is applied to the light emitting element LD, the light emitting element LD may not emit light in the first sub-period P_S1.

[0138] exist Figure 7A In the first sub-period P_S1, the second scan signal SCAN2 is shown as a pulse having a gate-on voltage level ON, but the present disclosure is not limited thereto. Figure 7BAs shown in , in the first sub-period P_S1 (and the first period P1 ), the second scan signal SCAN2 may have only the gate-off voltage level OFF.

[0139] Even in this case, since the fifth transistor T5 is turned off in the first period P1, the light emitting element LD may not emit light.

[0140] When the operation of the pixel PXL in the first sub-period P_S1 (or the first period P1) is summarized based on the first transistor T1, the gate electrode of the first transistor T1 has a first data value D1, the second electrode of the first transistor T1 has a voltage level corresponding to the initialization voltage (or the second power voltage VSS), and the gate-source voltage of the first transistor T1 (for example, the voltage between the gate electrode and the second electrode of the first transistor T1) can be equal to the difference between the first data value D1 and the initialization voltage (i.e., the voltage at the third node N3 or the second power voltage VSS).

[0141] In one or more exemplary embodiments, after the first sub-period P_S1 , each of the first and second scan signals SCAN1 and SCAN2 has the gate-off voltage level OFF, and each of the second, third, and fourth transistors T2 , T3 , and T4 may be turned off.

[0142] In the second period P2, the emission control signal EM has a gate-on voltage level ON, and the fifth transistor T5 can be turned on. Therefore, a current flow path is formed from the first power line PL1 through the light emitting element LD, the first transistor T1, and the fifth transistor T5 to the second power line PL2, and the light emitting element LD can emit light at a brightness corresponding to the gate-source voltage of the first transistor T1.

[0143] For reference, when the fifth transistor T5 is turned on, the third node N3 and the second power line PL2 are connected, and a voltage level of the third node N3 may be equal to a voltage level of the second power voltage VSS.

[0144] Although the voltage level of the third node N3 (e.g., the second electrode of the first transistor T1) partially changes, the voltage level of the gate electrode of the first transistor T1 that is not connected to the third node N3 can be maintained at the voltage level of the gate electrode of the first transistor T1 during the first period P1 (e.g., the first data value D1), and the gate-source voltage of the first transistor T1 can be equal to the difference between the first data value D1 and the second power voltage VSS.

[0145] For example, the gate-source voltage of the first transistor T1 is determined only by the first data value D1, and therefore, the driving current flowing through the first transistor T1 can be controlled (e.g., accurately controlled) regardless of variations in the characteristics of the light emitting element LD. Therefore, the pixel PXL can accurately emit light at a desired brightness, and the display device 100 ( Figure 5 ) can display an image with uniform brightness (or substantially uniform brightness) without deviation or variation in brightness (or without noticeable deviation or variation in brightness).

[0146] In the following, reference will be made to Figure 7C The operation of the pixel PXL in the sensing mode is described.

[0147] As reference Figure 5 As described, the characteristics of the pixel PXL (eg, the threshold voltage of the first transistor T1) may be Figure 7C is sensed in the sensing mode (or third period P3) shown in .

[0148] In the third period P3, the emission control signal EM may have a gate-off voltage level OFF (or a logic low level). Therefore, in the third period P3, the fifth transistor T5 may be turned off in response to the emission control signal EM having the gate-off voltage level OFF.

[0149] In the first sub-period P_S1' and the second sub-period P_S2' within the third period P3, the pulse of the first scan signal SCAN1 may have the gate-on voltage level ON. The entire width of the first sub-period P_S1' and the second sub-period P_S2' may be greater than the reference Figure 7A The width of the first sub-period P_S1 is described.

[0150] In this case, in the first and second sub-periods P_S1 ′ and P_S2 ′, the second transistor T2 may be turned on in response to the first scan signal SCAN1 having the gate-on voltage level ON, and the data line DL may be connected to the second node N2 .

[0151] In the first sub-period P_S1' (and the second sub-period P_S2'), when the reference voltage VREF is applied to the data line DL, the reference voltage VREF may be applied to the second node N2. Here, the reference voltage VREF has a voltage level for sensing the threshold voltage Vth of the first transistor T1, and, for example, the voltage level of the reference voltage VREF may be greater than the second power voltage VSS and may be less than the first power voltage VDD. For example, the reference voltage VREF may be greater than or equal to the maximum value of the data voltage VDATA applied to the data line DL in the display mode, but is not limited thereto.

[0152] The storage capacitor CST may store the reference voltage VREF supplied to the second node N2 in the first sub-period P_S1 ′ (and the second sub-period P_S2 ′).

[0153] Similar to the first scan signal SCAN1, the pulse of the second scan signal SCAN2 may have the gate-on voltage level ON in the first and second sub-periods P_S1' and P_S2'. The waveform and phase of the second scan signal SCAN2 may be substantially the same as those of the first scan signal SCAN1.

[0154] In this case, in the first sub-period P_S1′ and the second sub-period P_S2′, the third transistor T3 may be turned on in response to the second scan signal SCAN2 having the gate-on voltage level ON, and the sensing line RL and the third node N3 may be connected. In one or more exemplary embodiments, in the first sub-period P_S1′ and the second sub-period P_S2′, the fourth transistor T4 may be turned on in response to the second scan signal SCAN2 having the gate-on voltage level ON, and the first power line PL1 and the first node N1 may be connected.

[0155] When the sensing driver 150 (see Figure 5 ) When the initialization voltage VINT is applied to the sensing line RL, the initialization voltage VINT may be applied to the third node N3. Therefore, the node voltage V_N3 of the third node N3 may change from the voltage level of the second power voltage VSS to the voltage level of the initialization voltage VINT.

[0156] Thereafter, in the second sub-period P_S2′, the sensing driver 150 (see Figure 5 ) can stop providing the initialization voltage VINT (ie, VINT floats).

[0157] In this case, the first transistor T1 provides a current corresponding to the gate-source voltage to the third node N3, and thus, the node voltage V_N3 of the third node N3 can linearly increase to a specific voltage level. For example, the node voltage V_N3 of the third node N3 can increase to a voltage level corresponding to the difference between the reference voltage VREF and the threshold voltage Vth of the first transistor T1 (i.e., VREF-Vth).

[0158] Therefore, the sensing driver 150 (see Figure 5 ) can sense the threshold voltage Vth of the first transistor T1.

[0159] As reference Figure 6 、 Figure 7A and Figure 7B, the light emitting element LD is connected between the first power line PL1 and the first node N1 (e.g., the drain electrode of the first transistor T1), so that the gate-source voltage of the first transistor T1 can be determined or controlled only by the data voltage VDATA, and the light emitting element LD (and the pixel PXL) can emit light with a desired brightness.

[0160] In one or more exemplary embodiments, as shown in FIG. Figure 7C As described above, the pixel PXL includes a fourth transistor T4 connected between the first power line PL1 and the first node N1 and a third transistor T3 connected to the third node N3, so that the display device 100 (see FIG. 1 ) Figure 5 ) can sense the characteristics (eg, threshold voltage Vth) of the first transistor T1 and can compensate the data voltage VDATA (see Figure 7A ). Therefore, the pixel PXL can emit light with desired brightness.

[0161] Figure 8 Shown included in Figure 5 A circuit diagram of a comparative example of a pixel in a display device of FIG.

[0162] refer to Figure 8 , Figure 8 The pixel PXL_C may include a light emitting element LD', a first transistor T1', a second transistor T2', a third transistor T3' and a storage capacitor CST'. The first transistor T1', the second transistor T2' and the third transistor T3' are respectively connected to the reference Figure 7A (or Figure 6 ) are substantially the same as the first transistor T1, the second transistor T2 and the third transistor T3 described in conjunction with FIG. 1 , and thus the repeated description will not be repeated.

[0163] The light emitting element LD' may be connected between the third node N3 and the second power line PL2. A storage capacitor CST' may be formed between the second node N2 and the third node N3. In one or more exemplary embodiments, a parasitic capacitor Cpara may be formed between the first power line PL1 and the second node N2.

[0164] In reference Figure 7A In the described first sub-period P_S1 , it is assumed that a first scan signal having a gate-on voltage level is supplied to the scan line SC, and a second scan signal having a gate-on voltage level is supplied to the sensing scan line SS.

[0165] In this case, the gate voltage of the first transistor T1' may have the same voltage level as the data voltage of the data line DL, and the second electrode of the first transistor T1' (i.e., the third node N3) may have the same voltage level as the initialization voltage applied to the sensing line RL. Therefore, the gate-source voltage of the first transistor T1' may have a voltage corresponding to the difference between the data voltage and the initialization voltage, and the corresponding voltage may be stored in the storage capacitor CST'.

[0166] In one or more exemplary embodiments, in the first sub-period P_S1 (eg, as shown in FIG. Figure 7A After that, it is assumed that a first scan signal having a gate-off voltage level is supplied to the scan line SC, and a second scan signal having a gate-off voltage level is supplied to the sensing scan line SS.

[0167] In this case (see, for example, Figure 8 ), the first transistor T1' supplies a current corresponding to the gate-source voltage from the first power line PL1 to the third node N3, and the node voltage of the third node N3 may increase corresponding to the threshold voltage of the light-emitting element LD. The threshold voltage of the light-emitting element LD' changes due to light-emitting stress (for example, when continuously emitting light at maximum brightness, the threshold voltage of the light-emitting element LD' may shift), and therefore, the node voltage of the third node N3 may change. If the parasitic capacitor Cpara is not present, even if the node voltage of the third node N3 changes, the gate-source voltage of the first transistor T1' is maintained by the storage capacitor CST' to be the same as the gate-source voltage in the first sub-period P_S1 (for example, the period in which the data voltage is written). However, due to the parasitic capacitor Cpara, the amount of change in the node voltage of the third node N3 is divided between the storage capacitor CST' and the parasitic capacitor Cpara, and the gate-source voltage of the first transistor T1' (e.g., the voltage charged in the storage capacitor CST') may be different from the gate-source voltage in the first sub-period P_S1 (e.g., the period in which the data voltage is written). Therefore, depending on the stress on the light emitting element LD', the pixel PXL_C may not emit light at a desired brightness, and the light emitting element LD' may not emit light at a desired brightness. Figure 8 The pixel PXL_C of the display device may have brightness deviation.

[0168] In one or more exemplary embodiments, when the storage capacitor CST′ is connected between the third node N3 and the second node N2, a change in the node voltage of the third node N3 is reflected in the gate-source voltage of the first transistor T1′ as it is, and the pixel PXL_C does not emit light with desired brightness.

[0169] Optionally, Figure 6The pixel PXL includes a light emitting element LD provided between the first power line PL1 and the first node N1, thereby preventing or substantially preventing a parasitic capacitor (eg, Figure 8 The impact of Cpara).

[0170] Figure 9 Shown included in Figure 5 A circuit diagram of another example of a pixel in a display device.

[0171] refer to Figure 6 and Figure 9 , in addition to the connection configuration of the storage capacitor CST_1, the pixel PXL_1 can be connected to Figure 6 The pixels PXL are substantially the same or similar. Therefore, the repeated description will not be repeated.

[0172] The storage capacitor CST_1 may be connected between the second node N2 (or the gate electrode of the first transistor T1) and the third node N3 (or the second electrode of the first transistor T1). The storage capacitor CST_1 may store a voltage between the second node N2 and the third node N3.

[0173] Operation and reference of pixel PXL_1 7A to 7C The operations of the described pixel PXL are substantially the same or similar, and thus the repeated description will not be repeated.

[0174] In reference Figure 7A In the first sub-period P_S1 described above, a first scan signal having a gate-on voltage level may be supplied to the scan line SC, and a second scan signal having a gate-on voltage level may be supplied to the sensing scan line SS. In this case, the second transistor T2 and the third transistor T3 may be turned on, the data voltage of the data line DL may be applied to the second node N2, the initialization voltage of the sensing line RL may be supplied to the third node N3, and the storage capacitor CST_1 may be charged with a voltage corresponding to the difference between the data voltage and the initialization voltage.

[0175] Thereafter, when the fifth transistor T5 is turned on, the node voltage of the third node N3 may be changed from the initialization voltage to the second power voltage VSS.

[0176] A parasitic capacitor may be formed between the first power line PL1 and the second node N2, and the amount of change in the node voltage of the third node N3 (for example, the difference between the initialization voltage and the second power voltage VSS) may not be directly reflected by the parasitic capacitor. However, since the initialization voltage and the second power voltage VSS have fixed values ​​regardless of changes in the characteristics of the light-emitting element LD, the gate-source voltage of the first transistor T1 can be adjusted (for example, easily adjusted) to have a desired value.

[0177] In some embodiments, the initialization voltage applied to the sensing line RL can be set to be equal to the second power voltage VSS. In this case, when the pixel PXL_1 emits light, the node voltage of the third node N3 can be maintained at the same level as the node voltage of the third node N3 when the data voltage is written to the pixel PXL_1. For example, the node voltage of the third node N3 may not be changed. Therefore, the gate-source voltage of the first transistor T1 can be determined only by the data value, and the drive current flowing through the first transistor T1 can be accurately controlled regardless of changes in the characteristics of the light-emitting element LD.

[0178] As reference Figure 9 As described above, the pixel PXL_1 may include a storage capacitor CST_1 connected between the second node N2 and the third node N3.

[0179] Figure 10 Shown included in Figure 5 A circuit diagram of another example of a pixel in a display device.

[0180] refer to Figure 6 and Figure 10 , pixel PXL_2 and Figure 6 The pixel PXL_2 is different from the pixel PXL_2 in that the pixel PXL_2 includes the third transistor T3_1 and does not include the fourth transistor T4 and the fifth transistor T5.

[0181] The light emitting element LD, the reverse light emitting element LDR, the first transistor T1, the second transistor T2 and the storage capacitor CST can be connected to the reference Figure 6 The light emitting element LD, the reverse light emitting element LDR, the first transistor T1, the second transistor T2 and the storage capacitor CST described are substantially the same or similar, and therefore, the repeated description will not be repeated.

[0182] The first electrode (or first transistor electrode) of the first transistor T1 can be connected to the first node N1, and the second electrode (or second transistor electrode) of the first transistor T1 can be connected to the second power line PL2, and the gate electrode of the first transistor T1 can be connected to the second node N2. The first transistor T1 can control the amount of current flowing from the first power line PL1 to the second power line PL2 through the light emitting element LD in response to the voltage of the second node N2.

[0183] The first electrode of the third transistor T3_1 can be connected to the first node N1, the second electrode of the third transistor T3_1 can be connected to the sensing line RL, and the gate electrode of the third transistor T3_1 can be connected to the sensing scan line SS. When the second scan signal SCAN2 having the gate-on voltage level is provided to the sensing scan line SS, the third transistor T3_1 can be turned on, and the initialization voltage can be applied from the sensing line RL to the first node N1, or the sensing signal (e.g., sensing current) can be transmitted from the first node N1 to the sensing line RL.

[0184] The operation of the pixel PXL_2 in the display mode can be similar to the operation of the pixel PXL described with reference to Figure 7A .

[0185] With reference to Figure 7A and Figure 10 , in the first sub-period P_S1, the second scan signal SCAN2 having a pulse of the gate-on voltage level ON can be applied to the sensing scan line SS, the third transistor T3_1 can be turned on in response to the second scan signal SCAN2 having the gate-on voltage level ON, and the sensing line RL and the first node N1 can be connected. When the initialization voltage is applied from the sensing driver 150 to the sensing line RL, the initialization voltage can be applied to the first node N1. The initialization voltage applied to Figure 10 the pixel PXL_2 can be the same as or similar to the first power voltage VDD. The difference between the first power voltage VDD and the initialization voltage can be less than the driving voltage (or threshold voltage) of the light emitting element LD.

[0186] In addition, in the first sub-period P_S1, the first scan signal SCAN1 having a pulse of the gate-on voltage level ON can be applied to the scan line SC, the second transistor T2 can be turned on in response to the first scan signal SCAN1 having the gate-on voltage level ON, and the data voltage VDATA of the data line DL can be applied to the second node N2.

[0187] The storage capacitor CST can store the data voltage VDATA provided to the second node N2 in the first sub-period P_S1.

[0188] In the second period P2, each of the first scan signal SCAN1 and the second scan signal SCAN2 may have a gate-off voltage level OFF, and each of the second transistor T2 and the third transistor T3_1 may be turned off. In this case, a current flow path may be formed from the first power line PL1 through the light emitting element LD and the first transistor T1 to the second power line PL2, and the light emitting element LD may emit light at a brightness corresponding to the gate-source voltage of the first transistor T1.

[0189] The gate-source voltage of the first transistor T1 may be determined by the data voltage applied to the data line DL, and thus, the driving current flowing through the first transistor T1 may be controlled (e.g., accurately controlled) regardless of variations in the characteristics of the light emitting element LD. For example, the pixel PXL_2 may emit light at a desired brightness (e.g., accurately emit light), and the display device 100 ( Figure 5 ) can display images with uniform brightness (or substantially uniform brightness) without deviation or variation in brightness (or without noticeable deviation or variation in brightness).

[0190] You can refer to Figure 11 The operation of the pixel PXL_2 in the sensing mode is described below.

[0191] Figure 11 Shown for illustration Figure 10 Graph of pixel operations.

[0192] refer to Figure 11 , a first scan signal SCAN1 may be applied to the scan line SC, and a second scan signal SCAN2 may be applied to the sensing scan line SS.

[0193] In the third period P3, the first power voltage VDD may change from a high voltage level HIGH (or a first voltage level) to a low voltage level LOW (or a second voltage level). The second power voltage VSS may change from a low voltage level LOW to a high voltage level HIGH. For example, in the third period P3, the first power voltage VDD and the second power voltage VSS may have voltage levels that change oppositely to each other, or the power supply 170 (see Figure 5 ) Power voltages that change oppositely to each other may be applied to the first power line PL1 and the second power line PL2. In this case, since the voltage is applied to the light emitting element LD in the reverse direction, the light emitting element LD may not emit light (for example, the light emitting element LD may be reverse biased).

[0194] In the first and second sub-periods P_S1 ′ and P_S2 ′ within the third period P3 , the pulse of the first scan signal SCAN1 may have the gate-on voltage level ON.

[0195] In this case, in the first sub-period P_S1' and the second sub-period P_S2', the second transistor T2 may be turned on in response to the first scan signal SCAN1 having the gate-on voltage level ON, and the data line DL may be connected to the second node N2. In the first sub-period P_S1' (and the second sub-period P_S2'), when the reference voltage VREF is applied to the data line DL, the reference voltage VREF may be applied to the second node N2.

[0196] The storage capacitor CST may store the reference voltage VREF supplied to the second node N2 in the first sub-period P_S1 ′ (and the second sub-period P_S2 ′).

[0197] Similar to the first scan signal SCAN1 , in the first sub-period P_S1 ′ and the second sub-period P_S2 ′, the pulse of the second scan signal SCAN2 may have the gate-on voltage level ON.

[0198] In this case, in the first and second sub-periods P_S1 ′ and P_S2 ′, the third transistor T3_1 may be turned on in response to the second scan signal SCAN2 having the gate-on voltage level ON, and the sensing line RL and the first node N1 may be connected.

[0199] When the initialization voltage VINT is output from the sensing driver 150 (see FIG. Figure 5 ) is applied to the sensing line RL, the initialization voltage VINT may be applied to the first node N1. Therefore, the node voltage V_N1 of the first node N1 may have a voltage level of the initialization voltage VINT.

[0200] Thereafter, in the second sub-period P_S2 ′, the sensing driver 150 may stop providing the initialization voltage VINT (eg, VINT floats).

[0201] In this case, the first transistor T1 can supply a current corresponding to the gate-source voltage (or the voltage between the first node N1 and the second node N2) from the second power line PL2 to the first node N1, and thus, the node voltage V_N1 of the first node N1 can be linearly increased to a specific voltage level. For example, the node voltage V_N1 of the first node N1 can be increased to a voltage level corresponding to the difference between the reference voltage VREF and the threshold voltage Vth of the first transistor T1 (i.e., VREF-Vth).

[0202] Therefore, the sensing driver 150 (see Figure 5 ) can sense the threshold voltage Vth of the first transistor T1.

[0203] As reference Figure 10and Figure 11 As described, the light emitting element LD is connected between the first power line PL1 and the first node N1 (e.g., the drain electrode of the first transistor T1), so that the gate-source voltage of the first transistor T1 can be determined or controlled only by the data voltage applied via the data line DL, and the light emitting element LD (and the pixel PXL_2) can emit light with a desired brightness.

[0204] In one or more exemplary embodiments, the pixel PXL_2 includes a third transistor T3_1 connected to the first node N1 (e.g., the cathode electrode of the light emitting element LD or the first electrode of the first transistor T1), and in the sensing mode, the first power line PL1 and the second power line PL2 may be applied with voltages opposite to each other. Therefore, the display device 100 (see Figure 5 ) can sense the characteristics of the first transistor T1 (e.g., the threshold voltage Vth), can compensate the data voltage corresponding to the characteristics (or characteristic changes) of the first transistor T1, and can display an image with uniform brightness (or substantially uniform brightness) without causing brightness deviation or change (or without obvious deviation or change in brightness) due to the characteristics (or characteristic changes) of the first transistor T1.

[0205] Figure 12 Shown included in Figure 5 A circuit diagram of another example of a pixel in a display device.

[0206] refer to Figure 10 and Figure 12 , in addition to the connection configuration of the storage capacitor CST_1, the pixel PXL_3 can be connected with Figure 10 The pixels PXL_2 are substantially the same or similar. Therefore, the repeated description will not be repeated.

[0207] The storage capacitor CST_1 may be connected between the second node N2 (or the gate electrode of the first transistor T1) and the second power line PL2 (or the second electrode of the first transistor T1). The storage capacitor CST_1 may be charged by a voltage between the second node N2 and the second power line PL2.

[0208] Operation and reference of pixel PXL_3 Figure 10 and Figure 11 The operations of the described pixel PXL_2 are substantially the same or similar, and thus the repeated description will not be repeated.

[0209] The gate-source voltage of the first transistor T1 is equal to the voltage between the second node N2 and the second power line PL2, and therefore, the gate-source voltage of the first transistor T1 can be determined only by the data voltage, and the driving current flowing through the first transistor T1 can be accurately controlled regardless of the characteristic variation of the light emitting element LD.

[0210] As reference Figure 12 As described above, the pixel PXL_3 may include a storage capacitor CST_1 connected between the second node N2 and the second power line PL2 .

[0211] The technical scope of the present disclosure can be determined by the technical scope of the appended claims. In one or more exemplary embodiments, all changes or modifications within the meaning and scope of the claims and their equivalents will be interpreted as including the scope of the present disclosure.

Claims

1. A display device comprising: First Power Line; Second power line; Data cable; First scan line; Second scan line; a light emitting element connected between the first power line and a first node, wherein an anode electrode of the light emitting element is connected to the first power line; a first transistor connected between the first node and the second power line and including a gate electrode connected to a second node; a second transistor connected between the data line and the second node and including a gate electrode connected to the first scan line; a fourth transistor connected between the first power line and the first node and including a gate electrode connected to the second scan line; launch control line; a scan driver configured to provide a first scan signal to the first scan line and a second scan signal to the second scan line; an emission driver configured to provide an emission control signal to the emission control line; Data drives; as well as a sensing driver configured to receive a sensing signal corresponding to a threshold voltage of the first transistor through a sensing line, The emission driver provides the emission control signal having a gate-off voltage level to the emission control line in the second period, and the scan driver provides the first scan signal having a first gate-on voltage level to the first scan line and provides the second scan signal having a second gate-on voltage level to the second scan line in the second period. In the second cycle, the data driver provides a reference voltage to the data line, and The sensing driver applies an initialization voltage to the sensing line in a first sub-period of the second period, and receives the sensing signal in a second sub-period of the second period.

2. The display device according to claim 1, wherein A first power voltage applied to the first power line is greater than a second power voltage applied to the second power line.

3. The display device according to claim 1, further comprising: a third transistor connected to the second electrode of the first transistor and the sensing line and including a gate electrode connected to the second scan line, The first electrode of the first transistor is connected to the first node.

4. The display device according to claim 3, further comprising: A fifth transistor is connected between the second electrode of the first transistor and the second power line and includes a gate electrode connected to the emission control line.

5. The display device according to claim 4, wherein At least one of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor includes an oxide semiconductor.

6. The display device according to claim 4, further comprising: A storage capacitor is provided between the first power line and the second node.

7. The display device according to claim 6, wherein: The emission driver provides the emission control signal having a gate-off voltage level to the emission control line in a first cycle. In the first cycle: The scan driver provides the first scan signal having the first gate-on voltage level to the first scan line, and provides the second scan signal having the second gate-on voltage level to the second scan line; as well as The data driver provides data signals to the data lines.

8. The display device according to claim 6, wherein: The emission driver provides the emission control signal having a first gate-off voltage level to the emission control line in a first cycle. In the first cycle: The scan driver provides the first scan signal having a gate-on voltage level to the first scan line, and provides the second scan signal having a second gate-off voltage level to the second scan line; as well as The data driver provides data signals to the data lines.

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