Memory and boost circuit thereof

Abstract

The present invention relates generally to the field of semiconductor memory and in particular to a memory cell including a static random access memory (SRAM) bit cell (100). Leakage current in the read path is reduced by connecting the read access transistor terminal to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetric in size. The memory may include various boost circuits to allow low voltage operation or application of differentiated supply voltages.

Description

[0001] This application is a divisional application of the PCT international invention patent application with application number 201580084597.5, application date September 17, 2015, and invention name “SRAM architecture for reducing leakage”. Technical Field

[0002] The present invention relates generally to the field of electronic hardware memory, and in particular to memory cells including static random access memory (SRAM) bit cells. Background Art

[0003] The performance and reliability of SRAM in low voltage operation poses a challenge to the engineering community. One engineering challenge of low voltage SRAM is mainly due to the analog sense amplifiers that degrade in performance under scaled supply voltages. In addition, existing low voltage SRAM solutions have the following problems: high area cost due to the need for 8 transistors in the bit cell; high design and fabrication cost.

[0004] As new devices and applications have recently emerged in the field of Internet of Things (IoT), the demand for ultra-low voltage designs has increased. Most IoT devices will benefit from low-voltage memory to save battery and also benefit from memory with reduced production and area costs. The International Technology Roadmap for Semiconductors (ITRS Roadmap) points out that a revolutionary replacement for the current 6T SRAM structure is a challenge to be studied.

[0005] Therefore, a high-yield, low-voltage SRAM is needed. Summary of the invention

[0006] In view of the above, an object of the present invention is to solve or at least reduce one or several of the disadvantages discussed above. Generally, the above objects are achieved by the attached independent claims.

[0007] According to a first aspect, the present invention is implemented by a memory connected to a first power supply voltage, the memory comprising: a plurality of memory cells arranged in a matrix having rows and columns; a plurality of word lines, each word line WL comprising a row of the plurality of memory cells;

[0008] a plurality of bit line pairs, wherein each bit line pair comprises: a column of the plurality of memory cells;

[0009] a read bit line RBL arranged to read the memory cell of the bit line pair; and

[0010] A write bit line WBL arranged to write to the memory cell of the bit line pair;

[0011] Each memory cell comprises a static random access memory (SRAM) bit cell, the SRAM bit cell comprising:

[0012] two cross-coupled inverters;

[0013] a single write access transistor arranged to supply data from the WBL comprising the memory cell to the SRAM bit cell, wherein the single write access transistor is arranged to be activated using a write word line WWL signal; and

[0014] a first read access transistor and a second read access transistor arranged for feeding data from the SRAM bit cell, and wherein the second read access transistor is arranged to be activated using a read word line RWL signal, and wherein the first read access transistor is arranged for inverting data stored by the two cross-coupled inverters;

[0015] Therein, the SRAM bit cell is connected to an inverter arranged for connecting the first read access transistor to ground during a read operation on the memory cell and for connecting the first read access transistor to the first supply voltage in other cases.

[0016] By providing a virtual ground for the read transistor in the SRAM bit cell, using an inverter (tail buffer) that connects the first read access transistor to the first supply voltage (VDD) when the bit cell is not involved in a read operation, the bit cell leakage will be greatly reduced. In addition, by using only a single write access transistor, and therefore a single WBL for each bit cell, the area and energy cost of the bit cell can be greatly reduced.

[0017] According to some embodiments, the two cross-coupled inverters are asymmetric in size. Such an asymmetric design facilitates writing operations with low drive strength through a single write access transistor.

[0018] According to some embodiments, each of the plurality of word lines WL is connected to a first decoder and a second decoder,

[0019] wherein the first decoder is arranged to decode a read address and output the RWL signal to select a WL for reading data of the SRAM bit cell included in the memory cell of the WL, whereby the selected WL will supply read data to the read data access transistor of the memory cell of the selected WL; and

[0020] The second decoder is arranged to decode a write address and output the WWL signal to select a WL for writing data to the SRAM bit cell included in the memory cell of the selected WL, whereby the selected WL will be supplied with data to the write access transistor of the memory cell of the selected WL.

[0021] The decoder may be any decoder according to the prior art, but in order to reduce leakage current through the decoder, the first decoder and the second decoder may include a plurality of transistors,

[0022] wherein each transistor is connected to a selection signal arranged to activate and deactivate the transistor; and

[0023] The plurality of transistors are arranged in a tree structure, wherein each branch of the tree structure comprises a single transistor, wherein the tree structure comprises at least two root branches, wherein each branch of the tree structure that is not a root branch has a single parent branch, wherein each leaf branch of the tree structure is arranged to provide a RWL or WWL signal to select a WL for reading or writing data from or to the memory,

[0024] The read address or the write address is used to provide a selection signal to activate transistors along a path between a root branch and a leaf branch among the plurality of transistors so as to select a correct WL based on the read address or the write address, respectively.

[0025] Two properties are observed that are superior to conventional decoders: the capacitive loading of the decoder is significantly reduced, and the number of leakage paths experiences a significant reduction, for example, leakage in the address logic of the decoder is reduced by up to 200 times depending on the address space of the decoder.

[0026] According to some embodiments, the tree structure has a number n of levels, wherein the plurality of transistors arranged in the tree structure are PMOS transistors, wherein each PMOS transistor included in a leaf branch is connected to n parallel-arranged NMOS transistors that are grounded, wherein the read address or the write address is used to provide a selection signal for the n NMOS transistors so that at least one NMOS transistor at the leaf branch of the tree structure that does not represent the correct WL (target WL) will be activated so as to discharge any voltage present at the leaf branch to ground.

[0027] This embodiment adds an extra layer of safety in selecting the correct WL based on the read address or write address, since any remaining charge in the transistor or voltage present due to leakage will be drained through the NMOS transistor.

[0028] According to some embodiments, the plurality of transistors arranged in a tree structure are PMOS transistors, wherein each of the plurality of PMOS transistors is connected to a grounded NMOS transistor, wherein the read address or the write address is used to provide a selection signal for the NMOS transistor so that at least one NMOS transistor along the PMOS transistor route to the leaf branch of the tree structure that does not represent the correct WL will be activated to discharge any voltage present at the leaf branch to ground.

[0029] This embodiment adds an extra layer of safety in selecting the correct WL based on the read address or write address, since any residual voltage in the transistor or voltage present due to leakage will be discharged through the NMOS transistor.

[0030] According to some embodiments, the tree structure has exactly two root branches, wherein each branch in the tree structure that is not a leaf branch has two child branches, wherein the first bit in the read address or the write address is used to activate one of the two root branches, and wherein each subsequent bit in the read address or the write address is used to activate a transistor of one of the two child branches of the parent branch that has been activated by a previous bit in the read address or the write address.

[0031] This binary tree structure facilitates a one-stage decoder because a bit of a read address or a write address can be used directly to activate a transistor at the left branch or the right branch at each level of the decoder's tree structure.

[0032] According to some embodiments, the tree structure has a number n≥2 levels, wherein the tree structure comprises >2 root branches, wherein each branch of the tree structure that is not a leaf branch comprises >2 child branches; and

[0033] wherein the selection signal for each of the n levels in the tree structure is controlled by an additional decoder that receives a dedicated bit for the read address or the write address, wherein the additional decoder that controls the selection signal for each of the n levels in the tree structure is different from the first decoder or the second decoder.

[0034] The use of a two-stage decoder facilitates a larger address space of the decoder while keeping the number of levels of the tree structure low. In other words, pre-decoding of the select signal limits the transistor stacking in the tree-decoder to, for example, 3 levels, which results in a low on-resistance in the selected transistor branches of the tree decoder, i.e. in the selected route through the decoder. This in turn reduces the voltage drop on the word select signal RWL / WWL, since a higher level input voltage is transmitted through the decoder.

[0035] According to some embodiments, the further decoder is a decoder as described above.This means that the pre-decoding of the read / write address is done by a decoder implementing the above tree structure, wherein each branch in the tree structure that is not a root branch has a single parent branch.

[0036] According to some embodiments, a first boosting circuit is used to increase the voltage level of the single write access transistor to a voltage level higher than the level of the first voltage. Such boosting can be performed, for example, by raising the input voltage of a decoder that decodes the write address, thereby causing the voltage of the WLW signal to increase. This facilitates performing write operations using a single WBL from the bit cell.

[0037] According to some embodiments, the second boost circuit is used to increase the voltage level of the second read access transistor to a voltage level higher than the level of the first voltage. This can increase the speed of the read operation. This boost can be performed, for example, by increasing the input voltage of a decoder that decodes the read address, thereby causing the voltage of the WLR signal to increase.

[0038] According to some embodiments, each of the WBLs of the memory is coupled to a further boosting circuit arranged to increase the voltage level of the WBL to a voltage level higher than the level of the first voltage. This facilitates performing write operations using a single WBL from a bit cell.

[0039] According to some embodiments, the further voltage boosting circuit raises the voltage level of the WBL only when a one is written to the bit cell.When a zero is written, the voltage on the WBL is zero.

[0040] According to some embodiments, each of the RBLs of the memory is coupled to a further boosting circuit arranged to increase the voltage level of the RBL to a higher voltage level than the level of the first voltage. This increases the reading speed of the memory.

[0041] According to some embodiments, the first boost circuit, the second boost circuit and at least one of the multiple additional boost circuits include: at least a first charge pump unit and a second charge pump unit, each charge pump unit includes four cross-coupled transistors and two capacitors, each charge pump unit is fed by the power supply voltage, and each charge pump unit further includes an input terminal for receiving a first voltage and an output terminal for transmitting a second voltage higher than the first voltage, wherein each charge pump is arranged to receive a clock signal and a 180 degree phase-shifted version of the clock signal via the two capacitors, wherein the input terminal of the second charge pump is connected to the output terminal of the first charge pump through an inverter controlled by the clock signal.

[0042] The 180 degree phase shifted clock signal is the same as the inverted clock signal.

[0043] Phase shifting can be achieved by using an inverter.

[0044] This design of the voltage boost circuit helps to boost the first voltage to the second voltage within a single clock cycle.

[0045] According to some embodiments, the first power supply voltage is a single power supply voltage of the memory. By adopting a single power supply voltage and using a boost circuit to increase the voltage when necessary, a simplified architecture of the memory can be achieved. In addition, using a very low single power supply voltage, such as 300mV, can contribute to low-voltage operation of the memory.

[0046] However, some or all of the boost circuits may be replaced by a second power supply voltage having a higher voltage than the first power supply voltage. In other words, according to some embodiments,

[0047] - said single write access transistor,

[0048] - the second read access transistor,

[0049] - each of said write bit lines of said memory, and

[0050] - Each of the read bit lines of the memory

[0051] At least one of the first power supply voltages is coupled to a second power supply voltage having a higher voltage than the first power supply voltage.

[0052] Other objects, features and advantages of the present invention will become apparent from the following detailed disclosure and the accompanying drawings.

[0053] Generally, unless explicitly defined herein, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field. Unless explicitly stated otherwise, all references to "a / an / the [element, device, part, means, step, etc.]" are to be openly interpreted as referring to at least one instance of the element, device, part, means, step, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The above and additional objects, features and advantages of the present invention will be better understood through the following illustrative and non-limiting detailed description of embodiments of the present invention with reference to the accompanying drawings, in which the same reference numerals will be used for similar elements, wherein:

[0055] Figure 1 shows a 7T bit cell according to an embodiment of the present invention,

[0056] Figure 2 shows a schematic diagram of a 128kb ULV single-well 7T SRAM,

[0057] Figure 3 A schematic diagram of a three-level NAND-NOR scheme for a read operation on a memory is shown by way of example,

[0058] Figures 4 to 7 Four different embodiments of decoding schemes for decoding a word select signal are shown,

[0059] Figure 8 A schematic diagram showing a two-stage boost circuit capable of providing 2VDD in a single clock cycle is shown.

[0060] Fig. 9 shows that it is possible to provide n V in a single clock cycle DD Schematic diagram of the n-stage boost circuit,

[0061] Fig.10 shows a schematic diagram of a 3-stage boost circuit for DC-DC conversion,

[0062] Fig.11 A block diagram showing the connections between different parts of a chip including a ULV SRAM. DETAILED DESCRIPTION

[0063] Figure 1A 7T bit cell 100 according to an embodiment of the present invention is shown. The 7T bit cell 100 is a random access memory (SRAM) bit cell 100, which is included in a memory cell of a memory for a digital system. The SRAM bit cell 100 includes two cross-coupled inverters I1, I2 and a single write access transistor M1. In this embodiment, the bit cell 100 employs two inverters I1, I2, which are asymmetric in size to facilitate the write procedure and reduce the leakage current through the bit cell 100. The asymmetric design facilitates the operation of writing one through a single write access transistor M1. In other embodiments, the two cross-coupled inverters I1, I2 are symmetric in size. When a new value is written to the bit cell 100, first the single write access transistor M1 is activated and thereby turned on. This is done using a write word line signal WWL. When the single write access transistor M1 has been activated, new data is supplied to the SRAM bit cell 100 from the write bit line WBL.

[0064] It should be noted that the term turning on the transistor does not encompass leakage through the transistor, but is intended to mean that the transistor is active and in an operational mode.

[0065] The SRAM bit cell 100 further includes a first read access transistor M2 and a second read access transistor M3. M2 and M3 are connected in series. When a read operation is performed, the second read access transistor M3 is activated using the read word line signal RWL. Therefore, the second read access transistor M3 is arranged to be turned on using the read word line signal RWL. When the second read access transistor M3 is turned on, the data stored by the two cross-coupled inverters I1, I2 can be converted by the first read access transistor M2 because the gate of M2 is connected to the two cross-coupled inverters I1, I2. If the bit cell 100 contains a zero and WLR is high (WLR>0, in some embodiments, WLR=1), nothing will happen in the read bit line RBL. This means that the bit cell 100 contains a zero. But if the bit cell 100 contains a one, M2 will be activated (i.e., turned on), and if the bit cell 100 is selected by the high WLR, RBL will be discharged through M2 and M3, and it will be known that the bit cell 100 contains a one. Will be combined below Figure 2 The reading procedure is further described.

[0066] exist Figure 1 In the embodiment of FIG. 5 , M1 , M2 , and M3 are NMOS transistors, but for other applications, PMOS transistors or a combination of NMOS and PMOS transistors may be used.

[0067] The bit cell 100 is connected to a further inverter or tail buffer, which is arranged to connect the first read access transistor M2 to ground during a read operation on the memory cell and to connect the first read access transistor M2 to a power supply voltage VDD in other cases. In other words, the tail buffer forms a ground connection to the RBL during reading, while during idle mode, the RBL is connected to the power supply voltage VDD and thus precharges the RBL together with CHG. CHG is a control signal that activates the transistor 102 to precharge the RBL. This can eliminate leakage on the RBL because there is no potential difference during idle mode. Compared to a conventional 8T bit cell with the same footprint, this embodiment can reduce the leakage current of the bit cell 100 by up to 67%. In addition, the leakage path from the RBL is cut off, thereby ensuring that a stable precharge VDD is available on the RBL during slow and long read operations. It should be noted that the tail buffer is shared between the word line bit cells so that all bit cells in a word are connected to the same tail buffer.

[0068] The size of the bit cell 100 may be 0.261 μm 2 (Using standard design rules), this is comparable to an 8T bit cell with push rules. The push rule can reduce the bit cell area of ​​the bit cell 100 to 0.21 μm 2 .

[0069] According to some embodiments, some transistors in bit cell 100 are switched (turned on, conducting, etc.) using a boost signal. For example, according to some embodiments, the voltage level of a single write access transistor M1 is increased by boosting the WLW signal. Figure 1 Alternatively, the single write access transistor is connected to a second supply voltage having a higher voltage than the first supply voltage.

[0070] According to some embodiments, each of the write bit lines WBL of the memory is coupled to a boost circuit (the boost circuit will be further described below). Figure 1 denoted by an asterisk at the write bit line WBL. Alternatively, each of the WBLs of the memory is coupled to a second supply voltage having a higher voltage than the first supply voltage.

[0071] It should be noted that the voltage of WBL only needs to be raised during the operation of writing a one to the bit cell 100. Since there is a voltage drop in the single write access transistor M1 (NMOS) when passing the one to be written, the voltage raising of WBL is advantageous so that there is a voltage across the bit cell that is high enough to be able to write to the bit cell.

[0072] The above operation facilitates connecting only one WBL to each bit cell 100. Conventionally, two write bit lines are connected to each bit cell, which requires a second write access transistor. The total capacitive load of the WBL is reduced by 50% compared to conventional SRAM architectures, and thus the dynamic power is halved. According to some embodiments, during write operations, the bit lines / word lines are boosted to 2VDD to increase the speed and reliability of the write operation. The required boost voltage is used, for example Figure 8 According to other embodiments, a boost circuit including one or more stages, such as that shown in FIG. 9 and capable of providing n VDDs in a single clock cycle, may be used, where n corresponds to the number of stages of the boost circuit. Figures 8 to 10 Embodiments of a voltage boost circuit are further described.

[0073] According to some embodiments, for a memory having 64 WBLs, 66 such boosting circuits may be used, wherein 64 boosting circuits boost the 64 WBLs during a write operation, and the remaining 2 generate boosted WLW and WLR signals. Since the capacitors in the boosting circuits may be implemented using metal-insulator-metal (MIM) capacitors that may be accommodated on a higher metal layer of the chip, the area overhead of boosting may be as small as 2.7%.

[0074] According to some embodiments, the voltage level of the second read access transistor M3 is thus increased by boosting the WLR signal. Figure 1 denoted by an asterisk at the WLR signal. According to other embodiments, the second read access transistor M3 is coupled to a second power supply voltage having a higher voltage than the first power supply voltage. By increasing the voltage level at the second read access transistor M3, the drive strength of M3 is increased, so that the read operation is performed faster. Optionally, the RBL of the memory may also be coupled to a boost circuit or connected to a second power supply voltage having a higher voltage than the first power supply voltage, so that the voltage level of the RBL is increased. This will further increase the speed of reading data from the bit cell 100.

[0075] Figure 2 The architecture of a 128kb ULV SRAM 200 is described. In general, such a memory 200 includes a plurality of memory cells arranged in a matrix having rows and columns. The memory further includes a plurality of word lines, each word line WL including a row of the plurality of memory cells, and a plurality of bit line pairs. Each bit line pair includes: a column of the plurality of memory cells; a read bit line RBL arranged for reading the memory cells of the bit line pair; and a write bit line WBL arranged for writing to the memory cells of the bit line pair.

[0076] Figure 2 The memory 200 in the embodiment implements a read scheme without using a sense amplifier. The memory 200 complies with logic design rules. Figure 2 , each RBL comprises 32 bits, or in other words, each comprises 32 memory cells of the SRAM bit cell 100. Other numbers of bits, such as 16, 64 or 128 bits are also possible. As described above, the tail buffer eliminates the leakage path through M2 and M3 and, in addition to reduced static power, provides correct read operation even at very slow clock frequencies. Advantageously, the tail buffer is activated at a stage before activating M3. When a zero is read from the bit cell 100, the read propagation delay is 0. When a one is read, the RBL is discharged through M2 and M3, while all other RBLs in other RBL blocks remain at logic 1. The read path consists of multiple read RBLs (pre-charged with CHG) shared by the 32 words to achieve high read speed and lower dynamic power. The RBL discharge triggers the read multiplexer and the final value is transmitted through the read multiplexer as shown in FIG. Figure 2 The NAND-NOR chain 202, 204 propagates to the output terminal.

[0077] According to some embodiments, the first NAND 206 in the chain can be a NAND with a large PMOS transistor for fast pull-up. This means that the first NAND 206 in the chain can be adjusted to switch already when the corresponding RBL has been discharged by a small percentage (e.g., 10% or 15%). This in turn will greatly speed up reading. Measurements of this memory 200 verified a 150MHz read speed at 360mV.

[0078] Figure 3 A NAND-NOR scheme for three-level readout is described. Depending on the size of the memory, more or fewer levels may be required. For example, in Figure 2 In , a six-level readout scheme is adopted. Figure 3 In the example, the bit at RBL-Pos-0c is read. Figure 3 In the top portion of , the bit cell is not discharged because it reads a zero, as described above. This means that all RBL positions in the RBL remain at logic one. Figure 3 In the three-level readout scheme of , this propagates through the NAND-NOR chain and ends up at the output as a zero. However, in the bottom section, the bit cell is discharged and therefore the output from the read scheme will be zero.

[0079] Figures 4 to 7An address decoder according to an embodiment of the present invention is described. The address decoder 400, 500, 600, 700 has a repetitive architecture, wherein each level thereof is closer to a word select signal. The repetitive architecture and independence of the power wiring make it highly reconfigurable and tool-friendly. The decoder includes a plurality of transistors 402, 502, 602, 702 arranged in a tree structure. Each transistor is connected to a selection signal, wherein the selection signal is arranged to turn on and off (activate / deactivate, conduct / non-conduct, etc.) the transistor 402, 502, 602, 702 to which it is connected. In this architecture, each branch of the tree structure includes a single transistor. In addition, each branch in the tree structure that is not a root branch has a single parent branch. Compared with a conventional decoder, this can reduce leakage current by more than 5 orders of magnitude, because the possible leakage paths through the decoder between the power supply voltage (VDD) and the ground are greatly reduced.

[0080] For the memory described in this article, Figures 4 to 7 The decoder in can be used to decode the read address and output the RWL signal, or to decode the write address and output the WWL signal. The read address or the write address is used to provide a selection signal to activate the transistors along the path between the root branch and the leaf branch among the plurality of transistors so as to select the correct WL based on the read address or the write address, respectively. The selection of the conduction path through the tree structure is performed within one clock cycle because the selection signals on the transistors 402, 502, 602, 702 switch the selected transistors simultaneously, making the decoder inherently fault-free.

[0081] Figure 4 The decoder 400 in is a 3-8 decoder. The address space of the decoder is therefore 8 bits. The decoder comprises a plurality of transistors 402 arranged in a tree structure. Each transistor is connected to a selection / non-selection signal 404 (S0, S1, S2, S0N ...), which is arranged to switch on and off (activate / deactivate, conduct / non-conduct, etc.) the transistor 402 to which it is connected. Therefore, in this case, there are six selection signals, 3 selection signals + 3 inverted selection signals, all of which are derived from the bits of the read / write address.

[0082] In this architecture, each branch of the tree structure comprises a single transistor (in this case a PMOS transistor, but as will be explained below, NMOS transistors may also be used). Furthermore, each branch in the tree structure that is not the root branch has a single parent branch.

[0083] Each leaf branch of the decoder 400 is arranged to provide a RWL or WWL signal A0 to A7 (depending on whether the decoder is used to read or write in the memory) to select a word line for reading or writing data from or to the memory. In this embodiment, the input of the decoder is the supply voltage VDD. According to other embodiments, the input of the decoder is a boosted voltage received from a boost circuit. Different embodiments of possible boost circuits are described below. The boosted input voltage will result in a boosted RWL / WWL signal.

[0084] The tree structure of decoder 400 is a binary tree structure, because the tree structure just has two root branches, wherein, each branch that is not a leaf branch in the tree structure has two sub-branches.For this embodiment, the bit in the read address or write address can be directly used as selection signal 404, because for each level or branch in the tree structure, there are only two sub-branches for selection.Therefore, for example, the first bit with value zero in the read address or write address will make the transistor of the left root branch activated, and the bit with value one will make the transistor in the right root branch activated.In a similar manner, each subsequent bit in the read address or write address can be used to activate the transistor of one of the two sub-branches of the parent branch that has been activated by the previous bit in the read address or write address.In this embodiment, the most significant bit (MSB) in the read address or write address is used to select among the two root branches, and the least significant bit (LSB) is used to select among the two leaf branches, and the bit between them is used to select in the level between the root level and the leaf level of the tree structure. However, the opposite situation may also be true, ie, the MSB is used for selection at the leaf level, while the LSB is used for selection at the root level of the tree structure.

[0085] Figure 4 The decoder of FIG. 1 includes three levels of PMOS transistors 402, which results in low on-resistance in selected PMOS branches while reducing voltage leakage due to transistor stacking. The PMOS transistor in each leaf branch is associated or connected to three (the same number of levels in the tree structure) parallel-arranged NMOS transistors 406 connected to ground. Figure 4 As can be seen in FIG. 4 , the NMOS transistor 406 is connected to the same selection signal as the PMOS transistor, i.e., the read address or the write address is used to provide the selection signal for the NMOS transistor 406, so at least one NMOS transistor at the leaf branch of the tree structure that does not represent the correct word WL will be activated, so that any voltage present at the leaf branch (due to leakage or other reasons) will be discharged to ground. In other words, the unselected leaf branches will be discharged to ground. In other words, these NMOS short the unselected WWL / RWL to ground.

[0086] Figure 5The architecture of the decoder 500 in Figure 4 The architecture is similar. Decoder 500 is developed to pass the input supply voltage VDD to the selected WWL / RWL. In some embodiments, the input voltage is a boosted voltage, as will be described below. However, in Figure 5 In the decoder, the tree structure includes 8 root branches. In addition, each root branch or transistor 502 in the root branch is connected to 16 sub-branches (transistors). In addition, the third level of the tree structure includes 16 branches connected to a single parent branch. Therefore, this tree structure implements an 8×16×16 decoder 500, thereby providing a 2k address space. In other words, the tree structure has a number n≥2 levels, wherein the tree structure includes>2 root branches, wherein each branch that is not a leaf branch in the tree structure includes>2 sub-branches. For this reason, the decoder 500 is a two-stage decoder, wherein the second stage uses the selection signal 504 provided by the first stage to activate the correct route of the tree structure through the PMOS transistor. The first stage includes another decoder, wherein the selection signal of each level in the n (three in this case) levels in the tree structure is controlled by another decoder that receives a dedicated bit of a read address or a write address. This other decoder can be a conventional decoder known in the prior art, or they can be a decoder as described herein, that is, a decoder with a repeated tree architecture, wherein each branch that is not a root branch in the tree structure has a single parent branch. A mixture of such decoders may also be possible. For example, a decoder for decoding the selection signal C0:7 for the first level in the decoder 500 may be similar to Figure 4 The decoder for the second level providing the selection signal B0:15 for this level can be a conventional decoder or a decoder such as Figure 4 A decoder as described in but with an additional level of decoder for providing a 16-bit address space. This decoder may also be Figure 5 A decoder similar to the decoder in , having, for example, a 4×2×2 architecture.

[0087] exist Figure 5 In the decoder 500 of FIG. 5 , each leaf branch is connected to three NMOS transistors 506 arranged in parallel, which discharge the PMOS transistors of the unselected leaf branches to ground, as described above in conjunction with Figure 4 However, this discharge effect can be achieved in different ways, for example, as shown in FIG. Figure 6In this architecture, each of the plurality of PMOS transistors 602 is connected to a grounded NMOS transistor. The select signal for the NMOS transistor is the same as the select signal for the parent PMOS transistor. In this way, at least one NMOS transistor that does not represent the correct WL along the PMOS transistor route to the leaf branch of the tree structure will be activated to discharge any voltage present in the transistor at the leaf branch of the tree structure to ground.

[0088] like Figures 4 to 6 As described in, it may be advantageous to use a PMOS transistor to select the correct WL because, unlike an NMOS transistor, a PMOS transistor is better at passing an elevated voltage. This is an advantage in low-power applications because, without using an elevated voltage at the input of the transistor (the gate of the PMOS), the elevated voltage may be passed through the source-drain of the PMOS transistor due to the gate of the PMOS in the on-mode being connected to the ground. Therefore, even if the voltage of the selection signal is as low as 300mV, the decoder can pass 600mV to the WLW / RWL signal with negligible loss. Using a PMOS transistor like this will produce a hot WL selection signal. However, in some applications, a cold output from a decoder may be desirable. In these cases, the tree structure should include an NMOS transistor at the branch, and a PMOS transistor should be used to further ensure that the correct output from the decoder is achieved. Figure 7 Such an architecture is shown in FIG. 7 , where decoder 700 corresponds to Figure 6 Decoder 600. However, similarly, Figure 4 and Figure 5 The decoders 400 and 500 can be Figure 7 A similar approach as described in is rearranged to provide cold output.

[0089] Figure 8A boost circuit 800 is described in which the cross-connected stages are similar to the charge pump (CP) in "Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes" by Ming-Dou Ker et al. (IEEE Journal of Solid-State Circuits, Vol. 41, No. 5, pp. 1100-1107, May 200). However, unlike the charge pump developed by Ming-Dou Ker or other available CP architectures, the current boost unit provides 2×VDD in a single clock cycle. The boost unit includes a first CP unit 802 and a second CP unit 804. Each CP unit 802, 804 includes four cross-coupled transistors and two capacitors. Each CP unit also includes an input terminal and an output terminal. The four cross-coupled transistors in each CP unit include 2 NMOS transistors connected to the power supply voltage VDD and two PMOS transistors connected to the NMOS transistors and connected to the output terminal of the CP unit. Each charge pump unit is arranged to receive a clock signal IN and a 180 degree phase shifted version IN of the clock signal via the two capacitors. As described above, each CP unit is fed by a supply voltage VDD (or a first voltage) via an NMOS transistor. Due to the coupling between the NMOS transistor, the PMOS transistor and the capacitors 806 to 812 of each charge pump, the output of each CP unit 802, 804 will pass a second voltage higher than the first voltage. The CP units 802, 804 are connected in parallel, which means that the input of the second charge pump is connected to the output of the first charge pump via an inverter 814 controlled by the clock signal.

[0090] This design helps to output 2VDD (OUTPUT) in a single clock cycle. 升压 ). In the context of the memory for digital systems described herein, this means that a processor connected to the memory does not need to wait longer than required for a read / write operation, since the boosting of the voltage for read / write can be performed in a single clock cycle.

[0091] The capacitors 806 to 812 of the boost circuit 800 may have different capacitance values ​​(eg, Figure 8In the boost circuit 800, the capacitor 808 connected to the first CP unit 802 that provides charge to the output load has a full capacitance C. BST The actual capacitance value depends on the application in which the boost circuit should be used. For example, C may be selected with respect to the capacitive load on the write bit line WBL signal in which the voltage should be boosted. BST .

[0092] Thus, the other capacitors 806, 810, 812 may have lower capacitance to reduce cost. The capacitor 810 connected to the output of the first CP unit 802 may have a larger capacitance because it receives a boosted (higher) voltage.

[0093] Figure 8 The boost circuit in is a two-stage circuit that delivers 2VDD. However, the architecture of the boost circuit can be expanded to include any number of stages depending on the application. Fig. 9 FIG. 9 shows a boost circuit 900 using X number of stages. Therefore, the output OUT of this boost circuit is X times VDD. In addition to the increase in the number of stages, Fig. 9 The boost circuit 900 is similar to the boost circuit 800 of FIG. 800 .

[0094] The inventive architecture of the boost circuit explained above can also be used in a DC-DC converter. Fig.10 Such a boost circuit 1000 is shown in FIG. Fig.10 The boost circuit in includes three stages, but any number of stages, such as 2, 4, 5 or 10, may be used as well.

[0095] Fig.11 By way of example, the architecture of a memory (e.g., a memory embedded in an integrated circuit) connected to a processor unit PU 1100 for a digital system is shown. PU 1100 provides signals such as a read address 1102, a write address 1104, etc. to the memory. The read address 1102 and the write address 1104 are fed to a two-stage decoder, for example, as described above in conjunction with Figure 5The decoder explained above. The first stage WAD / RAD 1106, 1108 represents the first stage of the decoder, which provides selection signals to transistors in the tree structure of the decoder. The processor 1100 further provides read / write enable signals 1114, 1116, which enable boost units 1118, 1120 to provide a boosted VDD to the root branch of the second stage 1110, 1112 of the decoder. The boost units 1118, 1120 may be, for example, as shown in conjunction with Figure 8 and Fig. 9 As described above. By raising the input voltage of the second stage of the decoders 1110, 1112, the boosted WLR, WLW signals 1122, 1124 are achieved. This results in higher read / write speeds, and the boosted WLW signal 1124 also helps as described above in conjunction with Figure 1 The single write access transistor design of the bit cell is described. It should be noted that, according to some embodiments, the input voltage of the second stage 1110 of the decoder for decoding the WLR signal is not raised, which results in the WLR signal not being raised. It should also be noted that, according to some embodiments, the voltage input of the second stage 1110, 1112 of the decoder is the result of a second power supply voltage having a higher voltage than the first power supply voltage VDD, for example, the second power supply voltage may be 2VDD.

[0096] The boosted WLR / WLW 1122, 1124 are received by a memory array 1126. The memory array includes a plurality of memory cells arranged in a matrix having rows and columns. The memory array 1126 further includes a plurality of word lines, each word line WL including a row of the plurality of memory cells. The memory array further includes a plurality of bit line pairs, wherein each bit line pair includes: a column of the plurality of memory cells; a read bit line RBL arranged to read the memory cells of the bit line pair; and a write bit line WBL arranged to write to the memory cells of the bit line pair. Each memory cell in the memory array includes as described above in conjunction with Figure 1 A static random access memory (SRAM) bit cell is described.

[0097] exist Fig.11 In the embodiment, only a single write bit line WBL 1130 is shown, and the read bit line RBL has been omitted for ease of description. The WBL of the memory is coupled to an additional boost circuit 1128 so that the voltage level of the WBL is increased. This will increase the write speed to the memory. According to some embodiments, the WBL 1130 is instead coupled to a second power supply voltage having a higher voltage than the first power supply voltage.

[0098] Since WWL and WBL are boosted to 2×VDD during a write operation, the above operation can use a single write BL (WBL) to implement a write operation to the memory.

[0099] In summary, the disclosed embodiments relate generally to the field of electronic hardware memory, and in particular to low voltage SRAM.

Claims

1. A memory connected to a first power supply voltage (VDD), the memory comprising: a plurality of memory cells arranged in a matrix having rows and columns; a plurality of word lines, each word line comprising a row of the plurality of memory cells; A plurality of bit line pairs, wherein each bit line pair comprises: a column of the plurality of memory cells; a first bit line arranged to read or write the memory cell of the bit line pair; a second bit line arranged to read or write the memory cell of the bit line pair; Each memory cell comprises a static random access memory (SRAM) bit cell (100), the SRAM bit cell comprising: two cross-coupled inverters (I1, I2); a first access transistor (M1) connected to the first bit line; and a second access transistor (M2) connected to a second bit line; and At least one boost circuit, the at least one boost circuit comprising: At least a first charge pump unit and a second charge pump unit, each charge pump unit includes four cross-coupled transistors and two capacitors, each charge pump unit is fed by the first power supply voltage (VDD), each charge pump unit further includes an input terminal for receiving a first voltage and an output terminal for delivering a second voltage higher than the first voltage, wherein each charge pump unit is arranged to receive a clock signal and a phase-shifted version of the clock signal via the two capacitors, wherein the input terminal of the second charge pump unit is connected to the output terminal of the first charge pump unit through an inverter controlled by the clock signal.

2. The memory as claimed in claim 1, wherein: The voltage boost circuit is configured to provide a second voltage of the second charge pump unit in a single clock cycle, the second voltage of the second charge pump unit being at least twice the first voltage of the first charge pump unit.

3. The memory according to claim 1, wherein: The phase shifted version of the clock signal is 180 degrees phase shifted.

4. The memory as claimed in claim 1, wherein: The first charge pump unit and the second charge pump unit are connected in parallel.

5. The memory as claimed in claim 1, wherein: The at least one boosting circuit is selected from the following boosting circuits: a first boosting circuit for increasing the voltage level of the first access transistor to a voltage level higher than the level of the first voltage, a second boosting circuit for increasing the voltage level of the second access transistor to a voltage level higher than the level of the first voltage, and an additional boosting circuit arranged to increase the voltage level of the first bit line or the second bit line to a voltage higher than the level of the first voltage.

6. The memory of claim 1 , further comprising a third charge pump unit, the third charge pump unit comprising four cross-coupled transistors and two capacitors, the third charge pump unit being fed by a power supply voltage, the third charge pump unit further comprising an input terminal for receiving a first voltage and an output terminal for delivering a second voltage higher than the first voltage, wherein, The third charge pump unit is arranged for receiving the clock signal and a phase shifted version of the clock signal via the two capacitors, wherein an input of the third charge pump unit is connected to an output of the second charge pump unit via a further inverter controlled by the clock signal.

7. The memory as claimed in claim 6, wherein: The voltage boost circuit is configured to provide a second voltage of the third charge pump unit in a single clock cycle, the second voltage of the third charge pump unit being at least three times the first voltage of the first charge pump unit.

8. A memory as claimed in claim 1, comprising X charge pump cells, the X charge pump cells comprising four cross-coupled transistors and two capacitors, each charge pump cell being fed by a supply voltage, each charge pump cell further comprising an input for receiving a first voltage and an output for delivering a second voltage higher than the first voltage, each charge pump cell being arranged for receiving a clock signal and a phase-shifted version of the clock signal via the two capacitors, wherein The input terminal of the Xth charge pump unit is connected to the output terminal of the X-1th charge pump unit through an inverter controlled by the clock signal.

9. A boost circuit connected to a first power supply voltage (VDD), the boost circuit comprising: At least a first charge pump unit and a second charge pump unit, each charge pump unit includes four cross-coupled transistors and two capacitors, each charge pump unit is fed by a first power supply voltage (VDD), each charge pump unit further includes an input terminal for receiving a first voltage and an output terminal for delivering a second voltage higher than the first voltage, wherein each charge pump unit is arranged to receive a clock signal and a phase-shifted version of the clock signal via the two capacitors, wherein the input terminal of the second charge pump unit is connected to the output terminal of the first charge pump unit through an inverter controlled by the clock signal.

10. The voltage boost circuit according to claim 9, wherein: The voltage boost circuit is configured to provide a second voltage of the second charge pump unit in a single clock cycle, the second voltage of the second charge pump unit being at least twice the first voltage of the first charge pump unit.

11. The voltage boost circuit according to claim 9, wherein: The phase shifted version of the clock signal is 180 degrees phase shifted.

12. The voltage boost circuit according to claim 9, wherein: The first charge pump and the second charge pump are at least partially connected in parallel.

13. The boost circuit of claim 9 , further comprising a third charge pump unit, the third charge pump unit comprising four cross-coupled transistors and two capacitors, the third charge pump unit being fed by the supply voltage, the third charge pump unit further comprising an input terminal for receiving a first voltage and an output terminal for delivering a second voltage higher than the first voltage, the third charge pump unit being arranged to receive a clock signal and a phase-shifted version of the clock signal via the two capacitors, wherein An input terminal of the third charge pump unit is connected to an output terminal of the second charge pump through another inverter controlled by the clock signal.

14. The voltage boosting circuit according to claim 13, wherein: The voltage boost circuit is configured to provide a second voltage of the third charge pump within a single clock cycle, the second voltage of the third charge pump being at least three times the first voltage of the first charge pump.

15. The voltage boost circuit of claim 9, comprising X charge pump cells, the X charge pump cells comprising four cross-coupled transistors and two capacitors, each charge pump cell being fed by the supply voltage, each charge pump cell further comprising an input terminal for receiving a first voltage and an output terminal for delivering a second voltage higher than the first voltage, each charge pump cell being arranged for receiving a clock signal and a phase-shifted version of the clock signal via the two capacitors, wherein The input terminal of the Xth charge pump unit is connected to the output terminal of the X-1th charge pump unit through an inverter controlled by the clock signal.

16. The voltage boost circuit according to claim 15, wherein: The voltage boost circuit is configured to provide a second voltage of an Xth charge pump in a single clock cycle, wherein the second voltage of the Xth charge pump is at least X times the first voltage of the first charge pump.

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