Termination for trench field plate power mosfet

Abstract

A semiconductor device includes a substrate having first and second opposed major surfaces, an active region, and a termination region. Insulative trenches extend from the first major surface toward the second major surface, each of the insulative trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both the active region and the termination region and the gate electrode is absent in the termination region. A body region of a first conductivity type extends laterally between pairs of the insulative trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulative trenches at the termination region to create a segment of the first conductivity type between the first and second spacer regions, the segment isolated from the body region.

Description

Technical Field

[0001] This invention generally relates to power MOSFETs. More specifically, this invention relates to semiconductor device designs for power MOSFETs used to improve breakdown voltage characteristics. Background Technology

[0002] Compared to FETs with shorter conductive channels, vertical field-effect transistors (FETs) are suitable for high-voltage applications due to their relatively high breakdown voltage. Trench field-plate power metal-oxide-semiconductor FETs (MOSFETs) are a type of vertical FET that typically employs a reduced surface field (RESURF) effect under the influence of a field plate (shielding electrode) inside the gate trench. RESURF can achieve lower on-resistance (Ron). DS(on) While maintaining a high breakdown voltage (BV), the RESURF effect can achieve a BV-R... DS(on) While improvements are achieved in terms of trade-offs, the sensitivity to changes in doping and / or size is significantly increased. Furthermore, the termination structure of trench field-plate power MOSFET devices is particularly important because improperly designed terminations can lead to lower breakdown voltages, thus forcing the MOSFET device to be improperly designed and failing to achieve the ideal BV-R. DS(on) Compromise. Summary of the Invention

[0003] The appended claims define all aspects of this disclosure.

[0004] In a first aspect, a semiconductor device is provided, comprising: a substrate having opposing first and second main surfaces, an active region, and a termination region; insulating trenches extending from the first main surface toward the second main surface, each insulating trench including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator, wherein the conductive field plate extends longitudinally in both the active region and the termination region and the gate electrode is absent in the termination region; a body region of a first conductivity type extending laterally between the pairs of insulating trenches; and a first and second spacing regions of a second conductivity type extending laterally in the termination region between the pairs of insulating trenches to create a segment of the first conductivity type between the first and second spacing regions, the segment being isolated from the body region.

[0005] According to one or more embodiments, the segment is a first segment, and the semiconductor device further includes a third spacer region of the second conductivity type extending laterally between the pairs of insulating trenches in the terminal region, the third spacer region being spaced apart from the second spacer region to create a second segment of the first conductivity type between the second spacer region and the third spacer region, the second segment being isolated from the first segment and isolated from the body region.

[0006] According to one or more embodiments, the first segment has a first segment width parallel to the longitudinal dimension of the insulating trench; and the second segment has a second segment width parallel to the longitudinal dimension of the insulating trench, the second segment width being different from the first segment width.

[0007] According to one or more embodiments, the terminal region surrounds the active region, and the semiconductor device further includes an insulating terminal trench surrounding the terminal region, wherein a conductive shield is present in the terminal trench, and a third segment of the first conductivity type is present between the third spacing region and the insulating terminal trench, the third segment being isolated from the first segment and the second segment and isolated from the body region.

[0008] According to one or more embodiments, the first spacing region presents a first spacing width parallel to the longitudinal dimension of the insulating trench; and the second spacing region presents a second spacing parallel to the longitudinal dimension of the insulating trench, the second spacing width being different from the first spacing width.

[0009] According to one or more embodiments, each of the insulating trenches includes a first end portion and a second end portion, and an intermediate portion extending longitudinally between the first end portion and the second end portion, wherein the first spacer region and the second spacer region extend laterally between the first end portions of the pair of insulating trenches; and the semiconductor device further includes a third spacer region and a fourth spacer region of the second conductivity type, the third spacer region and the fourth spacer region extending laterally between the second end portions of the pair of insulating trenches to create an additional segment of the first conductivity type between the third spacer region and the fourth spacer region, the additional segment being isolated from the body region.

[0010] According to one or more embodiments, the distal end of the gate electrode in each of the insulating trenches defines the outer periphery of the active region, wherein at least one of the first spacer region and the second spacer region and the segment is adjacent to the gate electrode at the outer periphery of the active region and separated from the gate electrode by an insulator.

[0011] According to one or more embodiments, the first interval region and the second interval region, as well as at least one of the segments, are adjacent to the field plate in the terminal region and separated from the field plate by an insulator.

[0012] According to one or more embodiments, the body region and the segment of the first conductivity type are configured to be formed simultaneously in the same implantation process.

[0013] According to one or more embodiments, the semiconductor device further includes:

[0014] The source region above the body region at the first main surface between the trenches;

[0015] The drift region of the second conductivity type below the main body region; and

[0016] The drain region of the second conductivity type below the drift region, such that the source region, the body region, the drift region and the drain region extend from the first main surface toward the second main surface in the order stated therein, wherein the gate electrode is adjacent to the body region in the active region and separated from the body region by an insulator, and the field plate is adjacent to the drift region and separated from the drift region by the insulator.

[0017] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising: forming a drain region with a doped semiconductor substrate; growing an epitaxial layer on the drain region such that an outer surface of the epitaxial layer defines a first main surface of the semiconductor device and a second main surface of the semiconductor device is opposite to the first main surface; forming insulating trenches in the epitaxial layer, each of the insulating trenches being arranged parallel to each other and extending from the first main surface toward the second main surface; forming a conductive field plate in each of the insulating trenches, the conductive field plate being separated from the epitaxial layer by an insulator; and forming a square on the conductive field plate in each of the insulating trenches. A gate electrode is formed, the gate electrode being separated from the field plate by a gate-field plate insulator, wherein the semiconductor device has an active region and a terminal region surrounding the active region, the gate electrode being absent in the terminal region and the conductive field plate extending longitudinally in both the active region and the terminal region; a body region of a first conductivity type is formed extending laterally between the pairs of insulating trenches; and a segment of the first conductivity type is generated at the terminal region, the segment being generated between a first spacer region and a second spacer region of a second conductivity type extending laterally between the pairs of insulating trenches, the segment being isolated from the body region.

[0018] According to one or more embodiments, the formation of the main body region and the generation of the segment are performed simultaneously using the same injection process.

[0019] According to one or more embodiments, the segment is a first segment, and generating the segment includes generating a second segment of the first conductivity type, the second segment being generated between a second spacing region and a third spacing region of the second conductivity type extending laterally between the pairs of insulating trenches in the terminal region, the second segment being isolated from the first segment and the body region.

[0020] According to one or more embodiments, the method further includes forming an insulating terminal trench surrounding the terminal region and forming a conductive shield in the terminal trench; and generating the segment includes generating a third segment of the first conductivity type between the third interval region and the insulating terminal trench, the third segment being isolated from the first segment and the second segment and isolated from the body region.

[0021] According to one or more embodiments, forming the insulating trench produces an insulating trench including a first end portion and a second end portion and an intermediate portion extending longitudinally between the first end portion and the second end portion, wherein the first spacing region and the second spacing region extend laterally between the first end portions of the pair of insulating trenches; and producing the segment includes producing an additional segment of the first conductivity type between a third spacing region and a fourth spacing region of the second conductivity type extending laterally between the second end portions of the pair of insulating trenches, the additional segment being isolated from the body region.

[0022] According to one or more embodiments, generating the segment includes positioning the first interval region and the second interval region, as well as at least one of the segments, adjacent to the field plate in the terminal region and separated from the field plate by an insulator.

[0023] According to one or more embodiments, the distal end of the gate electrode in each of the insulating trenches defines the outer periphery of the active region, and generating the segment includes positioning at least one of the first spacer region and the second spacer region and the segment adjacent to the gate electrode at the outer periphery of the active region and separated from the gate electrode by an insulator.

[0024] In a third aspect, a semiconductor device is provided, comprising: a substrate having opposing first and second main surfaces, an active region, and a terminal region surrounding the active region; insulating trenches extending from the first main surface toward the second main surface, each insulating trench including a first terminal portion and a second terminal portion and a longitudinally extending intermediate portion between the first terminal portion and the second terminal portion, each insulating trench including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator, wherein the conductive field plate extends longitudinally in both the active region and the terminal region and the gate electrode is absent in the terminal region; and a body region of a first conductivity type, the body region being in the insulating trench... The insulating trenches extend laterally between pairs of insulating trenches; a first spacer region and a second spacer region of a second conductivity type, the first spacer region and the second spacer region extending laterally between the pairs of insulating trenches at the first end portion to create a first segment of the first conductivity type between the first spacer region and the second spacer region, the first segment being isolated from the body region; and a third spacer region and a fourth spacer region of the second conductivity type, the third spacer region and the fourth spacer region extending laterally between the pairs of insulating trenches at the second portion to create an additional segment of the first conductivity type between the third spacer region and the fourth spacer region, the additional segment being isolated from the body region, wherein the body region, the first segment and the additional segment are configured to be formed simultaneously in the same injection process.

[0025] According to one or more embodiments, the distal end of the gate electrode in each of the insulating trenches defines the outer periphery of the active region;

[0026] At least one of the first spacer region, the second spacer region, and the first segment is located at the first end portion adjacent to the gate electrode at the outer periphery of the active region and separated from the gate electrode by an insulator; and

[0027] At least one of the third and fourth spacer regions and the second segment is located at the second end portion adjacent to the gate electrode at the outer periphery of the active region and separated from the gate electrode by an insulator.

[0028] According to one or more embodiments, the semiconductor device further includes: a fifth spacer region of the second conductivity type, the fifth spacer region extending laterally between the pairs of insulating trenches at the first end portion of the terminal region, the fifth spacer region being spaced apart from the second spacer region to create a third segment of the first conductivity type between the second spacer region and the fifth spacer region, the third segment being isolated from the body region, wherein at least one of the fifth spacer region and the third segment is adjacent to the field plate in the terminal region and separated from the field plate by an insulator; and a sixth spacer region of the second conductivity type, the sixth spacer region extending laterally between the pairs of insulating trenches at the second end portion of the terminal region, the sixth spacer region being spaced apart from the fourth spacer region to create a fourth segment of the first conductivity type between the fourth spacer region and the sixth spacer region, the fourth segment being isolated from the body region, wherein at least one of the sixth spacer region and the fourth segment is adjacent to the field plate in the terminal region and separated from the field plate by an insulator. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate various embodiments and explain all the various principles and advantages of the invention. Similar reference numerals throughout the drawings refer to the same or functionally similar elements. The drawings are not necessarily drawn to scale. The drawings, together with the detailed description below, are incorporated into and form a part of this specification.

[0030] Figure 1 A plan view of a prior art trench power MOSFET is shown;

[0031] Figure 2 It shows along Figure 1 A cross-sectional view of a prior art trench power MOSFET taken from section line 2-2;

[0032] Figure 3 It shows along Figure 1 A cross-sectional view of a prior art trench power MOSFET taken from section line 3-3;

[0033] Figure 4 A partial plan view of a prior art trench power MOSFET is shown;

[0034] Figure 5 A plan view of a trench power MOSFET according to an embodiment is shown;

[0035] Figure 6 It shows along Figure 5 A cross-sectional view of the trench power MOSFET taken from section line 6-6';

[0036] Figure 7 The section voltage and Figure 5 A graphical view of the simulation results relating the drain voltages of a trench power MOSFET;

[0037] Figure 8 A cross-sectional view of a trench power MOSFET according to another embodiment is shown;

[0038] Figure 9 A flowchart representation of a method for manufacturing a semiconductor device according to another embodiment is shown;

[0039] Figure 10 It shows Figure 5 Another plan view of the trench power MOSFET to illustrate potential problems at the corner region of the trench power MOSFET;

[0040] Figure 11 A partial plan view of a trench power MOSFET at a corner region according to another embodiment is shown;

[0041] Figure 12 A partial plan view of a trench power MOSFET at the corner region according to another embodiment is shown; and

[0042] Figure 13 A plan view of a trench power MOSFET according to yet another embodiment is shown. Detailed Implementation

[0043] In summary, this disclosure relates to semiconductor devices with improved breakdown voltage characteristics and methods for manufacturing such semiconductor devices. Specifically, embodiments relate to trench fieldplate power metal-oxide-semiconductor field-effect transistors (MOSFETs) having a set of floating body sections formed between device trenches of the MOSFET. The floating body sections separate or otherwise isolate the active body region of the semiconductor device from the terminal region of the semiconductor device. Additionally, the floating body sections are self-biased to an appropriate positive voltage. Therefore, the electric field at the three-phase point region of the terminal region can be effectively suppressed, preventing breakdown voltage roll-off at the terminal region. In some embodiments, the floating body sections can be formed using the same body implantation / diffusion process as the active body region of the device. This method avoids the need for additional mask / process steps to form the floating body sections, thereby improving manufacturing efficiency and saving costs.

[0044] This disclosure is provided to further explain at least one embodiment of the invention by way of implementation. This disclosure is also provided to enhance the understanding and appreciation of the inventive principles and advantages of this disclosure, and not to limit the invention in any way. The invention is defined only by the appended claims, including any amendments made during the pending period of this application and all equivalents of those claims.

[0045] It should be understood that the use of terms such as first and second, top and bottom (if applicable) is solely for distinguishing entities or actions and does not necessarily require or imply any actual such relationship or order between such entities or actions. Furthermore, various shading and / or shading lines may be used to illustrate a portion of the drawing to distinguish different elements. These different elements can be produced using current and future microfabrication technologies. Therefore, although different shading and / or shading lines are used in the illustration, the different elements within the structural layer can be formed from the same material.

[0046] refer to Figures 1 to 3 , Figure 1 A plan view of a prior art trench power MOSFET 20 is shown. Figure 2 It shows along Figure 1 The cross-sectional view of the prior art trench power MOSFET 20, taken from section line 2-2, is shown below. Figure 3 It shows along Figure 1 The cross-sectional view of a prior art trench power MOSFET 20 taken by section line 3-3 is shown. In this prior art example, the MOSFET 20 includes a substrate 22 having opposing first main surfaces 24 and second main surfaces 26, an active region 28 (e.g., typically indicated by a dashed box), and a termination region 30 surrounding the active region 28 (e.g., the region outside the dashed box).

[0047] Parallel insulating trenches 32 extend from the first main surface 24 toward the second main surface 26. Each of the trenches 32 includes a conductive field plate 34 (e.g., a first polysilicon layer) and a gate electrode 36 (e.g., a second polysilicon layer) overlying the shielding plate 34, wherein the gate electrode 36 is connected to a gate-field plate insulator 38 (see [link to relevant documentation]). Figure 2 The field plate 34 is separated from the field plate 34. The field plate 34, which may also be referred to herein as the shielding plate 34, extends longitudinally in each trench 32 of the active region 28 and the termination region 30. However, the gate electrode 36 extends longitudinally in each trench 32 of the active region 28, but is absent from the trench 32 of the termination region 30. Therefore, Figure 2The cross-sectional view shows a trench 32 in the active region 28, which is lined with an insulator 40 (e.g., a shielding oxide) and both a shielding plate 34 and a gate electrode 36 separated by a gate-field plate insulator 38. Conversely, Figure 3 The cross-sectional view shows a trench 32 in the terminal region 30, which is lined with an insulator 40 but only with a shielding plate 34.

[0048] An insulating termination trench ring 42 surrounds the termination region 30. The termination trench 42 is also lined with an insulator 40, and a shielding plate 34 (e.g., a first polysilicon layer) is also present in the insulating termination trench ring 42. Although both the shielding plate 34 and the gate electrode 36 can be formed of the same polysilicon material, the shielding plate 34 is shown with a light dot pattern and the gate electrode 36 is shown with a darker dot pattern in order to distinguish them from each other.

[0049] In the prior art trench power MOSFET 20, a continuous body region 44 is formed in both the active region 28 and the termination region 30 above the epitaxial layer 46 of the substrate 22. The body region 44 extends in the silicon mesa between the trenches 32 and can cover the body region 44 between the trenches 32 in the active region 28 to form a source injection region 48. A source contact region 50 can be formed on a first main surface 24 of the substrate 22 covering the source injection region 48, and a drain contact region 52 can be formed on a second main surface 26 of the substrate 22 located below the drain region 54 of the substrate 22. For clarity, Figure 1 The source injection region 48 and the source contact region 50 are not shown in the diagram, making it easier to observe the continuous body region 44. However, the source injection region 48 and the source contact region 50 are presented in... Figures 2 to 3 In the middle, the source electrode contact area 50 is located between the trench pairs 32.

[0050] exist Figures 1 to 3 In this example, the drain region 54 can be an N++ doped substrate, and the insulating trench 32 (in which the shield 34 and the gate electrode 36 are formed) is etched into the N-epilayer 46. The N-epilayer 46 between the insulating trench pairs 32 is also a lightly doped N-drift region 56 of the MOSFET 20, wherein the body region 44 is formed by a P-type dopant (e.g., PHV) for forming the MOSFET channel, and the gate electrode 36 is formed between the shield 34 and the first main surface 24. In this n-channel example, under reverse bias, the depletion region in the drift region 56 (e.g., the epitaxial layer 46 between the trench pairs 32) grows under the influence of both the PN junction 58 (e.g., the junction between the body region 44 and the epitaxial layer 46) and the shield 34.

[0051] In cases of excessive depletion of charge in the silicon pillars between trench pairs 32 (e.g., narrow silicon pillars, lightly doped, thin insulator 40), breakdown occurs at the bottom of drift region 56. In cases of insufficient depletion of charge in the silicon pillars between trench pairs 32 (e.g., wide silicon pillars, heavily doped), breakdown occurs at the top of drift region 56. Whenever breakdown occurs at the bottom of the drift region, the breakdown voltage (BV) increases with the increase of the width 60 between trenches 32. When the width 60 is sufficiently wide, the electric field at the top of drift region 56 increases and the breakdown voltage decreases.

[0052] In a typical layout of a trench MOSFET 20, the active region 28 of the MOSFET 20 experiences a generally two-dimensional reduced surface field (RESURF) effect, and charge balance can be easily optimized. However, the termination region 30 can have a region that experiences a different RESURF effect than the active region 28, and can therefore have a different breakdown voltage (BV). That is, the conventional layout of the MOSFET 20, including the termination trench ring 42 surrounding all the trenches 32, experiences a generally three-dimensional RESURF.

[0053] Figure 4 A partial plan view of a prior art trench power MOSFET 20 is shown; a three-phase point region 62 (one shown) is formed at the termination region 30. The three-phase point region 62 is a generally triangular location defined by the intersection of the depletion fronts extending from the insulating trench 32 into the silicon pillar. In this example, a shield 34 is located in each trench pair 32 and within the surrounding termination trench ring 42. Drift region 56 in MOSFET 20 ( Figure 3 The depletion of the MOSFET 20 is influenced by the shield 34. At the termination region 30, there is asymmetrical growth of the depletion region at the three-phase point region 62 because the "three-phase point" is actually used as a wider region than the width 60 between the insulating trench pairs 32. That is, the three-phase point region 62 may become too wide to suppress the electric field at the top of the drift region at the location described in the three-phase point region 62, thereby degrading the RESURF effect, which in turn may lead to a decrease in the breakdown voltage of the MOSFET 20. Therefore, the breakdown voltage of the prior art trench MOSFET 20 is limited by the three-phase point region 62 in the termination region 30, rather than by the trench pairs 32 in the active region 28.

[0054] If the body region 44 at the triple point region 62 is biased to a sufficiently positive voltage, the electric field at the top of the drift region at the triple point region 62 can be suppressed. However, in prior art trench MOSFETs 20, the continuous body region 44 is connected through both the active region 28 and the termination region 30 via a PHV injection / diffusion region. Therefore, the embodiments disclosed herein implement a set of floating body segments formed between device trenches, which separate the continuous body of the trench MOSFET. Furthermore, the floating body segments can be self-biased to an appropriate positive voltage to achieve positive bias at the triple point region. Thus, the electric field in the triple point region can be effectively suppressed, and a reduction in breakdown voltage at the triple point region can be avoided.

[0055] refer to Figure 5 and Figure 6 , Figure 5 A plan view of a semiconductor device 70 according to an embodiment is shown, and Figure 6 It shows along Figure 5 The cross-sectional view of the semiconductor device 70 is taken by section line 6-6'. The semiconductor device 70 may be or may additionally include a trench field plate power MOSFET. Therefore, the semiconductor device 70 may also be referred to herein as a MOSFET 70 or a trench power MOSFET 70. The MOSFET 70 includes a semiconductor substrate 72 having opposing first main surfaces 74 and second main surfaces 76 (see Section 6-6'). Figure 6 ), active region 78 and terminal region 80 surrounding active region 78. In Figure 5 In the diagram, the active region 78 is typically surrounded by a dashed box. Figure 6 In the diagram, the dashed line delineates the active region 78 from the terminal region 80. For clarity, the following embodiments are based on an N-channel FET (NFET). However, the teachings also apply to embodiments based on a P-channel FET (PFET), where the doping polarity of the PFET is opposite to that of the NFET.

[0056] The semiconductor substrate 72 may include a plurality of epitaxial layers 82 supported by a pristine substrate 84. In this example, the semiconductor substrate 72 includes a single n-type epitaxial layer 82, and the pristine substrate 84 may be a heavily or moderately doped n-type substrate. The pristine substrate 84 may serve as a drain region and is therefore also referred to herein as drain region 84. Figure 6 In this illustration, the epitaxial layer 82 and drain region 84 are not necessarily drawn to scale. For example, in some cases, the drain region 84 may be thinned from its initial thickness after the growth of the epitaxial layer 82 and other fabrication processes. The structure, materials, and other properties of the semiconductor substrate 72 may differ from the example shown. For example, additional, fewer, or alternative layers may be included in the semiconductor substrate 72.

[0057] The MOSFET 70 further includes parallel insulating trenches 86 extending from a first main surface 74 in the semiconductor substrate 72 toward a second main surface 76. Each trench 86 includes a conductive field plate 88 (e.g., a first polysilicon layer) and a gate electrode 90 (e.g., a second polysilicon layer) overlying the conductive field plate 88, wherein the gate electrode 90 is connected through a gate-field insulator (not visible, but corresponding to...). Figure 2 The gate-field insulator plate 38 shown is separated from the conductive field plate 88. The conductive field plate 88, also referred to herein as a shielding plate 88, extends longitudinally in each trench 86 in the active region 78 and the terminal region 80. In some embodiments, the distal ends 94, 96 of the gate electrode 90 in each insulating trench 86 define the outer periphery 98 of the active region 78. Thus, the gate electrode 90 extends longitudinally in each trench 86 to the outer periphery 98 of the active region 78 of the gate electrode 90 (defined by the distal ends 94, 96), but there is no trench 86 in the terminal region 80. Therefore, the trench 86 in the active region 78 is lined with an insulator 100 (e.g., a shielding oxide) and lined with the gate electrode 90 and the conductive field plate 88 separated by the gate-field insulator. Conversely, the trench 86 in the terminal region 80 is lined with an insulator 100 but includes only the conductive field plate 88—also referred to herein as a shielding plate 88. For simplicity, only a few trenches 86 are shown in this document. However, it should be understood that the MOSFET 70 may have more or fewer trenches than the trenches 86 shown.

[0058] An insulating termination trench ring 102 surrounds the termination region 80. The termination trench ring 102 is also lined with an insulator 100, and a conductive field plate 88 (e.g., a first polysilicon layer) is also present in the insulating termination trench ring 102. Similarly, although both the conductive field plate 88 and the gate electrode 90 can be formed of the same polysilicon material, the conductive field plate 88 is shown with a light dot pattern and the gate electrode 90 is shown with a darker dot pattern in order to distinguish them from each other.

[0059] The body region 104 extends laterally between pairs of insulating trenches 86 above the epitaxial layer 82 of the semiconductor substrate 72. The body region 104 extends into the silicon mesas between the trenches 86. A drift region 105 is located below the body region 104 between the trenches 86 and may overlay the body region 104 between the trenches 86 in the active region 78 to form a source implantation region 106 (in...). Figure 6(As shown in the cross-sectional view). Therefore, the source region 106, the body region 104, the drift region 105, and the drain region 84 extend from the first main surface 74 toward the second main surface 76 in the aforementioned order. The source contact region 108 may be formed on the first main surface 74 of the substrate 72 covering the source injection region 106, and the drain contact region 110 may be formed on the second main surface 76 of the substrate 22 located below the drain region 84 of the substrate 72. For clarity, Figure 5 The source injection region 106 and source contact region 108 are not shown in the diagram, making the body region 104 easier to observe. During operation, channels are formed in each segment of the body region 104 between insulating trenches 86 for the transfer of charge carriers between the source contact region 108 and the drain contact region 110.

[0060] like Figure 5 As shown, the main body region 104 is generally present in the active region 78 and the terminal region 80, extending into the insulating trench ring 102. However, the spacer region 112 extends laterally between the insulating trench pairs 86 at the terminal region 80 to create a segment 114 isolated from the main body region 104 between the spacer regions 112. The phrase "at the terminal region 80" is intended to cover the spacer regions 112 and / or segments 114 located outside the outer perimeter 98 of the active region 78 and therefore in the terminal region 80, to cover the spacer regions 112 and / or segments 114 located inside the outer perimeter 98 and therefore in the active region 78 but near the distal ends 94, 96 and adjacent to the gate electrode 90 (but separated from the gate electrode 90 by the insulator 100), and to cover the spacer regions 112 and / or segments 114 spanning the outer perimeter 98.

[0061] The body region 104 is of a first conductivity type, and the epitaxial layer 82 is of a second conductivity type. In this n-channel example, the body region 104 is a p-type doped region, and more specifically a high-voltage P-region (PHV), and as previously mentioned, the epitaxial layer 82 is an n-type doped region. According to an embodiment, the spacer region 112 is of a second conductivity type—e.g., an n-type doped region—and the segment 114 is of a first conductivity type—e.g., a p-type doped region. In some embodiments, the segment 114 can be formed using the same body implantation / diffusion process as the active body region of the MOSFET 70 (e.g., body region 104) to avoid the need for additional mask / process steps to form the segment 114. Thus, the body region 104 and the segment 114 can extend to the same depth 113 ( Figure 6 ) Enter the substrate 72.

[0062] Segments 114 extend laterally between the trench pairs 86 (e.g., perpendicular to the longitudinal dimension 115 of the trench 86) and between the spacer regions 112 (e.g., parallel to the longitudinal dimension 115 of the trench 86). Furthermore, these segments 114 are isolated from and from the main body region 104. Figure 6 Specifically, p-type segments 114 are separated from and isolated from the host region 104 by n-type spacer regions 112 (e.g., a portion of the epitaxial layer 82 between segments 114). Therefore, segments 114 cannot be connected to or attached to the host region 104 via direct contact regions or regions of similar doping type. Since segments 114 and the host region 104 have the same doping type, the segments 114 can be formed using the same host implantation / diffusion process as the active host region, and they are not connected to or attached to the host region 104; therefore, segments 114 may be referred to herein as floating host segments 114.

[0063] Each insulating trench 86 includes a first end portion 116 and a second end portion 118, and an intermediate portion 120 extending longitudinally between the first end portion 116 and the second end portion 118. In this example configuration, a spacing region 112 extending between the insulating trench pairs 86 at the first end 116 includes spacing regions 1121, 1122, and 1123. Spacing region 1121 is adjacent to the body region 104. A floating body section 1141 exists between spacing regions 1121 and 1122. Additionally, a floating body section 1142 exists between spacing regions 1122 and 1123. Furthermore, a floating body section 1143 exists between spacing region 1123 and the insulating trench ring 102. Similarly, a spacing region 112 extending between the insulating trench pairs 86 at the second end 118 includes spacing regions 1124, 1125, and 1126. Spacing region 1124 is adjacent to the body region 104. Floating body segment 1144 exists between spacer 1124 and spacer 1125. Additionally, floating body segment 1145 exists between spacer 1125 and spacer 1126. Furthermore, floating body segment 1146 exists between spacer 1126 and insulating trench ring 102. In the illustrated configuration, floating body segments 1143 and 1146 form a continuous structure with respect to each other. However, in other embodiments, they may be discontinuous structures, such that floating body segment 1143 is isolated from floating body segment 1146.

[0064] The floating body section 114 introduced between the insulating trenches 86 effectively disconnects the terminal region 80 from the active region 78. Therefore, when a bias is applied to the drain region 84 relative to the body region 104, the epitaxial layer 82 begins to deplete. As the depletion region expands, it may eventually contact, for example, the floating body section 1141. At this point, the floating body section 1141 acquires the potential to "contact" it. Subsequently, the depletion region begins to expand from the floating body section 1141 and reaches the floating body section 1142. At this point, the floating body section 1142 acquires the potential to "contact" it. Finally, in this example, the depletion region begins to expand from the floating body section 1142 and reaches the floating body section 1143, at which point the floating body section 1143 acquires the potential to "contact" it. Although floating body sections 1141, 1142, and 1143 are mentioned in this explanation, equivalent behavior also occurs at 1144, 1145, and 1146. Therefore, when the drain region 84 is properly biased, the depletion region expands, which in turn allows the floating body section 114 to pick up a positive potential.

[0065] Due to the curvature of the PN junction (e.g., the junction between the n-type epitaxial layer 82 and the p-type floating body segment 114), the curvature region 122 of the floating body segment 114 (see...) Figure 6 The electric field at point 122 may be slightly enhanced. However, in a configuration of multiple floating body sections 114, the curvature region 122 can be effectively shielded by adjacent floating body sections 114. Therefore, the enhancement of the electric field at the curvature region can be controlled.

[0066] Figure 5 Examples include spacer regions 1121 and 1124 separated by insulator 100 adjacent to the gate electrode 90 in trench 86. Additionally, at least portions of floating body sections 1141 and 1144 are adjacent to the gate electrode 90 in trench 86. Positioning floating body sections 1141 and 1144 adjacent to the gate electrode 90 can mitigate the effect of electric field enhancement at curvature region 122. That is, the electric field at curvature region 122 in this scenario may be lower than the electric field at curvature region 122 when the floating body section 114 is in the terminal region 80 immediately adjacent to the conductive field plate 88. However, since the gate electrode 90 is physically closer to the silicon epitaxial layer 82 relative to the conductive field plate 88, the depletion region can expand rapidly, allowing the depletion region to reach the next section 114 with a relatively low voltage on the drain.

[0067] Therefore, some embodiments (e.g., one illustrated embodiment) may utilize a combination of a segment 114 adjacent to the gate electrode 90 in the active region 78 (separated by the insulator 100) and a segment 114 adjacent to the conductive field plate 88 in the terminal region 80 (separated by the insulator 100). In this configuration, the first segment 114 may be more susceptible to the electric field enhancement at the curvature region 122, such that the placement of the first segment 114 adjacent to the gate electrode 90 can effectively suppress the electric field at the curvature region 122. The latter half of the segment 114 adjacent to the conductive field plate 88 may have a higher voltage drop at the same distance and can therefore be used to obtain the desired voltage.

[0068] exist Figures 5 to 6 In the configuration, simulations showed that the breakdown voltage at the terminal region 80 first increases and then decreases. However, there is a large range of Sxt (e.g., the distance between the end of one of the trenches 86 and the insulating trench ring 102), where the breakdown voltage remains almost constant for a given combination of Sxa (e.g., the distance between the trenches 86) and the epitaxial layer 82. Therefore, there may be insignificant impact ions in the triple point region, such that these impact ions actually move into the active region 78. Thus, the breakdown voltage is not affected by Sxt (e.g., the distance between the end of one of the trenches 86 and the insulating trench ring 102) or the triple point region (e.g., Figure 4 The limitations of the triple point region 62 shown.

[0069] Figure 7 The section voltage 124 and the trench power MOSFET 70 are shown. Figures 5 to 6 A graphical view of the simulation results relating the drain voltage 126 to the floating main body segment 1141. Solid trace 128 represents the primary source voltage. Dashed trace 130 represents the segment voltage 124 at the floating main body segment 1141, which depends on the drain voltage 126. Dotted-dashed trace 132 represents the segment voltage 124 at the floating main body segment 1142, which depends on the drain voltage 126. Furthermore, double-dotted-dashed trace 134 represents the segment voltage 124 at the floating main body segment 1143, which depends on the drain voltage 126. Although the following discussion refers to floating main body segments 1141, 1142, and 1143, it should be understood that this discussion is equivalent to that for floating main body segments 1144, 1145, and 1146.

[0070] As the drain voltage 126 increases, the floating body section 114 picks up a potential. In this example, the three-phase point body region (e.g., floating body section 1143) acquires a voltage potential of approximately thirty volts. A potential of thirty volts may be sufficient to suppress the three-phase point region (e.g., Figure 4 The electric field in the triple point region 62 (shown) causes the shock ions to move into the active region 78. Provided Figure 7This illustrates a reasonable positive potential (e.g., thirty volts) that can be obtained from the terminal body (e.g., terminal region 30). In the case considered, a voltage potential of thirty volts may be sufficient to suppress the electric field in the triple point region 62. However, in general, the minimum voltage required to achieve this effect can vary between different designs and depends on the values ​​of Sxa, Sxt, doping, trench oxide thickness, etc.

[0071] exist Figures 1 to 3 In existing technology designs, the breakdown voltage drops rapidly to a critical value exceeding Sxt. In contrast, Figures 5 to 6 The floating body section design extends the rise period and transitions it into the steady-state period. Therefore, the ideal breakdown voltage of the floating body section design is higher than that of prior art designs, meaning that even with high column charge (e.g., highly doped, wide Sx), the breakdown voltage is limited by the device center (e.g., active region 78). In other words, utilizing the floating body section at the termination region suppresses the electric field in the triple point region, preventing the breakdown voltage from rolling off over a wide Sxt value. Therefore, even with high epitaxial layer doping and large Sx (Sxa and Sxt) values, the breakdown voltage can be higher and potentially limited by the active region, resulting in better breakdown voltage and lower on-resistance (BV-R). DS(on) This represents a compromise. Additionally, if desired, the floating body section design can be extended by employing a greater number of floating body sections and larger spacing, thereby achieving higher potentials at the triple point region. Therefore, the floating body section design allows for a wide range of design and process margins (e.g., doping and / or size).

[0072] Figure 8 A cross-sectional view of a trench power MOSFET 140 according to another embodiment is shown. The position of the cross-sectional view of MOSFET 140 corresponds to... Figure 6 The cross section shown Figure 6-6 The position of '. Additionally, MOSFET 140 includes multiple elements of MOSFET 70 ( Figures 5 to 6 Examples of these components include the main body region, termination region, epitaxial layer, drift region, drain region, parallel insulating trenches, conductive field plates, and gate electrode. Therefore, for the sake of brevity, descriptions of these components will not be repeated in this paper.

[0073] In this example, MOSFET 140 includes spacer regions 1421, 1422, and 1423 of a second conductivity type (e.g., n-type doped), which extend laterally between pairs of insulating trenches to create floating body regions 1441, 1442, and 1443 of a first conductivity type (e.g., p-type doped). Spacer region 1421 is adjacent to body region 146 of MOSFET 140. Floating body region 1441 exists between spacer regions 1421 and 1422. Additionally, floating body region 1442 exists between spacer regions 1422 and 1423. Furthermore, floating body region 1443 exists between spacer region 1423 and insulating termination trench ring (not shown).

[0074] Higher or lower voltages in the three-phase point region can be obtained by modifying the configuration of the floating body section. In the example shown here, the floating body section 1441 presents a longitudinal dimension parallel to the insulating trench (see [reference]). Figure 5 The first section has a width of 148, and the floating main body section 1442 has a second section width of 150, which is parallel to the longitudinal dimension of the insulating trench. The second section width 150 is different from the first section width 148. Additionally, the spacer sections 1421 and 1422 have longitudinal dimensions parallel to the insulating trench (see again). Figure 5 The first spacing width 152 and the spacing region 1423 having a second spacing width 154 parallel to the longitudinal dimension of the insulating trench, the second spacing width 154 being different from the first spacing width 152. In this generalized example, the second spacing width 154 is greater than the first spacing width 152. Generally, if the floating body sections are far apart, it is permissible for the floating body sections to have a large potential difference, so that the last section (e.g., floating body section 1443) reaches even a higher voltage potential.

[0075] supply Figure 8 This demonstrates that the width of the spacer region and / or the width of the floating body segment can be easily modified to achieve the desired voltage at the three-phase point region because no additional mask is required to generate the desired doped pattern. Furthermore, although three body segments are provided in the illustrated configuration, the design can be modified to include fewer or more body segments.

[0076] Figure 9 A flowchart representation of a method 160 for manufacturing a semiconductor device according to another embodiment is shown. Manufacturing method 160 can be performed to produce a semiconductor device having a floating body section that separates or otherwise isolates the active body region of the semiconductor device from the terminal region of the semiconductor device and is self-biased to an appropriate positive voltage. Therefore, the electric field at the three-phase point region of the terminal region can be effectively suppressed, preventing breakdown voltage roll-off at the terminal region.

[0077] In box 162, a drain region is formed using a doped semiconductor substrate (e.g., Figures 5 to 6 Drain region 84). In box 164, an epitaxial layer is grown on the drain region (e.g., Figures 5 to 6 The epitaxial layer 82), such that the outer surface of the epitaxial layer defines the first main surface of the semiconductor device (e.g., Figures 5 to 6 The first main surface 74) and the second main surface (e.g., opposite to the first main surface) Figures 5 to 6 The second primary surface 7).

[0078] In frame 166, insulating trenches are formed in the epitaxial layer (e.g., Figures 5 to 6 Insulating trenches 86 and insulating trench rings 102. The insulating trenches may be arranged parallel to each other and extend from the first main surface toward the second main surface. In block 168, a first polysilicon layer is formed in each of the trenches 86, 102 to form a shield separated from the epitaxial layer by an insulator. In block 170, a second polysilicon layer is formed in each trench 86 above the first polysilicon layer to form a shield separated from the epitaxial layer by a gate-field plate insulator (e.g., Figure 2 The gate-field plate insulator 38) and the shielded gate electrode (e.g., Figures 5 to 6 The gate electrode 90). The semiconductor device has an active region (e.g., Figures 5 to 6 The active region 78) and the terminal region surrounding the active region (e.g., Figures 5 to 6 The terminal region 80). There is no gate electrode in the terminal region and the conductive field plate extends longitudinally in both the active region and the terminal region.

[0079] In box 172, the main area is formed (e.g., Figures 5 to 6 The main body region 104) and segments are generated in the epitaxial layer between at least two insulating trenches and at least two spacer regions in the terminal region (e.g., Figures 5 to 6 The floating body segment 114). A body region can be formed, and segments can be generated simultaneously using the same implantation process. The body region and segments are of a first conductivity type (e.g., p-type doped), and the epitaxial layer and spacer region are of a second conductivity type (e.g., n-type doped). The configuration can include any suitable number of segments isolated from other segments and from the body region, and one or more segments can be formed in the spacer region and insulating termination trenches (e.g., Figures 5 to 6 Between the insulating trench rings 102. Additionally, the spacer region and / or segment may be located outside the outer periphery of the active region and therefore inside the outer periphery 98 in the terminal region and therefore in the active region 78 adjacent to the gate electrode 90, and / or may span the outer periphery of the active region. Furthermore, the spacer region and / or segment may be of any suitable width and may be of different widths relative to each other.

[0080] In frame 174, a source contact can be formed in the silicon mesa above the body region and between the insulating trench (e.g., ...). Figures 5 to 6 The source contact 108). Of course, other further operations may include forming the drain contact (e.g., Figures 5 to 6 The process includes forming a deposited layer on the drain contact 110 above the first main surface, encapsulation, testing, etc. After this, the manufacturing process 160 can be completed.

[0081] It should be understood that Figure 9 Some boxes in the process frames depicted can be executed in parallel with each other or together with other processes. Furthermore, it should be understood that modifications are possible. Figure 9 The specific order of the process blocks depicted in the invention achieves substantially the same result. Therefore, such modifications are intended to be included within the scope of the subject matter of this invention.

[0082] Figure 10 Another plan view of the trench power MOSFET 70 is shown to illustrate potential problems at the corner region 178 of the trench power MOSFET 70. The material of the termination region 80 is the same as that of the body region 78 (e.g., epitaxial layer 82, see...). Figure 6 In the configuration of MOSFET 70, the corner region 178 has a relatively small radius of curvature R. This relatively small radius of curvature R may result in a lower breakdown voltage at the termination region 80 due to electric field congestion. Undesirable low breakdown voltages may occur in standard termination designs (e.g., without floating body section 114) or in floating body section designs.

[0083] The undesirable low breakdown voltage at corner region 178 can be mitigated by increasing the width Sxc (e.g., the distance between the edge of one of the adjacent trenches 86 and the insulating trench ring 102 at corner region 178) and / or by increasing the radius of curvature R at corner region 178. The presence of the floating body section 114 makes it feasible to manufacture a wider Sxc to effectively increase the breakdown voltage at corner region 178. However, if a wider Sxc does not sufficiently increase the breakdown voltage at corner region 178, it may be necessary to increase the radius of curvature R at corner region 178. Figures 11 to 13 An example embodiment is shown for effectively increasing the radius of curvature R while maintaining the integrity of other regions. However, it should be understood that other design configurations are conceivable for increasing the radius of curvature R at corner region 178.

[0084] Figure 11A partial plan view of a trench power MOSFET 180 according to another embodiment is shown at a corner region 182. The MOSFET 180 includes parallel insulating trenches 184, each insulating trench 184 including a conductive field plate 186 (also referred to as a shield 186) and a gate electrode 188 covering the shield 186, wherein the gate electrode 188 is separated from the shield 186 by a gate-field insulator (not visible). An active region 190 of the MOSFET 180 is defined by the outermost insulating trench 184 and the corresponding ends of the trenches 184, and a termination region 192 surrounds the active region 190. The MOSFET 180 further includes insulating trenches 194 arranged parallel to the trenches 184 and located outside the active region 190. Each insulating trench 194 includes a shield 186. However, the gate electrode 188 is not included in the insulating trenches 194. In a rectangular configuration, the MOSFET 180 includes four corner regions 182 and insulating trenches 194 located on opposite sides of the active region 190.

[0085] The insulating trench 194 is offset or arranged in a stepped manner at the corner area 182, so that relative to Figure 10 The radius of curvature of the MOSFET 70 shown allows for a larger radius of curvature R at the corner region 182. In this configuration, the body region between the last few trenches 194 is connected to the termination region 192, indicated by the dotted-dashed curve. Therefore, the body regions between the active trenches 184 and the termination trench ring 196, between the trenches 194, and between the last trench 194 and the termination trench ring 196 will acquire a positive potential, thereby allowing the body regions to have a wider spacing Sx (indicated by the double-headed arrows) between the trenches and a higher local breakdown voltage.

[0086] MOSFET 180 further includes a spacer region 198 and a floating body section 200, as combined with the spacer region 112 and floating body section 114 of MOSFET 70. Figure 5 This is discussed in detail. A higher local breakdown voltage can be achieved at the corner region 182 by implementing trench 194 in the terminal region 192, combining the floating main body section 200, and effectively increasing the radius of curvature R. However, a sufficiently high local breakdown voltage can also be generated at the corner region by implementing trench 194 in the terminal region of a standard terminal layout (i.e., a layout without the floating main body section 200).

[0087] Figure 12A partial plan view of a trench power MOSFET 210 according to another embodiment is shown at corner regions 212. The MOSFET 180 includes parallel insulating trenches 214, each parallel insulating trench 214 including a conductive field plate 216 (also referred to as a shielding plate 216) and a gate electrode 218 covering the shielding plate 216, wherein the gate electrode 218 is separated from the shielding plate 216 by a gate-field insulator (not visible). An active region 220 of the MOSFET 210 is defined by the outermost insulating trench 214 and the corresponding ends of the trenches 214, and a termination region 222 surrounds the active region 220. A termination trench ring 224 surrounds the termination region 222. In a rectangular configuration, the MOSFET 210 includes four corner regions 212.

[0088] The insulating trench 214 is offset or arranged in a stepped manner at the corner area 212, so that relative to Figure 10 The radius of curvature of the MOSFET 70 shown can achieve a larger radius of curvature R at the corner region 212. The MOSFET 210 further includes a spacer region 226 and a floating body section 228, as in combination with the spacer region 112 and the floating body section 114 of the MOSFET 70. Figure 5 The details are as follows. The floating body section 228 exists between all the insulating trenches 214, including those offset or arranged in a stepped manner. Similarly, due to the positive potential generated by the floating body section 228 at the corner region 212, a wider spacing Sx (indicated by the double-headed arrow) can be achieved between the trench 214 and the terminal trench ring 224, resulting in a higher local breakdown voltage.

[0089] Figure 13 A plan view of a trench power MOSFET 230 having four corner regions 232 according to yet another embodiment is shown. The MOSFET 230 includes parallel insulating trenches 234, each parallel insulating trench 234 including a conductive field plate 236 (also referred to as a shielding plate 236) and a gate electrode 238 covering the shielding plate 236, wherein the gate electrode 238 is separated from the shielding plate 236 by a gate-field insulator (not visible). An active region 240 of the MOSFET 232 is defined by the outermost insulating trench 234 and the corresponding ends of the trenches 234, and a termination region 242 surrounds the active region 240. A primary termination trench ring 244 surrounds the termination region 242.

[0090] In this example embodiment, the secondary termination ring 246 is positioned on opposite sides of the outermost insulating trench 234 to achieve a larger radius of curvature R at each corner region 232. Therefore, in this example, there is no "three-phase point" region where the trench bends. Depending on specific design requirements, Sxc at the corner region 232 can be greater than or equal to Sxt. Although the size of the active region 240 can be sacrificed by the additional secondary termination ring 246, a larger radius of curvature may result in a higher local breakdown voltage.

[0091] MOSFET 230 further includes a spacer region 248 between insulating trenches 234 and a floating body section 250, as in combination with the spacer region 112 and floating body section 114 of MOSFET 70. Figure 5 This is discussed in detail. A higher local breakdown voltage can be achieved at the corner region 232 by implementing a secondary termination ring 246 in the terminal region 242, combining the floating main body section 250, and effectively increasing the radius of curvature R. However, a sufficiently high local breakdown voltage can also be generated at the corner region by implementing a secondary termination ring 246 in the terminal region of a standard terminal layout (i.e., a layout without the floating main body section 200).

[0092] The embodiments described herein relate to semiconductor devices with improved breakdown voltage characteristics and methods for manufacturing such semiconductor devices. Specifically, the embodiments relate to trench fieldplate power metal-oxide-semiconductor field-effect transistors (MOSFETs) having a set of floating body sections formed between device trenches of the MOSFET. The floating body sections separate or otherwise isolate the active body region of the semiconductor device from the terminal region of the semiconductor device. Additionally, the floating body sections are self-biased to an appropriate positive voltage. Therefore, the electric field at the three-phase point region of the terminal region can be effectively suppressed, preventing breakdown voltage roll-off at the terminal region. In some embodiments, the floating body sections can be formed using the same body implantation / diffusion process as the active body region of the device. This method avoids the need for additional mask / process steps to form the floating body sections, thereby improving manufacturing efficiency and saving costs.

[0093] This disclosure is intended to explain how to design and use various embodiments according to the invention, and not to limit the true, established, and fair scope and spirit of the invention. The foregoing description is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Modifications or variations may be made in light of the foregoing teachings. The embodiments were chosen and described to provide the best illustration of the principles of the invention and its practical application, and to enable one skilled in the art to utilize the invention in various embodiments and with various modifications suitable for the particular intended use. All such modifications and variations, and all their equivalents, are within the scope of the invention as defined by the appended claims when interpreted with the breadth of the clearly, lawfully, and fairly conferred rights, and may be amended during the pending period of this patent application.

Claims

1. A semiconductor device, characterized in that, include: A substrate having opposing first and second main surfaces, an active region, and a terminal region; An insulating trench extends from the first main surface toward the second main surface. Each insulating trench includes a conductive field plate and a gate electrode covered by the conductive field plate. The gate electrode is separated from the conductive field plate by a gate-field plate insulator. The conductive field plate extends longitudinally in both the active region and the terminal region, and the gate electrode is not present in the terminal region. A body region of a first conductivity type, the body region extending laterally between the insulating trench pairs; as well as A first and a second spacer of a second conductivity type, the first and second spacers extending laterally between the pairs of insulating trenches in the terminal region to create a segment of a first conductivity type between the first and second spacers, the segment being isolated from the body region.

2. The semiconductor device according to claim 1, characterized in that, The segment is a first segment, and the semiconductor device further includes a third spacer region of a second conductivity type extending laterally between the pairs of insulating trenches in the terminal region, the third spacer region being spaced apart from the second spacer region to create a second segment of a first conductivity type between the second spacer region and the third spacer region, the second segment being isolated from the first segment and isolated from the body region.

3. The semiconductor device according to claim 2, characterized in that: The first section has a width parallel to the longitudinal dimension of the insulating trench; and The second segment has a width parallel to the longitudinal dimension of the insulating trench, and the width of the second segment is different from the width of the first segment.

4. The semiconductor device according to claim 2, characterized in that, The terminal region surrounds the active region, and the semiconductor device further includes an insulating terminal trench surrounding the terminal region, wherein a conductive field plate is present in the terminal trench, and a third segment of a first conductivity type is present between the third spacer region and the insulating terminal trench, the third segment being isolated from the first segment and the second segment and isolated from the body region.

5. The semiconductor device according to claim 1, characterized in that: The first gap region has a first gap width parallel to the longitudinal dimension of the insulating trench; and The second gap region has a second gap width that is parallel to the longitudinal dimension of the insulating trench, and the second gap width is different from the first gap width.

6. The semiconductor device according to claim 1, characterized in that: Each of the insulating trenches includes a first end portion and a second end portion, and an intermediate portion extending longitudinally between the first end portion and the second end portion, wherein the first spacing region and the second spacing region extend laterally between the first end portions of the pair of insulating trenches; and The semiconductor device further includes a fourth and a fifth spacer region of a second conductivity type, the fourth and fifth spacer regions extending laterally between the second end portions of the pair of insulating trenches to create an additional segment of a first conductivity type between the fourth and fifth spacer regions, the additional segment being isolated from the body region.

7. The semiconductor device according to claim 1, characterized in that, The distal end of the gate electrode in each of the insulating trenches defines the outer periphery of the active region, wherein at least one of the first spacer region, the second spacer region, and the segment is adjacent to the gate electrode at the outer periphery of the active region and separated from the gate electrode by an insulator.

8. The semiconductor device according to claim 1, characterized in that, The first interval region, the second interval region, and at least one of the segments are adjacent to the conductive field plate in the terminal region and separated from the conductive field plate by an insulator.

9. A method for manufacturing a semiconductor device, characterized in that, include: The drain region is formed using a doped semiconductor substrate; An epitaxial layer is grown on the drain region such that the outer surface of the epitaxial layer defines a first main surface of the semiconductor device and a second main surface of the semiconductor device opposite to the first main surface; An insulating trench is formed in the epitaxial layer, each of the insulating trenches being arranged parallel to each other and extending from the first main surface toward the second main surface; A conductive field plate is formed in each of the insulating trenches, and the conductive field plate is separated from the epitaxial layer by an insulator; A gate electrode is formed above the conductive field plate in each of the insulating trenches, the gate electrode being separated from the conductive field plate by a gate-field plate insulator, wherein the semiconductor device has an active region and a terminal region surrounding the active region, the gate electrode being absent in the terminal region, and the conductive field plate extending longitudinally in both the active region and the terminal region; A first conductive type body region is formed extending laterally between the insulating trench pairs; as well as A segment of a first conductive type is generated at the terminal region, the segment being generated between a first and a second spacing region of a second conductive type extending laterally between the pairs of insulating trenches, the segment being isolated from the main body region.

10. A semiconductor device, characterized in that, include: A substrate having opposing first and second main surfaces, an active region, and a terminal region surrounding the active region; An insulating trench extends from a first main surface toward a second main surface. Each insulating trench includes a first end portion and a second end portion, and a middle portion extending longitudinally between the first end portion and the second end portion. Each insulating trench includes a conductive field plate and a gate electrode covering the conductive field plate. The gate electrode is separated from the conductive field plate by a gate-field plate insulator. The conductive field plate extends longitudinally in both the active region and the terminal region, and the gate electrode is not present in the terminal region. A body region of a first conductivity type, the body region extending laterally between the insulating trench pairs; A first and a second spacer of a second conductivity type, the first and second spacers extending laterally between the pairs of insulating trenches at the first end portions to create a first segment of a first conductivity type between the first and second spacers, the first segment being isolated from the body region; as well as The third and fourth spacer regions of the second conductivity type extend laterally between the pairs of insulating trenches at the second end portions to create an additional segment of the first conductivity type between the third and fourth spacer regions, the additional segment being isolated from the body region, wherein the body region, the first segment, and the additional segment are configured to be formed simultaneously in the same injection process.

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