Display device

Abstract

A display device is disclosed, which includes: a first pixel connected to a first write scan line and a first compensation scan line; a second pixel connected to a second write scan line and a second compensation scan line; a third pixel connected to a third write scan line and a third compensation scan line; a fourth pixel connected to a fourth write scan line and a fourth compensation scan line; a fifth pixel connected to a fifth write scan line and a fifth compensation scan line; a sixth pixel connected to a sixth write scan line and a sixth compensation scan line; a seventh pixel connected to a seventh write scan line and a seventh compensation scan line; and an eighth pixel connected to an eighth write scan line and an eighth compensation scan line, the first compensation scan line to the fourth compensation scan line being connected to a first node, the fifth compensation scan line and the sixth compensation scan line being connected to a second node, and the seventh compensation scan line and the eighth compensation scan line being connected to a third node.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2020-0048138, filed on April 21, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a display device. Background Art

[0003] With the development of information technology, display devices, which are a connecting medium between users and information, play a major role in absorbing information. Therefore, the use of high-quality display devices such as liquid crystal display devices, organic light emitting display devices, or plasma display devices has been increasing.

[0004] A display device can be divided into a display area in which pixels are positioned and a non-display area in which pixels are not positioned. As the display area increases, the display device can display a larger image. Therefore, a narrow-frame design in which the non-display area is reduced or a frameless design in which the non-display area is eliminated is being developed.

[0005] However, the non-display area still requires space for drivers that control pixels and load matching capacitors that compensate for resistance-capacitance (RC) delays between signals. Summary of the Invention

[0006] According to an exemplary embodiment of the inventive concept, a display device is provided, which includes: a first pixel, connected to a first write scan line and a first compensation scan line; a second pixel, connected to a second write scan line and a second compensation scan line; a third pixel, connected to a third write scan line and a third compensation scan line; a fourth pixel, connected to a fourth write scan line and a fourth compensation scan line; a fifth pixel, connected to a fifth write scan line and a fifth compensation scan line; a sixth pixel, connected to a sixth write scan line and a sixth compensation scan line; a seventh pixel, connected to a seventh write scan line and a seventh compensation scan line; and an eighth pixel, connected to an eighth write scan line and an eighth compensation scan line, wherein the number of the first pixels is less than the number of the fifth pixels, the first compensation scan line, the second compensation scan line, the third compensation scan line and the fourth compensation scan line are connected to a first node, the fifth compensation scan line and the sixth compensation scan line are connected to a second node, the seventh compensation scan line and the eighth compensation scan line are connected to a third node, and the first node, the second node and the third node are different nodes.

[0007] The display device may further include: a first compensation stage having an output terminal connected to the first node; a second compensation stage connected to the first compensation stage via a first compensation carry line; a third compensation stage connected to the second compensation stage via a second compensation carry line, wherein the third compensation stage has an output terminal connected to the second node; and a fourth compensation stage connected to the third compensation stage via a third compensation carry line, wherein the fourth compensation stage has an output terminal connected to the third node.

[0008] The first write scan line, the second write scan line, the third write scan line, the fourth write scan line, the fifth write scan line, the sixth write scan line, the seventh write scan line, and the eighth write scan line may be separated from each other.

[0009] The display device may further include: a first write level having an output terminal connected to a first write scan line; a second write level connected to the first write level through a first write carry line, wherein the second write level has an output terminal connected to the second write scan line; a third write level connected to the second write level through a second write carry line, wherein the third write level has an output terminal connected to the third write scan line; a fourth write level connected to the third write level through a third write carry line, wherein the fourth write level has an output terminal connected to the fourth write scan line; a fifth write level connected to the fourth write level through a fourth write carry line, wherein the fifth write level has an output terminal connected to the fifth write scan line; a sixth write level connected to the fifth write level through a fifth write carry line, wherein the sixth write level has an output terminal connected to the sixth write scan line; a seventh write level connected to the sixth write level through a sixth write carry line, wherein the seventh write level has an output terminal connected to the seventh write scan line; and an eighth write level connected to the seventh write level through a seventh write carry line, wherein the eighth write level has an output terminal connected to the eighth write scan line.

[0010] The display device may further include: a first initialization stage having an output terminal connected to the first pixel and the second pixel; a second initialization stage having an output terminal connected to the third pixel and the fourth pixel; a third initialization stage having an output terminal connected to the fifth pixel and the sixth pixel; and a fourth initialization stage having an output terminal connected to the seventh pixel and the eighth pixel.

[0011] The second initialization stage may be connected to the first initialization stage, the third initialization stage may be connected to the second initialization stage, and the fourth initialization stage may be connected to the third initialization stage.

[0012] The display device may further include: a first emission level having an output terminal connected to the first pixel and the second pixel; a second emission level having an output terminal connected to the third pixel and the fourth pixel; a third emission level having an output terminal connected to the fifth pixel and the sixth pixel; and a fourth emission level having an output terminal connected to the seventh pixel and the eighth pixel.

[0013] The second emitting stage may be connected to the first emitting stage, the third emitting stage may be connected to the second emitting stage, and the fourth emitting stage may be connected to the third emitting stage.

[0014] The display device may further include: a first bypass stage having an output terminal connected to the first pixel and the second pixel; a second bypass stage having an output terminal connected to the third pixel and the fourth pixel; a third bypass stage having an output terminal connected to the fifth pixel and the sixth pixel; and a fourth bypass stage having an output terminal connected to the seventh pixel and the eighth pixel.

[0015] The second bypass stage may be connected to the first bypass stage, the third bypass stage may be connected to the second bypass stage, and the fourth bypass stage may be connected to the third bypass stage.

[0016] The first pixel as one of the first pixels may include: a first transistor including a first electrode, a second electrode and a gate electrode; a second transistor having a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a first write scan line; and a third transistor having a first electrode connected to the second electrode of the first transistor, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the first compensation scan line.

[0017] The first pixel may further include: a fourth transistor having a first electrode connected to a first initialization line, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a first initialization scan line, wherein the first initialization scan line connects the first initialization level to the first pixel; a fifth transistor having a first electrode connected to a first power line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a first emission scan line, wherein the first emission scan line connects the first emission level to the first pixel; a sixth transistor having a first electrode connected to the second electrode of the first transistor, a second electrode, and a gate electrode connected to the first emission scan line; a capacitor having a first electrode connected to the first power line and a second electrode connected to the gate electrode of the first transistor; and a light emitting diode having an anode connected to the second electrode of the sixth transistor and a cathode connected to the second power line.

[0018] The first pixel may further include: a seventh transistor having a first electrode connected to an anode of the light-emitting diode, a second electrode connected to a second initialization line, and a gate electrode connected to a first bypass scan line, wherein the first bypass scan line connects the first bypass stage to the first pixel; and an eighth transistor having a first electrode connected to a third power line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first bypass scan line.

[0019] The first initialization stage may apply an initialization scan signal of a turn-on level to a first initialization scan line and a second initialization scan line during a first period, wherein the first initialization scan line connects the first initialization stage to the first pixel and the second initialization scan line connects the first initialization stage to the second pixel, and the first compensation stage may apply a compensation scan signal of a turn-on level to the first compensation scan line, the second compensation scan line, the third compensation scan line, and the fourth compensation scan line during a second period after the first period.

[0020] The third compensation level can apply a compensation scan signal of a conduction level to the fifth compensation scan line and the sixth compensation scan line during the third period, and the first write level, the second write level, the third write level and the fourth write level can sequentially output a write scan signal of a conduction level during a period other than the third period within the second period.

[0021] The fourth compensation level can apply a compensation scan signal of a conduction level to the seventh compensation scan line and the eighth compensation scan line during the fourth period, the fifth write level and the sixth write level can sequentially output a write scan signal of a conduction level during a period other than the fourth period within the third period, and the seventh write level and the eighth write level can sequentially output a write scan signal of a conduction level during the fourth period.

[0022] The first emission stage may apply an emission scan signal of an off level to the first emission scan line and the second emission scan line during a fifth period, wherein the first emission scan line connects the first emission stage to the first pixel and the second emission scan line connects the first emission stage to the second pixel, the fifth period includes the first period and the second period, the first bypass stage may apply a bypass scan signal of an on level to the first bypass scan line and the second bypass scan line during a sixth period, wherein the first bypass scan line connects the first bypass stage to the first pixel and the second bypass scan line connects the first bypass stage to the second pixel, the sixth period may overlap with the fifth period and may not overlap with the first period and the second period, and the period in which the second period overlaps with the third period may be shorter than the period in which the third period overlaps with the fourth period.

[0023] According to an exemplary embodiment of the inventive concept, a display device is provided, comprising: a first pixel connected to a first write scan line and a first compensation scan line, wherein the first pixel is located in a first pixel area having a first width; and a second pixel connected to a second write scan line and a second compensation scan line, wherein the second pixel is located in a second pixel area having a second width greater than the first width, wherein the second compensation scan line is connected to second pixels arranged in v horizontal lines, wherein v is an integer greater than 0, and the first compensation scan line is connected to first pixels arranged in u horizontal lines, wherein u is greater than v.

[0024] The display device may further include a third pixel connected to the first write scan line and the first compensation scan line, wherein the third pixel is located in a third pixel region having a third width smaller than the second width.

[0025] According to an exemplary embodiment of the inventive concept, a display device is provided, which includes: a first pixel connected to a first scan line; a second pixel connected to a second scan line adjacent to the first scan line; a third pixel connected to a third scan line; and a fourth pixel connected to a fourth scan line adjacent to the third scan line, wherein the number of the second pixels is different from the number of the third pixels, the scan signals of the conduction level supplied to the first scan line and the second scan line have the same phase, and the scan signals of the conduction level supplied to the third scan line and the fourth scan line have different phases.

[0026] According to an exemplary embodiment of the inventive concept, a display device is provided, which includes: a first pixel row connected to a first scan line, a second pixel row connected to a second scan line, a third pixel row connected to a third scan line, and a fourth pixel row connected to a fourth scan line, wherein the first scan line, the second scan line, the third scan line, and the fourth scan line are connected to a first node; a fifth pixel row connected to a fifth scan line and a sixth pixel row connected to a sixth scan line, wherein the fifth scan line and the sixth scan line are connected to a second node different from the first node; and a seventh pixel row connected to a seventh scan line and an eighth pixel row connected to an eighth scan line, wherein the seventh pixel row and the eighth pixel row are connected to a third node different from the second node.

[0027] The first node may be connected to the first compensation stage of the scan driver, the second node may be connected to the third compensation stage of the scan driver, and the third node may be connected to the fourth compensation stage of the scan driver.

[0028] The second compensation stage of the scan driver may not be connected to the first node, the second node, or the third node.

[0029] The second compensation stage may be connected between the first compensation stage and the third compensation stage.

[0030] The number of pixels in the first pixel row may be smaller than the number of pixels in the fifth pixel row. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the inventive concept will become more apparent by describing exemplary embodiments of the inventive concept in further detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a diagram for describing a display device according to an exemplary embodiment of the inventive concept;

[0033] Figure 2 is a diagram for describing a pixel according to an exemplary embodiment of the inventive concept;

[0034] Figure 3 is a diagram for describing a high-frequency driving method according to an exemplary embodiment of the inventive concept;

[0035] Figure 4 is a diagram for describing a data writing period according to an exemplary embodiment of the inventive concept;

[0036] Figure 5 is a diagram for describing a low-frequency driving method according to an exemplary embodiment of the inventive concept;

[0037] Figure 6 is a diagram for describing a bias refresh period according to an exemplary embodiment of the inventive concept;

[0038] Figure 7 is a diagram for describing a display device in which a substrate includes a recess according to an exemplary embodiment of the inventive concept;

[0039] Figure 8 is a diagram for describing a relationship between a first scan driver and a first pixel region according to an exemplary embodiment of the inventive concept;

[0040] Figure 9 is a diagram for describing a relationship between a first scan driver and a second pixel region according to an exemplary embodiment of the inventive concept;

[0041] Figure 10 is a diagram for describing a relationship between a second scan driver and a third pixel region according to an exemplary embodiment of the inventive concept;

[0042] Figure 11 is a diagram for describing a relationship between a second scan driver and a second pixel area according to an exemplary embodiment of the inventive concept;

[0043] Figure 12 and Figure 13is a diagram for describing a driving method of a first pixel region and a second pixel region according to an exemplary embodiment of the inventive concept; and

[0044] Figure 14 is a diagram for describing a display device in which a substrate includes a hole according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0045] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, it will be understood that the described embodiments can be implemented in a variety of different ways and therefore should not be limited to the embodiments described herein. The embodiments disclosed herein can be used in combination with each other or can be used independently of each other.

[0046] Like reference numerals may refer to like parts throughout the specification.

[0047] In addition, the sizes and thicknesses of elements shown in the drawings may be exaggerated for clarity of explanation.

[0048] Figure 1 is a diagram for describing a display device according to an exemplary embodiment of the inventive concept.

[0049] Reference Figure 1 , a display device 9 according to an exemplary embodiment of the inventive concept may include a timing controller 10 , a data driver 20 , a first scan driver 30 , a second scan driver 40 , and a pixel unit 50 .

[0050] The timing controller 10 may receive external input signals from an external processor. The external input signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and red, green, and blue (RGB) data.

[0051] The vertical synchronization signal may include multiple pulses and, based on the time at which each of the multiple pulses is generated, may indicate the end of the previous frame period and the beginning of the current frame period. The interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period. For example, the first pulse of the vertical synchronization signal may indicate the beginning of the current frame period, and the second pulse of the vertical synchronization signal may indicate the end of the current frame period. The horizontal synchronization signal may include multiple pulses and, based on the time at which each of the multiple pulses is generated, may indicate the end of the previous horizontal period and the beginning of a new horizontal period. The interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may indicate the supply of RGB data in a horizontal period. For example, RGB data may be supplied in pixel row units in the horizontal period corresponding to the data enable signal. The timing controller 10 may generate grayscale values ​​based on the RGB data to correspond to the specifications of the display device 9. For example, the grayscale values ​​may be RGB data rearranged to correspond to the resolution of the pixel unit 50, etc. The timing controller 10 may generate control signals to be supplied to the data driver 20 , the first scan driver 30 , the second scan driver 40 , etc. based on external input signals to correspond to the specifications of the display device 9 .

[0052] The data driver 20 may generate data voltages to be supplied to the data lines DL1, DL2, and DLm using the grayscale values ​​and control signals received from the timing controller 10. For example, the data driver 20 may sample the grayscale values ​​using the clock signal and may supply data voltages corresponding to the grayscale values ​​to the data lines DL1, DL2, and DLm in pixel row units (e.g., pixels connected to the same write scan line).

[0053] The first scan driver 30 may receive a control signal from the timing controller 10 and generate scan signals to be supplied to the scan lines GWL1 , GCL1 , GBL1 , GWLn, GCLn, and GBLn. Here, n may be an integer greater than 0.

[0054] The first scan driver 30 may include a first write scan driver, a compensation scan driver, and a bypass scan driver. The first write scan driver may be a shift register and may include a plurality of write stages connected to a write carry line. The write stages may sequentially generate write carry signals corresponding to write start signals received from the timing controller 10. In other words, the write stages may sequentially generate write carry signals in response to the write start signals. The write stages may sequentially generate write scan signals of a conduction level according to the write start signals and the write carry signals. The write scan signals of a conduction level may be provided to the corresponding write scan lines GWL1 and GWLn.

[0055] The compensation scan driver may be a shift register and may include a plurality of compensation stages connected to the compensation carry lines. The compensation stages may sequentially generate compensation carry signals in response to compensation start signals received from the timing controller 10. In other words, the compensation stages may sequentially generate compensation carry signals in response to the compensation start signals. The compensation stages may sequentially generate compensation scan signals of an on-level based on the compensation start signal and the compensation carry signal. The compensation scan signals of an on-level may be provided to the corresponding compensation scan lines GCL1 and GCLn.

[0056] The bypass scan driver may be a shift register and may include a plurality of bypass stages connected to the bypass carry lines. The bypass stages may sequentially generate bypass carry signals in response to a bypass start signal received from the timing controller 10. In other words, the bypass stages may sequentially generate bypass carry signals in response to the bypass start signal. The bypass stages may sequentially generate bypass scan signals of a conduction level based on the bypass start signal and the bypass carry signal. The conduction level bypass scan signals may be provided to the corresponding bypass scan lines GBL1 and GBLn.

[0057] The second scan driver 40 may receive a control signal from the timing controller 10 and generate a scan signal to be supplied to the scan lines GWL1 , GIL1 , EL1 , GWLn, GILn, and ELn.

[0058] The second scan driver 40 may include a second write scan driver, an initialization scan driver, and an emission scan driver. The second write scan driver may be a shift register and may include a plurality of write stages connected to the write carry lines. The write stages may sequentially generate write carry signals in response to write start signals received from the timing controller 10. The write stages may sequentially generate write scan signals of a conductive level based on the write start signal and the write carry signal. The conductive level write scan signals may be provided to the corresponding write scan lines GWL1 and GWLn.

[0059] The initialization scan driver may be a shift register and may include a plurality of initialization stages connected to the initialization carry lines. The initialization stages may sequentially generate initialization carry signals corresponding to the initialization start signals received from the timing controller 10. In other words, the initialization stages may sequentially generate initialization carry signals in response to the initialization start signals. The initialization stages may sequentially generate initialization scan signals of a conductive level based on the initialization start signals and the initialization carry signals. The conductive level initialization scan signals may be provided to the corresponding initialization scan lines GIL1 and GILn.

[0060] The emission scan driver may be a shift register and may include a plurality of emission stages connected to the emission carry lines. The emission stages may sequentially generate emission carry signals in response to emission stop signals received from the timing controller 10. In other words, the emission stages may sequentially generate emission carry signals in response to the emission stop signals. The emission stages may sequentially generate emission scan signals of an off-level according to the emission stop signals and the emission carry signals. The emission scan signals of an off-level may be provided to the corresponding emission scan lines EL1 and ELn.

[0061] The pixel unit 50 includes pixels. For example, the pixels PXnm may be connected to corresponding data lines DLm, write scan lines GWLn, compensation scan lines GCLn, bypass scan lines GBLn, initialization scan lines GILn, and emission scan lines ELn.

[0062] According to the present embodiment, each of the write scan lines GWL1 and GWLn can be connected to the write stage of the first scan driver 30 and the write stage of the second scan driver 40 to receive the write scan signal from both sides of the pixel unit 50. Therefore, the resistance-capacitance (RC) delay of the write scan signal can be minimized. Although the first scan driver 30 and the second scan driver 40 are shown at opposite sides of the pixel unit 50, in an alternative embodiment, the first scan driver 30 and the second scan driver 40 can be disposed below the pixel unit 50.

[0063] According to this embodiment, the first scan driver 30 may include a compensation stage and a bypass stage, and the second scan driver 40 may include an initialization stage and an emission stage. Therefore, the stages necessary for controlling the pixels can be distributed on both sides of the pixel unit 50, thereby minimizing the frame size.

[0064] Figure 2 is a diagram for describing a pixel according to an exemplary embodiment of the inventive concept.

[0065] Reference Figure 2 Pixel PXnm may include transistors T1, T2, T3, T4, T5, T6, T7, and T8, a capacitor Cst, and a light-emitting diode LD. Pixel PXnm is connected to the nth write scan line GWLn and the mth data line DLm. Since other pixels may have the same pixel circuit structure except for being connected to the control lines of other pixels, a repeated description thereof will be omitted.

[0066] The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The first transistor T1 may be referred to as a driving transistor.

[0067] The second transistor T2 may have a first electrode connected to the data line DLm, a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode connected to the write scan line GWLn.

[0068] The third transistor T3 may have a second electrode connected to the gate electrode of the first transistor T1 , a first electrode connected to the second electrode of the first transistor T1 , and a gate electrode connected to the compensation scan line GCLn.

[0069] The fourth transistor T4 may have a second electrode connected to the gate electrode of the first transistor T1 , a first electrode connected to the first initialization line VINTL1 , and a gate electrode connected to the initialization scan line GILn.

[0070] The fifth transistor T5 may have a first electrode connected to the first power line ELVDDL, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission scan line ELn.

[0071] The sixth transistor T6 may have a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the anode of the light emitting diode LD, and a gate electrode connected to the emission scan line ELn.

[0072] The seventh transistor T7 may have a first electrode connected to the anode of the light emitting diode LD, a second electrode connected to the second initialization line VINTL2 , and a gate electrode connected to the bypass scan line GBLn.

[0073] The eighth transistor T8 may have a first electrode connected to the third power line HVDDL, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the bypass scan line GBLn. According to another exemplary embodiment of the inventive concept, the first electrode of the eighth transistor T8 may be connected to the second electrode of the first transistor T1.

[0074] The capacitor Cst may have a first electrode connected to the first power line ELVDDL and a second electrode connected to the gate electrode of the first transistor T1 .

[0075] The light emitting diode LD may have an anode connected to the second electrode of the sixth transistor T6 and a cathode connected to the second power line ELVSSL. The light emitting diode LD may be an organic light emitting diode, a quantum dot / well light emitting diode, etc. Figure 2 In the embodiment, one light emitting diode is shown. However, in another exemplary embodiment of the inventive concept, a plurality of light emitting diodes connected in series, in parallel, or in series and in parallel may be configured. For example, another light emitting diode may be connected in parallel with the light emitting diode LD between the first electrode of the seventh transistor T7 and the second power line ELVSSL.

[0076] The voltage applied to the first and third power lines ELVDDL and HVDDL may be greater than the voltage applied to the first and second initialization lines VINTL1 and VINTL2 and the second power line ELVSSL. The voltage applied to the third power line HVDDL may be greater than the voltage applied to the first power line ELVDDL.

[0077] Transistors T1, T2, T5, T6, T7, and T8 may be P-type transistors. For example, transistors T1, T2, T5, T6, T7, and T8 may be P-channel metal oxide semiconductor (PMOS) transistors. For example, the channels of transistors T1, T2, T5, T6, T7, and T8 may be constructed of polysilicon. The polysilicon transistors may be low-temperature polysilicon (LTPS) transistors. Polysilicon transistors have high electron mobility, and therefore have fast driving characteristics.

[0078] Transistors T3 and T4 may be N-type transistors. For example, transistors T3 and T4 may be N-channel metal oxide semiconductor (NMOS) transistors. For example, the channels of transistors T3 and T4 may be constructed of oxide semiconductors. Compared to polysilicon, oxide semiconductor transistors have low charge mobility. Therefore, the amount of leakage current generated in the off state of the oxide semiconductor transistor is smaller than the amount of leakage current generated in the off state of the polysilicon transistor.

[0079] Figure 3 is a diagram for describing a high frequency driving method according to an exemplary embodiment of the inventive concept.

[0080] When the pixel unit 50 displays frames at a first driving frequency, the display device 9 may be in a first display mode. In addition, when the pixel unit 50 displays frames at a second driving frequency lower than the first driving frequency, the display device 9 may be in a second display mode.

[0081] In the first display mode, the display device 9 may display image frames at 20 Hz or greater (eg, 60 Hz).

[0082] The second display mode may be a low power display mode. In this case, the display device 9 may display image frames at less than 20 Hz (e.g., 1 Hz). For example, a situation where only the time and date are displayed in the "always on mode" may correspond to the second display mode.

[0083] Figure 3 The time period 1TP in the first display mode is used to compare the first display mode with the second display mode. The time period 1TP may be the same time interval in the first display mode and the second display mode.

[0084] In the first display mode, the period 1TP may include a plurality of frame periods 1FP. In the first display mode, each of the frame periods 1FP may sequentially include a data writing period WP and an emission period EP.

[0085] Therefore, the pixel PXnm may display a plurality of image frames corresponding to the number of frame periods 1FP during the period 1TP based on the data voltage received in the data write period WP.

[0086] Figure 4 is a diagram for describing a data writing period according to an exemplary embodiment of the inventive concept.

[0087] At time t1a, an emission scan signal En at an off level is supplied to the emission scan line ELn. For example, the emission scan signal En transitions from a low level to a high level. Consequently, the fifth transistor T5 and the sixth transistor T6 are turned off, and the driving current flowing from the first power line ELVDDL to the second power line ELVSSL is cut off.

[0088] At time point t2a, the bypass scan signal GBn of the conduction level is supplied to the bypass scan line GBLn. For example, the bypass scan signal GBn changes from a high level to a low level. Therefore, the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 is turned on, the initialization voltage of the second initialization line VINTL2 is applied to the anode of the light-emitting diode LD. Therefore, the voltage of the anode of the light-emitting diode LD can be initialized. When the eighth transistor T8 is turned on, the power voltage of the third power line HVDDL is applied to the first electrode of the first transistor T1. Therefore, the first transistor T1 can be turned on and biased by the voltage difference between the gate electrode and the source electrode (for example, the first electrode) of the first transistor T1. Therefore, the hysteresis caused by the grayscale of the previous frame period can be prevented. In particular, since the power voltage of the third power line HVDDL is used as the on-bias voltage of the first transistor T1, rather than the data voltage of the previous horizontal period, the on-bias of the first transistor T1 can be guaranteed in all frame periods.

[0089] At time t3a, an initialization scan signal GIn of a conduction level is supplied to the initialization scan line GILn. For example, the initialization scan signal GIn transitions from a low level to a high level. As a result, the fourth transistor T4 is turned on, and the initialization voltage of the first initialization line VINTL1 is applied to the gate electrode of the first transistor T1. Thus, the voltage of the gate electrode of the first transistor T1 is initialized.

[0090] At time point t4a, the compensation scan signal GCn of the conduction level is supplied to the compensation scan line GCLn. Therefore, the third transistor T3 is turned on, and the first transistor T1 is connected in a diode form. At time point t4a, the third transistor T3 can be turned on after the fourth transistor T4 is turned off.

[0091] At time t5a, a write scan signal GWn at an on-level is supplied to the write scan line GWLn. Consequently, the second transistor T2 is turned on. At this point, the data voltage Dm corresponding to the pixel PXnm can be applied to the data line DLm. The magnitude of the data voltage Dm can correspond to the grayscale value Gnm of the pixel PXnm. The data voltage Dm can be sequentially applied to the gate electrode of the first transistor T1 through the second transistor T2, the first transistor T1, and the third transistor T3. At this point, the voltage applied to the gate electrode of the first transistor T1 is the compensated data voltage Dm including a reduction corresponding to the threshold voltage of the first transistor T1.

[0092] Even when the write scan signal GWn is supplied at an off level, the first electrode of the first transistor T1 can maintain the data voltage Dm due to the parasitic capacitance. In other words, even when the write scan signal GWn transitions to high after time point t5a, the first electrode of the first transistor T1 maintains the data voltage Dm. Therefore, the threshold voltage of the first transistor T1 can be compensated from time point t5a to time point t6a. At time point t6a, the compensation scan signal GCn is supplied to the compensation scan line GCLn at an off level.

[0093] At time point t7a, a bypass scan signal GBn of a conduction level is supplied to the bypass scan line GBLn. Therefore, the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 is turned on, the initialization voltage of the second initialization line VINTL2 is applied to the anode of the light-emitting diode LD. Therefore, the voltage of the anode of the light-emitting diode LD can be initialized. When the eighth transistor T8 is turned on, the power voltage of the third power line HVDDL is applied to the first electrode of the first transistor T1. Therefore, the first transistor T1 can be biased by the voltage difference between the gate electrode and the source electrode (e.g., the first electrode) of the first transistor T1. According to an exemplary embodiment of the inventive concept, the bypass scan signal GBn of the conduction level can be supplied only at one of the time points t2a and t7a.

[0094] Figure 5 is a diagram for describing a low frequency driving method according to an exemplary embodiment of the inventive concept.

[0095] In the second display mode, the time interval of period 1TP may be the same as the time interval of one frame period 1FP. In the second display mode, each of the plurality of frame periods 1FP may sequentially include a data write period WP, ​​an emission period EP, a bias refresh period BP, and an emission period EP.

[0096] Since the third transistor T3 and the fourth transistor T4 of the pixel PXnm remain in the off state during the bias refresh period BP, the capacitor Cst maintains the same data voltage during one frame period 1FP. In particular, since the third transistor T3 and the fourth transistor T4 can be constructed by oxide semiconductor transistors, leakage current can be minimized.

[0097] Therefore, the pixels PXnm may display the same single image frame during the period 1TP based on the data voltage Dm received during the data writing period WP.

[0098] Figure 6 is a diagram for describing a bias refresh period according to an exemplary embodiment of the inventive concept.

[0099] Reference Figure 6 The waveforms of the emission scan signal En and the bypass scan signal GBn during the bias refresh period BP can be the same as the waveforms of the emission scan signal En and the bypass scan signal GBn during the data write period WP. Therefore, since the emission waveform of the light-emitting diode LD during the low-frequency driving period is similar to the emission waveform during the high-frequency driving period, the user does not recognize flickering.

[0100] However, the bias refresh period BP is different from the data write period WP in that the initialization scan signal GIn, the compensation scan signal GCn, and the write scan signal GWn maintain an off level in the bias refresh period BP.

[0101] In the bias refresh period BP, the data voltage Dm may be maintained at the reference voltage Vref. For another example, the data voltage Dm may not be supplied, or may be supplied at a different voltage level regardless of the grayscale of the pixel PXnm.

[0102] The period 1TP in which the pixel unit 50 is driven in the first display mode may be referred to as a first period (see Figure 3 The period 1TP in which the pixel unit 50 is driven in the second display mode may be referred to as a second period (see Figure 5 ). In this case, the time interval of the first period and the time interval of the second period may be the same.

[0103] The plurality of write stages may supply a write scan signal GWn of a turn-on level in a first cycle during a first period. Figure 3 and Figure 4 , the write scan signal GWn of the conductive level supplied may be proportional to the number of data write periods WP in the first period. The plurality of write stages may supply the write scan signal GWn of the conductive level in the second cycle during the second period. For example, referring to Figure 5 and Figure 6 The supply of the on-level write scan signal GWn may be proportional to the number of data write periods WP in the second period. The number of data write periods WP included in the second period is less than the number of data write periods WP included in the first period. Therefore, the first period is shorter than the second period.

[0104] Figure 7 is a diagram for describing a display device in which a substrate includes a recess according to an exemplary embodiment of the inventive concept.

[0105] Reference Figure 7 , the substrate SUB of the display device 9 may include a notch NT. The substrate SUB may include a first pixel region 501 located on a first side of the notch NT, a second pixel region 502 located on a second side of the notch NT, and a third pixel region 503 located on a third side of the notch NT. In addition, the substrate SUB may further include a first peripheral region PA1 located on the outer sides of the first pixel region 501 and the second pixel region 502, and a second peripheral region PA2 located on the outer sides of the third pixel region 503 and the second pixel region 502. For ease of description, it is assumed that the outer side of the substrate SUB and the notch NT are angled, but in another exemplary embodiment of the inventive concept, the outer side of the substrate SUB and the notch NT may be curved.

[0106] The first pixel region 501 may contact the second pixel region 502 and the first peripheral area PA1, and may be spaced apart from the third pixel region 503 and the second peripheral area PA2. The third pixel region 503 may contact the second pixel region 502 and the second peripheral area PA2, and may be spaced apart from the first pixel region 501 and the first peripheral area PA1. For example, the first pixel region 501 and the third pixel region 503 may be spaced apart from each other by a notch NT. The first pixel region 501 may have a first width W1. The second pixel region 502 may have a second width W2 that is wider than the first width W1. The third pixel region 503 may have a third width W3 that is narrower than the second width W2. The third width W3 may be the same as the first width W1, or the third width W3 and the first width W1 may be different.

[0107] The first scan driver 30 may be installed in the first peripheral area PA1. In another exemplary embodiment of the inventive concept, only pad electrodes connected to the first scan driver 30 may be installed in the first peripheral area PA1. In this case, the first scan driver 30 may be installed on an external circuit board and may be electrically connected to the pad electrodes.

[0108] The second scan driver 40 may be installed in the second peripheral area PA2. In another exemplary embodiment of the inventive concept, only the pad electrodes connected to the second scan driver 40 may be installed in the second peripheral area PA2. In this case, the second scan driver 40 may be installed on an external circuit board and may be electrically connected to the pad electrodes.

[0109] The first pixel region 501 and the third pixel region 503 may include pixels connected to the same write scan line. Pixels located on the same horizontal line may be connected to the same write scan line, the same compensation scan line, the same bypass scan line, the same initialization scan line, and the same emission scan line. For example, Figure 7 Pixels PX11, PX12, and PX1p in the top row shown in FIG can be connected to the same write scan line GWL1, the same compensation scan line, the same bypass scan line, the same initialization scan line, and the same emission scan line. Here, p can be an integer greater than 0. In addition, for example, pixels PX51, PX52, and PX5p can be connected to the same write scan line GWL5, the same compensation scan line, the same bypass scan line, the same initialization scan line, and the same emission scan line. The number of pixels PX11, PX12, and PX1p connected to the write scan line GWL1 can be the same as the number of pixels PX51, PX52, and PX5p connected to the write scan line GWL5. However, for example, when the outer side of the substrate SUB is bent, the number of pixels PX11, PX12, and PX1p can be different from the number of pixels PX51, PX52, and PX5p.

[0110] The pixels PX91, PX92, PX9s, and PX9q of the second pixel region 502 can be connected to the same write scan line GWL9, the same compensation scan line, the same bypass scan line, the same initialization scan line, and the same emission scan line. In addition, the pixels PX131, PX132, PX13s, and PX13q of the second pixel region 502 can be connected to the same write scan line GWL13, the same compensation scan line, the same bypass scan line, the same initialization scan line, and the same emission scan line.

[0111] The number of pixels PX91, PX92, PX9s, and PX9q connected to the same write scan line GWL9 in the second pixel region 502 may be greater than the number of pixels PX11, PX12, and PX1p connected to the same write scan line GWL1 in the first pixel region 501 and the third pixel region 503. In other words, q may be an integer greater than p. For example, as the width of the notch NT increases, the difference between q and p may increase.

[0112] The number of pixels PX11 , PX51 , PX91 , and PX131 connected to the same data line DL1 in the first and second pixel regions 501 and 502 may be greater than the number of pixels PX9 s and PX13 s connected to the same data line DLs in the second pixel region 502 .

[0113] For ease of description, Figure 7 , pixels PX11, PX51, PX91, and PX131 are sequentially connected to data line DL1. However, additional pixels may be connected to data line DL1 between pixels PX11, PX51, PX91, and PX131. In addition, data line DL1 may also extend below pixel PX131, and additional pixels may also be connected to the extended data line DL1. Figure 8 and Figure 9 This description is applicable to the other data lines DL2, DLs, and DLq.

[0114] Figure 8 is a diagram for describing a relationship between a first scan driver and a first pixel region according to an exemplary embodiment of the inventive concept. Figure 9 is a diagram for describing a relationship between a first scan driver and a second pixel region according to an exemplary embodiment of the inventive concept. Figure 10 is a diagram for describing a relationship between a second scan driver and a third pixel region according to an exemplary embodiment of the inventive concept. Figure 11 is a diagram for describing a relationship between a second scan driver and a second pixel region according to an exemplary embodiment of the inventive concept.

[0115] In the first pixel region 501 and the third pixel region 503, the first pixels PX51, PX52, and PX5p can be connected to the first write scan line GWL5 and the first compensation scan line GCL5. The second pixels PX61, PX62, and PX6p can be connected to the second write scan line GWL6 and the second compensation scan line GCL6. The third pixels PX71, PX72, and PX7p can be connected to the third write scan line GWL7 and the third compensation scan line GCL7. The fourth pixels PX81, PX82, and PX8p can be connected to the fourth write scan line GWL8 and the fourth compensation scan line GCL8. The first pixel region 501 and the third pixel region 503 may also include pixels PX11 to PX1p, PX21 to PX2p, PX31 to PX3p, and PX41 to PX4p.

[0116] In the second pixel region 502, the fifth pixels PX91, PX92, PX9s, and PX9q may be connected to the fifth write scan line GWL9 and the fifth compensation scan line GCL9. The sixth pixels PX101, PX102, and PX10q may be connected to the sixth write scan line GWL10 and the sixth compensation scan line GCL10. The seventh pixels PX111, PX112, and PX11q may be connected to the seventh write scan line GWL11 and the seventh compensation scan line GCL11. The eighth pixels PX121, PX122, and PX12q may be connected to the eighth write scan line GWL12 and the eighth compensation scan line GCL12. The number of the first pixels PX51, PX52, and PX5p may be less than the number of the fifth pixels PX91, PX92, PX9s, and PX9q. The second pixel region 502 may further include pixels PX131 to PX13q, PX141 to PX14q, PX151 to PX15q, and PX161 to PX16q.

[0117] The first compensation scan line GCL5, the second compensation scan line GCL6, the third compensation scan line GCL7, and the fourth compensation scan line GCL8 can be connected to a first node. The fifth compensation scan line GCL9 and the sixth compensation scan line GCL10 can be connected to a second node. The seventh compensation scan line GCL11 and the eighth compensation scan line GCL12 can be connected to a third node. In this case, the first node, the second node, and the third node can be electrically different nodes.

[0118] For example, the output terminal of the first compensation stage STC5-6 can be connected to the first node. The second compensation stage STC7-8 can be connected to the first compensation stage STC5-6 through the first compensation carry line CC5-6. The third compensation stage STC9-10 can be connected to the second compensation stage STC7-8 through the second compensation carry line CC7-8, and its output terminal can be connected to the second node. The fourth compensation stage STC11-12 can be connected to the third compensation stage STC9-10 through the third compensation carry line CC9-10, and its output terminal can be connected to the third node. The first scan driver 30 may further include compensation stages STC1-2, STC3-4, STC13-14, and STC15-16.

[0119] The first write scan line GWL5, the second write scan line GWL6, the third write scan line GWL7, the fourth write scan line GWL8, the fifth write scan line GWL9, the sixth write scan line GWL10, the seventh write scan line GWL11 and the eighth write scan line GWL12 can be connected to electrically different nodes.

[0120] For example, the output terminal of the first write stage STW5a can be connected to the first write scan line GWL5. The second write stage STW6a can be connected to the first write stage STW5a via the first write carry line CW5a, and the output terminal of the second write stage STW6a can be connected to the second write scan line GWL6. The third write stage STW7a can be connected to the second write stage STW6a via the second write carry line CW6a, and the output terminal of the third write stage STW7a can be connected to the third write scan line GWL7. The fourth write stage STW8a can be connected to the third write stage STW7a via the third write carry line CW7a, and the output terminal of the fourth write stage STW8a can be connected to the fourth write scan line GWL8.

[0121] The fifth write stage STW9a can be connected to the fourth write stage STW8a via the fourth write carry line CW8a, and the output terminal of the fifth write stage STW9a can be connected to the fifth write scan line GWL9. The sixth write stage STW10a can be connected to the fifth write stage STW9a via the fifth write carry line CW9a, and the output terminal of the sixth write stage STW10a can be connected to the sixth write scan line GWL10. The seventh write stage STW11a can be connected to the sixth write stage STW10a via the sixth write carry line CW10a, and the output terminal of the seventh write stage STW11a can be connected to the seventh write scan line GWL11. The eighth write stage STW12a can be connected to the seventh write stage STW11a via the seventh write carry line CW11a, and the output terminal of the eighth write stage STW12a can be connected to the eighth write scan line GWL12. The first scan driver 30 may further include write stages STW1a to STW4a and STW13a to STW16a.

[0122] The first initialization stages STI5-6 may have output terminals connected to the first pixels PX51, PX52, and PX5p through the first initialization scan line GIL5 and to the second pixels PX61, PX62, and PX6p through the second initialization scan line GIL6. For example, the line connecting the first initialization stage STI5-6 to the first pixel PX5p may have a branch connected to the second pixel PX6p. The second initialization stages STI7-8 may have output terminals connected to the third pixels PX71, PX72, and PX7p through the third initialization scan line GIL7 and to the fourth pixels PX81, PX82, and PX8p through the fourth initialization scan line GIL8. The third initialization stages STI9-10 may have output terminals connected to the fifth pixels PX91, PX92, PX9s, and PX9q through the fifth initialization scan line GIL9 and to the sixth pixels PX101, PX102, and PX10q through the sixth initialization scan line GIL10. The fourth initialization stage ST11 - 12 may have output terminals connected to seventh pixels PX111 , PX112 , and PX11q through a seventh initialization scan line GIL11 and to eighth pixels PX121 , PX122 , and PX12q through an eighth initialization scan line GIL12 .

[0123] The second initialization stages STI7-8 can be connected to the first initialization stages STI5-6 via the first initialization carry lines CI5-6. For example, the first initialization carry lines CI5-6 can be directly connected to each of the second initialization stages STI7-8 and the first initialization stages STI5-6. The third initialization stages STI9-10 can be connected to the second initialization stages STI7-8 via the second initialization carry lines CI7-8. The fourth initialization stages STI11-12 can be connected to the third initialization stages STI9-10 via the third initialization carry lines CI9-10. The second scan driver 40 may further include initialization stages STI1-2, STI3-4, STI13-14, and STI15-16.

[0124] The first emission stages STE5-6 may have output terminals connected to the first pixels PX51, PX52, and PX5p through the first emission scan line EL5 and to the second pixels PX61, PX62, and PX6p through the second emission scan line EL6. The second emission stages STE7-8 may have output terminals connected to the third pixels PX71, PX72, and PX7p through the third emission scan line EL7 and to the fourth pixels PX81, PX82, and PX8p through the fourth emission scan line EL8. The third emission stages STE9-10 may have output terminals connected to the fifth pixels PX91, PX92, PX9s, and PX9q through the fifth emission scan line EL9 and to the sixth pixels PX101, PX102, and PX10q through the sixth emission scan line EL10. The fourth emission stage STE11-12 may have an output terminal connected to the seventh pixels PX111, PX112, and PX11q through the seventh emission scan line EL11 and to the eighth pixels PX121, PX122, and PX12q through the eighth emission scan line EL12.

[0125] The second emitter stages STE7-8 can be connected to the first emitter stages STE5-6 via first emission carry lines CE5-6. For example, the first emission carry lines CE5-6 can be directly connected between the second emitter stages STE7-8 and the first emitter stages STE5-6. The third emitter stages STE9-10 can be connected to the second emitter stages STE7-8 via second emission carry lines CE7-8. The fourth emitter stages STE11-12 can be connected to the third emitter stages STE9-10 via third emission carry lines CE9-10. The second scan driver 40 may further include emitter stages STE1-2, STE3-4, STE13-14, and STE15-16.

[0126] The first bypass stages STB5-6 may have output terminals connected to the first pixels PX51, PX52, and PX5p through the first bypass scan line GBL5 and to the second pixels PX61, PX62, and PX6p through the second bypass scan line GBL6. The second bypass stages STB7-8 may have output terminals connected to the third pixels PX71, PX72, and PX7p through the third bypass scan line GBL7 and to the fourth pixels PX81, PX82, and PX8p through the fourth bypass scan line GBL8. The third bypass stages STB9-10 may have output terminals connected to the fifth pixels PX91, PX92, PX9s, and PX9q through the fifth bypass scan line GBL9 and to the sixth pixels PX101, PX102, and PX10q through the sixth bypass scan line GBL10. The fourth bypass stage STB11 - 12 may have output terminals connected to seventh pixels PX111 , PX112 , and PX11q through a seventh bypass scan line GBL11 and to eighth pixels PX121 , PX122 , and PX12q through an eighth bypass scan line GBL12 .

[0127] The second bypass stage STB7-8 can be connected to the first bypass stage STB5-6 through the first bypass carry line CB5-6. For example, the first bypass carry line CB5-6 can be directly connected between the second bypass stage STB7-8 and the first bypass stage STB5-6. The third bypass stage STB9-10 can be connected to the second bypass stage STB7-8 through the second bypass carry line CB7-8. The fourth bypass stage STB11-12 can be connected to the third bypass stage STB9-10 through the third bypass carry line CB9-10. The first scan driver 30 can also include bypass stages STB1-2, STB3-4, STB13-14 and STB15-16.

[0128] The other stages and pixels also have similar structures, so repeated descriptions are omitted. However, in the first scan driver 30, since there is no previous write stage, the write stage STW1a can receive the write start signal via the write start line FWLa instead of the write carry line. Since there is no previous compensation stage, the compensation stages STC1-2 can receive the compensation start signal via the compensation start line FCL instead of the compensation carry line. Since there is no previous bypass stage, the bypass stages STB1-2 can receive the bypass start signal via the bypass start line FBL instead of the bypass carry line.

[0129] In addition, in the second scan driver 40, since there is no previous write stage, the write stage STW1b can receive the write start signal via the write start line FWLb instead of the write carry line. Since there is no previous initialization stage, the initialization stages STI1-2 can receive the initialization start signal via the initialization start line FIL instead of the initialization carry line. Since there is no previous emission stage, the emission stages STE1-2 can receive the emission stop signal via the emission stop line FEL instead of the emission carry line.

[0130] according to Figures 7 to 11 In an exemplary embodiment of the inventive concept shown in FIG, a display device may include: a first pixel PX51 connected to a first write scan line GWL5 and a first compensation scan line GCL5; a second pixel PX61 connected to a second write scan line GWL6 and a second compensation scan line GCL6; a third pixel PX71 connected to a third write scan line GWL7 and a third compensation scan line GCL7; a fourth pixel PX81 connected to a fourth write scan line GWL8 and a fourth compensation scan line GCL8; a fifth pixel PX91 connected to a fifth write scan line GWL9 and a fifth compensation scan line GCL9; a sixth pixel PX101 connected to a sixth write scan line GWL10 and a sixth compensation scan line GCL10; a seventh pixel PX111 connected to a seventh write scan line GWL11 and a seventh compensation scan line GCL11; and an eighth pixel PX121 connected to an eighth write scan line GWL12 and an eighth compensation scan line GCL12.

[0131] like Figure 7 As shown in , the number of the first pixels PX51 . . . is less than the number of the fifth pixels PX91 . . . Figure 8 and Figure 9 As shown in , the first compensation scan line GCL5, the second compensation scan line GCL6, the third compensation scan line GCL7 and the fourth compensation scan line GCL8 are connected to the first node (for example, at the output of STC5-6), the fifth compensation scan line GCL9 and the sixth compensation scan line GCL10 are connected to the second node (for example, at the output of STC9-10), the seventh compensation scan line GCL11 and the eighth compensation scan line GCL12 are connected to the third node (for example, at the output of STC11-12), and the first node, the second node and the third node are different nodes.

[0132] Figure 12 and Figure 13 is a diagram for describing a driving method of a first pixel region and a second pixel region according to an exemplary embodiment of the inventive concept.

[0133] During the first period P1 , the first initialization stage STI5 - 6 may apply an initialization scan signal GI5 - 6 of a turn-on level to the first and second initialization scan lines GIL5 and GIL6 .

[0134] During a second period P2 following the first period P1, the first compensation stages STC5-6 may apply compensation scan signals GC5-8 of a turn-on level to the first, second, third, and fourth compensation scan lines GCL5, GCL6, GCL7, and GCL8. The first compensation stages STC5-6 may provide compensation carry signals to the second compensation stages STC7-8 through the first compensation carry lines CC5-6.

[0135] Since the second compensation stages STC7-8 receive the compensation carry signal but have no compensation scan line connected thereto, the second compensation stages STC7-8 do not supply the compensation scan signal of the on level. The second compensation stages STC7-8 provide the compensation carry signal to the third compensation stages STC9-10 through the second compensation carry line CC7-8.

[0136] During the third period P3, the third compensation stages STC9-10 may apply a compensation scan signal GC9-10 of a turn-on level to the fifth and sixth compensation scan lines GCL9 and GCL10. The third compensation stages STC9-10 provide a compensation carry signal to the fourth compensation stages STC11-12 through the third compensation carry line CC9-10.

[0137] During the fourth period P4, the fourth compensation stages STC11-12 may apply a compensation scan signal GC11-12 of a conduction level to the seventh and eighth compensation scan lines GCL11 and GCL12. The fourth compensation stages STC11-12 provide a compensation carry signal to the fifth compensation stages STC13-14 via the fourth compensation carry lines CC11-12. Since the operation of the fifth compensation stages STC13-14 and subsequent compensation stages is the same as described above, repeated description will be omitted.

[0138] According to the present embodiment, the period in which the second period P2 and the third period P3 overlap is shorter than the period in which the third period P3 and the fourth period P4 overlap. For example, during the period other than the third period P3 in the second period P2, the first write stages STW5a and STW5b, the second write stages STW6a and STW6b, the third write stages STW7a and STW7b, and the fourth write stages STW8a and STW8b can sequentially output write scan signals GW5, GW6, GW7, and GW8 of the on-level. For example, the write scan signals GW5, GW6, GW7, and GW8 can be turned low during the second period P2 before the third period P3. On the other hand, during the period other than the fourth period P4 in the third period P3, the fifth write stages STW9a and STW9b and the sixth write stages STW10a and STW10b can sequentially output write scan signals GW9 and GW10 of the on-level. In this case, the write scan signals GW9 and GW10 are turned low in the third period P3 before the fourth period P4.

[0139] According to this embodiment, the compensation scan lines of the first pixel region 501 and the third pixel region 503 simultaneously supply the compensation scan signals of the ON level to four pixel rows. In this case, the compensation scan line of the second pixel region 502 simultaneously supplies the compensation scan signals of the ON level to two pixel rows.

[0140] In another exemplary embodiment of the inventive concept, the compensation scan lines of the first pixel region 501 and the third pixel region 503 can simultaneously supply the compensation scan signals of the conduction level to u pixel rows. In this case, the compensation scan lines of the second pixel region 502 can simultaneously supply the compensation scan signals of the conduction level to v pixel rows. In this case, v can be an integer greater than 0. Here, u can be an integer greater than v. In an exemplary embodiment of the inventive concept in which the supply period of the compensation carry signal is constant, u can be an integer multiple of v.

[0141] According to these exemplary embodiments of the inventive concept, a resistance-capacitance (RC) delay of the compensation scan signal can be increased in the first pixel region 501 and the third pixel region 503, where the number of pixels in each pixel row is relatively small. Therefore, the RC delay of the compensation scan signal can be matched in the first pixel region 501, the second pixel region 502, and the third pixel region 503. Therefore, a load matching capacitor for the compensation scan signal is not required, and thus the size of the non-display area can be reduced.

[0142] During the fourth period P4, the seventh write stages STW11a and STW11b and the eighth write stages STW12a and STW12b may sequentially output the write scan signals GW11 and GW12 of the on level. In this case, the write scan signals GW11 and GW12 turn low in the fourth period P4.

[0143] During the fifth period P5, return to the reference Figure 12 , the first emission stage STE5-6 may apply the emission scan signal E5-6 of the off level to the first emission scan line EL5 and the second emission scan line EL6. The fifth period P5 may include the first period P1 and the second period P2.

[0144] During the sixth period P6a or P6b, the first bypass stage STB5-6 may apply the on-level bypass scan signal GB5-6 to the first and second bypass scan lines GBL5 and GBL6. The sixth period P6a or P6b may overlap with the fifth period P5 and may not overlap with the first and second periods P1 and P2.

[0145] Figure 14 is a diagram for describing a display device in which a substrate includes a hole according to an exemplary embodiment of the inventive concept.

[0146] Reference Figure 14 , substrate SUB' and Figure 7 The substrate SUB of FIG. 1 is different in that the substrate SUB′ includes the hole HL but does not include the notch NT.

[0147] The substrate SUB' may further include a fourth pixel region 504. The fourth pixel region 504 may contact the first pixel region 501, the first peripheral region PA1', the third pixel region 503, and the second peripheral region PA2'. Furthermore, the fourth pixel region 504 may be spaced apart from the second pixel region 502. The width of the fourth pixel region 504 may be the same as the width of the second pixel region 502.

[0148] The pixels PXR1 , PXR2 , PXRs, and PXRq of the fourth pixel region 504 may be connected to the same write scan line GWLR, the same compensation scan line, the same bypass scan line, the same initialization scan line, and the same emission scan line.

[0149] The number of pixels PXR1, PXR2, PXRs, and PXRq connected to the same write scan line GWLR in the fourth pixel region 504 may be greater than the number of pixels PX11, PX12, and PX1p connected to the same write scan line GWL1 in the first pixel region 501 and the third pixel region 503. In other words, q may be an integer greater than p. For example, as the width of the hole HL increases, the difference between q and p may increase.

[0150] The number of pixels PX11, PX51, PX91, and PX131 connected to the same data line DL1 in the first and second pixel regions 501 and 502 may be greater than the number of pixels PXRs, PX9s, and PX13s connected to the same data line DLs in the second and fourth pixel regions 502 and 504.

[0151] All the above embodiments can be applied to Figure 14 For example, the connection relationship between the pixels PXR1 to PXRq of the fourth pixel region 504 and the scan drivers 30 ′ and 40 ′ may be substantially the same as the connection relationship between the pixels PX91 to PX9q of the second pixel region 502 and the scan drivers 30 and 40 .

[0152] Even when the notch NT and the hole HL do not exist in the substrates SUB and SUB′, according to exemplary embodiments of the above-described inventive concepts, load matching occurring due to a difference between the numbers of pixels included in pixel rows may be resolved.

[0153] A display device according to an exemplary embodiment of the inventive concept can minimize or remove a non-display area by distributing drivers and minimizing or removing a load matching capacitor.

[0154] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A display device, comprising: A substrate comprising a first pixel region, a second pixel region, a third pixel region, and a recess or a hole, wherein the first pixel region and the third pixel region are arranged in a first direction, and the recess or the hole is provided between the first pixel region and the third pixel region, the first pixel region and the second pixel region are arranged in a second direction intersecting the first direction, the third pixel region and the second pixel region are arranged in the second direction, the first pixel region contacts the second pixel region, and the third pixel region contacts the second pixel region, and wherein, in the first direction, a width of the second pixel region is greater than a sum of a width of the first pixel region and a width of the third pixel region, a first pixel positioned in a first row and connected to a first write scan line and a first compensation scan line; a second pixel positioned in a second row and connected to a second write scan line and a second compensation scan line; a third pixel positioned in a third row and connected to a third write scan line and a third compensation scan line; a fourth pixel positioned in a fourth row and connected to a fourth write scan line and a fourth compensation scan line; a fifth pixel positioned in a fifth row and connected to a fifth write scan line and a fifth compensation scan line; a sixth pixel positioned in a sixth row and connected to a sixth write scan line and a sixth compensation scan line; a seventh pixel positioned in a seventh row and connected to a seventh write scan line and a seventh compensation scan line; and an eighth pixel, positioned in the eighth row and connected to the eighth writing scan line and the eighth compensation scan line, wherein some of the first pixel, the second pixel, the third pixel, and the fourth pixel are positioned in the first pixel region, and the remaining pixels of the first pixel, the second pixel, the third pixel, and the fourth pixel are positioned in the third pixel region, The fifth pixel, the sixth pixel, the seventh pixel, and the eighth pixel are located in the second pixel area. Each of the first pixel, the second pixel, the third pixel, the fourth pixel, the fifth pixel, the sixth pixel, the seventh pixel, and the eighth pixel includes a first transistor, a second transistor, and a third transistor, the second transistor includes a first electrode connected to a corresponding data line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a corresponding write scan line, the third transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a corresponding compensation scan line, The number of the first pixels is smaller than the number of the fifth pixels, The first compensation scan line, the second compensation scan line, the third compensation scan line, and the fourth compensation scan line are connected to a first node, The fifth compensation scan line and the sixth compensation scan line are connected to a second node, The seventh compensation scan line and the eighth compensation scan line are connected to a third node, and The first node, the second node, and the third node are different nodes, the first write scan line, the second write scan line, the third write scan line, the fourth write scan line, the fifth write scan line, the sixth write scan line, the seventh write scan line, and the eighth write scan line are separated from each other, and Wherein, the display device further includes: a first compensation stage having an output terminal connected to the first node and configured to apply a compensation scan signal to the first compensation scan line, the second compensation scan line, the third compensation scan line, and the fourth compensation scan line connected to the first node during a second period; a second compensation stage connected to the first compensation stage; a third compensation stage connected to the second compensation stage and having an output terminal connected to the second node, and configured to apply a compensation scan signal to the fifth compensation scan line and the sixth compensation scan line connected to the second node during a third period; and a fourth compensation stage connected to the third compensation stage and having an output terminal connected to the third node, and configured to apply a compensation scan signal to the seventh compensation scan line and the eighth compensation scan line connected to the third node during a fourth period, The second period is after a first period in which a gate electrode of a first transistor of each of the first pixel and the second pixel is initialized.

2. The display device according to claim 1, further comprising: a first writing stage having an output terminal connected to the first writing scan line; a second writing stage connected to the first writing stage and having an output terminal connected to the second writing scan line; a third writing stage connected to the second writing stage and having an output terminal connected to the third writing scan line; a fourth writing stage connected to the third writing stage and having an output terminal connected to the fourth writing scan line; a fifth writing stage connected to the fourth writing stage and having an output terminal connected to the fifth writing scan line; a sixth writing stage connected to the fifth writing stage and having an output terminal connected to the sixth writing scan line; a seventh writing stage connected to the sixth writing stage and having an output terminal connected to the seventh writing scan line; as well as The eighth writing stage is connected to the seventh writing stage and has an output terminal connected to the eighth writing scanning line.

3. The display device according to claim 2, further comprising: a first initialization stage having an output terminal connected to the first pixel and the second pixel; a second initialization stage having an output terminal connected to the third pixel and the fourth pixel; a third initialization stage having an output terminal connected to the fifth pixel and the sixth pixel; as well as A fourth initialization stage has an output terminal connected to the seventh pixel and the eighth pixel.

4. The display device according to claim 3, wherein the second initialization stage is connected to the first initialization stage, The third initialization stage is connected to the second initialization stage, and The fourth initialization stage is connected to the third initialization stage.

5. The display device according to claim 4, further comprising: a first emitting stage having an output terminal connected to the first pixel and the second pixel; a second emission stage having an output terminal connected to the third pixel and the fourth pixel; a third emission stage having an output terminal connected to the fifth pixel and the sixth pixel; as well as The fourth emission stage has an output terminal connected to the seventh pixel and the eighth pixel. The display device according to claim 5 , wherein: the second emitting stage is connected to the first emitting stage, The third emitter stage is connected to the second emitter stage, and The fourth emitting stage is connected to the third emitting stage.

7. The display device according to claim 6, further comprising: a first bypass stage having an output terminal connected to the first pixel and the second pixel; a second bypass stage having an output terminal connected to the third pixel and the fourth pixel; a third bypass stage having an output terminal connected to the fifth pixel and the sixth pixel; as well as The fourth bypass stage has an output terminal connected to the seventh pixel and the eighth pixel.

8. The display device according to claim 7, wherein: the second bypass stage is connected to the first bypass stage, The third bypass stage is connected to the second bypass stage, and The fourth bypass stage is connected to the third bypass stage.

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