Semiconductor device structure and manufacturing method thereof

Abstract

A semiconductor device structure includes first, second, and third gate electrode layers, first and second dielectric features, a first seed layer, a first conductor layer, a second seed layer, a second conductor layer, and a dielectric material. The first dielectric feature is disposed between the first and second gate electrode layers. The second dielectric feature is disposed between the second and third gate electrode layers. The first seed layer contacts the first gate electrode layer, the first dielectric feature, and the second gate electrode layer. The first conductor layer is disposed on the first seed layer. The second seed layer contacts the third gate electrode layer. The second conductor layer is disposed on the second seed layer. The dielectric material is disposed on the second dielectric feature, the first and second conductor layers. The dielectric material is between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor device structure and a method for manufacturing the same, and more particularly, to a semiconductor device structure including a seed layer. Background Art

[0002] The growth of semiconductor integrated circuits (ICs) has been rapid. Advances in IC materials and design have resulted in each generation of circuits becoming smaller and more complex than the previous one. As ICs advance, as geometry (e.g., the smallest component or line that can be produced using a manufacturing process) decreases, functional density (e.g., the number of devices per chip area) generally increases. This scaling process typically offers the advantages of increased throughput and lowered costs, but it also increases the difficulty of producing ICs.

[0003] Therefore, the manufacturing process of integrated circuits needs to be further optimized. Summary of the Invention

[0004] One embodiment provides a semiconductor device structure. The semiconductor device includes a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, a first dielectric feature, a second dielectric feature, a first seed layer, a first conductor layer, a second seed layer, a second conductor layer, and a dielectric material. The second gate electrode layer is adjacent to the first gate electrode layer. The third gate electrode layer is adjacent to the second gate electrode layer. The first dielectric feature is disposed between the first gate electrode layer and the second gate electrode layer. The second dielectric feature is disposed between the second gate electrode layer and the third gate electrode layer. The first seed layer contacts the first gate electrode layer, the first dielectric feature, and the second gate electrode layer. The first conductor layer is disposed on the first seed layer. The second seed layer contacts the third gate electrode layer. The second conductor layer is disposed on the second seed layer. The dielectric material is disposed on the second dielectric feature, the first conductor layer, and the second conductor layer, wherein the dielectric material is disposed between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer.

[0005] An embodiment provides a semiconductor device structure. The semiconductor device structure includes a first gate electrode layer, a second gate electrode layer, a dielectric feature, a first seed layer, a first conductor layer, a second seed layer, a second conductor layer, and a third dielectric material. The second gate electrode layer is adjacent to the first gate electrode layer. The dielectric feature is disposed between the first gate electrode layer and the second gate electrode layer, wherein the dielectric feature includes a liner layer, a first dielectric material, and a second dielectric material. The first dielectric material is disposed on the liner layer. The second dielectric material is disposed on the liner layer and the first dielectric material. A first seed layer is disposed on the first gate electrode layer. A first conductor layer is disposed on the first seed layer. A second seed layer is disposed on the second gate electrode layer. A second conductor layer is disposed on the second seed layer. The third dielectric material is disposed between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer.

[0006] An embodiment provides a semiconductor device structure. The semiconductor device structure includes a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, a first dielectric feature, a second dielectric feature, a first conductor layer, a second conductor layer, a first dielectric material, and a conductor feature. The second gate electrode layer is adjacent to the first gate electrode layer. The third gate electrode layer is adjacent to the second gate electrode layer. The first dielectric feature is disposed between the first gate electrode layer and the second gate electrode layer. The second dielectric feature is disposed between the second gate electrode layer and the third gate electrode layer. A first conductor layer is disposed on the first gate electrode layer. A second conductor layer is disposed on the second gate electrode layer and the third gate electrode layer, wherein the second conductor layer is electrically connected to the second gate electrode layer and the third gate electrode layer. A first dielectric material is disposed on the first dielectric feature, the first conductor layer, and the second conductor layer, wherein the first dielectric material is disposed between the first conductor layer and the second conductor layer. The conductor feature is disposed in the first dielectric material and contacts the second conductor layer.

[0007] An embodiment provides a method for fabricating a semiconductor device structure, comprising forming a first fin and a second fin from a substrate, wherein the first fin comprises a plurality of first semiconductor layers and the second fin comprises a plurality of second semiconductor layers. A dielectric feature is formed between the first fin and the second fin. A gate electrode layer is formed to surround the first semiconductor layer and the second semiconductor layer. A seed layer is formed on the gate electrode layer and the dielectric feature. A conductor layer is formed on the seed layer. A first opening is formed in the seed layer and the conductor layer to expose the dielectric feature. A first dielectric material is formed in the first opening over the dielectric feature.

[0008] An embodiment provides a method for manufacturing a semiconductor device structure, comprising forming a first fin and a second fin from a substrate. Forming a dielectric feature between the first fin and the second fin. Forming a gate electrode layer on the substrate, wherein the gate electrode layer is located at the bottom of a trench formed between two interlayer dielectric layers. Forming a seed layer on the gate electrode layer, on the dielectric feature, on the two interlayer dielectric layers, and at two adjacent interlayer dielectric layers. Removing portions of the seed layer formed on the two interlayer dielectric layers and at two adjacent interlayer dielectric layers. Forming a conductor layer on the seed layer. Forming an opening in the seed layer and the conductor layer to expose the dielectric feature. Forming a first dielectric material in the opening on the dielectric feature.

[0009] An embodiment provides a method for fabricating a semiconductor device structure, comprising forming a first gate electrode layer and a second gate electrode layer on a substrate; forming a seed layer on the first gate electrode layer and the second gate electrode layer; depositing a conductor layer on the seed layer; forming openings in the seed layer and the conductor layer, wherein a first portion of the first gate electrode layer and a first portion of the second gate electrode layer are exposed, and a second portion of the first gate electrode layer and a second portion of the second gate electrode layer contact the seed layer; and depositing a first dielectric material in the openings over and contacting the first gate electrode layer and the second gate electrode layer.

[0010] An embodiment provides a method for fabricating a semiconductor device structure, comprising forming a first fin and a second fin from a substrate; forming a dielectric feature between the first fin and the second fin; forming a gate electrode layer on the substrate and adjacent to the dielectric feature; forming a seed layer on the gate electrode layer and on the dielectric feature; forming a conductor layer on the seed layer; forming an opening in the seed layer and the conductor layer to expose the dielectric feature; and forming a first dielectric material in the opening over the dielectric feature.

[0011] An embodiment provides a method for manufacturing a semiconductor device structure, comprising forming a gate electrode layer on a substrate. Recessing the gate electrode layer, wherein the gate electrode layer is located at the bottom of a trench formed between two interlayer dielectric layers. Forming a seed layer on the gate electrode layer, on the two interlayer dielectric layers, and at two adjacent interlayer dielectric layers, wherein a portion of the seed layer formed on the gate electrode layer has a first thickness, and a portion of the seed layer formed at the two adjacent interlayer dielectric layers has a second thickness less than the first thickness. Removing a portion of the seed layer formed at the two adjacent interlayer dielectric layers. Forming a mask layer on the gate electrode layer and on the seed layer on the two interlayer dielectric layers. Removing a portion of the mask layer to expose a portion of the seed layer formed on the two interlayer dielectric layers. Removing the exposed portion of the seed layer. Removing the mask layer. Forming a conductor layer on the seed layer.

[0012] One embodiment provides a semiconductor device structure comprising a first gate electrode layer, a second gate electrode layer, a dielectric feature, a first seed layer, a first conductor layer, a second seed layer, a second conductor layer, and a first dielectric material. The second gate electrode layer is adjacent to the first gate electrode layer. The dielectric feature is disposed between the first gate electrode layer and the second gate electrode layer. The first seed layer is disposed on the first gate electrode layer. The first conductor layer is disposed on the first seed layer. The second seed layer is disposed on the second gate electrode layer. The second conductor layer is disposed on the second seed layer. The first dielectric material is disposed between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer, wherein the first dielectric material contacts the dielectric feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0014] Figures 1 to 18 is a perspective view of a semiconductor device structure at various manufacturing stages according to some embodiments;

[0015] Figures 19 to 20 According to some embodiments, in each manufacturing stage of a semiconductor device structure, Figure 18 A cross-sectional view of line AA in FIG;

[0016] Figure 21 According to some embodiments Figure 20 A top view of a semiconductor device structure;

[0017] Figures 22A to 22C According to some embodiments, in each manufacturing stage of the semiconductor device structure, Figure 21 Cross-sectional view along lines BB, CC, and DD;

[0018] 23A to 30A According to some embodiments, in each manufacturing stage of a semiconductor device structure, Figure 21 A cross-sectional view of line AA in FIG;

[0019] Figures 23B to 30B According to some embodiments, in each manufacturing stage of a semiconductor device structure, Figure 21 A cross-sectional view along line BB in FIG.

[0020] Figures 23C to 30C According to some embodiments, in each manufacturing stage of a semiconductor device structure, Figure 21 A cross-sectional view taken along line CC in FIG.

[0021] Figures 23D to 30DAccording to some embodiments, in each manufacturing stage of a semiconductor device structure, Figure 21 A cross-sectional view taken along line DD in FIG.

[0022] Figure 31 According to some embodiments, during one of the manufacturing stages of a semiconductor device structure, Figure 21 Cross-sectional view along line AA.

[0023]

Explanation of symbols

[0024] 100:Semiconductor device structure

[0025] 101:Substrate

[0026] 102a: substrate part

[0027] 102b: substrate part

[0028] 102c: substrate part

[0029] 102d:Substrate part

[0030] 102e: substrate part

[0031] 104: semiconductor layer stack

[0032] 106: first semiconductor layer

[0033] 108: Second semiconductor layer

[0034] 110: Mask structure

[0035] 112: oxygen layer

[0036] 114: Nitrogen-containing layer

[0037] 202a: Fin

[0038] 202b: Fin

[0039] 202c: Fin

[0040] 202d: Fin

[0041] 202e: Fin

[0042] 204: Groove

[0043] 302: Optional padding layer

[0044] 304: cushioning layer

[0045] 402: Insulation material

[0046] 502: Groove

[0047] 504: Top surface

[0048] 602: coating

[0049] 702: cushioning layer

[0050] 704: Dielectric material

[0051] 802: Top surface

[0052] 804: Top surface

[0053] 806: Groove

[0054] 904: Dielectric material

[0055] 906: dielectric feature portion

[0056] 908: bottom part

[0057] 1102: Sacrificial gate stack

[0058] 1104: Sacrificial gate dielectric layer

[0059] 1106: Sacrificial gate electrode layer

[0060] 1108: Mask structure

[0061] 1110: oxygen layer

[0062] 1112: Nitrogen-containing layer

[0063] 1202: spacer

[0064] 1204: Part 1

[0065] 1206: Part 2

[0066] 1302: Gap

[0067] 1402: Dielectric spacer

[0068] 1502: Source / drain epitaxial feature portion

[0069] 1602: Contact etch stop layer

[0070] 1604: Interlayer dielectric layer

[0071] 1606: Nitrogen-containing layer

[0072] 1802: Opening

[0073] 1902: Oxygen layer

[0074] 1904: Gate dielectric layer

[0075] 1906: Gate electrode layer

[0076] 2003: Surface

[0077] 2004: Surface

[0078] 2102: Groove

[0079] 2302: Seed layer

[0080] 2502:Mask

[0081] 2802: Conductor layer

[0082] 2902: Opening

[0083] 3002: Dielectric materials

[0084] 3102: Conductor feature portion

[0085] AA:Line

[0086] BB:Line

[0087] CC:Line

[0088] DD:Line

[0089] H1: Height

[0090] H2: Height

[0091] X: axis

[0092] Y: axis

[0093] Z: axis DETAILED DESCRIPTION

[0094] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature portion on or on a second feature portion may include an embodiment in which the first feature portion and the second feature portion are formed to be in direct contact, and may also include an embodiment in which an additional feature portion may be formed between the first feature portion and the second feature portion so that the first feature portion and the second feature portion may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0095] Additionally, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," and the like) may be used herein to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0096] Figures 1 to 31 1 shows an exemplary continuous process for manufacturing the semiconductor device structure 100 in some embodiments. It is understood that in other embodiments of this method, Figures 1 to 31 Other operations can be provided before, during, and after the process, and some of the operations mentioned below can be replaced or deleted. The order of operations and processes is interchangeable.

[0097] Figures 1 to 18 3D diagrams of various manufacturing stages of semiconductor device structures according to some embodiments of the present disclosure. Figure 1 As shown, a semiconductor layer stack 104 is formed on a substrate 101. The substrate 101 may be a semiconductor substrate. In some embodiments, the substrate 101 comprises a single crystal semiconductor material at least on its surface. The substrate 101 may comprise a single crystal semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimony (GaAsSb), and indium phosphide (InP). In this embodiment, the substrate 101 is made of silicon. In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) structure comprising an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide layer.

[0098] The substrate 101 may include one or more buffer layers (not shown) on the surface of the substrate 101. The function of the buffer layer is to gradually change the lattice constant of the substrate 101 to the source / drain region grown on the substrate 101. The buffer layer can be an epitaxially grown single crystal semiconductor material, such as silicon, germanium, germanium tin (GeSn), silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenide antimony, gallium nitride (GaN), and indium phosphide. In one embodiment, the substrate 101 includes a silicon germanium buffer layer epitaxially grown on the silicon substrate 101. The germanium concentration of the silicon germanium buffer layer can increase from 30% germanium atomic percentage in the bottom buffer layer to 70% germanium atomic percentage in the top buffer layer.

[0099] The substrate 101 may include a plurality of regions appropriately doped with impurities (e.g., p-type or n-type impurities). For example, the dopant for an n-type fin field effect transistor (FinFET) may be boron (B), and the dopant for a p-type FinFET may be phosphorus (P).

[0100] Semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 is made of silicon, and the second semiconductor layer 108 is made of silicon germanium. In some embodiments, semiconductor layer stack 104 includes alternating first and second semiconductor layers 106 and 108. The first semiconductor layer 106 or a portion thereof may subsequently form a nanosheet channel of semiconductor device structure 100. Semiconductor device structure 100 may include a nanosheet transistor. The term "nanosheet" is used herein to designate any nanometer-scale or micrometer-scale, elongated material portion, and does not limit the cross-sectional shape of such material portion. The term "nanosheet" designates elongated material portions with circular or substantially circular cross-sections, as well as beams or rods. For example, a rod may have a cylindrical or substantially rectangular cross-section. The nanosheet channel in semiconductor device structure 100 may be surrounded by a gate electrode layer. Nanosheet transistors can be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or other transistors with a gate electrode layer surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels in the semiconductor device structure 100 is discussed further below. In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 can be replaced with a single semiconductor material connected to the substrate 101, and the device is a FinFET.

[0101] It should be noted that Figure 1 The three first semiconductor layers 106 and the three second semiconductor layers 108 are arranged alternately. This is for illustration only and is not intended to limit the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104. The number of semiconductor layers depends on the predetermined number of channels in the semiconductor device structure 100. In some embodiments, the number of first semiconductor layers 106, and thus the number of channels, ranges from 3 to 8.

[0102] Specifically, the first semiconductor layer 106 can serve as channels in the semiconductor device structure 100, with the channel thickness determined based on device performance calculations. In some embodiments, each first semiconductor layer 106 has a thickness of approximately 6 nanometers to approximately 12 nanometers. The second semiconductor layer 108 can ultimately be removed and can be used to define the vertical distance between adjacent channels in the semiconductor device structure 100, with the width of the distance determined based on device performance calculations. In some embodiments, each second semiconductor layer 108 has a thickness of approximately 2 nanometers to approximately 6 nanometers.

[0103] The first semiconductor layer 106 and the second semiconductor layer 108 may be formed by any suitable deposition process (e.g., epitaxy). For example, the semiconductor layer stack 104 may be epitaxially grown by molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0104] A mask structure 110 is formed over the semiconductor layer stack 104. The mask structure 110 may include an oxygen-containing layer 112 and a nitrogen-containing layer 114. The oxygen-containing layer 112 may be a pad oxide layer, such as a silicon dioxide (SiO2) layer. The nitrogen-containing layer 114 may be a pad nitride layer, such as a silicon nitride (Si3N4) layer. The mask structure 110 may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0105] Figure 2 1 is a perspective view of a semiconductor device structure 100 at various stages of fabrication according to some embodiments. Figure 2As shown, fins 202a and fins 202b are formed. In some embodiments, each fin 202a and fin 202b includes substrate portions 102a and 102b formed from substrate 101, a portion of semiconductor layer stack 104, and a portion of mask structure 110. Fins 202a and fin 202b can be manufactured using a suitable process, including a double patterning or multi-patterning process. Generally, double patterning or multi-patterning processes combine photolithography processes and self-alignment processes to produce patterns with a pitch smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fins 202a and fin 202b by etching the semiconductor layer stack 104 and substrate 101. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. Figure 2 As shown, two fins are formed, but the number of fins is not limited to 2. In some embodiments, three or more fins are arranged in the X direction, such as Figure 20 shown.

[0106] In some embodiments, the fins 202a and fins 202b can be fabricated by a suitable process, including photolithography or etching. The photolithography process can include forming a photoresist layer (not shown) on the mask structure 110, exposing the photoresist to a pattern, performing a post-exposure bake, and finally developing the photoresist to form a patterned photoresist. In some embodiments, the photoresist can be patterned using an electron beam lithography process to form a patterned photoresist. The patterned photoresist can be used to protect areas of the substrate 101 and layers formed thereon. In areas not protected by the mask structure 110, trenches 204 can be formed in the semiconductor layer stack 104 and the substrate 101 by an etching process, thereby leaving extended fins 202a and fins 202b. The trenches 204 can be formed by dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof.

[0107] Figure 3 is a perspective view of a semiconductor device structure 100 at one of the manufacturing stages according to some embodiments. Figure 3As shown, a liner layer 304 is formed on the substrate 101, the fin 202a, and the fin 202b. In some embodiments, an optional liner layer 302 may be formed on the liner layer 304 on the substrate 101, the fin 202a, and the fin 202b, and the liner layer 304 may be formed on the optional liner layer 302. The liner layer 304 may be made of a semiconductor material, such as silicon. In some embodiments, the liner layer 304 may be made of the same material as the substrate 101. The optional liner layer 302 may be made of an oxygen-containing material, such as an oxide. The liner layer 304 may be a conformal layer and may be manufactured by a conformal process, such as an atomic layer deposition (ALD) process. The term "conformal" is used here to simplify the following description: a layer having substantially the same thickness in several regions. The optional liner layer 302 may be a conformal layer and may be manufactured by a conformal process, such as an atomic layer deposition process.

[0108] Figure 4 FIG. 1 is a perspective view of a semiconductor device structure 100 at one of the manufacturing stages in some embodiments. Figure 4 As shown, an insulating material 402 is formed on the substrate 101. The insulating material 402 fills the trench 204 ( Figure 2 First, an insulating material 402 is formed on the substrate 101, so that the fins 202a and 202b are embedded in the insulating material 402. Then, a planarization process, such as chemical mechanical polishing (CMP) and / or etch-back, is performed to expose the tops of the fins 202a and 202b (such as the liner layer 304) from the insulating material 402. Figure 4 As shown. Insulating material 402 can be made of an oxygen-containing material such as silicon oxide, fluorine-doped silicate glass (FSG), a nitrogen-containing material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), a low-k dielectric material, or other suitable dielectric materials. Insulating material 402 can be formed by any suitable process, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0109] Then, if Figure 5As shown, the insulating material 402 between adjacent fins 202a and 202b is removed to recess the insulating material 402 to form a trench 502. The trench 502 can be formed by any suitable process, such as dry etching or wet etching, that selectively removes the insulating material 402 without removing the semiconductor material of the liner layer 304. The recessed insulating material 402 can be a shallow trench isolation (STI) structure. The insulating material 402 includes a top surface 504 that is at or below the height of the surface of the second semiconductor layer 108 contacting the substrate portions 102a and 102b of the substrate 101.

[0110] Then, if Figure 6 As shown, on the exposed surface of the liner layer 304 ( Figure 5 ) and the optional liner layer 302 is omitted for clarity. During the formation of the cladding layer 602, the liner layer 304 may diffuse into the cladding layer 602. Therefore, in some embodiments where the optional liner layer 302 is not present, the cladding layer 602 contacts the semiconductor layer stack 104, such as Figure 6 As shown. In some embodiments, the cladding layer 602 comprises a semiconductor material. The cladding layer 602 is formed on the semiconductor material but not on the dielectric material. For example, the cladding layer 602 comprises silicon germanium and is formed on the silicon of the liner layer 304 but not on the dielectric material of the insulating material 402. In some embodiments, the cladding layer 602 can be formed by first forming a semiconductor layer on the liner layer 304 and the insulating material 402, and then removing a portion of the semiconductor layer formed on the insulating material 402 using an etching process. The etching process can remove some of the semiconductor layer formed on the top of the fins 202a and 202b, and the cladding layer 602 formed on the top of the fins 202a and 202b may have a curved surface rather than a flat surface. In some embodiments, the cladding layer 602 and the second semiconductor layer 108 can comprise the same material with the same etching selectivity. For example, the cladding layer 602 and the second semiconductor layer 108 comprise silicon germanium. The cladding layer 602 and the second semiconductor layer 108 may be removed sequentially to create a space for forming an electrode gate layer.

[0111] Then, if Figure 7As shown, a liner layer 702 is formed on the top surface 504 of the coating layer 602 and the insulating material 402. The liner layer 702 may include a low dielectric constant material (e.g., a material having a dielectric constant less than 7) such as silicon dioxide, silicon nitride, silicon carbonitride, silicon oxycarbide (SiOC), or silicon oxycarbonitride. The liner layer 702 may be formed by a conformal process, such as an atomic layer deposition process. The liner layer 702 has a thickness of about 1 nanometer to about 6 nanometers. The liner layer 702 may serve as a shell layer to protect the flowable oxide material formed in the trench 502 during the subsequent removal of the coating layer 602. Therefore, if the thickness of the liner layer 702 is less than about 1 nanometer, it is not sufficient to protect the flowable oxide material. On the other hand, if the thickness of the liner layer 702 is greater than about 6 nanometers, it may fill the trench 502 ( Figure 5 ).

[0112] A dielectric material 704 is formed in the trench 502 and on the liner layer 702, such as Figure 7 As shown. Dielectric material 704 may be an oxygen-containing material, such as an oxide formed by flowable chemical vapor deposition. The oxygen-containing material may have a dielectric constant of approximately less than 7, for example, less than approximately 3. The width of dielectric material 704 along the X-direction may be defined by the width of trench 502 and the thickness of liner layer 702. In some embodiments, dielectric material 704 has a width of approximately 8 nanometers to approximately 30 nanometers. A planarization process, such as a chemical mechanical polishing process, is performed to remove liner layer 702 and dielectric material 704 formed on top of fins 202a and 202b. After the planarization process, a portion of capping layer 602 disposed on nitrogen-containing layer 114 may be exposed.

[0113] Then, if Figure 8 As shown. The liner layer 702 and the dielectric material 704 are recessed to the height of the uppermost first semiconductor layer 106. For example, in some embodiments, after the recessing process, the dielectric material 704 may include a top surface 802 that is substantially flush with a top surface 804 of the uppermost first semiconductor layer 106. The top surface 804 of the uppermost first semiconductor layer 106 may contact the mask structure 110, for example, contact the oxygen-containing layer 112. The liner layer 702 is recessed to the same height as the dielectric material 704. The liner layer 702 and the dielectric material 704 can be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a first etching process is performed to recess the dielectric material 704, followed by a second etching process to recess the liner layer 702. The etching process can be a selective etching process that does not remove the semiconductor material of the cladding layer 602. After the recess process, a trench 806 is formed between the fins 202 a , 202 b .

[0114] In groove 806 ( Figure 8) and forming a dielectric material 904 on the dielectric material 704 and the liner layer 702, such as Figure 9 As shown. The dielectric material 904 may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), zirconium oxide (ZrO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), hafnium oxide (HfO) or other suitable dielectric materials. The dielectric material 904 may be formed by any suitable process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, flowable chemical vapor deposition or atomic layer deposition process. The dielectric material 904 may have a thickness of about 5 nanometers to about 20 nanometers. The dielectric material 904 may fill the trench 806 ( Figure 8 Therefore, if the thickness of dielectric material 904 is less than about 5 nanometers, it is insufficient to fill trench 806. On the other hand, if the thickness of dielectric material 904 is greater than about 20 nanometers, the manufacturing cost increases without bringing significant advantages.

[0115] A planarization process is performed to expose the nitrogen-containing layer 114 of the mask structure 110, such as Figure 9 As shown. The planarization process can be any suitable process, such as a chemical mechanical polishing process. The planarization process removes a portion of the encapsulation layer 602 and a portion of the dielectric material 904 disposed on the mask structure 110. The liner layer 702, the dielectric material 704, and the dielectric material 904 can be collectively referred to as a dielectric feature 906. The dielectric feature 906 includes a bottom portion 908, the shell of the bottom portion 908 is the liner layer 702, and the core of the bottom portion 908 is the dielectric material 704. The dielectric feature 906 also includes a top portion, the top portion is the dielectric material 904. The dielectric feature 906 can be a dielectric fin that separates the adjacent source / drain epitaxial feature 1502 ( Figure 15 ) and the adjacent gate electrode layer 1906 ( Figure 19 )separate.

[0116] Then, if Figure 10 As shown, the cladding layer 602 is recessed and the mask structure 110 is removed. The cladding layer 602 can be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process can be controlled so that the remaining cladding layer 602 is substantially at the same height as the top surface 804 of the uppermost first semiconductor layer 106 of the semiconductor layer stack 104. The etching process can be a selective etching process that does not remove the dielectric material 904. The mask structure 110 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. The mask structure 110 is removed to expose the top surface 804 of the uppermost first semiconductor layer 106 of the semiconductor layer stack 104.

[0117] The top portion of the dielectric feature 906 (e.g., dielectric material 904) may have a height H1 along the Z direction. The height H1 may be about 6 nanometers to about 15 nanometers. The dielectric material 904 may be disposed on the top surface 802 of the dielectric material 704, and the top surface 802 may be coplanar with the top surface 804 of the topmost first semiconductor layer 106 of the semiconductor layer stack 104. Therefore, in order to separate or cut off the adjacent gate electrode layers 1906, the dielectric material 904 having the height H1 may extend above the plane defined by the top surface 804. If the height H1 is less than about 6 nanometers, it may not be sufficient to separate or cut off the gate electrode layers 1906 ( Figure 19 On the other hand, if the height H1 is greater than about 15 nm, the manufacturing cost increases without bringing significant advantages.

[0118] Then, if Figure 11 As shown, one or more sacrificial gate stacks 1102 are formed on the semiconductor device structure 100. The sacrificial gate stacks 1102 may include a sacrificial gate dielectric layer 1104, a sacrificial gate electrode layer 1106, and a mask structure 1108. The sacrificial gate dielectric layer 1104 may include one or more layers of dielectric materials, such as silicon dioxide, silicon nitride, a high-k dielectric material, and / or other suitable dielectric materials. In some embodiments, the sacrificial gate dielectric layer 1104 includes a material different from the dielectric material 904. In some embodiments, the sacrificial gate dielectric layer 1104 may be deposited by chemical vapor deposition, sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable processes. The sacrificial gate electrode layer 1106 may include polysilicon. The mask structure 1108 may include an oxygen-containing layer 1110 and a nitrogen-containing layer 1112. In some embodiments, the sacrificial gate electrode layer 1106 and the mask structure 1108 can be formed by different processes such as layer deposition, such as chemical vapor deposition (including low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition), physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation (e-beam evaporation) or other suitable deposition processes or combinations thereof.

[0119] A blanket layer of a sacrificial gate dielectric layer 1104, a sacrificial gate electrode layer 1106, and a mask structure 1108 may be deposited first, and then a patterning and etching process may be performed to form the sacrificial gate stack 1102. For example, the patterning process includes a lithography process (e.g., photolithography or electron beam lithography), and the lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying, hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, other etching methods, and / or combinations thereof. By patterning the sacrificial gate stack 1102, the semiconductor layer stack 104 of the fins 202a, 202b is partially exposed on opposite sides of the sacrificial gate stack 1102. As Figure 11 As shown, two sacrificial gate stacks 1102 are formed, but the number of sacrificial gate stacks 1102 is not limited to 2. In some embodiments, more than two sacrificial gate stacks 1102 are arranged along the Y direction.

[0120] like Figure 12 As shown, spacers 1202 are formed on the sidewalls of the sacrificial gate stack 1102. Sidewall spacers 1202 can be formed by first depositing a conformal layer and then etching back the conformal layer. For example, a layer of spacer material can be conformally deposited on the exposed surfaces of the semiconductor device structure 100. The conformal spacer material layer can be formed by atomic layer deposition. The spacer material layer is then subjected to an anisotropic etch, such as a reactive ion etch. During the anisotropic etch, a majority of the spacer material layer is removed from horizontal surfaces, such as the top surfaces of the fins 202 and 202b, the cladding layer 602, and the dielectric material 904, leaving spacers 1202 on vertical surfaces, such as the sidewalls of the sacrificial gate stack 1102. Spacers 1202 can be made of a dielectric material selected from silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof. In some embodiments, the spacer 1202 includes multiple layers, such as a main spacer layer, a liner layer, and the like.

[0121] Next, the exposed portions of the fins 202a and 202b, the exposed portions of the cladding layer 602, and the exposed portions of the dielectric material 904 that are not covered by the sacrificial gate stack 1102 and the spacer 1202 are selectively recessed by one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. In some embodiments, the exposed portions of the semiconductor layer stack 104 of the fins 202a and 202b are removed to expose the substrate portions 102a and 102b, respectively. Figure 12As shown, the exposed portions of the fins 202a, 202b are recessed to a height lower than or equal to the top surface 504 of the insulating material 402. The recessing process may include an etching process that recesses the exposed portions of the fins 202a, 202b and the exposed portion of the cladding layer 602.

[0122] In some embodiments, the etching process may reduce the height of the top exposed portion (dielectric material 904) of the dielectric feature 906 from H1 to H2, as shown in FIG. Figure 12 Thus, the first portion 1204 of the dielectric material 904 beneath the sacrificial gate stack 1102 and the spacer 1202 has a height H1, while the first portion 1204 of the dielectric material 904 beneath the sacrificial gate stack 1102 and the spacer 1202 has a height H1. Figure 15 ) has a second height H2 that is less than the height H1.

[0123] At this stage, the trailing portions of the semiconductor layer stack 104 beneath the sacrificial gate stack 1102 and the spacers 1202 have substantially flat surfaces that are flush with the corresponding spacers 1202. In some embodiments, the trailing portions of the semiconductor layer stack 104 beneath the sacrificial gate stack 1102 and the spacers 1202 are etched slightly horizontally.

[0124] Then, if Figure 13 As shown, edge portions of each second semiconductor layer 108 and edge portions of the cladding layer 602 are removed to form gaps 1302. In some embodiments, portions of the second semiconductor layer 108 and the cladding layer 602 are removed by a selective wet etching process without removing the first semiconductor layer 106. For example, when the second semiconductor layer 108 is made of silicon germanium and the first semiconductor layer 106 is made of silicon, a selective wet etching process including an ammonia and hydrogen peroxide mixture (APM) can be used.

[0125] Then, if Figure 14 As shown, dielectric spacers 1402 are formed between gaps 1302. In some embodiments, dielectric spacers 1402 may be made of a low-k material, such as silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. In some embodiments, dielectric spacers 1402 may be formed by first depositing a dielectric layer using a conformal deposition process such as atomic layer deposition, and then removing the conformal dielectric layer except for dielectric spacers 1402 using anisotropic etching. During the anisotropic etching, first semiconductor layer 106 and spacers 1202 may protect dielectric spacers 1402. In some embodiments, dielectric spacers 1402 may be flush with spacers 1202.

[0126] Then, if Figure 15 As shown, source / drain epitaxial features 1502 are formed on substrate portions 102a, 102b of fins 202a, 202b. In an n-channel field effect transistor (n-channel FET), source / drain epitaxial features 1502 may comprise one or more layers of silicon, silicon phosphide (SiP), silicon carbide (SiC), and silicon carbon phosphide (SiCP). In a p-channel field effect transistor (p-channel FET), source / drain epitaxial features 1502 may comprise silicon, silicon germanium, or germanium. Source / drain epitaxial features 1502 may be grown vertically and horizontally to form facets. The facets may correspond to crystal planes of the material used for substrate portions 102a, 102b. Source / drain epitaxial features 1502 are formed using an epitaxial growth method, such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The source / drain epitaxial features 1502 contact the first semiconductor layer 106 and the dielectric spacer 1402 ( Figure 14 ). The source / drain epitaxial features 1502 can be source / drain regions. In this disclosure, source and drain can be used interchangeably, and the source device and the drain device are substantially the same.

[0127] Then, if Figure 16As shown, a contact etch stop layer (CESL) 1602 may be formed over the source / drain epitaxial features 1502, the dielectric features 906, and the adjacent spacers 1202. CESL 1602 may comprise an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, or the like, or a combination thereof. CESL 1602 may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, CESL 1602 is a conformal layer formed by atomic layer deposition. An interlayer dielectric (ILD) 1604 may be formed over CESL 1602. The material of the interlayer dielectric layer 1604 may include tetraethylorthosilicate (TEOS) oxide, undoped silica glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric layer 1604 may be deposited by plasma-enhanced chemical vapor deposition (PECVD) or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 1604, the semiconductor structure device 100 may be thermally treated to anneal the interlayer dielectric layer 1604.

[0128] A planarization process is performed to expose the sacrificial gate electrode layer 1106, such as Figure 16 The planarization process may be any suitable process, such as a chemical mechanical polishing process. The planarization process removes a portion of the interlayer dielectric layer 1604 and a portion of the contact etch stop layer 1602 disposed on the sacrificial gate stack 1102. The planarization process may also remove the mask structure 1108 ( Figure 11 The interlayer dielectric layer 1604 may be recessed to a height lower than or equal to the top surface of the sacrificial gate electrode layer 1106, and a nitrogen-containing layer 1606, such as a silicon carbonitride layer, may be formed on the recessed interlayer dielectric layer 1604. Figure 16 In the subsequent etching process, the nitrogen-containing layer 1606 can protect the interlayer dielectric layer 1604.

[0129] Figure 17 According to some embodiments, during one of the manufacturing stages of the semiconductor device structure 100, Figure 16 The stereogram of line AA in . Figure 17 As shown, the sacrificial gate electrode layer 1106 ( Figure 16 ) and the sacrificial gate dielectric layer 1104 to expose the capping layer 602 and the semiconductor layer stack 104. The sacrificial gate electrode layer 1106 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 1104 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively remove the sacrificial gate electrode layer 1106 without removing the spacers 1202, the nitrogen-containing layer 1606, the dielectric material 904 of the dielectric features 906, and the contact etch stop layer 1602. In some embodiments, the spacers 1202 can be recessed by the etchant used to remove the sacrificial gate electrode layer 1106 and / or the sacrificial gate dielectric layer 1104.

[0130] Then, if Figure 18 As shown, the cladding layer 602 and the second semiconductor layer 108 are removed. The removal process exposes the dielectric spacer 1402 and the first semiconductor layer 106. The removal process can be any suitable process, such as dry etching, wet etching, or a combination thereof. The etching process can be a selective etching process that removes the cladding layer 602 and the second semiconductor layer 108 but does not remove the spacer 1202, the contact etch stop layer 1602, the nitrogen-containing layer 1606, the dielectric material 904, and the first semiconductor layer 106. Thus, the opening 1802 is formed, as shown in FIG. Figure 18 As shown in FIG. 1 , in some embodiments, the size of the portion of liner layer 702 contacting the sidewalls of dielectric material 704 can be reduced so that the bottom portion 908 of dielectric feature 906 has a width that is smaller than the width of dielectric material 904 of dielectric feature 906. Portions of first semiconductor layer 106 not covered by dielectric spacer 1402 can be exposed in opening 1802. Each first semiconductor layer 106 can be a nanosheet channel or a nanosheet transistor.

[0131] Figure 19 and Figure 20 According to some embodiments, in each manufacturing stage of the semiconductor device structure 100, Figure 18 The cross-sectional view of line AA in FIG. Figure 19 As shown, an oxygen-containing layer 1902 may be formed around the exposed surfaces of the first semiconductor layer 106 and the substrate portions 102a and 102b of the fins 202a and 202b in the opening 1802. A gate dielectric layer 1904 may be formed on the oxygen-containing layer 1902 and the dielectric features 906 in the opening 1802. Figure 19 As shown. The oxygen-containing layer 1902 may be an oxide layer, and the gate dielectric layer 1904 may include a sacrificial gate dielectric layer 1104 ( Figure 11 ) are the same material. In some embodiments, gate dielectric layer 1904 comprises a high-k dielectric material. Oxygen-containing layer 1902 and gate dielectric layer 1904 can be formed by any suitable process, such as atomic layer deposition. In some embodiments, oxygen-containing layer 1902 and gate dielectric layer 1904 are formed by a conformal process.

[0132] Next, a gate electrode layer 1906 is formed in the opening 1802 and on the gate dielectric layer 1904. The gate electrode layer 1906 is formed on the gate dielectric layer 1904 to surround a portion of each first semiconductor layer 106. The gate electrode layer 1906 includes one or more layers of a conductive material, such as polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), tantalum nitride (TaN), nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), a metal alloy, other suitable materials, and / or combinations thereof. The gate electrode layer 1906 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable methods.

[0133] Next, the gate electrode layer 1906 is recessed to the same level as the top surface 2004 of the dielectric material 904 of the dielectric feature 906, as shown in FIG. Figure 20 As shown. Fins 202c, 202d, and 202e may additionally be formed from substrate 101. Fins 202a, 202b, 202c, 202d, and 202e may have different widths. For example, each fin 202a, 202b has a width greater than each fin 202c, 202d, and 202e. Wider fin widths result in wider channels, and different devices may have different channel widths. For example, a device with a wider channel may be more suitable for high-speed applications such as NAND devices. A device with a narrower channel may be more suitable for low-power, low-leakage applications such as inverter devices. The distance between adjacent gate electrode layers 1906 may vary. In other words, the width of the dielectric feature 906 may vary. For example, dielectric feature 906 disposed between gate electrode layer 1906 on substrate portion 102c and gate electrode layer 1906 on substrate portion 102d is wider than dielectric feature 906 disposed between gate electrode layer 1906 on substrate portion 102d and gate electrode layer 1906 on substrate portion 102e, as shown in FIG. Figure 20 shown.

[0134] The gate electrode layer 1906 may be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, the etching process may be a selective dry etching process that does not substantially affect the nitrogen-containing layer 1606 ( Figure 18 ), spacer 1202 ( Figure 18 ) and the contact etch stop layer 1602 ( Figure 18 After the recess process, the dielectric feature 906 separates or interrupts the adjacent gate electrode layer 1906 .

[0135] Figure 21 According to some embodiments of the present disclosure Figure 20 , a top view of the semiconductor device structure 100. Figure 21 As shown, semiconductor device structure 100 includes a plurality of fins 202a, 202b, 202c, 202d, and 202e, indicated by dashed lines. An interlayer dielectric layer 1604 is formed on fins 202a, 202b, 202c, 202d, and 202e. For clarity, contact etch stop layer 1602 and nitrogen-containing layer 1606 are omitted. Trenches 2102 are formed on portions of fins 202a, 202b, 202c, 202d, and 202e between interlayer dielectric layer 1604. The bottom of trench 2102 includes gate electrode layer 1906 separated by dielectric material 904 of dielectric features 906. Spacers 1202 are omitted for clarity.

[0136] Figures 22A to 22C According to some embodiments of the present disclosure, in each manufacturing stage of the semiconductor device structure 100, Figure 21 Cross-sectional view along line BB, line CC, and line DD. Figure 22A and Figure 22C is a cross-sectional view of trench 2102 on dielectric feature 906 . Figure 22B 2 is a cross-sectional view of the trench 2102 on the gate electrode layer 1906. Figure 22A 、 Figure 22B 、 Figure 22C As shown, trenches 2102 may be formed between interlayer dielectric layers 1604. Interlayer dielectric layer 1604 may be disposed on contact etch stop layer 1602, and nitrogen-containing layer 1606 may be disposed on interlayer dielectric layer 1604. Spacers 1202 may contact etch stop layer 1602. Figure 22A and Figure 22C As shown, the dielectric material 904 of the dielectric feature 906 includes a first portion 1204 and a second portion 1206. The first portion 1204 of the dielectric material 904 of the dielectric feature 906 may be located at the bottom of the trench 2102 section, as shown in FIG. Figure 22A and Figure 22C shown.

[0137] The trench 2102 includes various sections with different bottoms, such as the first portion 1204 of the dielectric feature 906, as shown in FIG. Figure 22A and Figure 22C As shown, with the gate electrode layer 1906, as Figure 22B In some embodiments, the surface 2003 of the gate electrode layer 1906 is coplanar with the surface 2004 of the dielectric material 904 .

[0138] 23A to 23D According to some embodiments of the present disclosure, in each manufacturing stage of the semiconductor device structure 100, Figure 21 The cross-sectional view of line AA, line BB, line CC and line DD. Figure 23A As shown, a seed layer 2302 is formed on the surface 2003 of the gate electrode layer 1906 and the surface 2004 of the dielectric material 904. The seed layer 2302 is formed on the nitrogen-containing layer 1606, the adjacent spacers 1202 and the bottom of the trench 2102 (e.g., the dielectric material 904 and the gate electrode layer 1906). Figure 23B 、 Figure 23C 、 Figure 23D As shown. The seed layer 2302 may include a conductive material, such as titanium nitride, tantalum nitride, tungsten, ruthenium, or other suitable conductive material. The seed layer 2302 may be formed by any suitable process, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, or physical vapor deposition. Due to the less conformal nature of this deposition process, portions of the seed layer 2302 formed on horizontal surfaces, such as the nitrogen-containing layer 1606, the dielectric material 904, and the gate electrode layer 1906, may be thicker than portions of the seed layer 2302 formed on vertical surfaces, such as the spacer 1202. The seed layer 2302 is formed on the dielectric material 904 and the gate electrode layer 1906, and in a subsequent stage, a conductive layer 2802 is formed on the seed layer 2302 ( 28A to 28D Conductive layer 2802 comprises a conductive material, which is formed on the conductive material but not on the dielectric material. Therefore, without seed layer 2302, conductive layer 2802 cannot be formed on the multiple gate electrode layers 1906 that penetrate dielectric material 904. Seed layer 2302 and conductive layer 2802 electrically connect two or more gate electrode layers 1906.

[0139] In some embodiments, the seed layer 2302 and the conductor layer 2802 may be divided into different sections (eg Figure 29A The segmentation process may include first forming openings 2902 in the seed layer 2302 and the conductive layer 2802 ( Figure 29A ), and then forming a dielectric material 3002 in the opening 2902 ( Figure 30AIn some embodiments, the portion of seed layer 2302 formed on the horizontal surface has a thickness of approximately 1 nanometer to approximately 2 nanometers. If the seed layer 2302 is less than approximately 1 nanometer thick, there may not be enough seed layer 2302 to allow the conductive layer 2802 to form on the seed layer 2302. On the other hand, if the seed layer 2302 is thicker than approximately 2 nanometers, the etching process used to form the opening 2902 may damage the gate electrode layer 1906 beneath the seed layer 2302.

[0140] Then, if Figure 24B 、 Figure 24C 、 Figure 24D As shown, a portion of the seed layer 2302 disposed on adjacent spacers 1202 is removed. The portion of the seed layer 2302 can be removed by any suitable process, such as wet etching. The wet etching removes the seed layer 2302 disposed on the vertical surfaces to expose the spacers 1202. Because the portion of the seed layer 2302 disposed on the vertical surfaces is thinner than the portion of the seed layer 2302 disposed on the horizontal surfaces, the portion of the seed layer 2302 disposed on the horizontal surfaces is not completely removed.

[0141] Next, a mask 2502 is formed on the trench 2102 and the nitrogen-containing layer 1606, as shown in FIG. 25A to 25D In some embodiments, the mask 2502 may include an oxygen-containing layer and / or a nitrogen-containing layer. In some embodiments, the mask 2502 is a photoresist. The portion of the mask 2502 on the seed layer 2302 disposed on the nitrogen-containing layer 1606 may be removed, as shown. 26A to 26D As shown. The portion of mask 2502 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. The removal process does not affect the portion of mask 2502 in trench 2102. The removal process exposes the portion of seed layer 2302 disposed on nitrogen-containing layer 1606.

[0142] Then, if 27A to 27D As shown, the portion of the seed layer 2302 disposed on the nitrogen-containing layer 1606 is removed, and then the portion of the mask 2502 in the trench 2102 is removed to expose the portion of the seed layer 2302 formed on the bottom of the trench 2102. The portion of the seed layer 2302 disposed on the nitrogen-containing layer 1606 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, as Figures 26B to 26D and Figures 27B to 27D As shown, two etching processes are used to remove portions of the mask 2502 and the seed layer 2302 disposed on the nitrogen-containing layer 1606. Alternatively, a planarization process such as chemical mechanical polishing can be used to remove portions of the mask 2502 and the seed layer 2302 disposed on the nitrogen-containing layer 1606.

[0143] The portion of the mask 2502 disposed in the trench 2102 may be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. The removal of the portion of the mask 2502 may be selective, such that the nitrogen-containing layer 1606, the spacer 1202, and the seed layer 2302 disposed on the bottom of the trench 2102 are not removed due to different etching selectivities.

[0144] Then, if 28A to 28D As shown, a conductive layer 2802 is formed on the seed layer 2302. The conductive layer 2802 may include a metal such as tungsten, ruthenium, cobalt, or other suitable conductive material. The conductive layer 2802 may be formed by any suitable process, such as physical vapor deposition or atomic layer deposition. The conductive layer 2802 is formed on the conductive material of the seed layer 2302 but not on the dielectric material of the nitrogen-containing layer 1606. The conductive layer 2802 may have a thickness of approximately 2 nanometers to approximately 5 nanometers. The conductive layer 2802 may serve as an electrical path for the gate electrode layer 1906. Therefore, if the thickness of the conductive layer 2802 is less than approximately 2 nanometers, the resistance may be high. On the other hand, if the thickness of the conductive layer 2802 is greater than approximately 5 nanometers, the manufacturing cost increases without providing a significant advantage.

[0145] An opening 2902 is formed in the conductor layer 2802 and the seed layer 2302, as shown in FIG. 29A to 29D As shown. In some embodiments, opening 2902 is formed using two etching processes. A first etching process is performed to remove a portion of conductive layer 2802 to expose a portion of seed layer 2302. The first etching process can be a dry etch, a wet etch, or a combination thereof. The first etching process can be a selective etching process that removes conductive layer 2802 but does not remove nitrogen-containing layer 1606 and spacers 1202. Seed layer 2302 protects gate electrode layer 1906 located beneath the removed portion of conductive layer 2802 from being damaged by the etchant used to remove the portion of conductive layer 2802. A second etching process is performed to remove the exposed portion of seed layer 2302 to form opening 2902. The second etching process can be a dry etch, a wet etch, or a combination thereof. The second etching process can be a selective etching process that removes a portion of seed layer 2302 but does not remove nitrogen-containing layer 1606, spacers 1202, conductive layer 2802, dielectric material 904, and gate electrode layer 1906. The opening 2902 exposes the dielectric material 904 of one of the dielectric features 906 and may also expose the gate electrode layer 1906 adjacent to the dielectric feature 906 .

[0146] Then, if 30A to 30DAs shown, dielectric material 3002 is formed in opening 2902 and on conductive layer 2802. Dielectric material 3002 may include the same material as dielectric material 904 and may have the same process as dielectric material 904. Dielectric material 3002 may be formed in opening 2902 and contact dielectric material 904 and a portion of gate electrode layer 1906. Figure 30A As shown, dielectric material 3002 divides seed layer 2302 and conductor layer 2802 into multiple segments, such as two segments. One segment of seed layer 2302 and conductor layer 2802 is electrically connected to gate electrode layer 1906 located on substrate portions 102c, 102d, and 102e, while the other segment of seed layer 2302 and conductor layer 2802 is electrically connected to gate electrode layer 1906 located on substrate portions 102a and 102b. For example, a first seed layer 2302 contacts two or more gate electrode layers 1906 separated by one or more dielectric features 906, and a first conductor layer 2802 is disposed on the first seed layer 2302. A second seed layer 2302 contacts two or more gate electrode layers 1906 separated by one or more dielectric features 906, and a second conductor layer 2802 is disposed on the second seed layer 2302. The dielectric material 3002 separates the first seed layer 2302 and the first conductor layer 2802 from the second seed layer 2302 and the second conductor layer 2802 .

[0147] Conductor feature 3102 may be formed to penetrate dielectric material 3002, conductor layer 2802, seed layer 2302 and contact gate electrode layer 1906, as shown in FIG. Figure 31 As shown. Conductive feature 3102 may include one or more of ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride, and may be formed by any suitable process, such as physical vapor deposition, electrical copper plating (ECP), or chemical vapor deposition. Conductive feature 3102 can provide a signal, such as a current, to gate electrode layer 1906 located below conductive feature 3102. Furthermore, a signal can be provided to an adjacent gate electrode layer 1906 via conductive layer 2802 and seed layer 2302. Thus, the adjacent gate electrode layer 1906 can receive a signal transmitted from conductive feature 3102 via conductive layer 2802 and seed layer 2302. Dielectric material 3002 interrupts conductive layer 2802 and seed layer 2302, so that a signal is not provided to conductive layer 2802 and seed layer 2302 on the other side of dielectric material 3002.

[0148] The present disclosure provides a semiconductor device structure 100 comprising first, second, and third gate electrode layers 1906 separated by dielectric features 906. A first conductor layer 2802 and a first seed layer 2302 are disposed on the first and second gate electrode layers 1906, and a second conductor layer 2802 and a second seed layer 2302 are disposed on the third gate electrode layer 1906. A dielectric material 3002 separates the first conductor layer 2802 and the first seed layer 2302 from the second semiconductor layer 2802 and the second seed layer 2302, and the dielectric material 3002 is disposed on the first and second conductor layers 2802. Certain embodiments may achieve advantages. For example, the seed layer 2302 allows the conductor layer 2802 to be formed on and electrically connect the two or more gate electrode layers 1906. Because of the presence of the seed layer 2302, the conductor layer 2802 can be removed to form the opening 2902 without damaging the gate electrode layer 1906.

[0149] One embodiment provides a semiconductor device structure. The semiconductor device includes a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, a first dielectric feature, a second dielectric feature, a first seed layer, a first conductor layer, a second seed layer, a second conductor layer, and a dielectric material. The second gate electrode layer is adjacent to the first gate electrode layer. The third gate electrode layer is adjacent to the second gate electrode layer. The first dielectric feature is disposed between the first gate electrode layer and the second gate electrode layer. The second dielectric feature is disposed between the second gate electrode layer and the third gate electrode layer. The first seed layer contacts the first gate electrode layer, the first dielectric feature, and the second gate electrode layer. The first conductor layer is disposed on the first seed layer. The second seed layer contacts the third gate electrode layer. The second conductor layer is disposed on the second seed layer. The dielectric material is disposed on the second dielectric feature, the first conductor layer, and the second conductor layer, wherein the dielectric material is disposed between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer.

[0150] In some embodiments, the semiconductor device structure further comprises: a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first gate electrode layer surrounds the first semiconductor layer, the second gate electrode layer surrounds the second semiconductor layer, and the third gate electrode layer surrounds the third semiconductor layer.

[0151] In some embodiments, the semiconductor device structure further includes a first source / drain epitaxial feature and a second source / drain epitaxial feature, wherein the first source / drain epitaxial feature contacts the first semiconductor layer, and the second source / drain epitaxial feature contacts the second semiconductor layer.

[0152] In some embodiments, the first dielectric feature is disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature.

[0153] In some embodiments, each of the first seed layer and the second seed layer comprises titanium nitride, tantalum nitride, tungsten, or ruthenium.

[0154] In some embodiments, the first semiconductor layer and the second semiconductor layer include a metal.

[0155] In some embodiments, the metal is tungsten, ruthenium, or cobalt.

[0156] Another embodiment is a semiconductor device structure. The semiconductor device structure includes a first gate electrode layer, a second gate electrode layer, and a dielectric feature. The second gate electrode layer is adjacent to the first gate electrode layer. The dielectric feature is positioned between the first gate electrode layer and the second gate electrode layer, wherein the dielectric feature includes a liner layer, a first dielectric material, and a second dielectric material. The first dielectric material is positioned on the liner layer, and the second dielectric material is positioned on the liner layer and the first dielectric material. The semiconductor device structure further includes a first seed layer, a first conductor layer, a second seed layer, a second conductor layer, and a third dielectric material. The first seed layer is positioned on the first gate electrode layer. The first conductor layer is positioned on the first seed layer. The second seed layer is positioned on the second gate electrode layer. The second conductor layer is positioned on the second seed layer. The third dielectric material is positioned between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer.

[0157] In some embodiments, the semiconductor device structure further includes a first semiconductor layer and a second semiconductor layer. The first gate electrode layer surrounds the first semiconductor layer, and the second gate electrode layer surrounds the second semiconductor layer.

[0158] In some embodiments, the semiconductor device structure further includes a first source / drain epitaxial feature and a second source / drain epitaxial feature, wherein the first source / drain epitaxial feature contacts the first semiconductor layer and the second source / drain epitaxial feature contacts the second semiconductor layer.

[0159] In some embodiments, the dielectric feature is disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature.

[0160] In some embodiments, the second dielectric material has a first portion and a second portion, the first portion is between the first gate electrode layer and the second gate electrode layer, and the second portion is placed between the first source / drain epitaxial feature portion and the second source / drain epitaxial feature portion, wherein the first portion has a first height and the second portion has a second height less than the first height.

[0161] Another embodiment is a method. The method includes forming a first fin and a second fin from a substrate, wherein the first fin includes a plurality of first semiconductor layers and the second fin includes a plurality of second semiconductor layers, forming a dielectric feature between the first fin and the second fin, forming a gate electrode layer to surround the first semiconductor layer and the second semiconductor layer, forming a seed layer on the gate electrode layer and the dielectric feature, forming a conductor layer on the seed layer, forming a first opening in the seed layer and the conductor layer to expose the dielectric feature, and forming a first dielectric material in the first opening on the dielectric feature.

[0162] In some embodiments, the dielectric feature includes forming a liner layer between the first fin and the second fin, forming a second dielectric material on the liner layer, and forming a third dielectric material on the liner layer and the second dielectric material.

[0163] In some embodiments, the method further includes forming an interlayer dielectric layer on a portion of the gate electrode layer and the dielectric feature, wherein the interlayer dielectric layer defines a trench, and forming a seed layer and a conductor layer at the bottom of the trench.

[0164] In some embodiments, forming the seed layer includes forming a cladding layer on the interlayer dielectric layer, the adjacent spacer layer in the trench, and the trench bottom, forming a mask layer on the cladding layer, and removing the mask layer and a portion of the cladding layer to form the seed layer.

[0165] In some embodiments, forming the seed layer further includes: removing a portion of the mask on the interlayer dielectric layer by a first etching process to expose a portion of the cladding layer; and exposing a portion of the cladding layer by a second etching process.

[0166] In some embodiments, forming the seed layer further includes: removing a portion of the mask layer and a portion of the cladding layer on the interlayer dielectric layer by a planarization process.

[0167] In some embodiments, forming the first dielectric material in the first opening includes forming the first dielectric material on the conductive layer.

[0168] In some embodiments, the method further includes forming a second opening on the first dielectric material, the conductive layer, and the seed layer, and forming a conductive feature in the second opening on the gate electrode layer.

[0169] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the benefits of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: Include: a first gate electrode layer; a second gate electrode layer adjacent to the first gate electrode layer; a third gate electrode layer adjacent to the second gate electrode layer; a first dielectric feature disposed between the first gate electrode layer and the second gate electrode layer; a second dielectric feature disposed between the second gate electrode layer and the third gate electrode layer; a first seed layer contacting the first gate electrode layer, the first dielectric feature, and the second gate electrode layer; a first conductor layer disposed on the first seed layer; a second seed layer contacting the third gate electrode layer; a second conductor layer disposed on the second seed layer; and A dielectric material is disposed on the second dielectric feature, the first conductor layer, and the second conductor layer, wherein the dielectric material is between the first seed layer and the second seed layer and between the first conductor layer and the second conductor layer.

2. The semiconductor device structure according to claim 1, wherein: Also includes: a plurality of first semiconductor layers, wherein the first gate electrode layer surrounds the first semiconductor layers; a plurality of second semiconductor layers, wherein the second gate electrode layer surrounds the second semiconductor layers; and A plurality of third semiconductor layers, wherein the third gate electrode layer surrounds the third semiconductor layers.

3. The semiconductor device structure according to claim 2, wherein: Also includes: a first source / drain epitaxial feature contacting the first semiconductor layers; and A second source / drain epitaxial feature portion contacts the second semiconductor layers.

4. The semiconductor device structure according to claim 3, wherein: The first dielectric feature is disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature.

5. The semiconductor device structure according to claim 1, wherein: Each of the first seed layer and the second seed layer comprises titanium nitride, tantalum nitride, tungsten or ruthenium.

6. The semiconductor device structure according to claim 5, wherein: Each of the first conductive layer and the second conductive layer comprises a metal.

7. The semiconductor device structure according to claim 6, wherein: wherein the metal is tungsten, ruthenium or cobalt.

8. A semiconductor device structure, characterized in that: Include: a first gate electrode layer; a second gate electrode layer adjacent to the first gate electrode layer; a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer, wherein the dielectric feature comprises: a cushion layer; a first dielectric material disposed on the liner layer; and a second dielectric material disposed on the liner layer and the first dielectric material; a first seed layer disposed on the first gate electrode layer; a first conductor layer disposed on the first seed layer; a second seed layer disposed on the second gate electrode layer; a second conductor layer disposed on the second seed layer; and A third dielectric material is disposed between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

9. The semiconductor device structure according to claim 8, wherein: Also includes: a plurality of first semiconductor layers, wherein the first gate electrode layer surrounds the first semiconductor layers; and A plurality of second semiconductor layers, wherein the second gate electrode layer surrounds the second semiconductor layers.

10. The semiconductor device structure according to claim 9, wherein: Also includes: a first source / drain epitaxial feature contacting the first semiconductor layers; and A second source / drain epitaxial feature portion contacts the second semiconductor layers.

11. The semiconductor device structure according to claim 10, wherein: The dielectric feature portion is disposed between the first source / drain epitaxial feature portion and the second source / drain epitaxial feature portion.

12. The semiconductor device structure according to claim 11, wherein: The second dielectric material has a first portion and a second portion, the first portion is between the first gate electrode layer and the second gate electrode layer, and the second portion is placed between the first source / drain epitaxial feature portion and the second source / drain epitaxial feature portion, wherein the first portion has a first height and the second portion has a second height less than the first height.

13. A semiconductor device structure, characterized in that: Include: a first gate electrode layer; a second gate electrode layer adjacent to the first gate electrode layer; a third gate electrode layer adjacent to the second gate electrode layer; a first dielectric feature disposed between the first gate electrode layer and the second gate electrode layer; a second dielectric feature disposed between the second gate electrode layer and the third gate electrode layer; a first conductor layer disposed on the first gate electrode layer; a second conductive layer disposed on the second gate electrode layer and the third gate electrode layer, wherein the second conductive layer is electrically connected to the second gate electrode layer and the third gate electrode layer; a first dielectric material disposed on the first dielectric feature, the first conductive layer, and the second conductive layer, wherein the first dielectric material is between the first conductive layer and the second conductive layer; and A conductive feature is disposed in the first dielectric material and contacts the second conductive layer.

14. The semiconductor device structure according to claim 13, wherein: Also includes: a plurality of first semiconductor layers, wherein the first gate electrode layer surrounds the first semiconductor layers; a plurality of second semiconductor layers, wherein the second gate electrode layer surrounds the second semiconductor layers; and A plurality of third semiconductor layers, wherein the third gate electrode layer surrounds the third semiconductor layers.

15. The semiconductor device structure according to claim 14, wherein: Also includes: a first source / drain epitaxial feature contacting the first semiconductor layers; and A second source / drain epitaxial feature portion contacts the second semiconductor layers.

16. The semiconductor device structure according to claim 15, wherein: The first dielectric feature is disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature.

17. The semiconductor device structure according to claim 16, wherein: The first dielectric feature portion has a first portion and a second portion, the first portion is between the first gate electrode layer and the second gate electrode layer, and the second portion is placed between the first source / drain epitaxial feature portion and the second source / drain epitaxial feature portion, wherein the first portion has a first height and the second portion has a second height less than the first height.

18. The semiconductor device structure according to claim 13, wherein: The first dielectric feature comprises: a cushion layer; a second dielectric material disposed on the liner layer; and A third dielectric material is disposed on the liner layer and the second dielectric material.

19. The semiconductor device structure according to claim 18, wherein: The first dielectric material contacts the third dielectric material.

20. The semiconductor device structure according to claim 13, wherein: The conductive feature contacts the third gate electrode layer.

21. A method for manufacturing a semiconductor device structure, characterized in that: Include: Forming a first fin and a second fin from a substrate, wherein the first fin comprises a plurality of first semiconductor layers, and the second fin comprises a plurality of second semiconductor layers; forming a dielectric feature between the first fin and the second fin; forming a gate electrode layer to surround the first semiconductor layers and the second semiconductor layers; forming a seed layer on the gate electrode layer and the dielectric feature; forming a conductor layer on the seed layer; forming a first opening in the seed layer and the conductor layer to expose the dielectric feature; and A first dielectric material is formed in the first opening on the dielectric feature.

22. The method according to claim 21, wherein Wherein forming the dielectric feature comprises: forming a liner layer between the first fin and the second fin; forming a second dielectric material on the liner layer; and A third dielectric material is formed on the liner layer and the second dielectric material.

23. The method according to claim 21, wherein Also includes: A plurality of interlayer dielectric layers are formed on the gate electrode layer and portions of the dielectric feature, wherein the interlayer dielectric layers define a trench, and the seed layer and the conductor layer are formed at a bottom of the trench.

24. The method according to claim 23, wherein The forming of the seed layer comprises: forming a cladding layer on the interlayer dielectric layers, adjacent to the plurality of spacers in the trench and on the bottom of the trench; forming a mask layer on the cladding layer; and Portions of the mask layer and the cladding layer are removed to form the seed layer.

25. The method of claim 24, wherein: The forming of the seed layer further comprises: removing portions of the mask on the interlayer dielectric layers through a first etching process to expose portions of the cladding layer; and The exposed portions of the cladding layer are removed by a second etching process.

26. The method of claim 24, wherein: The forming of the seed layer further comprises: A planarization process is performed to remove portions of the mask layer and portions of the cladding layer on the interlayer dielectric layers.

27. The method of claim 21, wherein: Forming the first dielectric material in the first opening includes forming the first dielectric material on the conductive layer.

28. The method of claim 27, wherein: Also includes: forming a second opening in the first dielectric material, the conductive layer, and the seed layer; and A conductor feature is formed in the second opening on the gate electrode layer.

29. A method for manufacturing a semiconductor device structure, characterized in that: Include: forming a first fin and a second fin from a substrate; forming a dielectric feature between the first fin and the second fin; forming a gate electrode layer on the substrate, wherein the gate electrode layer is located at a bottom of a trench, and the trench is formed between two interlayer dielectric layers; forming a seed layer on the gate electrode layer, on the dielectric feature, on the two interlayer dielectric layers, and adjacent to the two interlayer dielectric layers; removing portions of the seed layer formed on and adjacent to the two interlayer dielectric layers; forming a conductor layer on the seed layer; forming an opening in the seed layer and the conductor layer to expose the dielectric feature; and A first dielectric material is formed in the opening on the dielectric feature.

30. The method of claim 29, wherein: Wherein forming the dielectric feature comprises: forming a liner layer between the first fin and the second fin; forming a second dielectric material on the liner layer; and A third dielectric material is formed on the liner layer and the second dielectric material.

31. The method of claim 29, wherein: Also includes: The gate electrode layer is recessed to a height equal to a top surface of the dielectric feature, wherein the step of recessing the gate electrode layer separates the gate electrode layer into two gate electrode layers.

32. The method of claim 31, wherein The first fin includes a plurality of first semiconductor layers, and the second fin includes a plurality of second semiconductor layers.

33. The method of claim 32, wherein: One of the two gate electrode layers surrounds the first semiconductor layers, and the other of the two gate electrode layers surrounds the second semiconductor layers.

34. The method of claim 29, wherein: The conductor layer is selectively formed on the seed layer.

35. A method for manufacturing a semiconductor device structure, characterized in that: Include: forming a first gate electrode layer and a second gate electrode layer on a substrate; forming a seed layer on the first gate electrode layer and the second gate electrode layer; depositing a conductor layer on the seed layer; forming an opening in the seed layer and the conductor layer, wherein a first portion of the first gate electrode layer and a first portion of the second gate electrode layer are exposed, and a second portion of the first gate electrode layer and a second portion of the second gate electrode layer contact the seed layer; and A first dielectric material is deposited in the opening on the first gate electrode layer and the second gate electrode layer and in contact with the first gate electrode layer and the second gate electrode layer.

36. The method of claim 35, wherein: Also includes: A dielectric feature is formed between the first gate electrode layer and the second gate electrode layer.

37. The method of claim 36, wherein: Wherein forming the dielectric feature comprises: forming a liner layer between the first gate electrode layer and the second gate electrode layer; forming a second dielectric material on the liner layer; and A third dielectric material is formed on the liner layer and the second dielectric material.

38. The method of claim 36, wherein: The first dielectric material is deposited on the dielectric feature.

39. The method of claim 38, wherein The first dielectric material is deposited on the conductor layer.

40. The method of claim 39, wherein The method further includes forming a conductive feature through the first dielectric material, the conductive layer and the seed layer, wherein the conductive feature contacts a third gate electrode layer.

41. A method for manufacturing a semiconductor device structure, characterized in that: Include: forming a first fin and a second fin from a substrate; forming a dielectric feature between the first fin and the second fin; forming a gate electrode layer on the substrate and adjacent to the dielectric feature; forming a seed layer on the gate electrode layer and the dielectric feature; forming a conductor layer on the seed layer; forming a first opening in the seed layer and the conductor layer to expose the dielectric feature; and A first dielectric material is formed in the first opening on the dielectric feature.

42. The method of claim 41, wherein Wherein forming the dielectric feature comprises: forming a liner layer between the first fin and the second fin; forming a second dielectric material on the liner layer; and A third dielectric material is formed on the liner layer and the second dielectric material.

43. The method of claim 41, wherein Also includes: A plurality of interlayer dielectric layers are formed on the substrate, wherein the interlayer dielectric layers define a trench, and the seed layer and the conductor layer are formed on a bottom of the trench.

44. The method of claim 43, wherein: The forming of the seed layer comprises: forming a cladding layer on the interlayer dielectric layers, adjacent to the plurality of spacers in the trench and on the bottom of the trench; removing portions of the cladding layer formed adjacent to the spacers in the trench; and Portions of the cladding layer formed on the interlayer dielectric layers are removed.

45. The method of claim 44, wherein The forming of the seed layer further comprises: forming a mask layer on the cladding layer after removing the portions of the cladding layer formed adjacent to the spacers in the trench; removing portions of the mask on the interlayer dielectric layers through a first etching process to expose portions of the cladding layer; and The exposed portions of the cladding layer are removed by a second etching process.

46. ​​The method of claim 44, wherein: The forming of the seed layer further comprises: forming a mask layer on the cladding layer after removing the portions of the cladding layer formed adjacent to the spacers in the trench; and A planarization process is performed to remove portions of the mask layer and portions of the cladding layer on the interlayer dielectric layers.

47. The method of claim 41, wherein Forming the first dielectric material in the first opening includes forming the first dielectric material on the conductive layer.

48. The method of claim 47, wherein Also includes: forming a second opening in the first dielectric material, the conductive layer, and the seed layer; and A conductor feature is formed in the second opening on the gate electrode layer.

49. A method for manufacturing a semiconductor device structure, characterized in that: Include: forming a gate electrode layer on a substrate; recessing the gate electrode layer, wherein the gate electrode layer is located at a bottom of a trench formed between two interlayer dielectric layers; forming a seed layer on the gate electrode layer, on the two interlayer dielectric layers, and adjacent to the two interlayer dielectric layers, wherein a portion of the seed layer formed on the gate electrode layer has a first thickness, and a portion of the seed layer formed adjacent to the two interlayer dielectric layers has a second thickness smaller than the first thickness; removing the portion of the seed layer formed adjacent to the two interlayer dielectric layers; forming a mask layer on the gate electrode layer and on the seed layer on the two interlayer dielectric layers; removing a portion of the mask layer to expose a portion of the seed layer formed on the two interlayer dielectric layers; removing the exposed portion of the seed layer; Remove the mask layer; and A conductor layer is formed on the seed layer.

50. The method of claim 49, wherein The method further includes forming a contact etching stop layer on the two interlayer dielectric layers.

51. The method of claim 50, wherein: The method further includes forming a plurality of spacers adjacent to and contacting the contact etch stop layer, wherein the portion of the seed layer adjacent to the two interlayer dielectric layers contacts the spacers.

52. The method of claim 51, wherein The method further includes forming a nitrogen-containing layer on any one of the two interlayer dielectric layers, wherein the portion of the seed layer on the two interlayer dielectric layers is on the nitrogen-containing layer.

53. The method of claim 49, wherein: The method further includes forming an opening in the conductor layer and the seed layer.

54. The method of claim 53, wherein: The opening is formed by removing a portion of the conductive layer through a first etching process and removing a portion of the seed layer through a second etching process.

55. A semiconductor device structure, characterized in that Include: a first gate electrode layer; a second gate electrode layer adjacent to the first gate electrode layer; a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer; a seed layer having a first portion disposed on the first gate electrode layer and a second portion disposed on the second gate electrode layer; a conductive layer having a first portion disposed on the first portion of the seed layer and a second portion disposed on the second portion of the seed layer; and A first dielectric material is formed through the seed layer and through the conductor layer, wherein the first dielectric material contacts the dielectric feature, the first and second portions of the seed layer, and the first and second portions of the conductor layer.

56. The semiconductor device structure according to claim 55, wherein Also includes: a plurality of first semiconductor layers, wherein the first gate electrode layer surrounds the first semiconductor layers; and A plurality of second semiconductor layers, wherein the second gate electrode layer surrounds the second semiconductor layers.

57. The semiconductor device structure according to claim 56, wherein: Also includes: a first source / drain epitaxial feature contacting the first semiconductor layers; and A second source / drain epitaxial feature portion contacts the second semiconductor layers.

58. The semiconductor device structure according to claim 57, wherein: The dielectric feature is disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature.

59. The semiconductor device structure according to claim 58, wherein The dielectric feature portion includes a second dielectric material.

60. The semiconductor device structure according to claim 59, wherein The second dielectric material has a first portion and a second portion, the first portion of the second dielectric material is between the first gate electrode layer and the second gate electrode layer, and the second portion of the second dielectric material is placed between the first source / drain epitaxial feature portion and the second source / drain epitaxial feature portion, wherein the first portion of the second dielectric material has a first height, and the second portion of the second dielectric material has a second height less than the first height.

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