Data driver, display apparatus including the same

Abstract

The present invention relates to a data driver and a display apparatus including the same. The data driver includes a digital-to-analog converter, a buffer, and a buffer controller. The digital-to-analog converter is configured to receive a data signal having a digital type and convert the data signal into a data voltage having an analog type. The buffer is configured to buffer the data voltage and output the data voltage. The buffer controller is configured to determine a parameter of the buffer based on previous line data of the data signal and current line data of the data signal.

Description

Technical Field

[0001] Example embodiments of the present invention relate to a data driver, a display device including the data driver, and a method for driving a display panel using the display device. More specifically, example embodiments of the present invention relate to a data driver that compares previous line data and current line data to change parameters of a buffer, a display device including the data driver, and a method for driving a display panel using the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel displays images based on an input image. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver, a data driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The drive controller controls the gate driver and the data driver.

[0003] The data driver includes a buffer. The buffer can transfer the data voltage to the pixel circuitry within a given time (e.g., 1H). As the resolution of the display panel increases, the 1H time is shortened and the bias current of the buffer increases to transfer the data voltage to the pixel circuitry within the shortened 1H time. Increasing the bias current of the buffer can potentially increase the power consumption of the display device. Summary of the Invention

[0004] An exemplary embodiment of the present invention provides a data driver that compares previous line data and current line data to change the parameters of a buffer in order to reduce the power consumption of a display device.

[0005] An exemplary embodiment of the present invention also provides a display device including the data driver.

[0006] An exemplary embodiment of the present invention also provides a method for driving a display panel using the display device.

[0007] In an example embodiment of a data driver according to the present invention, the data driver includes a digital-to-analog converter (DAC), a buffer, and a buffer controller. The DAC is configured to receive a data signal of digital type and convert the data signal into a data voltage of analog type. The buffer is configured to buffer the data voltage and output a data voltage. The buffer controller is configured to determine parameters of the buffer based on previous line data and current line data of the data signal.

[0008] In an example embodiment, the buffer controller may be a subtractor configured to calculate the difference between previous line data and current line data.

[0009] In an example embodiment, the buffer controller can be configured to determine the bias current based on previous line data and current line data.

[0010] In an example embodiment, the buffer may include: a first current source connected to a first power voltage terminal and a first node and configured to have a first bias current; a second current source connected to the first power voltage terminal and the first node and configured to have a second bias current different from the first bias current; and a first switch connected between the second current source and the first node.

[0011] In an example embodiment, the buffer may further include: 1-2 current sources connected between the second node and the second power voltage terminal and configured to have a first bias current; 2-2 current sources connected between the second node and the second power voltage terminal and configured to have a second bias current; and 1-2 switches connected between the second node and the 2-2 current sources.

[0012] In an example embodiment, the buffer may further include: a third current source connected between the first power voltage terminal and the first node, and configured to have a third bias current different from the first bias current and the second bias current; and a second switch connected between the third current source and the first node.

[0013] In an example embodiment, the buffer may further include: 3-2 current sources connected between the second node and the second power voltage terminal and configured to have a third bias current; and 2-2 switches connected between the second node and the 3-2 current sources.

[0014] In an example embodiment, the buffer may include: a differential input section configured to receive an input voltage; a power supply configured to provide bias current to the differential input section; an amplifier configured to amplify the input voltage; and an output section configured to output the amplified input voltage as an output voltage.

[0015] In an example embodiment, the differential input section may include: a first p-type transistor connected to a first input terminal; a first n-type transistor connected to the first input terminal; a second p-type transistor connected to a second input terminal and connected to the first p-type transistor; and a second n-type transistor connected to the second input terminal and connected to the first n-type transistor.

[0016] In an example embodiment, the power supply may include: a first current source connected to a first power voltage terminal and a first node, and configured to have a first bias current; a second current source connected to the first power voltage terminal and the first node, and configured to have a second bias current different from the first bias current; a first switch connected between the second current source and the first node; a 1-2 current source connected between the second node and the second power voltage terminal, and configured to have a first bias current; a 2-2 current source connected between the second node and the second power voltage terminal, and configured to have a second bias current; and a 1-2 switch connected between the second node and the 2-2 current source. A first p-type transistor and a second p-type transistor may be connected at the first node. A first n-type transistor and a second n-type transistor may be connected at the second node.

[0017] In an example embodiment, the amplifier may include: a seventh p-type transistor and an eighth p-type transistor configured to receive a first voltage; a seventh n-type transistor and an eighth n-type transistor configured to receive a second voltage; a third p-type transistor and a fifth p-type transistor connected in series between the first power voltage terminal and the seventh p-type transistor; a fourth p-type transistor and a sixth p-type transistor connected in series between the first power voltage terminal and the eighth p-type transistor; a third n-type transistor and a fifth n-type transistor connected in series between the seventh n-type transistor and the second power voltage terminal; and a fourth n-type transistor and a sixth n-type transistor connected in series between the eighth n-type transistor and the second power voltage terminal.

[0018] In an example embodiment, the output section may include: a ninth p-type transistor connected between a first power voltage terminal and an output terminal; a ninth n-type transistor connected between an output terminal and a second power voltage terminal; a first capacitor including a first electrode connected to a fourth p-type transistor and a sixth p-type transistor and a second electrode connected to the output terminal; and a second capacitor including a first electrode connected to a fourth n-type transistor and a sixth n-type transistor and a second electrode connected to the output terminal.

[0019] In an example embodiment, the data driver may further include: a memory configured to receive current line data, delay the current line data by one line period to generate previous line data, and output the previous line data to a buffer controller.

[0020] In an example embodiment, the memory may include a trigger.

[0021] In the example embodiment, the current line data may have N bits. The buffer controller can be configured to compare the high M bits of the current line data with the high M bits of the previous line data. N is a positive integer. M is a positive integer less than N.

[0022] In an example embodiment of a display device according to the present invention, the display device includes a display panel, a drive controller, a data driver, and a buffer controller. The display panel is configured to display an image based on an input image data. The drive controller is configured to generate a data signal of digital type based on the input image data. The data driver includes a digital-to-analog converter (DAC) and a buffer. The DAC is configured to receive the data signal and convert it into a data voltage of analog type. The buffer is configured to buffer the data voltage and output the data voltage to the display panel. The buffer controller is configured to determine parameters of the buffer based on previous line data and current line data of the data signal.

[0023] In an example embodiment, the buffer controller can be configured to determine the bias current based on previous line data and current line data.

[0024] In an example embodiment, the buffer controller may be located within the data driver.

[0025] In an example embodiment, the buffer controller may be arranged within the drive controller.

[0026] In an example embodiment of a method for driving a display panel according to the present invention, the method includes: generating a data signal of digital type based on input image data; determining a bias current of a buffer based on previous line data and current line data of the input image data; converting the data signal into a data voltage of analog type; buffering the data voltage using the buffer via the bias current; and outputting the data voltage to the display panel.

[0027] Based on the data driver, display device, and method of driving the display panel, previous line data and current line data can be compared to change the parameters of the buffer, thereby reducing the power consumption of the buffer and allowing the buffer to have a high slew rate. Therefore, the display quality of the display device can be maintained at a high level while reducing the power consumption of the display device.

[0028] Furthermore, the buffer controller circuit for adjusting the parameters of the buffer is arranged in the preceding stage of the digital-to-analog converter, allowing the buffer controller circuit to be implemented as a digital circuit operating at low voltage. Therefore, the increase in the area of ​​the data driver due to the buffer controller circuit can be minimized. Attached Figure Description

[0029] The above and other features of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0030] Figure 1 This is a block diagram illustrating an example embodiment of a display device according to a concept of the present invention.

[0031] Figure 2 It is shown in the figure. Figure 1 A block diagram of the data driver.

[0032] Figure 3 It is shown in the figure. Figure 1 A conceptual diagram of the digital-to-analog converter, memory, buffer controller, and buffer of a data driver.

[0033] Figure 4 It is shown in the figure. Figure 1 A conceptual diagram of a data driver's digital-to-analog converter, flip-flops, subtractors, and buffers.

[0034] Figure 5 It is shown in the figure. Figure 2 The circuit diagram of the buffer.

[0035] Figure 6 The graph shows that when the difference between the previous line data and the current line data is small, from Figure 2 A conceptual diagram of the waveform of the data voltage output by the buffer.

[0036] Figure 7 The graph illustrates what happens when the difference between the previous line data and the current line data is large. Figure 2 A conceptual diagram of the waveform of the data voltage output by the buffer.

[0037] Figure 8 It is shown in the figure. Figure 2 The buffer's bias current is based on the absolute value of the difference between the previous line data and the current line data.

[0038] Figure 9 This is a circuit diagram illustrating a buffer of a display device according to an example embodiment of the present invention.

[0039] Figure 10 This is a conceptual diagram illustrating a digital-to-analog converter and buffer for a data driver, as well as a memory and buffer controller for a display device, according to an example embodiment of the present invention. Detailed Implementation

[0040] The concept of the invention will be described in detail below with reference to the accompanying drawings.

[0041] Figure 1 This is a block diagram illustrating an example embodiment of a display device according to a concept of the present invention.

[0042] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0043] For example, the drive controller 200 and the data driver 500 can be integrally formed. For example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed. A drive module that includes at least the integrally formed drive controller 200 and data driver 500 can be a timing controller embedded data driver (TED).

[0044] The display panel 100 has a display area for displaying images and a peripheral area adjacent to the display area.

[0045] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 that intersects the first direction D1.

[0046] The drive controller 200 receives input image data IMG and input control signal CONT from an external device. The input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may further include white image data. The input image data IMG may also include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0047] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0048] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0049] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0050] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0051] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0052] The gate driver 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL. For example, the gate driver 300 may be mounted on the peripheral area of ​​the display panel 100. For example, the gate driver 300 may be integrated into the peripheral area of ​​the display panel 100.

[0053] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0054] In an example embodiment, the gamma reference voltage generator 400 may be arranged in the drive controller 200 or the data driver 500.

[0055] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0056] Reference Figures 2 to 8 Provide a detailed description of the structure and operation of the data drive 500.

[0057] Figure 2 It is shown in the figure. Figure 1 Block diagram of data driver 500.

[0058] Refer to together Figure 1 and Figure 2 The data driver 500 may include a shift register 520, a latch 540, a digital-to-analog converter (DAC) 560, and multiple buffers B1 to BX.

[0059] Shift register 520 sequentially shifts the data signal DATA.

[0060] Latch 540 receives the data signal DATA and temporarily stores the data signal DATA.

[0061] The digital-to-analog converter 560 converts a digital data signal DATA into an analog data voltage based on a gamma reference voltage VGREF. The digital-to-analog converter 560 may include a level shifter for increasing the level of the data signal DATA.

[0062] Buffers B1 to BX buffer the data voltage and output the data voltage to the data line DL of the display panel 100. Buffers B1 to BX can be connected to the data line DL in a one-to-one connection. The number of buffers B1 to BX can be the same as the number of data lines DL.

[0063] Figure 3 It is shown in the figure. Figure 1 Conceptual diagram of the N-BIT DAC1 digital-to-analog converter, MEM memory, buffer controller 580, and buffer B1 of the data driver 500.

[0064] Reference Figures 1 to 3 The data driver 500 may include an N-BIT DAC1 (digital-to-analog converter), a buffer B1, and a buffer controller 580 (sometimes referred to as buffer controller circuitry 580). The N-BIT DAC1 can receive a data signal of digital type (e.g., data signal N-BIT DATA) and convert the data signal (e.g., data signal N-BIT DATA) into a data voltage VD of analog type. The buffer B1 can buffer the data voltage VD and output the data voltage VD. The buffer controller 580 can determine the parameter PAR of the buffer B1 based on the previous line data and the current line data of the data signal (e.g., data signal N-BIT DATA).

[0065] The buffer controller 580 can output the parameter PAR of buffer B1 to buffer B1. Buffer controller circuits 580 can be arranged for each buffer B1 to BX. Therefore, the number of buffer controller circuits 580 can be the same as the number of buffers B1 to BX.

[0066] The data driver 500 may further include a memory MEM. The memory MEM can receive the current line data (PRESENT DATA) and delay the current line data (PRESENT DATA) by one line period to generate the previous line data (PREVIOUS DATA). The memory MEM can output the previous line data (PREVIOUS DATA) to the buffer controller 580.

[0067] For example, the current line data (PRESENT DATA) can have N bits. For example, the buffer controller 580 can compare the high M bits of the current line data (PRESENT DATA) with the high M bits of the previous line data (PREVIOUS DATA). In this document, the memory MEM can receive the high M bits of the current line data (PRESENT DATA) and output the high M bits of the previous line data (PREVIOUS DATA). In this document, N can be a natural number. M can be a natural number less than N.

[0068] When comparing the high M bits of the current line data (PRESENT DATA) with the high M bits of the previous line data (PREVIOUS DATA), the difference between the current line data (PRESENT DATA) and the previous line data (PREVIOUS DATA) can be determined using a small load. This comparison allows for a reduction in the size of the memory (MEM) and lowers the power consumption of the buffer controller 580.

[0069] Alternatively, the buffer controller 580 can compare N bits of the current line data (PRESENT DATA) with N bits of the previous line data. If there are no limitations on the load or power consumption due to the size of the memory MEM and the operation of the buffer controller 580, the buffer controller 580 can compare N bits of the current line data (PRESENT DATA) with N bits of the previous line data (PREVIOUS DATA) to allow for more precise control of the parameter PAR of the buffer B1.

[0070] Figure 4 It is shown in the figure. Figure 1 A conceptual diagram of the N-BIT DAC1 digital-to-analog converter, flip-flop FF, subtractor 582, and buffer B1 of the data driver 500. Figure 4 It can be illustrated as including Figure 3 Specific examples of circuit components.

[0071] Reference Figures 1 to 4 An example of a buffer controller could be a subtractor 582 that calculates the difference between the previous line data PREVIOUS DATA and the current line data PRESENT DATA. For instance, subtractor 582 could calculate the absolute value of the difference between the previous line data PREVIOUS DATA and the current line data PRESENT DATA. Subtractor 582 could then determine the bias current IB of buffer B1 based on the absolute value of the difference between the previous line data PREVIOUS DATA and the current line data PRESENT DATA.

[0072] Buffer B1 may have a bias current IB that varies according to the previous line data PREVIOUS DATA and the current line data PRESENT DATA. For example, as the absolute value of the difference between the previous line data PREVIOUS DATA and the current line data PRESENT DATA increases, the bias current IB of buffer B1 corresponding to the current line data PRESENT DATA may increase. Conversely, as the absolute value of the difference between the previous line data PREVIOUS DATA and the current line data PRESENT DATA decreases, the bias current IB of buffer B1 corresponding to the current line data PRESENT DATA may decrease.

[0073] For example, a memory example could be a flip-flop FF. The size of the flip-flop FF could correspond to the high M bits of the current line data PRESENTDATA.

[0074] Figure 5 It is shown in the figure. Figure 2 The circuit diagram of buffer B1.

[0075] Reference Figures 1 to 5 The buffer (e.g., buffer B1) may include a differential input section 20, power supplies 40A and 40B, an amplifier 60, and an output section 80.

[0076] The differential input section 20 can receive input voltages VIN(+) and VIN(-). The input voltages VIN(+) and VIN(-) can be of differential type.

[0077] Power supplies 40A and 40B can provide bias current IB to the differential input section 20.

[0078] Amplifier 60 can receive input voltages VIN(+) and VIN(-) from differential input section 20 and amplify input voltages VIN(+) and VIN(-).

[0079] The output section 80 can output an amplified input voltage as the output voltage VOUT.

[0080] The differential input section 20 may include a first p-type transistor P1 connected to a first input terminal receiving a first differential input voltage VIN(+) and a first n-type transistor N1 connected to the first input terminal. The differential input section 20 may further include a second p-type transistor P2 connected to a second input terminal receiving a second differential input voltage VIN(-) and connected to the first p-type transistor P1, and a second n-type transistor N2 connected to the second input terminal and connected to the first n-type transistor N1.

[0081] Power supplies 40A and 40B may include a first current source IB11 connected between a first power voltage terminal receiving a first power voltage VDD and a first node, a second current source IB21 connected between the first power voltage terminal and the first node, and a first switch SW11 connected between the second current source IB21 and the first node. The first current source IB11 may have a first bias current. The second current source IB21 may have a second bias current different from the first bias current.

[0082] For example, the first bias current of the first current source IB11 can be represented as the first bias current IB1, and the second bias current of the second current source IB21 can be represented as the second bias current IB2. For example, the first bias current IB1 can be greater than the second bias current IB2.

[0083] The first switch SW11 can be turned on and off by the first switch control signal CTRL1 of the buffer controller 580. When the first switch SW11 is off, the bias current of the buffer B1 can be the first bias current IB1. When the first switch SW11 is on, the bias current of the buffer B1 can be the sum of the first bias current IB1 and the second bias current IB2, which is IB1 + IB2.

[0084] Power supplies 40A and 40B may further include a 1-2 current source IB12 connected between the second node and the second power voltage terminal receiving the second power voltage VSS, a 2-2 current source IB22 connected between the second node and the second power voltage terminal, and a 1-2 switch SW12 connected between the second node and the 2-2 current source IB22. The 1-2 current source IB12 may have a first bias current IB1. The 2-2 current source IB22 may have a second bias current IB2.

[0085] Similar to the first switch SW11, the 1-2 switch SW12 can be controlled by the first switch control signal CTRL1.

[0086] Appropriately, the current IB1 of the first current source IB11 and the current source IB12 can be the same as each other. However, in practice, the current IB1 of the first current source IB11 and the current source IB12 can be slightly different from each other.

[0087] Appropriately, the current IB2 of the second current source IB21 and the 2-2 current source IB22 can be the same as each other. However, in practice, the current IB2 of the second current source IB21 and the 2-2 current source IB22 can be slightly different from each other.

[0088] In this example embodiment, power supplies 40A and 40B may further include a third current source IB31 connected between the first power voltage terminal and the first node, and a second switch SW21 connected between the third current source IB31 and the first node. The third current source IB31 may have a third bias current IB3 that is different from the first bias current IB1 and the second bias current IB2.

[0089] For example, the third bias current IB3 can be less than the first bias current IB1 and the second bias current IB2.

[0090] The second switch SW21 can be turned on and off via the second switch control signal CTRL2 of the buffer controller 580. When the second switch SW21 is off, the bias current of the buffer B1 can be the first bias current IB1. When the second switch SW21 is on, the bias current of the buffer B1 can be the sum of the first bias current IB1 and the third bias current IB3, which is IB1 + IB3.

[0091] When both the first switch SW11 and the second switch SW21 are turned on, the bias current of the buffer B1 can be the sum of the first bias current IB1, the second bias current IB2, and the third bias current IB3, which is IB1+IB2+IB3.

[0092] In this example embodiment, power supplies 40A and 40B may further include a 3-2 current source IB32 connected between the second node and the second power voltage terminal, and a 2-2 switch SW22 connected between the second node and the 3-2 current source IB32. The 3-2 current source IB32 may have a third bias current IB3.

[0093] Similar to the second switch SW21, the 2-2 switch SW22 can be controlled by the second switch control signal CTRL2.

[0094] Appropriately, the current IB3 of the third current source IB31 and the 3-2 current source IB32 can be the same as each other. However, in practice, the current IB3 of the third current source IB31 and the 3-2 current source IB32 can be slightly different from each other.

[0095] Amplifier 60 may include a seventh p-type transistor P7 and an eighth p-type transistor P8 that receive a first voltage VBP, and a seventh n-type transistor N7 and an eighth n-type transistor N8 that receive a second voltage VBN. Amplifier 60 may further include a third p-type transistor P3 and a fifth p-type transistor P5 connected in series between the first power voltage terminal and the seventh p-type transistor P7. Amplifier 60 may further include a fourth p-type transistor P4 and a sixth p-type transistor P6 connected in series between the first power voltage terminal and the eighth p-type transistor P8. Amplifier 60 may further include a third n-type transistor N3 and a fifth n-type transistor N5 connected in series between the seventh n-type transistor N7 and the second power voltage terminal. Amplifier 60 may further include a fourth n-type transistor N4 and a sixth n-type transistor N6 connected in series between the eighth n-type transistor N8 and the second power voltage terminal.

[0096] The output section 80 may include a ninth p-type transistor P9 connected between the first power voltage terminal and the output terminal of the output voltage VOUT, and a ninth n-type transistor N9 connected between the output terminal and the second power voltage terminal.

[0097] The output section 80 may further include a first capacitor C1, which includes a first electrode connected to the fourth p-type transistor P4 and the sixth p-type transistor P6, and a second electrode connected to the output terminal. The output section 80 may further include a second capacitor C2, which includes a first electrode connected to the fourth n-type transistor N4 and the sixth n-type transistor N6, and a second electrode connected to the output terminal.

[0098] Figure 6 The graph shows that when the difference between the previous line data VA and the current line data VB is small, from Figure 2 The data voltage VD output by the buffer (see) Figure 3 or Figure 4 A conceptual diagram of the waveform. In one embodiment, Figure 6 and Figure 7 The previous line data VA and the current line data VB are as described above. Figure 3 and Figure 4 The PREVIOUS DATA and PRESENT DATA in the previous line data are the same data. Figure 7 The graph illustrates what happens when the difference between the previous line data VA and the current line data VB is large. Figure 2 A conceptual diagram of the waveform of the data voltage VD output by the buffer. Figure 8 It is shown in the figure. Figure 2 The buffer's bias current IB is based on the absolute value of the difference between the previous line data VA and the current line data VB.

[0099] exist Figure 6 In the diagram, the first curve CV1 represents the data voltage when the bias current IB is set to the sum of the first bias current IB1, the second bias current IB2, and the third bias current IB3, which is IB1+IB2+IB3, and the second curve CV2 represents the data voltage when the bias current IB is set to the first bias current IB1.

[0100] exist Figure 7 In the diagram, the third curve CV3 represents the data voltage when the bias current IB is set to the sum of the first bias current IB1, the second bias current IB2, and the third bias current IB3, which is IB1+IB2+IB3, and the fourth curve CV4 represents the data voltage when the bias current IB is set to the first bias current IB1.

[0101] exist Figure 6 In this case, the absolute value of the difference between the previous line data VA and the current line data VB is small, so that even if the bias current IB is set to a small value, the data voltage can be sufficiently transmitted to the pixel within the 1H period, for example, see the second curve CV2.

[0102] For example, in Figure 6 In this context, the bias current IB can be set to the first bias current IB1, and Figure 5 The first switch SW11, the 1-2 switch SW12, the second switch SW21, and the 2-2 switch SW22 can be disconnected.

[0103] On the contrary, Figure 7 In this case, the absolute value of the difference between the previous line data VA and the current line data VB is large, which means that if the bias current IB is set to small, the data voltage may not be sufficiently transmitted to the pixel within the 1H period, for example, see the fourth curve CV4.

[0104] For example, in Figure 7 In this configuration, the bias current IB can be set as the sum of the first bias current IB1, the second bias current IB2, and the third bias current IB3, i.e., IB1 + IB2 + IB3. Figure 5 The first switch SW11, the 1-2 switch SW12, the second switch SW21, and the 2-2 switch SW22 can be connected.

[0105] Figure 8 This example demonstrates how to set the buffer's bias current IB based on the absolute value of the difference between the previous line data VA and the current line data VB.

[0106] When the absolute value of the difference between the previous line data VA and the current line data VB is equal to or less than VDD / 4, the bias current IB can be set to the first bias current IB1.

[0107] When the absolute value of the difference between the previous line data VA and the current line data VB is greater than VDD / 4 and equal to or less than VDD / 2, the bias current IB can be set to the sum of the first bias current IB1 and the second bias current IB2, IB1+IB2.

[0108] When the absolute value of the difference between the previous line data VA and the current line data VB is greater than VDD / 2 and equal to or less than 3VDD / 4, the bias current IB can be set to the sum of the first bias current IB1 and the third bias current IB3, IB1+IB3.

[0109] When the absolute value of the difference between the previous line data VA and the current line data VB is greater than 3VDD / 4, the bias current IB can be set to the sum of the first bias current IB1, the second bias current IB2, and the third bias current IB3, which is IB1+IB2+IB3.

[0110] According to this example embodiment, the parameters of the buffer can be changed by comparing previous line data and current line data, thereby reducing the power consumption of the buffer and allowing the buffer to have a high slew rate. Therefore, the display quality of the display device can be maintained at a high level while reducing the power consumption of the display device.

[0111] Furthermore, the buffer controller circuit for adjusting the parameters of the buffer is arranged in the preceding stage of the digital-to-analog converter, allowing the buffer controller circuit to be implemented as a digital circuit operating at low voltage. Therefore, the increase in the area of ​​the data driver due to the buffer controller circuit can be minimized.

[0112] Figure 9 This is a circuit diagram illustrating a buffer of a display device according to an example embodiment of the present invention.

[0113] Apart from the structure of the power supply for the buffer, the data driver, display device, and method for driving the display panel according to this example embodiment are also referenced. Figures 1 to 8 The data driver, display device, and method of driving the display panel described in the previous example embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the data driver, display device, and method of driving the display panel described in the previous examples. Figures 1 to 8 The parts described in the previous example embodiments are the same or similar to those described above, and any repeated descriptions of the above elements will be omitted.

[0114] Reference Figures 1 to 4 and Figure 9 The buffer (e.g., buffer B1) may include a differential input section 20, power supplies 41A and 41B, an amplifier 60, and an output section 80.

[0115] The differential input section 20 can receive input voltages VIN(+) and VIN(-). The input voltages VIN(+) and VIN(-) can be of differential type.

[0116] Power supplies 41A and 41B can provide bias current IB to differential input section 20.

[0117] Amplifier 60 can receive input voltages VIN(+) and VIN(-) from differential input section 20 and amplify input voltages VIN(+) and VIN(-).

[0118] The output section 80 can output an amplified input voltage as the output voltage VOUT.

[0119] The differential input section 20 may include a first p-type transistor P1 connected to a first input terminal receiving a first differential input voltage VIN(+) and a first n-type transistor N1 connected to the first input terminal. The differential input section 20 may further include a second p-type transistor P2 connected to a second input terminal receiving a second differential input voltage VIN(-) and connected to the first p-type transistor P1, and a second n-type transistor N2 connected to the second input terminal and connected to the first n-type transistor N1.

[0120] Power supplies 41A and 41B may include a first current source IB11 connected between a first power voltage terminal receiving a first power voltage VDD and a first node, a second current source IB21 connected between the first power voltage terminal and the first node, and a first switch SW11 connected between the second current source IB21 and the first node. The first current source IB11 may have a first bias current. The second current source IB21 may have a second bias current different from the first bias current.

[0121] For example, the first bias current of the first current source IB11 can be represented as the first bias current IB1, and the second bias current of the second current source IB21 can be represented as the second bias current IB2. For example, the first bias current IB1 can be greater than the second bias current IB2.

[0122] The first switch SW11 can be turned on and off by the switch control signal CTRL of the buffer controller 580. When the first switch SW11 is off, the bias current of the buffer B1 can be the first bias current IB1. When the first switch SW11 is on, the bias current of the buffer B1 can be the sum of the first bias current IB1 and the second bias current IB2, IB1 + IB2.

[0123] Power supplies 41A and 41B may further include a 1-2 current source IB12 connected between the second node and the second power voltage terminal receiving the second power voltage VSS, a 2-2 current source IB22 connected between the second node and the second power voltage terminal, and a 1-2 switch SW12 connected between the second node and the 2-2 current source IB22. The 1-2 current source IB12 may have a first bias current IB1. The 2-2 current source IB22 may have a second bias current IB2.

[0124] Similar to the first switch SW11, the 1-2 switch SW12 can be controlled by the switch control signal CTRL.

[0125] Appropriately, the current IB1 of the first current source IB11 and the current source IB12 can be the same as each other. However, in practice, the current IB1 of the first current source IB11 and the current source IB12 can be slightly different from each other.

[0126] Appropriately, the current IB2 of the second current source IB21 and the 2-2 current source IB22 can be the same as each other. However, in practice, the current IB2 of the second current source IB21 and the 2-2 current source IB22 can be slightly different from each other.

[0127] According to this example embodiment, the parameters of the buffer can be changed by comparing previous line data and current line data, thereby reducing the power consumption of the buffer and allowing the buffer to have a high slew rate. Therefore, the display quality of the display device can be maintained at a high level while reducing the power consumption of the display device.

[0128] Furthermore, the buffer controller circuit for adjusting the parameters of the buffer is arranged in the preceding stage of the digital-to-analog converter, allowing the buffer controller circuit to be implemented as a digital circuit operating at low voltage. Therefore, the increase in the area of ​​the data driver due to the buffer controller circuit can be minimized.

[0129] Figure 10 This is a conceptual diagram illustrating a digital-to-analog converter and buffer for a data driver, as well as a memory and buffer controller for a display device, according to an example embodiment of the present invention.

[0130] Apart from the memory and buffer controller being arranged in the drive controller, the data driver, display device, and method for driving the display panel according to this example embodiment are also described. Figures 1 to 8 The data driver, display device, and method of driving the display panel described in the previous example embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the data driver, display device, and method of driving the display panel described in the previous examples. Figures 1 to 8 The parts described in the previous example embodiments are the same or similar to those described above, and any repeated descriptions of the above elements will be omitted.

[0131] Reference Figure 1 , Figure 2 and Figure 10 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0132] The data driver 500 may include a shift register 520, a latch 540, a digital-to-analog converter (DAC) 560, and multiple buffers B1 to BX.

[0133] Shift register 520 sequentially shifts the data signal DATA.

[0134] Latch 540 receives the data signal DATA and temporarily stores the data signal DATA.

[0135] The digital-to-analog converter 560 converts a digital data signal DATA into an analog data voltage based on a gamma reference voltage VGREF. The digital-to-analog converter 560 may include a level shifter for increasing the level of the data signal DATA.

[0136] Buffers B1 to BX buffer the data voltage and output the data voltage to the data line DL of the display panel 100. Buffers B1 to BX can be connected to the data line DL in a one-to-one connection. The number of buffers B1 to BX can be the same as the number of data lines DL.

[0137] The data driver 500 may include an N-BIT DAC1 (digital-to-analog converter) and a buffer B1. The N-BIT DAC1 can receive a data signal of digital type (e.g., a data signal N-BIT DATA) and convert the data signal (e.g., the data signal N-BIT DATA) into a data voltage VD of analog type. The buffer B1 can buffer the data voltage VD and output the data voltage VD.

[0138] The display device may include a buffer controller 220 (sometimes referred to as buffer controller circuit 220). The buffer controller 220 may determine the parameter PAR of the buffer B1 based on the previous line data of the data signal (e.g., the data signal N-BIT DATA) and the current line data of the data signal (e.g., the data signal N-BIT DATA).

[0139] The buffer controller 220 can output the parameter PAR of buffer B1 to buffer B1.

[0140] In this example embodiment, the buffer controller 220 may be arranged within the drive controller 200.

[0141] According to this example embodiment, the parameters of the buffer can be changed by comparing previous line data and current line data, thereby reducing the power consumption of the buffer and allowing the buffer to have a high slew rate. Therefore, the display quality of the display device can be maintained at a high level while reducing the power consumption of the display device.

[0142] Furthermore, the buffer controller circuit for adjusting the parameters of the buffer is arranged in the preceding stage of the digital-to-analog converter, allowing the buffer controller circuit to be implemented as a digital circuit operating at low voltage. Therefore, the increase in the area of ​​the data driver due to the buffer controller circuit can be minimized.

[0143] According to this example embodiment, the power consumption of the display device can be reduced.

[0144] The foregoing is illustrative of the inventive concept and should not be construed as limiting. Although some exemplary embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications to the exemplary embodiments are possible without substantially departing from the novelty and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the clauses "mean plus function" are intended to cover structures described herein as performing the stated function, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and equivalents of the claims are included within the inventive concept.

Claims

1. A data driver, comprising: A digital-to-analog converter is configured to receive a data signal of digital type and convert the data signal into a data voltage of analog type; A buffer is configured to buffer the data voltage and output the data voltage. and A buffer controller is configured to determine the parameters of the buffer based on previous line data and current line data of the data signal. The buffer controller is configured to reduce the power consumption of the buffer and set a high slew rate of the buffer by changing the parameters of the buffer.

2. The data driver according to claim 1, wherein, The buffer controller is a subtractor configured to calculate the difference between the previous line data and the current line data.

3. The data driver according to claim 1, wherein, The buffer controller is configured to determine the bias current based on the previous line data and the current line data.

4. The data driver according to claim 3, wherein, The buffer includes: A first current source is connected to a first power voltage terminal and a first node, and is configured to have a first bias current; A second current source, connected to the first power voltage terminal and the first node, is configured to have a second bias current different from the first bias current; and The first switch is connected between the second current source and the first node.

5. The data driver according to claim 4, wherein, The buffer further includes: 1-2 current sources are connected between the second node and the second power voltage terminal and are configured to have the first bias current; 2-2 Current source, connected between the second node and the second power voltage terminal, and configured to have the second bias current; and Switch 1-2 is connected between the second node and the current source 2-2.

6. The data driver according to claim 5, wherein, The buffer further includes: A third current source is connected between the first power voltage terminal and the first node, and is configured to have a third bias current different from the first bias current and the second bias current; and The second switch is connected between the third current source and the first node.

7. The data driver according to claim 6, wherein, The buffer further includes: 3-2 A current source, connected between the second node and the second power voltage terminal, and configured to have the third bias current; and Switch 2-2 is connected between the second node and the current source 3-2.

8. The data driver according to claim 3, wherein, The buffer includes: The differential input section is configured to receive the input voltage; A power supply is configured to provide the bias current to the differential input portion; An amplifier is configured to amplify the input voltage; and The output section is configured to output the amplified input voltage as the output voltage.

9. The data driver according to claim 8, wherein, The differential input section includes: The first p-type transistor is connected to the first input terminal; A first n-type transistor is connected to the first input terminal; The second p-type transistor is connected to the second input terminal and also connected to the first p-type transistor; and The second n-type transistor is connected to the second input terminal and to the first n-type transistor.

10. The data driver according to claim 9, wherein, The power supply includes: A first current source is connected to a first power voltage terminal and a first node, and is configured to have a first bias current; A second current source is connected to the first power voltage terminal and the first node, and is configured to have a second bias current that is different from the first bias current; A first switch is connected between the second current source and the first node; 1-2 current sources are connected between the second node and the second power voltage terminal and are configured to have the first bias current; 2-2 Current source, connected between the second node and the second power voltage terminal, and configured to have the second bias current; and Switch 1-2 is connected between the second node and the current source 2-2. Wherein, the first p-type transistor and the second p-type transistor are connected at the first node, and The first n-type transistor and the second n-type transistor are connected at the second node.

11. The data driver of claim 10, wherein, The amplifier includes: The seventh p-type transistor and the eighth p-type transistor are configured to receive the first voltage; The seventh n-type transistor and the eighth n-type transistor are configured to receive the second voltage; The third p-type transistor and the fifth p-type transistor are connected in series between the first power voltage terminal and the seventh p-type transistor; The fourth p-type transistor and the sixth p-type transistor are connected in series between the first power voltage terminal and the eighth p-type transistor; The third n-type transistor and the fifth n-type transistor are connected in series between the seventh n-type transistor and the second power voltage terminal; and The fourth n-type transistor and the sixth n-type transistor are connected in series between the eighth n-type transistor and the second power voltage terminal.

12. The data driver according to claim 11, wherein, The output section includes: The ninth p-type transistor is connected between the first power voltage terminal and the output terminal; The ninth n-type transistor is connected between the output terminal and the second power voltage terminal; The first capacitor includes a first electrode connected to the fourth p-type transistor and the sixth p-type transistor, and a second electrode connected to the output terminal; and The second capacitor includes a first electrode connected to the fourth n-type transistor and the sixth n-type transistor, and a second electrode connected to the output terminal.

13. The data driver of claim 1, further comprising: The memory is configured to receive the current line data, delay the current line data by one line period to generate the previous line data, and output the previous line data to the buffer controller.

14. The data driver according to claim 13, wherein, The memory includes triggers.

15. The data driver according to claim 1, wherein, The current line data has N bits. The buffer controller is configured to compare the high M bits of the current line data with the high M bits of the previous line data. Where N is a positive integer, and Where M is a positive integer less than N.

16. A display device, comprising: The display panel is configured to display images based on the input image; The drive controller is configured to generate a data signal of digital type based on the input image data; A data driver includes a digital-to-analog converter and a buffer, the digital-to-analog converter being configured to receive the data signal and convert the data signal into a data voltage of analog type, and the buffer being configured to buffer the data voltage and output the data voltage to the display panel; as well as A buffer controller is configured to determine the parameters of the buffer based on previous line data and current line data of the data signal. The buffer controller is configured to reduce the power consumption of the buffer and set a high slew rate of the buffer by changing the parameters of the buffer.

17. The display device according to claim 16, wherein, The buffer controller is configured to determine the bias current based on the previous line data and the current line data.

18. The display device according to claim 17, wherein, The buffer controller is located in the data driver.

19. The display device according to claim 17, wherein, The buffer controller is located within the drive controller.

20. A display device, comprising: The display panel is configured to display images based on the input image; The drive controller is configured to generate a data signal of digital type based on the input image data; A data driver includes a digital-to-analog converter and a buffer, the digital-to-analog converter being configured to receive the data signal and convert the data signal into a data voltage of analog type, and the buffer being configured to buffer the data voltage and output the data voltage to the display panel; as well as A buffer controller is configured to determine the parameters of the buffer based on previous line data and current line data of the data signal. The buffer includes: A first current source is connected to a first power voltage terminal and a first node, and is configured to have a first bias current; A second current source is connected to the first power voltage terminal and the first node, and is configured to have a second bias current that is different from the first bias current; A first switch is connected between the second current source and the first node; 1-2 current sources are connected between the second node and the second power voltage terminal and are configured to have the first bias current; 2-2 Current source, connected between the second node and the second power voltage terminal, and configured to have the second bias current; and Switch 1-2 is connected between the second node and the current source 2-2. The first switch is controlled by a first switch control signal, the 1-2 switches are controlled by the first switch control signal, the first current source is directly connected to the first node, and the 1-2 current sources are directly connected to the second node.

21. The display device according to claim 20, wherein, The buffer controller is configured to determine the bias current based on the previous line data and the current line data.

22. The display device according to claim 21, wherein, The buffer controller is located in the data driver.

23. The display device according to claim 21, wherein, The buffer controller is located within the drive controller.

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