Power supply voltage generation section and display device including the same

Abstract

A power supply voltage generation section and a display device including the same are provided. The display device includes a display section, a gate drive section, a data drive section, and a power supply voltage generation section. The display section displays an image. The gate drive section supplies a gate signal to the display section. The data drive section supplies a data voltage to the display section. The power supply voltage generation section outputs a power supply voltage to at least one of the display section, the gate drive section, and the data drive section. The power supply voltage generation section includes a charge pump that generates a charge pump voltage that is automatically set to have a headroom and is variable in accordance with a target voltage, and a regulator that generates the power supply voltage based on the charge pump voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to a power supply voltage generating part, a display device including the same, and a power supply voltage generating method using the same, and more particularly, to a power supply voltage generating part generating a charge pump voltage having an automatically set head room margin and being variable according to a target voltage, a display device including the same, and a power supply voltage generating method using the same. BACKGROUND

[0002] Generally, a display device includes a display panel and a display panel driving part. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driving part includes a gate driving part providing a gate signal to the plurality of gate lines, a data driving part providing a data voltage to the plurality of data lines, an emission driving part providing an emission signal to the plurality of emission lines, a power supply voltage generating part generating a power supply voltage, and a driving control part controlling the gate driving part, the data driving part, and the emission driving part.

[0003] The power supply voltage generating part can include a charge pump circuit generating a charge pump voltage used to generate the power supply voltage. The charge pump circuit generates several fixed charge pump voltages, and thus there is a problem in that a head room margin is not optimized and power consumption is large. SUMMARY

[0004] An object of the present application is to provide a power supply voltage generating part generating a charge pump voltage having an automatically set head room margin and being variable according to a target voltage to reduce power consumption of a display device.

[0005] Another object of the present application is to provide a display device including the power supply voltage generating part.

[0006] Another object of the present application is to provide a power supply voltage generating method using the power supply voltage generating part.

[0007] An embodiment of the present application to achieve the object of the present application relates to a power supply voltage generating part including a charge pump and a regulator. The charge pump generates a charge pump voltage having an automatically set head room margin and being variable according to a target voltage. The regulator generates a power supply voltage based on the charge pump voltage.

[0008] In an embodiment of the present application, the absolute value of the charge pump voltage can increase if the absolute value of the target voltage increases.

[0009] In an embodiment of the present application, the head room margin can be variable according to an output load.

[0010] In one embodiment of the present application, it can be that if the output load increases, the absolute value of the headroom increases. It can be that if the output load increases, the absolute value of the charge pump voltage increases.

[0011] In one embodiment of the present application, it can be that the charge pump includes an operator that generates a reference charge pump voltage variable according to the target voltage, a comparator that compares a feedback voltage of the charge pump voltage with the reference charge pump voltage, a flip-flop that outputs a control signal based on a clock signal and an output signal of the comparator, and a switch controller that generates a switch control signal based on an output signal of the flip-flop.

[0012] In one embodiment of the present application, it can be that the charge pump further includes a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier that receive the switch control signal, a first switch connected to the first amplifier, a second switch connected to the second amplifier, a third switch connected to the third amplifier, and a fourth switch connected to the fourth amplifier. It can be that the first switch, the fourth switch, the second switch, and the third switch are connected in series.

[0013] In one embodiment of the present application, it can be that the charge pump further includes a first capacitor including a first electrode connected to the first switch and the fourth switch and a second electrode connected to the second switch and the third switch, and a second capacitor including a first electrode connected to the third switch and a second electrode connected to ground.

[0014] In one embodiment of the present application, it can be that when the switch control signal has a first level, the first switch and the second switch are turned on and the third switch and the fourth switch are turned off. It can be that when the switch control signal has a second level, the third switch and the fourth switch are turned on and the first switch and the second switch are turned off.

[0015] In one embodiment of the present application, it can be that when the switch control signal has the first level, the first capacitor is charged. It can be that when the switch control signal has the second level, a voltage charged to the first capacitor is output to the regulator through the third switch.

[0016] In one embodiment of the present application, it can be that the charge pump further includes a level shifter disposed between the switch controller and the first amplifier to the fourth amplifier.

[0017] In one embodiment of the present application, it can be that the output of the comparator has a first level if the absolute value of the feedback voltage is less than the reference charge pump voltage, and the output of the comparator has a second level if the absolute value of the feedback voltage is greater than or equal to the reference charge pump voltage.

[0018] In one embodiment of the present application, it can be that the regulator includes a fifth amplifier, and a fifth switch connected to an output node of the fifth amplifier. It can be that a control node of the fifth switch is connected to the output node of the fifth amplifier, a input node of the fifth switch is applied with the charge pump voltage, and an output node of the fifth switch outputs the power supply voltage.

[0019] In one embodiment of the present application, it can be that the regulator further includes a first resistor including a first terminal connected to the output node of the fifth switch and a second terminal connected to a first input node of the fifth amplifier, a second resistor including a first terminal connected to the second terminal of the first resistor and a second terminal connected to a ground, and a stabilization capacitor including a first electrode connected to the output node of the fifth switch and a second electrode connected to the ground.

[0020] One embodiment for achieving the other object of the present application relates to a display device including a display section, a gate drive section, a data drive section, and a power supply voltage generation section. The display section displays an image. The gate drive section supplies a gate signal to the display section. The data drive section supplies a data voltage to the display section. The power supply voltage generation section outputs a power supply voltage to at least one of the display section, the gate drive section, and the data drive section. The power supply voltage generation section includes a charge pump that generates a charge pump voltage having an automatically set headroom and being variable according to a target voltage, and a regulator that generates the power supply voltage based on the charge pump voltage.

[0021] In one embodiment of the present application, it can be that the power supply voltage is an initialization voltage output to a pixel of the display section.

[0022] In one embodiment of the present application, it can be that the power supply voltage is a gate low voltage output to the gate drive section and defining a low level of the gate signal.

[0023] In one embodiment of the present application, it can be that the power supply voltage generation section further includes a second charge pump that generates a second charge pump voltage having an automatically set second headroom and being variable according to a second target voltage, and a second regulator that generates a second power supply voltage based on the second charge pump voltage.

[0024] In an embodiment of the present application, the power supply voltage can be an initialization voltage output to pixels of the display section. The second power supply voltage can be a gate low voltage output to the gate drive section and defining a low level of the gate signal.

[0025] In an embodiment of the present application, the headroom can be variable according to an output load.

[0026] An embodiment for achieving the other object of the present application relates to a power supply voltage generation method including the steps of generating a charge pump voltage having an automatically set headroom and being variable according to a target voltage, and generating a power supply voltage based on the charge pump voltage. The headroom can be variable according to an output load.

[0027] (EFFECT OF INVENTION)

[0028] According to the power supply voltage generation section, the display device including the same, and the power supply voltage generation method using the same as described above, the charge pump generates a charge pump voltage having an automatically set headroom and being variable according to a target voltage, so that the headroom of the charge pump voltage can be optimized. Therefore, the power consumption of the display device can be reduced.

[0029] In addition, the power supply voltage generation section can adjust the headroom of the charge pump voltage according to the size of an output load, so that the headroom of the charge pump voltage can be further optimized. Therefore, the power consumption of the display device can be further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a block diagram showing a display device according to an embodiment of the present application.

[0031] Figure 2 is a circuit diagram showing a pixel of the display panel of Figure 1

[0032] Figure 3 is a timing chart showing input signals applied to the pixel of Figure 2

[0033] Figure 4 is a block diagram showing a power supply voltage generation section of Figure 1

[0034] Figure 5 is a circuit diagram showing a first charge pump of Figure 4

[0035] Figure 6 is a timing chart showing input signals, node signals, and output signals of the first charge pump of Figure 5 ​​​​​

[0036] Figure 7 is a timing chart showing an input signal, an output signal of a flip-flop of Figure 5 , and an output signal of a first charge pump of Figure 5 .

[0037] Figure 8 is a table showing a register for setting an arithmetic unit of Figure 5 .

[0038] Figure 9 is a circuit diagram showing a first regulator of Figure 4 .

[0039] Figure 10 is a table showing power consumption of a comparative example and power consumption of the present embodiment.

[0040] Figure 11 is a timing chart showing a first charge pump voltage of a comparative example and a first charge pump voltage of the present embodiment based on a target voltage.

[0041] Figure 12 is a timing chart showing a first charge pump voltage of a comparative example and a first charge pump voltage of the present embodiment based on an output load.

[0042] Symbol explanation:

[0043] 100: display panel; 200: drive control section; 300: gate drive section; 400: gamma reference voltage generation section; 500: data drive section; 600: light emission drive section; 700: power supply voltage generation section; 710: first charge pump; 711: arithmetic unit; 712: switch controller; 713: level shifter; 720: first regulator; 730: second charge pump; 740: second regulator. DETAILED DESCRIPTION

[0044] Hereinafter, the present application will be described in more detail with reference to the accompanying drawings.

[0045] Figure 1 is a block diagram showing a display device to which an embodiment of the present application relates.

[0046] Referring to Figure 1 , the display device includes a display panel 100 and a display panel drive section. The display panel drive section includes a drive control section 200, a gate drive section 300, a gamma reference voltage generation section 400, a data drive section 500, and a light emission drive section 600. The display panel drive section further includes a power supply voltage generation section 700.

[0047] The display panel 100 includes a display section that displays an image and a peripheral section that is disposed adjacent to the display section.

[0048] The display panel 100 includes a plurality of gate lines GWL, GIL, GBL, a plurality of data lines DL, a plurality of light-emitting lines EL, and a plurality of pixels electrically connected to the gate lines GWL, GIL, GBL, the data lines DL, and the light-emitting lines EL, respectively. The gate lines GWL, GIL, GBL extend in a first direction D1, the data lines DL extend in a second direction D2 intersecting the first direction D1, and the light-emitting lines EL extend in the first direction D1.

[0049] The drive control section 200 receives input image data IMG and input control signals CONT from an external device (not shown). For example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, yellow image data, and cyan image data. The input control signals CONT can include a main clock signal and a data strobe signal. The input control signals CONT can also include a vertical synchronization signal and a horizontal synchronization signal.

[0050] The drive control section 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signals CONT.

[0051] The drive control section 200 generates and outputs the first control signal CONT1 for controlling the operation of the gate drive section 300 to the gate drive section 300 based on the input control signals CONT. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0052] The drive control section 200 generates and outputs the second control signal CONT2 for controlling the operation of the data drive section 500 to the data drive section 500 based on the input control signals CONT. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0053] The drive control section 200 generates a data signal DATA based on the input image data IMG. The drive control section 200 outputs the data signal DATA to the data drive section 500.

[0054] The drive control section 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generation section 400 based on the input control signal CONT and outputs it to the gamma reference voltage generation section 400.

[0055] The drive control section 200 generates the fourth control signal CONT4 for controlling the operation of the light emission drive section 600 based on the input control signal CONT and outputs it to the light emission drive section 600.

[0056] The gate drive section 300 generates a gate signal for driving the gate lines GWL, GIL, GBL in response to the first control signal CONT1 input from the drive control section 200. The gate drive section 300 can output the gate signal to the gate lines GWL, GIL, GBL. For example, the gate drive section 300 can be integrated in the peripheral portion of the display panel 100. For example, the gate drive section 300 can be mounted in the peripheral portion of the display panel 100.

[0057] The gamma reference voltage generation section 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 input from the drive control section 200. The gamma reference voltage generation section 400 supplies the gamma reference voltage VGREF to the data drive section 500. The gamma reference voltage VGREF has a value corresponding to each data signal DATA.

[0058] For example, the gamma reference voltage generation section 400 can be arranged in the drive control section 200 or can be arranged in the data drive section 500.

[0059] The data drive section 500 receives the input of the second control signal CONT2 and the data signal DATA from the drive control section 200 and receives the input of the gamma reference voltage VGREF from the gamma reference voltage generation section 400. The data drive section 500 converts the data signal DATA into a data voltage in an analog form using the gamma reference voltage VGREF. The data drive section 500 outputs the data voltage to the data line DL.

[0060] The light emission drive section 600 generates a light emission signal for driving the light emission line EL in response to the fourth control signal CONT4 input from the drive control section 200. The light emission drive section 600 can output the light emission signal to the light emission line EL. For example, the light emission drive section 600 can be integrated in the peripheral portion of the display panel 100. For example, the light emission drive section 600 can be mounted in the peripheral portion of the display panel 100. Figure 1The illustration shows a case where the gate driving portion 300 is disposed on a first side of the display panel 100 and the light-emitting driving portion 600 is disposed on a second side opposite to the first side of the display panel 100; however, the present invention is not limited thereto. The gate driving portion 300 and the light-emitting driving portion 600 may be disposed on the same side with reference to the display panel 100. For example, the gate driving portion 300 and the light-emitting driving portion 600 may be integrated in a peripheral portion on the same side with reference to the display portion of the display panel 100.

[0061] The power supply voltage generation unit 700 can provide power supply voltage to at least one of the display panel 100, the drive control unit 200, the gate drive unit 300, the gamma reference voltage generation unit 400, the data drive unit 500, and the light emission drive unit 600.

[0062] For example, the power supply voltage generation unit 700 can output an initialization voltage VINT to the pixels of the display panel 100. For example, the power supply voltage generation unit 700 can output a high power supply voltage ELVDD and a low power supply voltage ELVSS to the pixels of the display panel 100. In this embodiment, the display device can be an organic light-emitting display device including organic light-emitting elements. However, the present invention is not limited to organic light-emitting display devices.

[0063] For example, the power supply voltage generation unit 700 can generate a gate high voltage VGH and a gate low voltage VGL used to generate the gate signal and output them to the gate driving unit 300.

[0064] For example, the power supply voltage generation unit 700 can generate an analog high voltage that determines the level of the data voltage and output it to the data drive unit 500.

[0065] Figure 2 It means Figure 1 Circuit diagram of a display panel with 100 pixels. Figure 3 It means to Figure 2 A timing diagram of the input signal applied to the pixels.

[0066] Reference Figures 1 to 3 The display panel 100 includes a plurality of pixels, each of which includes an organic light-emitting element (OLED).

[0067] The pixel input data is written to the gate signal GW, the data initialization gate signal GI, the organic light-emitting element initialization gate signal GB, the data voltage VDATA, and the light emission signal EM. The organic light-emitting element OLED is made to emit light according to the level of the data voltage VDATA, thereby displaying the image.

[0068] At least one of the plurality of pixels can include a first thin film transistor T1 to a seventh thin film transistor T7, an energy storage capacitor CST, and the organic light emitting element OLED.

[0069] The first thin film transistor T1 includes a control electrode connected to a first pixel node N1, an input electrode connected to a second pixel node N2, and an output electrode connected to a third pixel node N3.

[0070] For example, the first thin film transistor T1 can be a P-type thin film transistor. The control electrode of the first thin film transistor T1 can be a gate electrode, the input electrode of the first thin film transistor T1 can be a source electrode, and the output electrode of the first thin film transistor T1 can be a drain electrode.

[0071] The second thin film transistor T2 includes a control electrode to which the data write gate signal GW is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second pixel node N2.

[0072] The third thin film transistor T3 includes a control electrode to which the data write gate signal GW is applied, an input electrode connected to the first pixel node N1, and an output electrode connected to the third pixel node N3.

[0073] The fourth thin film transistor T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the first pixel node N1.

[0074] The fifth thin film transistor T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which a high power voltage ELVDD is applied, and an output electrode connected to the second pixel node N2.

[0075] The sixth thin film transistor T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third pixel node N3, and an output electrode connected to an anode of the organic light emitting element OLED.

[0076] The seventh thin film transistor T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage VINT is applied, and an output electrode connected to the anode of the organic light emitting element OLED.

[0077] For example, the first to seventh thin film transistors T1 to T7 can be P-type thin film transistors. The control electrodes of the first to seventh thin film transistors T1 to T7 can be gate electrodes, the input electrodes of the first to seventh thin film transistors T1 to T7 can be source electrodes, and the output electrodes of the first to seventh thin film transistors T1 to T7 can be drain electrodes.

[0078] Differently from this, the first to seventh thin film transistors T1 to T7 can be N-type thin film transistors.

[0079] The storage capacitor CST includes a first electrode to which the high power supply voltage ELVDD is applied and a second electrode connected to the first pixel node N1.

[0080] The organic light emitting element OLED includes the anode and a cathode to which a low power supply voltage ELVSS is applied.

[0081] Referring to Figure 3 In the first interval DU1, the first pixel node N1 and the storage capacitor CST are initialized by the data initialization gate signal GI. In the second interval DU2, the threshold voltage |VTH| of the first thin film transistor T1 is compensated for by the data write gate signal GW, and the data voltage VDATA, which is compensated for the threshold voltage |VTH|, is written to the first pixel node N1. In the third interval DU3, the anode of the organic light emitting element OLED is initialized by the organic light emitting element initialization gate signal GB. In the fourth interval DU4, the organic light emitting element OLED emits light by the emission signal EM, so that the display panel 100 displays an image. That is, in the first to third intervals DU1 to DU3, the emission signal EM[N] can be a high level.

[0082] In the first interval DU1, the data initialization gate signal GI can have an active level. For example, the active level of the data initialization gate signal GI can be a low level. When the data initialization gate signal GI has the active level, the fourth thin film transistor T4 is turned on, and the initialization voltage VINT can be applied to the first pixel node N1. The data initialization gate signal GI[N] of the current drive stage can be the scan signal SCAN[N-1] of the previous drive stage.

[0083] In the second interval DU2, the data write gate signal GW can have an active level. For example, the active level of the data write gate signal GW can be a low level. When the data write gate signal GW has the active level, the second thin film transistor T2 and the third thin film transistor T3 are turned on. In addition, the first thin film transistor Tl is also turned on by the initialization voltage VINT. The data write gate signal GW[N] of the current drive stage can be a scan signal SCAN[N] of the current drive stage.

[0084] Along the path formed by the turned-on first thin film transistor Tl to the third thin film transistor T3, a voltage obtained by subtracting the threshold voltage |VTH| of the first thin film transistor Tl from the data voltage VDATA is set at the first pixel node Nl.

[0085] In the third interval DU3, the organic light emitting element initialization gate signal GB can have an active level. For example, the active level of the organic light emitting element initialization gate signal GB can be a low level. When the organic light emitting element initialization gate signal GB has the active level, the seventh thin film transistor T7 is turned on, and the initialization voltage VINT can be applied to the anode of the organic light emitting element OLED. The organic light emitting element initialization gate signal GB[N] of the current drive stage can be a scan signal SCAN[N+1] of the next drive stage.

[0086] In the present embodiment, a case where the active interval of the organic light emitting element initialization gate signal GB is different from the active interval of the data write gate signal GW is exemplified, but the active interval of the organic light emitting element initialization gate signal GB can coincide with the active interval of the data write gate signal GW. For example, the organic light emitting element initialization gate signal GB[N] of the current drive stage can be a scan signal SCAN[N] of the current drive stage. In this case, the control electrode of the seventh thin film transistor T7 can be connected to the control electrode of the second thin film transistor T2.

[0087] In the fourth interval DU4, the emission signal EM can have an active level. For example, the active level of the emission signal EM can be a low level. When the emission signal EM has the active level, the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned on. In addition, the first thin film transistor Tl is also turned on by the data voltage VDATA.

[0088] A drive current can flow through the fifth thin film transistor T5, the first thin film transistor T1, and the sixth thin film transistor T6 in this order, thereby driving the organic light emitting element OLED. An intensity of the drive current can be determined in accordance with a level of the data voltage VDATA. A luminance of the organic light emitting element OLED can be determined in accordance with the intensity of the drive current.

[0089] Figure 4 is a block diagram of a power supply voltage generation section 700. Figure 1

[0090] According to Figures 1 to 4 , the power supply voltage generation section 700 can include a first charge pump 710 that generates a first charge pump voltage VCP1 having an automatically set first headroom and being variable in accordance with a first target voltage, and a first regulator 720 that generates a first power supply voltage (e.g., VINT) based on the first charge pump voltage VCP1.

[0091] The first charge pump 710 can generate the first charge pump voltage VCP1 based on a charge pump power supply voltage PAVDD.

[0092] For example, the first power supply voltage VINT can be the initialization voltage VINT that is output to the pixels of the display panel 100. The initialization voltage VINT can be applied to an input electrode of the fourth thin film transistor T4 of Figure 2

[0093] In the present embodiment, if an absolute value of the first target voltage (a target value of VINT) increases, an absolute value of the first charge pump voltage VCP1 can increase. For example, if the first headroom is 0.3 V and the first target voltage is -3.5 V, the first charge pump voltage VCP1 can be set to -3.8 V that is -3.5 V minus 0.3 V. For example, if the first headroom is 0.3 V and the first target voltage is -3.7 V, the first charge pump voltage VCP1 can be set to -4.0 V that is -3.7 V minus 0.3 V.

[0094] ​​In addition, the first headroom margin can be variable according to an output load of the first power supply voltage VINT. If the output load of the first power supply voltage VINT increases, the absolute value of the first headroom margin can increase. For example, if the first headroom margin with respect to a first output load is 0.3 V and the first target voltage is -3.5 V, the first charge pump voltage VCP1 can be set to -3.8 V, which is -3.5 V minus 0.3 V. For example, in a case where the output load is a second output load that is larger than the first output load, the first headroom margin can be set to 0.4 V instead of 0.3 V. Thus, if the first headroom margin with respect to the second output load is 0.4 V and the first target voltage is -3.5 V, the first charge pump voltage VCP1 can be set to -3.9 V, which is -3.5 V minus 0.4 V. As described above, if the output load increases, the absolute value of the first charge pump voltage VCP1 increases.

[0095] The power supply voltage generation section 700 can further include a second charge pump 730 that generates a second charge pump voltage VCP2 having a second headroom margin that is automatically set and is variable according to a second target voltage, and a second regulator 740 that generates a second power supply voltage (for example, VGL) based on the second charge pump voltage VCP2.

[0096] The second charge pump 730 can generate the second charge pump voltage VCP2 based on the charge pump power supply voltage PAVDD.

[0097] As with the above, if the absolute value of the second target voltage (a target value of VGL) increases, the absolute value of the second charge pump voltage VCP2 increases. For example, if the second headroom margin is 0.3 V and the second target voltage is -8.8 V, the second charge pump voltage VCP2 can be set to -9.1 V, which is -8.8 V minus 0.3 V. For example, if the second headroom margin is 0.3 V and the second target voltage is -9.0 V, the second charge pump voltage VCP2 can be set to -9.3 V, which is -9.0 V minus 0.3 V.

[0098] In addition, the second headroom margin can be variable according to an output load of the second power supply voltage VGL. If the output load of the second power supply voltage VGL increases, the absolute value of the second headroom margin increases.

[0099] In Figures 5 to 8 , the structure and operation of the first charge pump 710 are described in detail. In Figures 5 to 8 , the first charge pump 710 is exemplified, and the second charge pump 730 can also have the same structure as the first charge pump 710 and can operate in the same manner.

[0100] exist Figure 9 The structure and operation of the first regulator 720 are described in detail below. Figure 9 The first regulator 720 is illustrated in the figure. The second regulator 740 may also have the same structure as the first regulator 720 and may operate in the same manner.

[0101] Figure 5 It means Figure 4 The circuit diagram of the first charge pump 710. Figure 6 It means Figure 5 Timing diagram of the input signal, node signal and output signal of the first charge pump 710. Figure 7 It means Figure 5 The input signal, output signal, and of the trigger FF Figure 5 Timing diagram of the output signal of the first charge pump 710.

[0102] Reference Figures 1 to 7 The first charge pump 710 may include: an arithmetic unit 711 that generates a reference charge pump voltage that is variable according to the target voltage; a comparator A5 that compares the feedback voltage of the first charge pump voltage VCP1 with the reference charge pump voltage; a trigger FF that outputs a control signal based on a clock signal CLK and the output signal of the comparator A5; and a switch controller 712 that generates a switch control signal SWS based on the output signal of the trigger FF.

[0103] The feedback voltage of the first charge pump voltage VCP1 can be input to the comparator A5 through the feedback resistor string FRS connected to the output node of the first charge pump voltage VCP1.

[0104] If the absolute value of the feedback voltage is less than the reference charge pump voltage, then the output of comparator A5 ( Figure 7 The D) can have a first level. Conversely, if the absolute value of the feedback voltage is greater than or equal to the reference charge pump voltage, then the output of the comparator A5 ( Figure 7 The first level (D) can have a second level. Here, the first level can be a high level, and the second level can be a low level.

[0105] The first charge pump 710 may further include: a first amplifier A1, a second amplifier A2, a third amplifier A3 and a fourth amplifier A4, which receive the switch control signal SWS; a first switch S1 connected to the first amplifier A1; a second switch S2 connected to the second amplifier A2; a third switch S3 connected to the third amplifier A3; and a fourth switch S4 connected to the fourth amplifier A4.

[0106] The output signals of the first amplifier A1 and the second amplifier A2 can be inverted.

[0107] The first switch S1, the fourth switch S4, the second switch S2 and the third switch S3 can be connected in series in turn.

[0108] The first charge pump 710 can further include a first capacitor C1 including a first electrode connected with the first switch S1 and the fourth switch S4 (i.e., a node SWN) and a second electrode connected with the second switch S2 and the third switch S3 (i.e., a node CPN), and a second capacitor C2 including a first electrode connected with the third switch S3 and a second electrode connected with the ground. The first capacitor C1 can be a charging capacitor, and the second capacitor C2 can be a stabilizing capacitor of the charge pump voltage. Figure 5 Figure 5 The first capacitor C1 can be a charging capacitor, and the second capacitor C2 can be a stabilizing capacitor of the charge pump voltage.

[0109] When the switch control signal SWS has a first level SWSH, the first switch S1 and the second switch S2 can be turned on, and the third switch S3 and the fourth switch S4 can be turned off, and when the switch control signal SWS has a second level SWSL, the third switch S3 and the fourth switch S4 can be turned on, and the first switch S1 and the second switch S2 can be turned off. Here, the first level SWSH can be a high level, and the second level SWSL can be a low level.

[0110] When the switch control signal SWS has the first level SWSH, the first capacitor C1 is charged. When the switch control signal SWS has the second level SWSL, the voltage charged to the first capacitor C1 can be output to the first regulator 720 through the third switch S3. In Figure 5 In the first regulator 720, the flow of current when the switch control signal SWS has the first level SWSH and the flow of current when the switch control signal SWS has the second level SWSL are shown by dotted lines.

[0111] Referring to Figure 6 When the switch control signal SWS has a first level SWSH (PE2), the first capacitor C1 is charged, the current IC1 of the first capacitor C1 is represented as a negative sign, and the second switch S2 is turned on (i.e., the third switch S3 is turned off), and when the switch control signal SWS has a second level SWSL (PE3), the first capacitor C1 is discharged, the current IC1 of the first capacitor C1 is represented as a positive sign, and the second switch S2 is turned off (i.e., the third switch S3 is turned on). Figure 6 ​IS2 is positive). When the switch control signal SWS has the second level SWSL (PE1, PE3), the first capacitor C1 is discharged, the current IC1 of the first capacitor C1 is represented as a positive sign, and the first switch S1 and the third switch S3 are turned on (i.e., Figure 6 IS3 is positive).

[0112] The first charge pump voltage VCP1 is maintained at a certain target level while the switch control signal SWS alternately has the first level SWSH and the second level SWSL.

[0113] In Figure 7 In the case where the absolute value of the first charge pump voltage VCP1 is smaller than the absolute value of the target voltage VTAR, the output D of the first comparator A5 has a high level. When the output D of the first comparator A5 is high, the flip-flop FF outputs the clock signal CLK as the output signal Q. In Figure 7 The symbol GND represents a ground level (the same in other figures).

[0114] In the case where the absolute value of the first charge pump voltage VCP1 is larger than or equal to the absolute value of the target voltage VTAR, the output D of the first comparator A5 has a low level. When the output D of the first comparator A5 is low, the flip-flop FF outputs a low level as the output signal Q.

[0115] The switch controller 712 generates the switch control signal SWS based on the output signal of the flip-flop FF.

[0116] The first charge pump 710 can further include a level shifter 713 disposed between the switch controller 712 and the first to fourth amplifiers A1 to A4. The level shifter 713 increases the level of the switch control signal SWS to output to the first to fourth amplifiers A1 to A4.

[0117] Figure 8An example of a register that sets the arithmetic unit 711 is shown. The arithmetic unit 711 of the first charge pump 710 can generate a reference charge pump voltage based on a register that stores a headroom corresponding to the headroom HM-VCP1 of the first charge pump voltage VCP1 and the output load ILOAD1 to ILOADN. Similarly, the arithmetic unit of the second charge pump 730 can generate a reference charge pump voltage based on a register that stores a headroom corresponding to the headroom HM-VCP2 of the second charge pump voltage VCP2 and the output load ILOAD1 to ILOADN. In addition, in the register, the effective / ineffective HM-VCP1-EN of the headroom adjustment function of the first charge pump 710 and the effective / ineffective HM-VCP2-EN of the headroom adjustment function of the second charge pump 730 can be set.

[0118] Figure 9 is a circuit diagram of the first regulator 720. Figure 4

[0119] According to Figures 1 to 9 , the first regulator 720 can include a fifth amplifier AMP and a fifth switch SWT connected to an output node of the fifth amplifier AMP. A control node of the fifth switch SWT can be connected to the output node of the fifth amplifier AMP, an input node of the fifth switch SWT can be applied with the first charge pump voltage VCP1, and an output node of the fifth switch SWT can output the first power supply voltage VINT.

[0120] The first regulator 720 can further include a first resistor R1 including a first end connected to the output node of the fifth switch SWT and a second end connected to a first input node of the fifth amplifier AMP, a second resistor R2 including a first end connected to the second end of the first resistor R1 and a second end connected to a ground, and a stabilization capacitor CINT including a first electrode connected to the output node of the fifth switch SWT and a second electrode connected to the ground.

[0121] A target voltage VREF1 of the first power supply voltage VINT can be input to a second input node of the fifth amplifier AMP.

[0122] Figure 10 is a table showing the power consumption of the comparative example and the power consumption of the present embodiment.

[0123] Referring to Figures 1 to 10 ​, the power supply voltage generation section involved in the comparative example does not adjust the headroom based on the target voltage, and therefore exhibits relatively high power consumption (10.5 mW, 20.5 mW, 31 mW). In the comparative example, the first charge pump voltage VCP1 for generating the initialization voltage (i.e., the first power supply voltage) VINT of -3.5 V can be fixed to -7.8 V (-PAVDD). The headroom of the first charge pump voltage VCP1 for generating the initialization voltage VINT can be 4.3 V. The power consumption can be calculated by the multiplication of the headroom and the load current. In the comparative example, the second charge pump voltage VCP2 for generating the gate low voltage (i.e., the second power supply voltage) VGL of -8.8 V can be fixed to -11.1 V (-PAVDD-VIN). The headroom of the second charge pump voltage VCP2 for generating the gate low voltage VGL can be 2.3 V.

[0124] In contrast, the power supply voltage generation section 700 involved in the present embodiment adjusts the headroom based on the target voltage, and therefore exhibits relatively low power consumption (1.5 mW, 1.5 mW, 3 mW). In the present embodiment, the first charge pump voltage VCP1 for generating the initialization voltage VINT of -3.5 V can be adjusted to -3.8 V, which is -3.5 V minus the preset headroom 0.3 V. The headroom of the first charge pump voltage VCP1 for generating the initialization voltage VINT can be 0.3 V. Therefore, the power consumption for generating the initialization voltage VINT has a significantly smaller value compared to the comparative example. In the present embodiment, the second charge pump voltage VCP2 for generating the gate low voltage VGL of -8.8 V can be adjusted to -9.1 V, which is -8.8 V minus the preset headroom 0.3 V. The headroom of the second charge pump voltage VCP2 for generating the gate low voltage VGL can be 0.3 V. Therefore, the power consumption for generating the gate low voltage VGL has a significantly smaller value compared to the comparative example. The difference in power consumption between the comparative example and the present embodiment for generating the initialization voltage VINT and the difference in power consumption between the comparative example and the present embodiment for generating the gate low voltage VGL can be 9 mW and 19 mW, respectively. Therefore, the difference in total power consumption between the comparative example and the present embodiment can be 28 mW.

[0125] Figure 11 is a timing chart showing the first charge pump voltage of the comparative example and the first charge pump voltage of the present embodiment based on the target voltage. Figure 12 is a timing chart showing the first charge pump voltage of the comparative example and the first charge pump voltage of the present embodiment based on the output load.

[0126] As Figure 11As shown, in the case of the comparative example, even if the target voltage VREF1 decreases, a fixed first charge pump voltage VCP1 (FIXED) is generated, in contrast, in the case of the present embodiment, as the target voltage VREF1 decreases, a first charge pump voltage VCP1 (VAR) that decreases in accordance therewith is generated. (As the absolute value of the target voltage VREF1 increases, the absolute value of the first charge pump voltage VCP1 (VAR) increases.)

[0127] As shown, in the case of the comparative example, even if the current IINT based on the output load increases, a fixed first charge pump voltage VCP1 (FIXED) is generated, in contrast, in the case of the present embodiment, as the output load increases, a first charge pump voltage VCP1 (VAR) that decreases in accordance therewith is generated in a state in which the target voltage VREF1 is fixed. (As the output load increases, the absolute value of the first charge pump voltage VCP1 (VAR) increases.) Figure 12

[0128] According to the present embodiment, the charge pump generates a charge pump voltage that has an automatically set headroom and is variable in accordance with a target voltage, and thus the headroom of the charge pump voltage can be optimized. Therefore, the power consumption of the display device can be reduced.

[0129] In addition, the power supply voltage generation section adjusts the headroom of the charge pump voltage in accordance with the size of the output load, and thus the headroom of the charge pump voltage can be further optimized. Therefore, the power consumption of the display device can be further reduced.

[0130] (Industrial Applicability)

[0131] The power supply voltage generation section, the display device, and the power supply voltage generation method according to the present application described above can reduce the power consumption of a display device.

[0132] The above has been described with reference to each embodiment, but it will be understood by those skilled in the art that various modifications and changes can be made to the present application without departing from the spirit and scope of the present application.​

Claims

1. A power supply voltage generation section comprising: a charge pump generating a charge pump voltage variable according to a target voltage with an automatically set headroom; and a regulator generating a power supply voltage based on the charge pump voltage, the charge pump comprising: a calculator generating a reference charge pump voltage variable according to the target voltage; a comparator comparing a feedback voltage of the charge pump voltage with the reference charge pump voltage; a flip-flop outputting a control signal based on a clock signal and an output signal of the comparator; and a switch controller generating a switch control signal based on an output signal of the flip-flop, the charge pump further comprising: a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier receiving the switch control signal; a first switch connected to the first amplifier; a second switch connected to the second amplifier; a third switch connected to the third amplifier; and a fourth switch connected to the fourth amplifier, the first switch, the fourth switch, the second switch, and the third switch being connected in series, the charge pump further comprising: a first capacitor including a first electrode connected to the first switch and the fourth switch, and a second electrode connected to the second switch and the third switch; and a second capacitor including a first electrode connected to the third switch, and a second electrode connected to ground.

2. The power supply voltage generation section according to claim 1, wherein if an absolute value of the target voltage increases, an absolute value of the charge pump voltage increases.

3. The power supply voltage generation section according to claim 1, wherein the headroom is variable according to an output load.

4. The power supply voltage generation section according to claim 3, wherein if the output load increases, an absolute value of the headroom increases, if the output load increases, an absolute value of the charge pump voltage increases.

5. The power supply voltage generation section according to claim 1, wherein the charge pump further comprises a level shifter disposed between the switch controller and the first amplifier to the fourth amplifier.

6. The power supply voltage generation section according to claim 1, wherein if an absolute value of the feedback voltage is smaller than the reference charge pump voltage, an output of the comparator has a first level, if the absolute value of the feedback voltage is larger than or equal to the reference charge pump voltage, the output of the comparator has a second level.

7. A display device comprising: a display section displaying an image; a gate drive section supplying a gate signal to the display section; a data drive section supplying a data voltage to the display section; and a power supply voltage generation section outputting a power supply voltage to at least one of the display section, the gate drive section, and the data drive section, the power supply voltage generation section comprising: a charge pump generating a charge pump voltage variable according to a target voltage with an automatically set headroom; and a regulator generating the power supply voltage based on the charge pump voltage, the charge pump comprising: a calculator generating a reference charge pump voltage variable according to the target voltage; ​ a comparator configured to compare a feedback voltage of the charge pump voltage with the reference charge pump voltage; a flip-flop configured to output a control signal based on a clock signal and an output signal of the comparator; and a switch controller configured to generate a switch control signal based on an output signal of the flip-flop, the charge pump further comprises: a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier configured to receive the switch control signal; a first switch connected to the first amplifier; a second switch connected to the second amplifier; a third switch connected to the third amplifier; and a fourth switch connected to the fourth amplifier, the first switch, the fourth switch, the second switch, and the third switch are connected in series, the charge pump further comprises: a first capacitor comprising a first electrode connected to the first switch and the fourth switch, and a second electrode connected to the second switch and the third switch; and a second capacitor comprising a first electrode connected to the third switch, and a second electrode connected to ground.

Images