Memory controller device and phase correction method

Abstract

The present application provides a memory controller device and a phase correction method. The memory controller device includes a delay line circuit system, a plurality of data sampling circuits, a plurality of phase detection circuits, and a control logic circuit. The delay line circuit system delays a data selection signal to generate first to third clock signals, wherein the second clock signal is used to read a data signal, and the phases of the first to third clock signals differ in sequence by a predetermined value. Each data sampling circuit samples the data signal according to a corresponding one of the first to third clock signals to generate a corresponding one of the first to third signals. A plurality of phase detection circuits compare the first signal with the second signal to generate a first detection signal, and compare the third signal with the second signal to generate a second detection signal. The control logic circuit adjusts the first to third clock signals according to the first detection signal and the second detection signal.

Description

Technical Field

[0001] The present disclosure relates to a memory controller device, and more particularly to a data reading circuit and a phase correction method that do not use an analog phase-locked loop. Background Art

[0002] In some common memories, the read and write operations are performed based on the data strobe signal. In order to correctly read the data stored in the memory, the phase of the data strobe signal needs to be aligned with the data window. However, as the operating conditions (e.g., temperature, voltage) change, the phase of the data strobe signal will drift, resulting in incorrect data being read. Summary of the invention

[0003] In some embodiments, the memory controller device includes a delay line circuit system, a plurality of data sampling circuits, a plurality of phase detection circuits, and a control logic circuit. The delay line circuit system is used to delay a data strobe signal to generate a first clock signal, a second clock signal, and a third clock signal, wherein the second clock signal is used to read a data signal, and the phases of the first clock signal, the second clock signal, and the third clock signal are sequentially different by a predetermined value. Each of the data sampling circuits is used to sample the data signal according to a corresponding one of the first clock signal, the second clock signal, and the third clock signal to generate a corresponding one of the first signal, the second signal, and the third signal. The plurality of phase detection circuits are used to compare the first signal with the second signal to generate a first detection signal, and to compare the third signal with the second signal to generate a second detection signal. The control logic circuit is used to adjust the first clock signal, the second clock signal, and the third clock signal according to the first detection signal and the second detection signal.

[0004] In some embodiments, the phase correction method includes the following operations: delaying a data selection signal to generate a first clock signal, a second clock signal, and a third clock signal, wherein the second clock signal is used to read a data signal, and the phase of the first clock signal, the phase of the second clock signal, and the phase of the third clock signal differ by a predetermined value in sequence; sampling the data signal according to corresponding ones of the first clock signal, the second clock signal, and the third clock signal to generate corresponding ones of the first signal, the second signal, and the third signal; comparing the first signal with the second signal to generate a first detection signal, and comparing the third signal with the second signal to generate a second detection signal; and adjusting the first clock signal, the second clock signal, and the third clock signal according to the first detection signal and the second detection signal.

[0005] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A schematic diagram of an electronic system is drawn according to some embodiments of the present disclosure;

[0007] Figure 1B According to some embodiments of the present disclosure Figure 1A Schematic diagram of the waveform of the relevant signal;

[0008] Figure 2 According to some embodiments of the present disclosure Figure 1A A schematic diagram of a memory controller device;

[0009] Figure 3 According to some embodiments of the present disclosure Figure 2 Schematic diagram of the delay line circuit system;

[0010] Figure 4A A flow chart of a phase correction method according to some embodiments of the present disclosure;

[0011] Figure 4B According to some embodiments of the present disclosure Figure 4A A flowchart of an operation in; and

[0012] Figure 5 According to some embodiments of the present disclosure Figure 2 Schematic diagram of the relevant waveforms in .

[0013] Explanation of symbols

[0014] 100: Electronic Systems

[0015] 110: Processing circuit

[0016] 120: Memory controller device

[0017] 130: Memory

[0018] CLK1~CLK3: clock signal

[0019] D0~D3:Data

[0020] DQ: data signal

[0021] DQS: Data strobe signal

[0022] N1, N2: Negative edge

[0023] P1, P2: Righteousness

[0024] S1~S3:Signal

[0025] Texp: scheduled time

[0026] 210: Delay Line Circuit System

[0027] 220,222,224: Data sampling circuit

[0028] 230,232: Phase detection circuit

[0029] 240: Control logic circuit

[0030] j_max: preset maximum value

[0031] j_min: preset minimum value

[0032] n_max: preset maximum value

[0033] SEL1~SEL3: selection signal

[0034] 310: Buffer Circuit

[0035] 320,330,340: Multiplexer circuit

[0036] O1~Om:output signal

[0037] T: Delay time

[0038] 400: Phase Correction Method

[0039] S410, S420, S430, S440, S450: Operation

[0040] S1-1~S1-4, S2-1~S2-3, S3-1~S3-3, S4-1~S4-5: Steps

[0041] n: Phase

[0042] j: default value DETAILED DESCRIPTION

[0043] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein in the content of this disclosure are only illustrative and should not limit the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.

[0044] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device that is connected in a certain manner by at least one transistor and / or at least one active and passive element to process signals.

[0045] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this article, the words first, second, third, etc. are used to describe and distinguish each element. Therefore, the first element in this article can also be called the second element without departing from the original intention of the present disclosure. For ease of understanding, similar elements in the various drawings will be designated with the same reference numerals.

[0046] Figure 1A FIG. 1 is a schematic diagram of an electronic system 100 according to some embodiments of the present disclosure. In some embodiments, the electronic system 100 may be any type of electronic device (e.g., a computer, a smart phone, etc.) that uses memory. The electronic system 100 includes a processing circuit 110 , a memory controller device 120 , and a memory 130 .

[0047] In some embodiments, the processing circuit 110 may be a circuit having a computing capability of executing software, such as a central processing unit circuit, a microprocessor circuit, etc. In some embodiments, the processing circuit 110 may be various types of data processing chips. The processing circuit 110 may read the data signal DQ from the memory 130 via the memory controller device 120. The memory controller device 120 may be operated as an interface circuit between the processing circuit 110 and the memory 130, which may be used to generate a clock signal CLK2 (such as a clock signal CLK3) according to a data strobe signal DQS from the memory 130. Figure 1B ). The memory controller device 120 can automatically adjust the phase of the clock signal CLK2, and read the data of the data signal DQ according to the clock signal CLK2 to output it as a signal S2 to the processing circuit 110. Through the operation of the memory controller device 120, it can be ensured that the processing circuit 110 can obtain valid data in the data signal DQ by reading the signal S2.

[0048] In some embodiments, the memory 130 may be a double data rate (DDR) synchronous dynamic random access memory. In some embodiments, the memory 130 may be a single data rate (SDR) synchronous dynamic random access memory. The above types of memory 130 are for example only, and the present disclosure is not limited thereto. In other embodiments, the memory 130 may be various memories that use a data selection signal DQS to read / write data.

[0049] Figure 1B According to some embodiments of the present disclosure Figure 1ASchematic diagram of waveforms of related signals in FIG. 1 . In this example, the memory 130 is a DDR synchronous dynamic random access memory. In the read and write operations of the DDR synchronous dynamic random access memory, the data selection signal DQS is either edge-aligned with the data signal DQ or center-aligned with the data signal DQ.

[0050] For example, in the data writing operation, the memory 130 stores one data entry each according to the positive edge and the negative edge of the data strobe signal DQS. For example, the memory 130 stores data D0 at the positive edge P1 of the data strobe signal DQS, and stores data D1 at the negative edge N1 of the data strobe signal DQS. Similarly, the memory 130 stores data D2 and data D3 at the positive edge P2 and the negative edge N2 in sequence.

[0051] Alternatively, in a data read operation, the memory 130 sends a data strobe signal DQS and a data signal DQ to the processing circuit 110, and the processing circuit 110 can delay the data strobe signal DQS by a predetermined time Texp through software (or firmware) to generate a clock signal CLK2. By delaying the predetermined time Texp, the phase of the clock signal CLK2 has a phase difference of about 90 degrees with the phase of the data signal DQ. In this way, the positive edge and the negative edge of the clock signal CLK2 can be aligned with the center of the data D0-D3. The memory controller device 120 can read the data signal DQ according to the positive edge or the negative edge of the clock signal CLK2 to output the valid data in the data signal DQ as the signal S2 to the processing circuit 110. In some embodiments, the memory controller device 120 can automatically adjust the phase of the clock signal CLK2 to avoid the phase of the clock signal CLK2 from drifting due to changes in operating conditions (e.g., temperature, voltage, etc.). In this way, it can be ensured that the processing circuit 110 can stably read the valid data of the data signal DQ.

[0052] Figure 2 According to some embodiments of the present disclosure Figure 1A Schematic diagram of the memory controller device 120 in FIG. In some embodiments, the memory controller device 120 includes a delay line circuit system 210 , a plurality of data sampling circuits 220 , 222 , and 224 , a plurality of phase detection circuits 230 and 232 , and a control logic circuit 240 .

[0053] The delay line circuit system 210 receives the data strobe signal DQS from the memory 130, and is used to delay the data strobe signal DQS to generate the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3. The phases of the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3 are sequentially different by a predetermined value j. For example, if the phase of the clock signal CLK2 is represented as n, the phase of the clock signal CLK1 can be represented as nj, and the phase of the clock signal CLK3 can be represented as n+j. In other words, the phase of the clock signal CLK1 lags behind the phase of the clock signal CLK2 by a predetermined value j, and the phase of the clock signal CL3 leads the phase of the clock signal CLK2 by a predetermined value j. In some embodiments, each of the phase n and the predetermined value j can be represented as a data value, and the control logic circuit 240 can update the selection signal SEL1, the selection signal SEL2, and the selection signal SEL3 according to these data values. The delay line circuit system 210 may adjust the clock signals CLK1 , CLK2 , and CLK3 according to the selection signals SEL1 , SEL2 , and SEL3 .

[0054] Each of the plurality of data sampling circuits 220, 222, and 224 is used to sample the data signal DQ according to a corresponding one of the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3 to generate a corresponding one of the signal S1, the signal S2, and the signal S3. Specifically, the data sampling circuit 220 may be triggered by the positive edge (and / or the negative edge) of the clock signal CLK1 to output the data signal DQ as the signal S1. The data sampling circuit 222 may be triggered by the positive edge (and / or the negative edge) of the clock signal CLK2 to output the data signal DQ as the signal S2, and provide the signal S2 to the MCU. Figure 1A In other words, as previously described Figure 1A As mentioned above, the clock signal CLK2 is used to read the data signal DQ. The data sampling circuit 224 can be triggered according to the positive edge (and / or negative edge) of the clock signal CLK3 to output the data signal DQ as the signal S3.

[0055] In some embodiments, each of the plurality of data sampling circuits 220, 222, and 224 may be implemented by (but not limited to) a D-type flip-flop circuit. The above implementations of the plurality of data sampling circuits 220, 222, and 224 are for example only, and various sampling circuits that can obtain current data according to a clock signal are within the scope of the present disclosure.

[0056] The plurality of phase detection circuits 230 and 232 are used to compare the signal S1 with the signal S2 to generate the detection signal D1, and to compare the signal S3 with the signal S2 to generate the detection signal D2. For example, the phase detection circuit 230 may be used to compare the signal S1 with the signal S2. If the signal S1 is the same as the signal S2, the phase detection circuit 230 may output the detection signal D1 having a first logic value (e.g., a logic value of 1). Alternatively, if the signal S1 is different from the signal S2, the phase detection circuit 230 may output the detection signal D1 having a second logic value (e.g., a logic value of 0). Similarly, the phase detection circuit 232 may be used to compare the signal S3 with the signal S2. If the signal S3 is the same as the signal S2, the phase detection circuit 232 may output the detection signal D2 having a first logic value. Alternatively, if the signal S3 is different from the signal S2, the phase detection circuit 232 may output the detection signal D2 having a second logic value.

[0057] In some embodiments, each of the multiple phase detection circuits 230 and 232 can be implemented by (but not limited to) an XNOR gate. The above implementation of the multiple phase detection circuits 230 and 232 is for example only, and various detection circuits that can determine the difference between data values ​​are within the scope of the present disclosure.

[0058] The control logic circuit 240 is used to adjust the clock signals CLK1, CLK2, and CLK3 according to the detection signals D1 and D2 to ensure that the phase of the clock signal CLK2 can be stably aligned with the center of the data valid interval in the data signal DQ. In some embodiments, the control logic circuit 240 is used to output the selection signals SEL1, SEL2, and SEL3 according to the detection signals D1 and D2. The description here will be referred to later. Figures 2 to 5 illustrate.

[0059] In some embodiments, the control logic circuit 240 may include at least one register, which may be used to store a preset maximum value j_max, a preset minimum value j_min, and a preset maximum value n_max. The preset maximum value j_max and the preset minimum value j_min are used to set the range of the preset value j, and the preset maximum value n_max is used to set the upper limit of the phase n of the clock signal CLK2. In some embodiments, the above-mentioned multiple values ​​may be automatically set by the software executed by the processing circuit 110, or directly input by the user. In some embodiments, these values ​​may be used to adjust the speed of tracking the phase of the clock signal CLK2.

[0060] In some embodiments, the control logic circuit 240 may be implemented by at least one digital circuit. In some embodiments, the at least one digital circuit may be used to execute the following Figure 4AIn some embodiments, the at least one digital circuit may be (but not limited to) a digital signal processing circuit, a microcontroller, etc.

[0061] Figure 3 According to some embodiments of the present disclosure Figure 2 Schematic diagram of the delay line circuit system 210 in FIG. In some embodiments, the delay line circuit system 210 includes a plurality of buffer circuits 310 and a plurality of multiplexer circuits 320, 330, and 340. The plurality of buffer circuits 310 are coupled in series in sequence to delay the data strobe signal DQS. The plurality of output signals O1-Om of the plurality of buffer circuits 310 are transmitted to each of the plurality of multiplexer circuits 320, 330, and 340. Each of the plurality of multiplexer circuits 320, 330, and 340 can output a corresponding one of the plurality of output signals O1-Om as a corresponding one of the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3 according to a corresponding one of the selection signal SEL1, the selection signal SEL2, and the selection signal SEL3.

[0062] For example, the multiplexer circuit 330 may output the output signal On among the multiple output signals O1 to Om as the clock signal CLK2 according to the selection signal SEL2. The multiplexer circuit 320 may output the output signal On-j (not shown in the figure) among the multiple output signals O1 to Om as the clock signal CLK1 according to the selection signal SEL1. The multiplexer circuit 340 may output the output signal On+j (not shown in the figure) among the multiple output signals O1 to Om as the clock signal CLK3 according to the selection signal SEL3. In other words, if a buffer circuit 310 introduces a delay time T, the clock signal CLK2 may be regarded as a signal after the data selection signal DQS is delayed by n buffer circuits 310. Similarly, the clock signal CLK1 may be regarded as a signal after the data selection signal DQS is delayed by nj buffer circuits 310, and the clock signal CLK3 may be regarded as a signal after the data selection signal DQS is delayed by n+j buffer circuits 310. In some embodiments, the processing circuit 110 may select n buffer circuits 310 through software (or firmware), and delay the data strobe signal DQS through the n buffer circuits 310 to generate the clock signal CLK2. In other words, Figure 1B The predetermined time Texp in is equivalent to the sum of n delay times T.

[0063] Refer to Figure 2 , Figure 4A , Figure 4B and Figure 5 , to illustrate the operation of the memory controller device 120. Figure 4A FIG. 4 is a flow chart of a phase correction method 400 according to some embodiments of the present disclosure. Figure 4B According to some embodiments of the present disclosure Figure 4A , and Figure 5 According to some embodiments of the present disclosure Figure 2 In some embodiments, the phase correction method 400 may be (but not limited to) Figure 2 The control logic circuit 240 executes.

[0064] In operation S410, after the electronic system 100 is powered on, the phase of the clock signal CLK2 is automatically corrected to phase n. For example, when the electronic system 100 is powered on, the processing circuit 110 may execute a software to issue a reset instruction (not shown) to the delay line circuit system 210. In response to the reset instruction, the delay line circuit system 210 may delay the data strobe signal DQS for a predetermined time Texp to generate a clock signal CLK2 with phase n, wherein the phase difference between the phase n and the data strobe signal DQS is approximately 90 degrees (as previously described). Figure 1B shown).

[0065] In operation S420, the data strobe signal DQS is delayed and clock signals CLK1, CLK2, and CLK3 are generated according to the selection signals SEL1, SEL2, and SEL3. In operation S430, the data signal DQ is sampled according to the clock signal CLK1 to generate a signal S1, the data signal DQ is sampled according to the clock signal CLK2 to generate a signal S2, and the data signal DQ is sampled according to the clock signal CLK3 to generate a signal S3. In operation S440, the signal S1 is compared with the signal S2 to generate a detection signal D1, and the signal S3 is compared with the signal S2 to generate a detection signal D2. Operations S420, S430, and S440 may refer to the aforementioned Figure 2 and Figure 3 Therefore, no further repetition is given here.

[0066] In operation S450, the selection signals SEL1, SEL2, and SEL3 are updated according to the detection signals D1 and D2 to adjust the phases of the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3. By repeatedly performing operations S420 to S450, the memory controller device 120 can automatically adjust the phase of the clock signal CLK to ensure that the processing circuit 110 can stably read valid data.

[0067] To understand operation S450, refer to Figure 4B and Figure 5, operation S450 may include a plurality of steps S1-1 to S1-4, S2-1 to S2-3, S3-1 to S3-3, and S4-1 to S4-5.

[0068] In step S1-1, the phase n is maintained. In step S1-2, it is confirmed whether the preset value j is the preset maximum value j_max. If the preset value j is not the preset maximum value j_max, step S1-3 is executed. In step S1-3, the preset value j is increased. If the preset value j is the preset maximum value j_max, step S1-4 is executed. In step S1-4, the selection signal SEL1, the selection signal SEL2 and the selection signal SEL3 are updated.

[0069] For example, if Figure 5 As shown, in the first case, the sampling points corresponding to the phase nj of the clock signal CLK1, the phase n of the clock signal CLK2, and the phase n+j of the clock signal CLK3 all fall into the data valid interval of the data signal DQ (i.e., the central area close to the data window). Under this condition, the signal S2 will be the same as each of the signal S1 and the signal S3, so the detection signal D1 and the detection signal D2 both have the first logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can maintain the phase n (i.e., step S1-1), and gradually increase the predetermined value j to the preset maximum value j_max (i.e., steps S1-2 to S1-4) to increase the margin of data sampling. In this way, multiple sampling points can cover the entire range of the data valid interval as much as possible.

[0070] Continue to refer to Figure 4B In step S2-1, the preset value j is maintained. In step S2-2, the phase n is reduced. In step S2-3, the selection signal SEL1, the selection signal SEL2 and the selection signal SEL3 are updated. For example, Figure 5 As shown, in the second case, the multiple sampling points corresponding to the phase nj of the clock signal CLK1 and the phase n of the clock signal CLK2 all fall into the data valid interval of the data signal DQ, and the sampling points corresponding to the phase n+j of the clock signal CLK3 fall into the data fuzzy area (represented by a dotted area, i.e., an area close to the transition edge) of the data signal DQ. Under this condition, the signal S2 will be the same as the signal S1 and different from the signal S3, so the detection signal D1 has a first logic value and the detection signal D2 has a second logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can maintain the preset value j (i.e., step S2-1) and shift the phase n to the left (i.e., step S2-2). In this way, the multiple sampling points can be corrected back to the data valid interval.

[0071] Continue to refer to Figure 4BIn step S3-1, the preset value j is maintained. In step S3-2, the phase n is increased. In step S3-3, the selection signal SEL1, the selection signal SEL2 and the selection signal SEL3 are updated. For example, Figure 5 As shown, in the third case, the sampling point corresponding to the phase nj of the clock signal CLK1 falls into the data fuzzy area in the data signal DQ, and the multiple sampling points corresponding to the phase n of the clock signal CLK2 and the phase n+j of the clock signal CLK3 all fall into the data valid interval. Under this condition, the signal S2 will be the same as the signal S3 and different from the signal S1, so the detection signal D1 has the second logic value and the detection signal D2 has the first logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can maintain the preset value j (i.e., step S3-1) and right shift the phase n (i.e., step S3-2). In this way, the multiple sampling points can be corrected back to the data valid interval. In other words, when the signal S2 is different from one of the signals S1 and S3 and the same as the other of the signals S1 and S3 (i.e., the second case or the third case), the control logic circuit 240 can ensure that valid data can be sampled by shifting the phase n of the clock signal CLK2.

[0072] Continue to refer to Figure 4B , in step S4-1, the phase n is maintained, and the preset value j is set to the preset minimum value j_min. In step S4-2, the selection signal SEL1, the selection signal SEL2 and the selection signal SEL3 are updated. In step S4-3, it is determined whether the signal S2 is the same as the signal S1 and the signal S3 according to the detection signal D1 and the detection signal D2 received in the next cycle. If the signal S2 is different from each of the signal S1 and the signal S3, step S4-4 is executed. If the signal S2 is the same as each of the signal S1 and the signal S3, step S4-5 is executed. In step S4-4, the phase n is reset. In step S4-5, the selection signal SEL1, the selection signal SEL2 and the selection signal SEL3 are updated.

[0073] For example, if Figure 5As shown, the fourth situation may occur under two conditions. Under the first condition, the phase n is wrong and at least two sampling points (including the sampling points corresponding to the phase n) fall into the data fuzzy area. Under the second condition, the preset value j is too large and the multiple sampling points corresponding to the phase nj of the clock signal CLK1 and the phase n+j of the clock signal CLK3 fall into the data fuzzy area. Under these two conditions, the signal S2 will be different from each of the signals S1 and S3, so the detection signal D1 and the detection signal D2 both have the second logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can maintain the phase n, and set the preset value j to the preset minimum value j_min (i.e., step S4-1), and determine whether the signal S2 is the same as the signal S1 and the signal S3 according to the detection signal D1 and the detection signal D2 received in the next stage (i.e., step S4-2 and step S4-3).

[0074] It should be understood that if the preset value j is the preset minimum value j_min and the subsequent signal S2 is still different from each of the signals S1 and S3, it means that the phase n is wrong, so that at least two sampling points (including the sampling points corresponding to the phase n) are still located in the data fuzzy area (i.e., the aforementioned first condition occurs). Under this condition, the detection signal D1 and the detection signal D2 still have the second logic value. In response to the detection signal D1 and the detection signal D2, the control logic circuit 240 can reset the phase n (i.e., step S4-4) to correct the multiple sampling points back to the data valid interval. Alternatively, if the preset value j is the preset minimum value j_min and the subsequent signal S2 is the same as each of the signals S1 and S3, it means that the previous preset value j is too large (i.e., the aforementioned second condition occurs). Under this condition, the detection signal D1 and the detection signal D2 both have the first logic value, and at this time, the selection signal SEL1, the selection signal SEL2, and the selection signal SEL3 can be updated according to the current relevant parameters. In other words, by reducing the preset value j, it is sufficient to correct the plurality of sampling points back to the data valid interval.

[0075] The above operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present disclosure, various operations under the phase correction method 400 can be appropriately added, replaced, omitted or performed in a different order. Alternatively, one or more operations under the phase correction method 400 can be performed simultaneously or partially simultaneously.

[0076] In summary, the memory controller device and phase correction method in some embodiments of the present disclosure do not need to use analog circuits such as phase-locked loops to automatically adjust the phase of the clock signal used to read the data signal. In this way, the circuit layout and phase adjustment mechanism can be simplified. In addition, in some embodiments of the present disclosure, the relevant parameters for phase tracking can be set by software, so it has higher flexibility in use.

[0077] Although the embodiments of the present disclosure are described above, the embodiments are not intended to limit the present disclosure. Technicians in this technical field may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be based on what is defined in the claims of this specification.

Claims

1. A memory controller device, comprising: A delay line circuit system, for delaying a data strobe signal to generate a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal is used to read a data signal, and the phases of the first clock signal, the second clock signal and the third clock signal are sequentially different by a predetermined value; a plurality of data sampling circuits, wherein each of the plurality of data sampling circuits is used to sample the data signal according to a corresponding one of the first clock signal, the second clock signal and the third clock signal to generate a corresponding one of a first signal, a second signal and a third signal; a plurality of phase detection circuits for comparing whether the first signal is identical to the second signal to generate a first detection signal, and for comparing whether the third signal is identical to the second signal to generate a second detection signal; and A control logic circuit is used to adjust the phases of the first clock signal, the second clock signal and the third clock signal according to the first detection signal and the second detection signal to ensure that the phases of the clock signals are stably aligned with the data valid interval in the data signal.

2. The memory controller device of claim 1 , wherein the delay line circuit system comprises: a plurality of buffer circuits, wherein the plurality of buffer circuits are coupled in series in sequence and used to delay the data strobe signal; and a plurality of multiplexer circuits, wherein each of the plurality of multiplexer circuits is configured to output an output signal of a corresponding one of the plurality of buffer circuits as a corresponding one of the first clock signal, the second clock signal, and the third clock signal according to a corresponding one of a first selection signal, a second selection signal, and a third selection signal, The control logic circuit is further configured to output the first selection signal, the second selection signal and the third selection signal in response to the first detection signal and the second detection signal, so as to adjust the first clock signal, the second clock signal and the third clock signal. 3 . The memory controller device of claim 1 , wherein if the second signal is the same as each of the first signal and the third signal, the control logic circuit is configured to gradually increase the predetermined value to a preset maximum value in response to the first detection signal and the second detection signal. 4 . The memory controller device of claim 1 , wherein if the second signal is identical to each of the first signal and the third signal, the control logic circuit is configured to maintain a phase of the second clock signal in response to the first detection signal and the second detection signal.

5. The memory controller device of claim 1 , wherein if the second signal is the same as one of the first signal and the third signal and different from the other of the first signal and the third signal, the control logic circuit is used to shift the phase of the second clock signal in response to the first detection signal and the second detection signal.

6. The memory controller device of claim 1 , wherein if the second signal is the same as one of the first signal and the third signal and different from the other of the first signal and the third signal, the control logic circuit is configured to maintain the predetermined value in response to the first detection signal and the second detection signal.

7. The memory controller device of claim 1 , wherein if the second signal is different from each of the first signal and the third signal, the control logic circuit is used to set the predetermined value to a preset minimum value in response to the first detection signal and the second detection signal, and to determine whether the second signal is the same as the first signal and the third signal based on the first detection signal and the second detection signal received in the next stage. 8 . The memory controller device of claim 7 , wherein if the control logic circuit determines that the second signal is different from each of the first signal and the third signal, the control logic circuit is further configured to reset the phase of the second clock signal.

9. The memory controller device of claim 1 , wherein the phase detection circuit comprises: a first phase detection circuit, configured to output the first detection signal having a first logic value when the first signal is the same as the second signal, and to output the first detection signal having a second logic value when the first signal is different from the second signal; and A second phase detection circuit is used to output the second detection signal with the first logic value when the third signal is the same as the second signal, and to output the second detection signal with the second logic value when the third signal is different from the second signal.

10. A phase correction method, comprising: Delaying a data strobe signal to generate a first clock signal, a second clock signal and a third clock signal, wherein the second clock signal is used to read a data signal, and the phases of the first clock signal, the second clock signal and the third clock signal are sequentially different by a predetermined value; Sampling the data signal according to a corresponding one of the first clock signal, the second clock signal and the third clock signal to generate a corresponding one of a first signal, a second signal and a third signal; Comparing whether the first signal is identical to the second signal to generate a first detection signal, and comparing whether the third signal is identical to the second signal to generate a second detection signal; and The phases of the first clock signal, the second clock signal and the third clock signal are adjusted according to the first detection signal and the second detection signal to ensure that the phases of the clock signals are stably aligned with the data valid interval in the data signal.

Images