A data processing system

Abstract

The present disclosure relates to a data processing system, which can be implemented in a board. The board includes a chip and other supporting components, and the supporting components include, but are not limited to, a storage device, an interface device, and a control device. The storage device is connected to the chip in the chip package structure through a bus and is used for storing data. The storage device may include multiple groups of storage units.

Description

Technical Field

[0001] The present disclosure generally relates to the field of circuits, and more particularly, to a data processing system. Background Art

[0002] Traditionally, a data collector (such as an image sensor, a deserialiser, etc.) and a processor are connected by single-ended signals and clock signals with a width of 8 bits or more. Taking an image sensor as an example, this interconnection method has a short signal transmission distance, a low image resolution, and a low image frame rate. Currently, this transmission method is only applicable to some low-end application scenarios and cannot meet the requirements of complex applications such as transportation, mobile phones, single-lens reflex cameras, and tablet computers.

[0003] With the rapid development of intelligent mobile electronic devices, the interface transmission bandwidth between high-pixel and large-frame-rate data collectors and processors has brought new challenges, and the traditional interface can no longer meet the requirements. Driven by market demand, differential signals have become the bridge for interconnecting data collectors and processors. The Mobile Industry Processor Interface (MIPI) alliance, initiated by companies such as Texas Instruments (TI), Nokia, ARM in the UK, and STMicroelectronics (ST), has taken on this important task. The alliance aims to define and promote standards for interfaces between data collectors, liquid crystal displays, basebands, etc. and processors.

[0004] Currently, mobile devices are no longer satisfied with a single data collector. Taking a mobile phone as an example, multiple data collectors (such as image sensors) have become standard. The traditional method is to add multiple MIPI interfaces to the processor to enable access to multiple data collectors. However, multiple MIPI interfaces have no relevant connection and are completely independent.

[0005] However, since the MIPI signal bandwidth requirements of data collectors vary in different scenarios, configuring multiple high-speed MIPI interfaces on the processor will cause certain waste, increasing the cost and volume of the processor; configuring multiple low-speed MIPI interfaces can only meet some scenarios, reducing the competitiveness of the processor; therefore, the configuration and standard of MIPI interface numbers cannot be unified, and flexible configuration between multiple MIPI interfaces is impossible. Summary of the Invention

[0006] In order to at least partially solve the defect of poor system scalability mentioned in the background art, a data processing system with strong scalability is provided.

[0007] According to a first aspect of the present disclosure, there is provided a data processing system, including a data interface, a clock interface, a mode switching component, and a processor. A first port and a second port are provided on the processor. The data interface includes first, second, third, and fourth data interfaces. The clock interface includes a first clock interface and a second clock interface. The first and second data interfaces are configured to receive first data signals of a data collector and are respectively connected to the first port of the processor through a first data channel and a second data channel. The third and fourth data interfaces are configured to receive second data signals of the data collector and are respectively connected to the second port of the processor through a third data channel and a fourth data channel. The clock interface is configured to receive a clock signal of the data collector and, through the switching of the mode switching component, is connected to the first port and the second port of the processor via corresponding clock channels.

[0008] According to a second aspect of the present disclosure, there is provided a data processing system, including a data interface, a clock interface, a mode switching component, and a processor. A first port, a second port, a third port, and a fourth port are provided on the processor. The data interface includes first to eighth data interfaces. The clock interface includes first to fourth clock interfaces. The data interface is configured to connect to a data collector. The mode switching component includes a first mode switching component and a second mode switching component. Wherein, the data collector includes a first low-precision sensor, a second low-precision sensor, and a high-precision sensor. The first low-precision sensor is connected to the first and second data interfaces and is respectively connected to the first port of the processor through a first data channel and a second data channel. The second low-precision sensor is connected to the third and fourth data interfaces and is respectively connected to the second port of the processor through a third data channel and a fourth data channel. The first mode switching component is switched such that: the first low-precision sensor is connected to the first clock interface and is connected to the first port of the processor through a first clock channel; the second low-precision sensor is connected to the second clock interface and is connected to the second port of the processor through a second clock channel; and the high-precision sensor is connected to the fifth and sixth data interfaces and is respectively connected to the third port of the processor through a fifth data channel and a sixth data channel; the high-precision sensor is connected to the seventh and eighth data interfaces and is respectively connected to the fourth port of the processor through a seventh data channel and an eighth data channel; the high-precision sensor is connected to the third port and the fourth port of the processor through the third clock interface or the fourth clock interface, via the switching of the second mode switching component, and through a third clock channel and a fourth clock channel.

[0009] According to a third aspect of the present disclosure, there is provided a board card including the data processing system as described above.

[0010] According to a fourth aspect of the present disclosure, an electronic device is provided, including the data processing system as described above.

[0011] The technical solution of the present disclosure can be flexibly configured according to actual needs to connect data collectors with different precisions, such as image sensors with different resolutions and different frame rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0013] Figure 1 A schematic diagram of a data processing system according to an embodiment of the present disclosure is shown;

[0014] Figure 2 A schematic diagram of a data processing system when the data collector is a low-precision sensor according to an embodiment of the present disclosure is shown;

[0015] Figure 3 A schematic diagram of a data processing system according to an embodiment of the present disclosure is shown;

[0016] Figure 4 A schematic diagram of a data processing system according to another embodiment of the present disclosure is shown;

[0017] Figure 5 A schematic diagram of a data processing system according to an embodiment of the present disclosure is shown;

[0018] Figures 6a to 6f For Figure 5 More specifically represented, they show a schematic diagram of a data processing system according to an embodiment of the present disclosure;

[0019] Figures 7a - 7d Multiple embodiments of switching from one connection mode to another are shown;

[0020] Figure 8 A schematic diagram of a data processing system according to an embodiment of the present disclosure is shown;

[0021] Figure 9 A schematic diagram of a board is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure.

[0023] Figure 1 A schematic diagram of a data processing system according to an embodiment of the present disclosure is shown.

[0024] As Figure 1 shown, the processing system may include a data interface, a clock interface, a mode switching component 130, and a processor 20. A first port 210 and a second port 220 are provided on the processor 20. The data interface includes a first data interface 1110, a second data interface 1120, a third data interface 1130, and a fourth data interface 1140. The clock interface includes a first clock interface 1210 and a second clock interface 1220. The first data interface 1110 and the second data interface 1120 are used to receive the first data signals of the data collector and are respectively connected to the first port 210 of the processor 20 through a first data channel L1 and a second data channel L2. The third data interface 1130 and the fourth data interface 1140 are used to receive the second data signals of the data collector and are respectively connected to the second port 220 of the processor 20 through a third data channel L3 and a fourth data channel L4. The clock interface is used to receive the clock signal of the data collector and, through the switching of the mode switching component 130, is connected to the first port 210 and the second port 220 of the processor through corresponding clock channels. These components can all be provided on a circuit board 10 or a board.

[0025] It should be understood that the data interfaces 1110-1140 and the clock interfaces 1210-1220 described above are only exemplary representations. In actual applications, corresponding data interfaces and clock interfaces can be added or deleted according to actual needs so that they can cooperate with the corresponding data collectors. The types of these interfaces can also be adjusted accordingly according to the types of the data collectors used. It should also be understood that the mode switching component 130 herein can be a switching switch, and various connections are formed by adjusting this switching switch, or it can be a resistor or discrete devices, and various connections are formed by adjusting the positions of these mode switching components 130.

[0026] The data channels L1-L4 can be data channels for transmitting data signals. Figure 2 An embodiment of the data channels L1-L4 is shown. In Figure 2Among them, each data channel is divided into a P channel and an N channel. That is, the first data channel L1 is divided into channel P1 and channel N1, the second data channel L2 is divided into channel P2 and channel N2, the third data channel L3 is divided into channel P3 and channel N3, and the fourth data channel L4 is divided into channel P4 and channel N4.

[0027] The clock channel can receive a differential clock signal and, according to the type of data collector adopted, be input into different ports of the processor under the control of the mode switching component, so as to facilitate the processing of signals obtained by different types of data collectors. The clock channel is also divided into a P channel and an N channel, namely clock channels CLK P1 and CLK N1, and clock channels CLK P2 and CLK N2.

[0028] Data collectors can be divided into various types such as low-precision sensors and high-precision sensors. The precision here can represent, for example, resolution, frame rate, etc., or other factors that can affect precision. The amount of data transmitted by low-precision sensors is less, so the data can be transmitted through a smaller number of data channels, while the amount of data transmitted by high-precision sensors is more, so a larger number of data channels are required to transmit the data. It should be understood that low precision and high precision are relative concepts. When a certain amount (such as two) of data channels is sufficient to complete data transmission within a predetermined time, the data is considered low-precision data; while when a certain amount of data channels cannot complete data transmission within a predetermined time, the data is considered high-precision.

[0029] The ports of the processor 20 can include various types. For example, they can include a Mobile Industry Processor Interface (MIPI) or a Low Voltage Differential Signaling (LVDS) port. The processor in this application can also adopt any other appropriate type of interface.

[0030] The mode switching component 130 can be switched according to the type of data collector adopted to select an appropriate clock channel. This switching can be manual or automatic. It should be understood that the mode switching component 130 can be a group of switches rather than just a single switch, and a group of switches can respectively control the connection and disconnection of multiple lines. The mode switching component 130 can be a small resistor, and its resistance value can be slightly greater than 0 to replace the switching chip (such as a clock chip or a clock buffer) in the prior art. One advantage of using a small resistor as the mode switching component is that it can reduce costs. In addition, using a small resistor as the mode switching component can complete the switching by means of removal, replacement, etc.

[0031] Figure 3 FIG. 1 shows a schematic diagram of a data processing system when the data collector is a low-precision sensor according to an embodiment of the present disclosure.

[0032] As Figure 3 shown, when the data collector 30 includes a first low-precision sensor 310 and a second low-precision sensor 320, the first low-precision sensor 310 is connected to a first data interface 1110 and a second data interface 1120, and is respectively connected to a first port 210 of the processor through a first data channel L1 and a second data channel L2; the second low-precision sensor 320 is connected to a third data interface 1130 and a fourth data interface 1140, and is respectively connected to a second port 220 of the processor through a third data channel L3 and a fourth data channel L4.

[0033] In this embodiment, two low-precision sensors 310 and 320 are exemplarily connected. Since the data transmitted by the low-precision sensors is less, each port of the processor can be connected to a low-precision sensor.

[0034] As Figure 3 shown, the mode switching component 130 can be switched such that: the first low-precision sensor 310 is connected to a first clock interface 1210, and through the mode switching component 130, is connected to the first port 210 of the processor through a first clock channel; the second low-precision sensor 320 is connected to a second clock interface 1220 and is connected to the second port 220 of the processor through a second clock channel.

[0035] In Figure 3 , the mode switching component 130 can be represented by a resistor. In Figure 3 , only the clock signal of the first low-precision sensor 310 reaches the first port 210 of the processor through the mode switching component, while the clock signal of the second low-precision sensor 320 can be directly connected to the second port 220 of the processor through a wire.

[0036] In this embodiment, the mode switching component 130 can be disconnected, so that the clock signal of the first low-precision sensor 310 can be disconnected from the first port 210 of the processor, while the second low-precision sensor 320 can be always connected to the second port 220 of the processor through a wire.

[0037] Figure 4 FIG. 2 shows a schematic diagram of a data processing system according to another embodiment of the present disclosure.

[0038] As Figure 4As shown, when the data collector 30 includes a first low-precision sensor 310 and a second low-precision sensor 320, the first low-precision sensor 310 is connected to a first data interface 1110 and a second data interface 1120, and is respectively connected to a first port 210 of the processor through a first data channel L1 and a second data channel L2; the second low-precision sensor 320 is connected to a third data interface 1130 and a fourth data interface 1140, and is respectively connected to a second port 220 of the processor through a third data channel L3 and a fourth data channel L4.

[0039] Different from Figure 3 the circuit shown, the mode switching component 130 can be switched such that: the first low-precision sensor 310 is connected to a first clock interface 1210 and is connected to the first port 210 of the processor through a first clock channel; the second low-precision sensor 320 is connected to a second clock interface 1220 and, via the mode switching component 130, is connected to the second port 220 of the processor through a second clock channel.

[0040] In Figure 4 , the mode switching component 130 can be represented by a resistor. In Figure 4 , only the clock signal of the second low-precision sensor 320 reaches the second port 220 of the processor through the mode switching component, while the clock signal of the first low-precision sensor 310 can be directly connected to the first port 210 of the processor through a wire.

[0041] In this embodiment, the mode switching component 130 can be disconnected, so that the clock signal of the second low-precision sensor 320 can be disconnected from the second port 220 of the processor, while the first low-precision sensor 310 can be always connected to the first port 210 of the processor through a wire.

[0042] Figure 5 FIG. shows a schematic diagram of a data processing system according to an embodiment of the present disclosure.

[0043] As Figure 5As shown, when the data collector includes a high-precision sensor 330, the high-precision sensor 330 is connected to a first data interface 1110 and a second data interface 1120, and is respectively connected to a first port 210 of the processor through a first data channel L1 and a second data channel L2; the high-precision sensor 330 is connected to a third data interface 1130 and a fourth data interface 1140, and is respectively connected to a second port 220 of the processor through a third data channel L3 and a fourth data channel L4; the high-precision sensor 330 is connected to the first port 210 and the second port 220 of the processor through a first clock channel and a second clock channel via the switching of the mode switching component 130 through a first clock interface 1210 or a second clock interface 1220.

[0044] In Figure 5 , four data interfaces of the high-precision sensor 330 are respectively connected to the first port 210 of the processor through the first data interface 1110 and the second data interface 1120, and are connected to the second port 220 of the processor through the third data interface 1130 and the fourth data interface 1140, so that a large amount of data obtained by the high-precision sensor 330 can be input into the processor through more data channels.

[0045] In Figure 5 , the high-precision sensor 330 only needs to be connected to one clock interface 1210 or 1220 (exemplarily, in Figure 5 , the clock signal channels connecting the first clock interface 1210 and the second clock interface 1220 are shown by dashed lines exemplarily). Thus, the clock signal received by the clock interface 1210 or 1220 is input into the first port 210 and the second port 220 in two paths. In this embodiment. The mode switching component can be a resistor of a passive device, and the passive device will ensure that the clock signals input into the first port 210 and the second port 220 are synchronized. Compared with the prior art where a chip (active device) is used as the mode switching component, this reduces the need for clock signal synchronization control.

[0046] Figures 6a to 6f For Figure 5 more specific illustration, they show a schematic diagram of a data processing system according to an embodiment of the present disclosure.

[0047] As Figure 6a shown, the high-precision sensor 330 is connected to the first port 210 of the processor through a first clock channel via the mode switching component 130 through a first clock interface 1210; and the high-precision sensor 330 is connected to the second port 220 of the processor through a second clock channel through the first clock interface 1210.

[0048] In Figure 6a , the second clock interface 1220 can be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the first clock interface 1210. One path enters the first port 210 through the mode switching component 130, and the other path enters the second port 220 through a direct connection.

[0049] As Figure 6b shown, the high-precision sensor 330 is connected to the first port 210 of the processor through the first clock interface 1210 via the first clock channel; and the high-precision sensor 330 is connected to the second port 220 of the processor through the first clock interface 1210 via the mode switching component 130 through the second clock channel.

[0050] In Figure 6b , the second clock interface 1220 can be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the first clock interface 1210. One path enters the second port 220 through the mode switching component 130, and the other path enters the first port 210 through a direct connection.

[0051] As Figure 6c shown, the high-precision sensor 330 is connected to the first port 210 of the processor through the second clock interface 1220 via the mode switching component 130 through the first clock channel; and the high-precision sensor 330 is connected to the second port 220 of the processor through the second clock interface 1220 through the second clock channel.

[0052] In Figure 6c , the first clock interface 1210 can be idle without receiving any clock signal. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the second clock interface 1220. One path enters the first port 210 through the mode switching component 130, and the other path enters the second port 220 through a direct connection.

[0053] As Figure 6d shown, the high-precision sensor 330 is connected to the first port 210 of the processor through the second clock interface 1220 through the first clock channel; and the high-precision sensor 330 is connected to the second port 220 of the processor through the second clock interface 1220 via the mode switching component 130 through the second clock channel.

[0054] In Figure 6dIn [description], the first clock interface 1210 can be idle without receiving any clock signals. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the second clock interface 1220. One path enters the second port 220 through the mode switching component 130, and the other path enters the first port 210 through a direct connection.

[0055] Figure 6e Yes Figure 6b An electrical equivalent deformation of the data processing system shown. As Figure 6e shown, as Figure 6b electrically equivalent is that the high-precision sensor 330 is connected to the first port 210 of the processor through the first clock interface 1210 via the first clock channel; and the high-precision sensor 330 is connected to the second port 220 of the processor through the first clock interface 1210 via the mode switching component 130 through the second clock channel. In Figure 6e In [description], the second clock interface 1220 can be idle without receiving any clock signals. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the first clock interface 1210. One path enters the second port 220 through the mode switching component 130, and the other path enters the first port 210 through a direct connection.

[0056] Figure 6b And Figure 6e are electrically equivalent from an electrical aspect, but in Figure 6e In [description], the mode switching component 130 can be arranged on the connection line between the two clock channels, which enables no adjustment to the existing clock channels and only requires setting a new line between the two clock channels, thus simplifying the circuit design. In other embodiments, the signal transmission quality can also be improved by adjusting or removing redundant lines or devices in the clock channels.

[0057] Figure 6f Yes Figure 6c An electrical equivalent deformation of the data processing system shown. As Figure 6f shown, as Figure 6f shown, the high-precision sensor 330 is connected to the first port 210 of the processor through the second clock interface 1220 via the mode switching component 130 through the first clock channel; and the high-precision sensor 330 is connected to the second port 220 of the processor through the second clock interface 1220 through the second clock channel. In Figure 6f In [description], the first clock interface 1210 can be idle without receiving any clock signals. The clock signal of the high-precision sensor 330 is divided into two paths after passing through the second clock interface 1220. One path enters the first port 210 through the mode switching component 130, and the other path enters the second port 220 through a direct connection.

[0058] Figure 6c and Figure 6f are electrically equivalent, but in Figure 6f , the mode switching component 130 can be arranged on the connection line between two clock channels, which enables no adjustment to the existing clock channels and only requires setting a new line between the two clock channels, thus simplifying the circuit design. In other embodiments, the signal transmission quality can also be improved by adjusting or removing redundant lines or devices in the clock channels.

[0059] The above Figures 6a to 6f shown connection manners are essentially equivalent, and any one of them can be adopted in the actual circuit design. It should also be understood that Figures 6a to 6f the position of the mode switching component in

[0060] is only an example, and any circuit that is equivalent to this structure in terms of circuit structure is within the protection scope of the present disclosure.

[0061] Figures 7a - 7d shows multiple embodiments of switching from one connection mode to another.

[0062] As Figure 7a shown, when connecting the first low-precision sensor 310 and the second low-precision sensor 320, the first low-precision sensor 310 can be connected to the contact T1 through the first clock interface 1210, and the contact T1 is then connected to the first port 210 through the mode switching component 130; the second low-precision sensor 320 can be connected to the contact T2 through the second clock interface 1220, and then connected to the second port 220 through the contact T2.

[0063] When connecting the high-precision sensor 330, the mode switching component 130 can be switched, that is, the connection with the contact T1 is disconnected and the connection with the contact T2 is connected, so that the high-precision sensor 330 is connected to the second port 220 through the second clock interface 1220 and the contact T2, and is connected to the first port 210 through the second clock interface 1220 and the mode switching component 130.

[0064] Figure 7b The structure shown in Figure 7a is equivalent to the structure of Figure 7b in terms of circuit structure, but Figure 7a the physical position where the mode switching component 130 is located in

[0065] Figure 7c It shows a schematic diagram of switching from connecting a low-precision sensor to connecting a high-precision sensor.

[0066] As Figure 7c shown, when connecting a low-precision sensor, it behaves as shown in the upper figure of Figure 7c , where the mode switching component 130 is connected between the first clock interface 1210 and the first port 210. When it is necessary to connect a high-precision sensor, the first clock interface 1210 can be disabled without connecting the low-precision sensor, and the mode switching component 130 can be removed. For ease of understanding, the removal and disabling in Figure 7c are indicated by an "X" mark.

[0067] When connecting a high-precision sensor, the first clock interface 1210 is disabled, while the second clock interface 1220 receives the clock signal of the high-precision sensor. The removed mode switching component 130 is connected between the two clock channels, so that the clock signal from the high-precision sensor directly reaches the second port 220 of the processor along one path, and reaches the first port 210 of the processor through the mode switching component 130 along the other path. Thus, the switching from connecting a low-precision sensor to connecting a high-precision sensor is completed. Figure 7d It shows a schematic diagram of switching from connecting a high-precision sensor to connecting a low-precision sensor.

[0068] Figure 7d For Figure 7c the reverse operation. As Figure 7d shown, when connecting a high-precision sensor, the mode switching component 130 is connected between the two clock channels. When it is necessary to connect a low-precision sensor, the first clock interface 1210 can be enabled, and the mode switching component 130 connected between the two clock channels can be removed. For ease of understanding, the removal in Figure 7d is also indicated by an "X" mark.

[0069] When connecting a low-precision sensor, the first clock interface 1210 is enabled and receives the clock signal from the first low-precision sensor 310, while the second clock interface 1220 receives the clock signal from the second low-precision sensor 320. The removed mode switching component 130 is connected between the first clock interface 1210 and the first port 210 (or connected between the second clock interface 1220 and the second port 220), thus completing the switching from connecting a high-precision sensor to connecting a low-precision sensor.

[0070] It should be understood that the mode switching component 130 in the circuit for connecting a low-precision sensor and the mode switching component 130 in the circuit for connecting a high-precision sensor may not be the same, as long as the circuit connection can be achieved.

[0071] The switching described above is merely an example, and those skilled in the art can design various mode switching components to achieve various switching functions.

[0072] Figure 8 A schematic diagram of a data processing system according to an embodiment of the present disclosure is shown.

[0073] As Figure 8 shown, the data processing system includes a data interface, a clock interface, mode switching components 130, and a processor 20. A first port 210, a second port 220, a third port 230, and a fourth port 240 are provided on the processor 20. The data interface includes first to eighth data interfaces 1110 - 1180, and the clock interface includes first to fourth clock interfaces 1210 - 1240. The data interface is used to connect to a data collector 30. The mode switching components 130 include a first mode switching component 1310 and a second mode switching component 1320. Among them, the data collector 30 includes a first low-precision sensor 310, a second low-precision sensor 320, and a high-precision sensor 330. The first low-precision sensor 310 is connected to the first data interface 1110 and the second data interface 1120, and is respectively connected to the first port 210 of the processor through a first data channel L1 and a second data channel L2; the second low-precision sensor 320 is connected to the third data interface 1130 and the fourth data interface 1140, and is respectively connected to the second port 220 of the processor through a third data channel L3 and a fourth data channel L4; the first mode switching component 1310 is switched so that: the first low-precision sensor 310 is connected to the first clock interface 1210 and is connected to the first port 210 of the processor through a first clock channel; the second low-precision sensor 320 is connected to the second clock interface 1220 and is connected to the second port 220 of the processor through a second clock channel; and the high-precision sensor 330 is connected to the fifth data interface 1150 and the sixth data interface 1160, and is respectively connected to the third port 230 of the processor through a fifth data channel L5 and a sixth data channel L6; the high-precision sensor is connected to the seventh data interface 1170 and the eighth data interface 1180, and is respectively connected to the fourth port 240 of the processor through a seventh data channel L7 and an eighth data channel L8; the high-precision sensor 330 is connected to the third port 230 and the fourth port 240 of the processor through the third clock interface 1230 or the fourth clock interface 1240, via the second mode switching component 1320, and through a third clock channel and a fourth clock channel. These components can all be provided on a circuit board 10.

[0074] In Figure 8 it, the connection of the low-precision sensor can be based on the above in combination withFigure 4 and Figure 5 vary as described, and the connection of the high-precision sensor can be varied according to the combination in the foregoing text Figures 6a - 6f vary as described, and the high-precision sensor and the low-precision sensor can be varied according to the combination in the foregoing text Figures 7a - 7d vary as described.

[0075] In Figure 8 , each processor 20 may have multiple ports. Taking four ports as an example, it can be connected to two low-precision sensors and one high-precision sensor; with different requirements, the mode switching component can be adjusted, so that it can be connected to four low-precision sensors or two high-precision sensors. Thus, the technical solution of the present disclosure can be flexibly configured according to actual requirements.

[0076] It should be understood that the number of ports of the processor 20 in the present disclosure is not limited, so various changes can be made to the above data processing system.

[0077] In some embodiments, the present disclosure also discloses a board card, which includes a chip, and the chip can be the processor 20 described above. Refer to Figure 9 , which provides an exemplary board card. In addition to including the above chip 902, the above board card may further include other supporting components, and the supporting components include but are not limited to: a storage device 904, an interface device 906 (which can be the data interface and the clock interface described above in the present disclosure), and a control device 908.

[0078] The storage device is connected to the chip in the chip package structure through a bus for storing data. The storage device may include multiple groups of storage units 910. Each group of the storage units is connected to the chip through a bus. It can be understood that each group of the storage units can be DDR SDRAM (English: Double Data Rate SDRAM, double data rate synchronous dynamic random access memory).

[0079] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of the storage units. Each group of the storage units may include a plurality of DDR4 dies (chips). In one embodiment, the interior of the chip may include 4 72-bit DDR4 controllers, where 64 bits of the 72-bit DDR4 controllers are used for data transmission and 8 bits are used for ECC check. In one embodiment, each group of the storage units includes a plurality of double data rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling DDR is provided in the chip to control data transmission and data storage of each of the storage units.

[0080] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to implement data transmission between the chip and an external device 912 (such as a server, a computer, or the high-precision and / or low-precision sensor described above in the present disclosure). For example, in one embodiment, the interface device may be a standard PCIE interface. For instance, the data to be processed is transferred from the server to the chip through the standard PCIE interface to achieve data transfer. In another embodiment, the interface device may also be other interfaces. The present disclosure does not limit the specific forms of the above other interfaces, as long as the interface unit can achieve the transfer function. Additionally, the calculation result of the chip is still transmitted back to the external device (such as a server) by the interface device.

[0081] The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a microcontroller unit (MCU). For example, the chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Therefore, the chip may be in different working states such as multi-load and light-load. Through the control device, the working states of multiple processing chips, multiple processes, and / or multiple processing circuits in the chip can be regulated.

[0082] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present disclosure is not limited by the described action sequence, because according to the present disclosure, certain steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present disclosure.

[0083] In the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0084] In several embodiments provided by this disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, optical, acoustic, magnetic or other forms.

[0085] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0086] In addition, in each embodiment of this disclosure, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software program modules.

[0087] If the above integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on such an understanding, when the technical solution of this disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, including several instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of this disclosure. And the aforementioned memory includes: various media such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks or optical discs that can store program codes.

[0088] The above has introduced the embodiments of the present disclosure in detail. Specific examples are used in this article to elaborate on the principles and implementation manners of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

Claims

1. A data processing system, comprising a data interface, a clock interface, a mode switching component, and a processor. A first port and a second port are provided on the processor. The data interface includes first, second, third, and fourth data interfaces, and the clock interface includes a first clock interface and a second clock interface; The first and second data interfaces are used to receive the first data signals of a data collector, and are respectively connected to the first port of the processor through a first data channel and a second data channel; The third and fourth data interfaces are used to receive the second data signals of the data collector, and are respectively connected to the second port of the processor through a third data channel and a fourth data channel; The clock interface is used to receive the clock signal of the data collector, and through the switching of the mode switching component according to the type of the data collector, is connected to the first port and the second port of the processor via corresponding clock channels.

2. The data processing system according to claim 1, wherein, When the data collector includes a first low-precision sensor and a second low-precision sensor, The first low-precision sensor is connected to the first and second data interfaces, and is respectively connected to the first port of the processor through a first data channel and a second data channel; The second low-precision sensor is connected to the third and fourth data interfaces, and is respectively connected to the second port of the processor through a third data channel and a fourth data channel; The mode switching component is switched such that: The first low-precision sensor is connected to the first clock interface and is connected to the first port of the processor through a first clock channel; The second low-precision sensor is connected to the second clock interface and is connected to the second port of the processor through a second clock channel.

3. The data processing system according to claim 2, wherein, The mode switching component is switched such that: The first low-precision sensor is connected to the first clock interface and, via the mode switching component, is connected to the first port of the processor through a first clock channel; The second low-precision sensor is connected to the second clock interface and is connected to the second port of the processor through a second clock channel.

4. The data processing system according to claim 2, wherein, The mode switching component is switched such that: The first low-precision sensor is connected to the first clock interface and is connected to the first port of the processor through a first clock channel; The second low-precision sensor is connected to the second clock interface and, via the mode switching component, is connected to the second port of the processor through a second clock channel.

5. The data processing system according to claim 1, wherein, When the data collector includes a high-precision sensor, The high-precision sensor is connected to the first and second data interfaces, and is respectively connected to the first port of the processor through a first data channel and a second data channel; The high-precision sensor is connected to the third and fourth data interfaces, and is respectively connected to the second port of the processor through a third data channel and a fourth data channel; The high-precision sensor is connected to the first port and the second port of the processor through the first clock interface or the second clock interface, via the switching of the mode switching component, and through the first clock channel and the second clock channel.

6. The data processing system according to claim 5, wherein, The high-precision sensor is connected to a first port of the processor through a first clock interface, via the mode switching component, through a first clock channel; and The high-precision sensor is connected to a second port of the processor through a first clock interface, through a second clock channel; or The high-precision sensor is connected to a first port of the processor through a first clock interface, through a first clock channel; And The high-precision sensor is connected to a second port of the processor through a first clock interface, via the mode switching component, through a second clock channel.

7. The data processing system according to claim 5, wherein The high-precision sensor is connected to a first port of the processor through a second clock interface, via the mode switching component, through a first clock channel; and The high-precision sensor is connected to a second port of the processor through a second clock interface, through a second clock channel; or The high-precision sensor is connected to a first port of the processor through a second clock interface, through a first clock channel; And The high-precision sensor is connected to a second port of the processor through a second clock interface, via the mode switching component, through a second clock channel.

8. The data processing system according to any one of claims 1-7, wherein, The mode switching component is a resistor.

9. The data processing system according to any one of claims 1-8, wherein, The port includes a Mobile Industry Processor Port or a Low Voltage Differential Signaling Port.

10. A data processing system, comprising a data interface, a clock interface, a mode switching component, and a processor. A first port, a second port, a third port, and a fourth port are provided on the processor. The data interface includes first to eighth data interfaces, and the clock interface includes first to fourth clock interfaces. The data interface is used to connect a data collector. The mode switching component includes a first mode switching component and a second mode switching component, wherein, The data collector includes a first low-precision sensor, a second low-precision sensor, and a high-precision sensor, The first low-precision sensor is connected to first and second data interfaces, and is respectively connected to a first port of the processor through a first data channel and a second data channel; The second low-precision sensor is connected to third and fourth data interfaces, and is respectively connected to a second port of the processor through a third data channel and a fourth data channel; The first mode switching component is switched such that: The first low-precision sensor is connected to a first clock interface, and is connected to a first port of the processor through a first clock channel; The second low-precision sensor is connected to a second clock interface, and is connected to a second port of the processor through a second clock channel; And The high-precision sensor is connected to fifth and sixth data interfaces, and is respectively connected to a third port of the processor through a fifth data channel and a sixth data channel; The high-precision sensor is connected to seventh and eighth data interfaces, and is respectively connected to a fourth port of the processor through a seventh data channel and an eighth data channel; The high-precision sensor is connected to a third port and a fourth port of the processor through a third clock channel and a fourth clock channel through switching of the second mode switching component through a third clock interface or a fourth clock interface.

11. The data processing system according to claim 10, wherein, The mode switching component is a resistor.

12. The data processing system according to any one of claims 10-11, wherein, The port includes a Mobile Industry Processor Port or a Low Voltage Differential Signaling Port.

13. A board card, comprising the data processing system according to any one of claims 1 to 12.

14. An electronic device, comprising the data processing system according to any one of claims 1 to 12.

Images