A method and device for dynamically processing high-speed data in an image simulator

Abstract

The present invention discloses a method and device for dynamically processing high-speed data in an image simulator, comprising: preprocessing the camera data on the CPU side of the image simulator in memory according to a first preset rule; sending the camera data preprocessed by the CPU side of the image simulator to the FPGA side of the image simulator according to a second preset rule; the FPGA side receives the data preprocessed by the CPU side, parses it, and dynamically processes the original image. When the image file length is not an integer multiple of the camera data frame, the present invention can pad the tail of the image file length, and during the data transmission process, the image can be changed in brightness, contrast, visual enhancement, etc.

Description

Technical Field

[0001] The present invention relates to the field of image data processing, and in particular to a method and device for dynamically processing high-speed data in an image simulator. Background Art

[0002] As the resolution of high-resolution cameras on space satellites increases, the rate requirements for image transmission increase dramatically. Therefore, the ground test system also needs to keep up with the needs of the times in terms of various performances. When testing on the ground, the data transmission subsystem and the storage subsystem need to be able to generate large amounts of data and have flexible configurations like real high-resolution cameras. In order to take into account the above two requirements, today's image simulation source equipment will adopt a heterogeneous hardware solution such as FPGA plus CPU, such as the Chinese patent CN2020103376500 "A test data simulation method and device with flexible customizable frame format". The advantage of this invention is that it fully utilizes the advantages and disadvantages of the two processing methods to complement each other. The advantage of FPGA is that it has strong timing and high throughput to realize high-speed interfaces such as 10Gb / s or more. At the same time, the CPU is used as the configuration surface of the image data, and the configuration of the image frame format is flexible and more universal. The connection between the FPGA and the CPU is realized through DMA. After the image data is prepared on the CPU side, it can be sent to the FPGA through DMA. The transmission speed can reach 40Gb / s, and finally the FPGA forms a fiber optic transmission protocol for transmission.

[0003] However, this solution still lacks the need to dynamically change the data content and implement data adjustment after the data starts to be sent, such as the brightness, contrast, dynamic enhancement, etc. of the transmitted image. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a method and device for dynamically processing high-speed data in an image simulator that overcomes the above problems or at least partially solves the above problems.

[0005] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0006] A method for dynamically processing high-speed data in an image simulator, comprising:

[0007] S100. The camera data on the CPU side of the image simulator is preprocessed in memory according to the first preset rule;

[0008] S200. The camera data pre-processed on the CPU side of the image simulator is sent to the FPGA side of the image simulator according to the second preset rule;

[0009] S300.FPGA side receives the data pre-processed by the CPU side, parses it, and dynamically processes the original image.

[0010] Furthermore, in S100 , each frame of camera data includes DMA header data, auxiliary data, and image data.

[0011] Furthermore, the numbers of DMA header data, auxiliary data, and image data are the same.

[0012] Furthermore, the method for memory preprocessing of DMA header data, auxiliary data and image data according to the first preset rule is: the DMA header data and the auxiliary data are connected in a front-to-back order and stored together in a memory address, and the image data is stored separately in another memory address.

[0013] Further, after the DMA header data is connected to the auxiliary data, the DMA header data and the auxiliary data connected to the next frame are arranged in sequence, and the image data and the next frame of image data are arranged in sequence.

[0014] Further, in S200, the second preset rule is: the CPU side sends to the corresponding port on the FPGA side via 2-way DMA, the DMA header data and auxiliary data are sent to the auxiliary data port via the auxiliary data channel, and the image data is sent to the data port via the image data channel.

[0015] Furthermore, in S100, when the length of the file stored in the memory is not an integral multiple of the camera data frame, the tail of the file length needs to be cyclically padded.

[0016] Furthermore, the method for looping and padding the tail of the file length is as follows:

[0017] Get the length S of the graphic file and the length of the image part in the camera data frame, record it as M;

[0018] The remainder of dividing the length S of the graphic file by the length M of the image portion in the camera data frame is recorded as N, that is, N = S% M;

[0019] Assuming that the sending cycle is K+1, then K+1 = the least common multiple of (MN) and M;

[0020] The length of the image file to be cyclically padded is denoted as S', and the padded length is calculated by S'=K(MN).

[0021] Furthermore, when the camera data on the CPU side is sent to the FPGA side, the parameters for adjusting the image characteristics will be written into the DMA header. When the image frame enters the FPGA, the FPGA parses the change information in the DMA header and then processes the image data accordingly.

[0022] Furthermore, the parameters for adjusting image characteristics at least include: image brightness adjustment parameters, image contrast adjustment parameters and image visual enhancement parameters.

[0023] The present invention also discloses a dynamic processing device for high-speed data in an image simulator, comprising: a memory preprocessing module, a data transmission module, and a data analysis module; wherein:

[0024] A memory preprocessing module is used to perform memory preprocessing on the camera data on the CPU side of the image simulator according to a first preset rule, wherein the method for performing memory preprocessing on the DMA header data, the auxiliary data and the image data according to the first preset rule is as follows: the DMA header data and the auxiliary data are connected in a front-to-back order and stored together in a memory address, and the image data is stored separately in another memory address; after the DMA header data and the auxiliary data are connected, the DMA header data and the auxiliary data connected to the next frame are arranged in sequence, and the image data and the next frame of image data are arranged in sequence; and it also includes cyclic padding of the tail of the file length when the length of the file stored in the memory is not an integer multiple of the camera data frame.

[0025] The data transmission module is used to send the camera data preprocessed by the CPU side in the image simulator to the FPGA side in the image simulator according to the second preset rule; specifically, the second preset rule is: the CPU side sends it to the corresponding port on the FPGA side through 2-way DMA, the DMA header data and auxiliary data are sent to the auxiliary data port through the auxiliary data channel, and the image data is sent to the data port through the image data channel.

[0026] The data analysis module is used to receive the data pre-processed by the CPU side, analyze it, adjust the image characteristics, and dynamically process the original image. The parameters for adjusting the image characteristics include at least: image brightness adjustment parameters, image contrast adjustment parameters and image visual enhancement parameters.

[0027] The beneficial effects of the above technical solution provided by the embodiment of the present invention include at least:

[0028] The present invention discloses a method and device for dynamically processing high-speed data in an image simulator, comprising: preprocessing the camera data on the CPU side of the image simulator in memory according to a first preset rule; sending the camera data preprocessed by the CPU side of the image simulator to the FPGA side of the image simulator according to a second preset rule; the FPGA side receives the data preprocessed by the CPU side, parses it, and dynamically processes the original image. The present invention solves the problem in the prior art that, in the process of sending camera data on the CPU side and the FPGA side, after the data starts to be sent, the data content is dynamically changed to achieve data adjustment.

[0029] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0031] Figure 1 This is a flow chart of a method for dynamically processing high-speed data in an image simulator in Embodiment 1 of the present invention;

[0032] Figure 2 The arrangement of DMA header data, auxiliary data and image data in the memory in Embodiment 1 of the present invention;

[0033] Figure 3 This is a schematic diagram of circularly padding the tail of an image file length in Embodiment 1 of the present invention;

[0034] Figure 4 This is a schematic diagram of the FPGA side receiving the data pre-processed by the CPU side in Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a method and device for dynamically processing high-speed data in an image simulator.

[0037] Example 1

[0038] This embodiment discloses a method for dynamically processing high-speed data in an image simulator, such as Figure 1 ,include:

[0039] S100. Perform memory preprocessing on the camera data on the CPU side in the image simulator according to a first preset rule.

[0040] Specifically, in this embodiment, each frame of camera data includes DMA header data, auxiliary data, and image data. Figure 2, the method for performing memory preprocessing on the DMA header data, the auxiliary data and the image data according to the first preset rule is: the DMA header data and the auxiliary data are connected in a front-to-back order and stored together in a memory address, and the image data is stored separately in another memory address. After the DMA header data and the auxiliary data are connected, the DMA header data and the auxiliary data connected to the next frame are arranged in sequence, and the image data and the next frame of image data are arranged in sequence.

[0041] In this embodiment, the auxiliary data and image data are stored independently in the memory, and a DMA frame is composed of multiple continuous auxiliary headers or multiple continuous image data frames. When sending, the auxiliary data header DMA and the image data DMA are sent alternately, and the number of user frames included is the same. The FPGA agrees that after reading an auxiliary data header from the auxiliary data pipeline, it takes the image data of a user frame from the image data channel, splices it, and sends it out.

[0042] In some embodiments, Figure 3 When the length of the file stored in the memory is not an integer multiple of the camera data frame, the tail of the file length needs to be cyclically padded. Specifically, the method of cyclically padded the tail of the file length is:

[0043] Get the length S of the graphic file and the length of the image part in the camera data frame, record it as M;

[0044] The remainder of dividing the length S of the graphic file by the length M of the image portion in the camera data frame is recorded as N, that is, N = S% M;

[0045] Assuming that the sending cycle is K+1, then K+1 = the least common multiple of (MN) and M / (MN);

[0046] The length of the image file to be cyclically padded is denoted as S', and the padded length is calculated by S'=K(MN).

[0047] For example, when the file length S = 4096 bytes and the length of the image part in the camera data frame M = 1012 bytes, through N = S%M, we get the least common multiple of N = 48, MN = 964 and M = 1012 is 243982, then K+1 = 243982 / 964 = 252; K = 252. Then the length of the image file after cyclic padding S' = K (MN) = 252x964 = 242928 bytes.

[0048] Therefore, when sending the 4th M, 964 bytes of data in S' will be sent more. When sending the 5th M, it will start from the beginning of S with an offset of 964 bytes, so that it can be connected with the content of the 4th M. Similarly, after sending the 8th M, 964*2 bytes of data in S' will be sent more, and the 9th M will start from the 964*2 bytes of S.

[0049] Finally, when K+1=253, the offset sent by the first M returns to S's 0 offset point.

[0050] Finally, the image data area in the memory must be filled with (S+S')×(K+1) image data to satisfy a circular sending buffer.

[0051] S200. The camera data pre-processed by the CPU side in the image simulator is sent to the FPGA side in the image simulator according to the second preset rule; specifically, in this embodiment, Figure 4 ,The second preset rule is: the CPU side sends the data to the corresponding port on the FPGA side through 2-way DMA, the DMA ,header data and auxiliary data are sent to the auxiliary data port through the ,auxiliary data channel, and the image data is sent to the data port through the ,image data channel.

[0052] S300. The FPGA side receives the data pre-processed by the CPU side, parses it, and dynamically processes the original image. Specifically, when the data is sent, the channel adjusts the image characteristics by dynamically writing the changes to be sent into the DMA header through the CPU. When the image frame enters the FPGA, the FPGA parses the change information in the DMA header, and then performs corresponding processing on the image data. For example, the original image is changed in brightness, contrast, visual enhancement, etc. In some preferred embodiments, the data structure of the camera data is as shown in Table 1.

[0053] Table 1

[0054]

[0055] The specific parsing method of FPGA parsing the change information in the DMA header and then performing corresponding processing on the image data is shown in Table 2.

[0056] Table 2

[0057]

[0058] The present embodiment discloses a method for dynamically processing high-speed data in an image simulator, comprising: preprocessing the camera data on the CPU side of the image simulator in memory according to a first preset rule; sending the camera data preprocessed on the CPU side of the image simulator to the FPGA side of the image simulator according to a second preset rule; the FPGA side receives the data preprocessed on the CPU side, parses it, and dynamically processes the original image. The present invention solves the problem in the prior art that, during the camera data transmission process on the CPU side and the FPGA side, after the data starts to be transmitted, the data content is dynamically changed to achieve data adjustment.

[0059] Example 2

[0060] This embodiment discloses a dynamic processing device for high-speed data in an image simulator, including: a memory preprocessing module, a data transmission module, and a data analysis module; wherein:

[0061] A memory preprocessing module is used to perform memory preprocessing on the camera data on the CPU side of the image simulator according to a first preset rule, wherein the method for performing memory preprocessing on the DMA header data, the auxiliary data and the image data according to the first preset rule is as follows: the DMA header data and the auxiliary data are connected in a front-to-back order and stored together in a memory address, and the image data is stored separately in another memory address; after the DMA header data and the auxiliary data are connected, the DMA header data and the auxiliary data connected to the next frame are arranged in sequence, and the image data and the next frame of image data are arranged in sequence; and it also includes cyclic padding of the tail of the file length when the length of the file stored in the memory is not an integer multiple of the camera data frame.

[0062] Specifically, the method for looping and padding the tail of the file length is:

[0063] Get the length S of the graphic file and the length of the image part in the camera data frame, record it as M;

[0064] The remainder of dividing the length S of the graphic file by the length M of the image portion in the camera data frame is recorded as N, that is, N = S% M;

[0065] Assuming that the sending cycle is K+1, then K+1 = the least common multiple of (MN) and M / (MN);

[0066] The length of the image file to be cyclically padded is recorded as S', and the padded length is calculated by S'=K(MN). The specific example of padded has been described in detail in Embodiment 1, and will not be described in detail in this embodiment.

[0067] The data transmission module is used to send the camera data preprocessed by the CPU side in the image simulator to the FPGA side in the image simulator according to the second preset rule; specifically, the second preset rule is: the CPU side sends it to the corresponding port on the FPGA side through 2-way DMA, the DMA header data and auxiliary data are sent to the auxiliary data port through the auxiliary data channel, and the image data is sent to the data port through the image data channel.

[0068] The specific transmission rules of the data transmission module have been described in detail in Example 1, and will not be repeated in this embodiment.

[0069] The data analysis module is used to receive the data pre-processed by the CPU side, analyze it, adjust the image characteristics, and dynamically process the original image. The parameters for adjusting the image characteristics at least include: image brightness adjustment parameters, image contrast adjustment parameters, and image visual enhancement parameters. The data structure and analysis method analyzed by the data analysis module have been described in detail in Tables 1 and 2 of Example 1.

[0070] The present embodiment discloses a device for dynamically processing high-speed data in an image simulator, which performs memory preprocessing on the camera data on the CPU side of the image simulator according to a first preset rule through a memory preprocessing module; sends the camera data preprocessed on the CPU side of the image simulator to the FPGA side of the image simulator according to a second preset rule through a data transmission module; and receives the data preprocessed on the CPU side on the FPGA side through a data parsing module, and performs parsing to dynamically process the original image. The present invention solves the problem in the prior art that, during the camera data transmission process on the CPU side and the FPGA side, after the data starts to be sent, the data content needs to be dynamically changed to achieve data adjustment.

[0071] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0072] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the appended claims, the invention is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0073] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments herein can all be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above around their functions. Whether such functions are implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. A skilled person can implement the described functions in an alternative manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of the present disclosure.

[0074] The steps of the method or algorithm described in conjunction with the embodiments herein may be directly embodied as hardware, a software module executed by a processor, or a combination thereof. The software module may be located in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a mobile disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in an ASIC. The ASIC may be located in a user terminal. Of course, the processor and the storage medium may also be present in a user terminal as discrete components.

[0075] For software implementation, the techniques described in this application can be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described in this application. These software codes can be stored in a memory unit and executed by a processor. The memory unit can be implemented within the processor or outside the processor. In the latter case, it is coupled to the processor in a communication manner via various means, which are well known in the art.

[0076] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

Claims

1. A method for dynamic processing of high-speed data in an image simulator, characterized in that: include: S100. The camera data on the CPU side of the image simulator is preprocessed in memory according to the first preset rule; in S100, each frame of the camera data includes DMA header data, auxiliary data and image data, and the number of DMA header data, auxiliary data and image data is the same; the method of preprocessing the DMA header data, auxiliary data and image data in memory according to the first preset rule is: the DMA header data and the auxiliary data are connected in a front-to-back order and stored together in a memory address, and the image data is stored separately in another memory address; S200. The camera data pre-processed by the CPU side in the image simulator is sent to the FPGA side in the image simulator according to the second preset rule; in S200, the second preset rule is: the CPU side sends the data to the corresponding port on the FPGA side through 2-way DMA, the DMA header data and auxiliary data are sent to the auxiliary data port through the auxiliary data channel, and the image data is sent to the data port through the image data channel; S300. The FPGA side receives the pre-processed data from the CPU side, parses it, and dynamically processes the original image. When the camera data from the CPU side is sent to the FPGA side, the parameters for adjusting the image characteristics are written into the DMA header. When the image frame enters the FPGA, the FPGA parses the change information in the DMA header and then processes the image data accordingly.

2. A method for dynamically processing high-speed data in an image simulator as claimed in claim 1, characterized in that: After the DMA header data is connected to the auxiliary data, the DMA header data and the auxiliary data connected to the next frame are arranged in sequence, and the image data and the next frame image data are arranged in sequence.

3. The method for dynamically processing high-speed data in an image simulator according to claim 1, characterized in that: In S200, the second preset rule is: the CPU side sends to the corresponding port on the FPGA side via 2-way DMA, the DMA header data and auxiliary data are sent to the auxiliary data port via the auxiliary data channel, and the image data is sent to the data port via the image data channel.

4. The method for dynamically processing high-speed data in an image simulator according to claim 1, characterized in that: In S100, when the length of the file stored in the memory is not an integral multiple of the camera data frame, the tail of the file length needs to be cyclically padded.

5. The method for dynamically processing high-speed data in an image simulator according to claim 1, characterized in that: The method to loop and fill the tail of the file length is: Get the length S of the graphic file and the length of the image part in the camera data frame, record it as M; The remainder of dividing the length S of the graphic file by the length M of the image portion in the camera data frame is recorded as N, that is, N = S% M; Assuming that the sending cycle is K+1, then K+1 = the least common multiple of (MN) and M; The length of the image file to be cyclically padded is denoted as S', and the padded length is calculated by S'=K(MN).

6. A method for dynamically processing high-speed data in an image simulator as claimed in claim 5, characterized in that: The parameters for adjusting image characteristics at least include: image brightness adjustment parameters, image contrast adjustment parameters and image visual enhancement parameters.

7. A device for dynamically processing high-speed data in an image simulator, characterized in that: include: Memory preprocessing module, data transmission module, data analysis module; among them: A memory preprocessing module is used to perform memory preprocessing on the camera data on the CPU side of the image simulator according to a first preset rule, wherein the method for performing memory preprocessing on the DMA header data, the auxiliary data and the image data according to the first preset rule is as follows: the DMA header data and the auxiliary data are connected in a front-to-back order and stored together in a memory address, and the image data is stored separately in another memory address; after the DMA header data and the auxiliary data are connected, the DMA header data and the auxiliary data connected to the next frame are arranged in sequence, and the image data and the next frame of image data are arranged in sequence; and also includes cyclic padding of the tail of the file length when the length of the file stored in the memory is not an integer multiple of the camera data frame; The data transmission module is used to send the camera data preprocessed by the CPU side in the image simulator to the FPGA side in the image simulator according to the second preset rule; specifically, the second preset rule is: the CPU side sends the data to the corresponding port on the FPGA side through 2-way DMA, the DMA header data and auxiliary data are sent to the auxiliary data port through the auxiliary data channel, and the image data is sent to the data port through the image data channel; The data analysis module is used to receive the data pre-processed by the CPU side, analyze it, adjust the image characteristics, and dynamically process the original image. The parameters for adjusting the image characteristics at least include: image brightness adjustment parameters, image contrast adjustment parameters and image visual enhancement parameters; specifically, when the data is sent, the channel adjusts the image characteristics by dynamically writing the changes to be sent into the DMA header through the CPU. When the image frame enters the FPGA, the FPGA analyzes the change information in the DMA header and then performs corresponding processing on the image data.

Images