Fault-tolerant processing method, device, and server

Abstract

The present application provides a fault-tolerant processing method, comprising: a server sending a read data message to an external controller, the read data message being used to request the external controller to read data from an indicated storage location, the message format of the read data message conforming to the message format specified by the memory semantic network protocol; the server receiving indication information sent by the external controller, the indication information being used to indicate the external controller's response status to the read data message; the server determining the external controller's response status to the read data message based on the indication information, and performing fault-tolerant processing if the response status is abnormal. This method can effectively reduce the probability of a data access system failing and restarting.

Description

Technical Field

[0001] The present application relates to the field of information technology, and more particularly, to a method, device, and server for fault-tolerant processing. Background Art

[0002] New storage class memory (SCM) has reached commercial standards. For example, 3DXPoint has begun commercialization. The access latency of this type of memory can reach 200 to 500 nanoseconds (ns).

[0003] Traditional infiniband (IB) networks, remote direct memory access (RDMA) networks, and RDMA over converged Ethernet networks typically have access latencies of 10 microseconds (µs). This latency is not compatible with the access latency of new storage-class memories. This is why memory-semantic network protocols have emerged.

[0004] In a memory semantic network, since communication between different servers is cross-network communication, different servers must pass through multiple physical media (for example, switches or servers used to forward communication messages), and even need to go through multiple levels of switches for exchange, which makes the probability of network congestion or anomalies higher during cross-network communication.

[0005] In existing data processing, the processor's read data access mechanism assumes that read data access must succeed. However, in the event of a storage medium anomaly, the external controller returns invalid data in response to the read data message. In the event of a read data message timeout, the internal controller generates invalid data in response to the read data message. In these anomalies, if the processor needs to consume this invalid data, for example, by performing operations on it, it triggers a data access system failure and restart. Summary of the Invention

[0006] The present application provides a fault-tolerant processing method, which can effectively reduce the probability of a data access system failing and restarting.

[0007] In a first aspect, a method for fault-tolerant processing is provided, which is applied to a server, wherein the server communicates with an external controller via a memory semantic network protocol, and the external controller is located outside the server, comprising: the server sending a read data message to the external controller, wherein the read data message is used to request the external controller to read data from an indicated storage location, and the message format of the read data message complies with the message format specified by the memory semantic network protocol; the server receives indication information sent by the external controller, wherein the indication information is used to indicate the response status of the external controller to the read data message; the server determines the response status of the external controller to the read data message based on the indication information, and performs fault-tolerant processing when the response status is an abnormal response.

[0008] When the server is accessing read data, it determines the response status of the server requested to read the data to the read data message before the processor core performs operations on the invalid data returned by the external controller, and performs fault tolerance processing when the response status is an abnormal response, thereby avoiding the data access system from failing to restart when performing operations on invalid data without detecting the abnormal response.

[0009] In one possible implementation, the server includes a processor, the processor includes an internal controller and a processor core, and the processor core and the internal controller communicate through an internal bus network protocol; the server sends a read data message to the external controller, including: the internal controller converts the format of the message from the processor to generate the read data message; and the internal controller sends the read data message to the external controller.

[0010] In one possible implementation, the server determines the response status of the external controller to the read data message, including: the internal controller determines the read data result of the external controller based on the indication information, and the read data result is used to indicate whether the external controller successfully reads the data; the internal controller generates a notification message based on the read data result, and the notification message includes a response status identifier, and the response status identifier indicates that the external controller failed to read the target data from the storage space indicated by the read data message.

[0011] In the event of a response anomaly in data access (for example, failure to read target data), different faults are distinguished by generating a notification message carrying a response status identifier, and the response status identifier is stored in the register of the processor core. At the same time, an instruction is added to the internal memory of the server so that the processor core executes the instruction to read the response status identifier from the register, ensuring that the processor core can determine the response status of the external controller to the read data message based on the response status identifier before performing operations on invalid data. When the response status is abnormal, fault tolerance processing can be performed for the response anomaly to avoid the data access system from failing to restart when performing operations on the invalid data without detecting the response anomaly.

[0012] In one possible implementation, the method further includes: the internal controller sends the notification message to the processor; the processor core obtains the response status identifier from the notification message; the processor saves the response status identifier to the register of the processor; the processor core obtains the response status identifier from the register; the server determines the response status of the external controller to the read data message based on the indication information, including: the processor core determines the response status of the external controller to the read data message based on the response status identifier.

[0013] Optionally, there is only one register in the processor core for storing the response status identifier. The register can be any one of the original registers of the processor, and only some fields in the register can be used to store the response status identifier. Alternatively, the register is a newly added register in the processor, and the register can be dedicated to storing the identifier.

[0014] The register may be used to store multiple response status identifiers carried in multiple notification messages returned by the internal controller to multiple read data messages (for example, the multiple read data messages include the read data message) of the processor core.

[0015] At this time, the multiple identifiers may be stored in an overlay storage manner, and the identifier obtained from the register by the processor core after receiving the notification message is the identifier carried by the notification message;

[0016] The multiple identifiers may also be stored in a non-overlapping manner. For example, fields may be allocated in the register for the multiple identifiers corresponding to the multiple read data messages sent by the processor core. The allocated fields are used to store the multiple identifiers and create an association relationship between the multiple read data messages and the fields allocated to the identifiers corresponding to the multiple read data messages. When the processor core obtains the identifier carried by the notification message from the register, it can obtain the response status identifier carried by the notification message from the corresponding field in the register based on the association relationship.

[0017] Optionally, the processor core includes at least two registers for storing the response status identifier carried in the notification message returned by the internal controller. The at least two registers may belong to the original registers of the processor, and only some fields in the at least two registers may be used to store the identifier; or, the at least two registers are newly added registers in the processor core, and the at least two registers may be dedicated to storing the identifier.

[0018] The register may be used to store multiple response status identifiers carried in multiple notification messages returned by the internal controller to multiple read data messages (for example, the multiple read data messages include the read data message) of the processor.

[0019] At this time, the multiple identifiers are stored in different registers. For example, there can be a one-to-one correspondence between the multiple identifiers and the multiple registers, that is, one register is only used to store one identifier. At this time, an association relationship can be created between the multiple read data messages and the multiple registers.

[0020] When obtaining the identifier carried in the notification message, the processor core may determine the register corresponding to the notification message according to the association relationship, and obtain the response status identifier from the register.

[0021] For example, there is a many-to-one relationship between the multiple identifiers and the multiple registers. That is, one register stores at least two identifiers. In this case, an association relationship can be established between the multiple read data messages, the multiple registers, and the fields in the registers for storing identifiers.

[0022] When the processor core obtains a notification message, it can determine the register corresponding to the notification message based on the association relationship, and further determine the field in the register used to store the identifier carried by the notification message, thereby obtaining the identifier carried by the notification message in the corresponding storage space in the register.

[0023] By having the processor core store the response status identifier obtained from the notification message into a register and adding an instruction in the internal memory of the server, the processor core executes the instruction to obtain the response status identifier from the register, so that the processor core can determine the response status of the external controller to the read data message based on the response status identifier before performing operations on the returned invalid data, and when the response status is a response exception, fault tolerance processing is performed for the response exception, thereby avoiding the data access system from failing to restart when performing operations on invalid data without detecting the response exception.

[0024] In a possible implementation, the fault-tolerant processing includes degraded reading or replica reading.

[0025] When the processor core determines that the external controller fails to read the target data from the storage space indicated by the read data message, the processor can implement read data access through degraded read or copy read.

[0026] In a second aspect, a method for fault-tolerant processing is provided, which is applied to a server, wherein the server communicates with an external controller via a memory semantic network protocol, and the external controller is located outside the server, comprising: the server sending a read data message to the external controller, wherein the read data message includes destination address information of the data to be read, and the destination address information is used to indicate the storage location of the data to be read, and the message format of the read data message complies with the message format specified by the memory semantic network protocol; the server determines that the response status of the external controller to the read data message is a response timeout, and performs fault-tolerant processing when the response status is a response timeout.

[0027] When the server is accessing read data, before the processor core performs operations on invalid data returned by the external controller, it determines the response status of the server requested to read data to the read data message, and performs fault tolerance processing when the response status is a response timeout, thereby avoiding the failure and restart of the data access system when operations are performed on invalid data without detecting a response timeout.

[0028] In one possible implementation, the server includes a processor, the processor includes an internal controller and a processor core, and the processor core and the internal controller communicate through an internal bus network protocol; the server sends a read data message to the external controller, including: the internal controller converts the format of the message from the processor to generate the read data message; and the internal controller sends the read data message to the external controller.

[0029] In one possible implementation, the server determines that the response status of the external controller to the read data message is a response timeout, including: when the duration recorded by the timer in the internal controller is greater than or equal to a first threshold, if the internal controller does not receive the indication information returned by the external controller, the internal controller determines that the response status of the external controller to the read data message is a response timeout, and generates a notification message, wherein the notification message includes a response status identifier, and the response status identifier is used to indicate that the response status of the external controller to the read data message is a response timeout.

[0030] In the event of a response timeout in data access, a notification message carrying a response status identifier is generated to indicate that the external controller's response status to the read data message is a response timeout, and the response status identifier is stored in the register of the processor core. At the same time, an instruction is added to the server's internal memory so that the processor executes the instruction to read the response status identifier from the register, ensuring that the processor core can determine the external controller's response status to the read data message based on the response status identifier before performing operations on invalid data. When the response status is a timeout, fault tolerance processing can be performed for the response anomaly to avoid the data access system failing to restart when performing operations on the invalid data without detecting the response anomaly.

[0031] In one possible implementation, the method further includes: the internal controller sends the notification message to the processor core; the processor core obtains the response status identifier from the notification message; saves the response status identifier to the register of the processor; the processor core obtains the response status identifier from the register; and the processor core determines, based on the response status identifier, that the response status of the external controller to the read data message is a response timeout.

[0032] In a possible implementation, when the response status identifier indicates that the external controller times out in reading target data from the storage space indicated by the read data message, the fault-tolerant processing includes retrying, degraded reading, or replica reading.

[0033] When the processor core determines that the external controller has timed out reading the target data from the storage space indicated by the read data message, the processor core may implement read data access by retrying, degrading read, or replica read.

[0034] In a third aspect, a fault-tolerant processing apparatus is provided, wherein the apparatus is configured to execute the method of the first aspect or any possible implementation of the first aspect. Specifically, the apparatus may include a module configured to execute the method of the first aspect or any possible implementation of the second aspect.

[0035] In a fourth aspect, a server is provided, wherein the server communicates with an external controller via a memory semantic network protocol, the external controller is located outside the server, the server includes a processor, the processor includes an internal controller and a processor core, the internal controller is used to execute the operating steps of the method executed by the internal controller in the first aspect or any possible implementation of the first aspect, and the processor core is used to execute the operating steps of the method executed by the processor core in the first aspect or any possible implementation of the first aspect.

[0036] In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the method in any possible implementation of the first aspect or the second aspect.

[0037] In a sixth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method in any possible implementation of the first aspect or the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a structural diagram of a data access system provided by this application.

[0039] Figure 2 This is a flowchart of the fault-tolerant processing method provided by this application.

[0040] Figure 3 It is a schematic block diagram of the fault-tolerant processing device provided in this application.

[0041] Figure 4 It is a structural diagram of the server provided in this application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0043] Figure 1 A data access system is provided in an embodiment of the present invention. The data access system includes a plurality of servers (e.g., server 0 to server N, where N≥2). Any two servers communicate with each other via a memory-semantic network protocol. The memory-semantic network may be a Gen-Z (generation-z) network.

[0044] In addition, the data access system also includes a resource pool consisting of several storage units (e.g., storage unit 0 to storage unit M, where M ≥ 2). Any server from server 0 to server N can access data from any storage unit in the resource pool via the memory semantic network protocol. The storage unit can be a new type of storage class memory (SCM), such as 3D XPoint.

[0045] The memory semantic network consists of multiple switches cascaded together ( Figure 1 (not shown), different servers communicate with each other through different ports on the switch, and servers communicate with storage units in the resource pool through different ports on the switch.

[0046] Figure 1 Each server may include a processor and an internal memory, wherein the processor may be a general-purpose central processing unit (CPU) or a system on chip (SoC).

[0047] In the embodiments of the present invention, the processor is described as a SoC. The SoC can support running an instruction set based on the X86 architecture or an instruction set based on the Advanced RISC Machine (ARM) architecture. For example, the internal memory can be a dual inline memory module (DIMM).

[0048] The SoC integrates multiple processor cores (for example, processor core 0 to processor core L, L ≥ 2) and an internal controller. Each processor core is deployed with one or more registers ( Figure 1 Only one register is shown in the figure), the internal controller is used to enable the multi-core processor to access data to other servers or local resource pools. The internal controller can also be used to enable the multi-core processor to access data to the internal memory, wherein the multi-core processor in the server and the internal controller communicate through an internal bus network protocol.

[0049] Optionally, the internal controller may include two controllers, for example, a first internal controller and a second internal controller, wherein the first internal controller is used to enable the multi-core processor to access data from other servers or a local resource pool, and the second internal controller is used to enable the multi-core processor to access data from an internal memory, and the multi-core processor in the server communicates with the first and second internal controllers via an internal bus network protocol. Exemplarily, the first internal controller may be a memory controller built into a Gen-Z controller, and the second internal controller may be an internal memory controller (IMC).

[0050] Any storage unit in the resource pool includes a storage controller and storage media. The storage controller is used to access data from the storage media in the storage unit based on data access requests received from other servers. For example, a storage unit in the resource pool may be a storage class memory (SCM), which may be 3D XPoint memory. The storage controller performs both protocol conversion and media access functions.

[0051] In order to save computing resources of the processor in the server, a field programmable gate array (FPGA) or other hardware can also be used to perform all operations of the processor in the embodiment of the present invention. For example, at least one processor core in the above-mentioned multi-core processor can be replaced with an FPGA or other hardware.

[0052] The same data access process includes multiple instructions. Processor cores 0 to L are used to execute multiple instructions stored in internal memory in parallel. These multiple instructions can correspond to multiple applications. In traditional technical solutions, the processor core read data access mechanism assumes that read data access must be successful, and no exception check is performed on the data returned by the external controller. If the returned data is invalid data, when the processor core consumes the invalid data, for example, when performing an operation on the invalid data (the operation is to read the data in the storage unit), it will trigger a data access system failure restart.

[0053] An embodiment of the present invention proposes a fault-tolerant processing method. In this method, when a response exception occurs in data access (for example, a response timeout or a failure to read target data), an external controller sends an indication message and invalid data generated according to a preset rule to an internal controller of a server. The internal controller generates a response status identifier based on the indication message sent by the external controller, uses the response status identifier to distinguish different faults, and stores the response status identifier in a register of a processor core, and stores the invalid data in the internal memory of the server. Wherein, the target data refers to the data in the storage unit to be accessed by the read data message; the invalid data includes the data generated by the external controller according to the preset rule when the storage unit is abnormal, and the data generated by the internal controller according to the preset rule when the data access timeout occurs. The preset rule can be to set all the fields storing the target data by default in the message corresponding to the return result to 0 or 1. At the same time, an instruction is added to the internal memory of the server so that the processor core executes the instruction to read the response status identifier from the register, ensuring that the processor core can determine the response status of the external controller to the read data message based on the response status identifier before performing an operation on the invalid data. Compared with the traditional technical solution in which the processor core assumes that the read data access is successful and does not check whether the returned result is invalid data, the embodiment of the present invention can pre-identify the response anomaly by reading the response status identifier before the processor core performs operations on the invalid data, and perform fault-tolerant processing to avoid the data access system from failing to restart when performing operations on the invalid data without detecting the response anomaly.

[0054] It's worth noting that in conventional technical solutions, regardless of whether a read access is successful, the processor core receives a read result. If the read access is successful, the result is the target data. If the storage medium containing the target data fails, the result is invalid data generated by the external controller according to preset rules. If the read access times out, the result is invalid data generated by the internal controller according to preset generation rules. This result is stored in the internal memory of the server that sent the read access.

[0055] Next, the fault tolerance processing method of the embodiment of the present invention is introduced by taking an example in which a processor core in a server executes instructions of an application program to access data from other servers or a resource pool, and a server includes an internal controller.

[0056] It should be noted that for Figure 1 In the system architecture shown, if server 0 is the server requesting to read data and server N is the server receiving the request, then the internal controller in server N is the external controller relative to server 0. In the following description of this embodiment, server 0 is used as an example to describe the server requesting to read data. In this case, the external controller includes the storage controller of any storage unit in the resource pool and the internal controller in server N.

[0057] like Figure 1 In the described data access system, a processor core in any server is used to execute instructions stored in an internal memory to implement read data access, and when a read data access failure occurs, a fault-tolerant processing method provided by an embodiment of the present invention is used to perform fault-tolerant processing.

[0058] Figure 2 The present invention provides a flowchart of a method 200 for fault tolerance processing according to an embodiment of the present invention. The method 200 includes at least the following steps.

[0059] 201. The server sends a read data message to the external controller, where the read data message is used to request the external controller to read data from an indicated storage location. The message format of the read data message complies with the message format specified by the memory semantic network protocol. The external controller is located outside the server.

[0060] Exemplarily, the server includes a processor, the processor includes an internal controller and a processor core, the processor core and the internal controller communicate through an internal bus network protocol, and the server sends a read data message to the external controller, including: the internal controller converts the format of the message from the processor core to generate the read data message; and the internal controller sends the read data message to the external controller.

[0061] Specifically, the processor core in the server executes a read data request from the client and generates a read data message based on the read data request. The read data request is sent to a remote server or storage unit in the form of a message. The data request is used to request to read data (for example, target data) from other servers or from a storage unit in a resource pool.

[0062] For example, the processor core sends a read data message to the internal controller, and the read data message is used to request the internal controller in the peer server (for example, the server requested to read data) or the storage controller in the storage unit in the peer resource pool (for example, the storage unit requested to read data) to read the target data from the storage space indicated by the destination address information of the data to be read carried by the read data message.

[0063] The internal controller converts the format of the received read data message, for example, converts the read data message from the internal bus network protocol format to the memory semantic network protocol format, and sends the converted read data message to the switch through the port on the switch responsible for communicating with the server where the external controller is located. The switch parses the converted read data message, determines the port on the switch responsible for communicating with the storage unit requested to read the data based on the destination address information of the data to be read carried in the converted read data message, and sends the converted read data message to the external controller through the port.

[0064] The internal bus network protocol may be any one of a quick path interconnect (QPI) network protocol, a hyper transport (HT) network protocol, and a HiSilicon cache coherent connect specification (HCCS) network protocol.

[0065] Taking the conversion of the message from the processor core from the message format specified by the HT network protocol to the message format specified by the memory semantic network protocol as an example, the process of format conversion of the message from the processor core is briefly introduced.

[0066] Specifically, the message from the processor core conforms to the message format specified by the HT network protocol. The destination address carried in the message from the processor core is carried in byte4_bit[0] to byte4_bit[7], byte5_bit[0] to byte5_bit[7], byte6_bit[0] to byte6_bit[7], and byte7_bit[0] to byte7_bit[7], where byte represents a byte and bit represents a bit included in a byte. byte0_bit[0] to byte0_bit[5] carry an operation code, which indicates the specific type of read operation requested by the message from the processor core.

[0067] After the format conversion of the message from the processor core, the generated read data message conforms to the message format specified by the memory semantic network protocol. The destination address carried in the converted read data message is carried in byte0_bit[4]~byte0_bit[7], byte1_bit[0]~byte0_bit[7], byte2_bit[0]~byte2_bit[7], byte3_bit[0]~byte3_bit[7], byte8_bit[0]~byte8_bit[7] and byte9_bit[0]~byte9_bit[3], and the operation code is carried in byte4_bit[0]~byte4_bit[3].

[0068] 202. The server receives an indication message sent by the external controller, the indication message being used to indicate the external controller's response status to the read data message. 203. The server determines the external controller's response status to the read data message based on the indication message, and performs fault tolerance processing if the response status is abnormal.

[0069] Exemplarily, the server determines the response status of the external controller to the read data message, including: the internal controller determines the read data result of the external controller based on the indication information, and generates a notification message, which includes a response status identifier, and the response status identifier is used to indicate the response status of the external controller to the read data message.

[0070] Specifically, the internal controller determines whether the external controller successfully reads the target data from the storage space indicated by the read data message, and generates a notification message based on the read data result of the external controller for the storage space indicated by the converted read data message. The notification message includes a response status identifier, which is used to indicate the response status of the external controller to the read data message.

[0071] The external controller's response status to the read data message may include any one of response timeout, data read failure, and successful target data read. The following describes in detail several methods for the internal controller to determine the above three response states and how to generate notification messages for each response state.

[0072] Among them, the internal controller can determine the two response states of failure to read data and successful reading of target data based on the indication information sent by the external controller. The internal controller can determine that the response status of the external controller to the read data message is response timeout based on other methods, which are introduced below.

[0073] Scenario 1: The external controller responds to the read data message with a status indicating that the data read failed.

[0074] The internal controller determines that the response status of the external controller to the read data message is failure to read target data, and generates a notification message including a response status identifier indicating that the response status of the external controller to the converted read data message is failure to read data.

[0075] Specifically, the internal controller sends a read data message to the external controller, and the external controller parses the converted read data message and reads target data from a storage space indicated by a destination address carried in the converted read data message.

[0076] If the external controller finds that the storage medium storing the target data is abnormal when reading the target data and cannot read the target data, the external controller will generate an indication message, which is used to indicate that the response status of the external controller to the read data message is failure to read the target data.

[0077] For example, the indication information carries a response fault indication, which can be NULL. The response fault indication is used to indicate that the external controller's response status to the read data message is a failure to read the target data, that is, to indicate that the processor core has failed to access the data of the storage unit in the peer server or the peer resource pool.

[0078] The external controller sends the indication information to the internal controller. When the internal controller determines that the indication information carries a response failure indication based on the indication information, it determines that the external controller fails to read the target data from the storage space indicated by the destination address of the read data message.

[0079] The internal controller generates a notification message according to the indication information, wherein the notification message includes a response status identifier, which is used to indicate to the processor core that the processor core has failed to access data of the storage unit in the peer server or peer resource pool, and sends the notification message to the processor core.

[0080] Optionally, the notification message may be sent by the internal controller to the processor core in the form of an internal bus protocol message.

[0081] For example, the internal controller and the processor core communicate via the Hyper Transport (HT) network protocol. The message format of the notification message generated by the internal controller is the message format of the HT network protocol. The message conforming to the HT network protocol includes 4 bytes (e.g., byte0 to byte3), and each byte includes 8 bits (e.g., bit0 to bit7), where byte0_bit[6] and byte1_bit[5] are reserved bits.

[0082] When the internal controller generates a message carrying a notification message based on the HT network protocol, it can add a response status identifier at byte0_bit[6] and byte1_bit[5] of the message. For example, when the values of byte0_bit[6] and byte1_bit[5] are "10", it means that the processor core has failed to access data from the storage unit in the peer server or peer resource pool.

[0083] Scenario 2: The external controller responds to the read data message with the status of successfully reading the target data.

[0084] The internal controller determines that the response status of the external controller to the read data message is successful reading of the target data, and generates a notification message including a response status identifier indicating that the response status of the external controller to the converted read data message is successful reading of the target data.

[0085] Specifically, the internal controller sends the converted read data message to the external controller, and the external controller parses the converted read data message and reads the target data from the storage space indicated by the destination address carried in the converted read data message.

[0086] If the external controller successfully reads the target data from the storage space indicated by the converted read data message, the external controller generates indication information. The indication information is used to instruct the external controller to successfully read the target data from the storage space indicated by the read data message.

[0087] For example, the indication information carries a successful response indication, which is used to indicate that the external controller successfully reads the target data from the storage space indicated by the read data message, that is, to indicate that the processor core successfully accesses the data of the storage unit in the peer server or peer resource pool.

[0088] The external controller sends the indication information to the internal controller, and the internal controller determines, based on the response success indication included in the indication information, that the external controller successfully reads the target data from the storage space indicated by the read data message.

[0089] The internal controller generates a notification message based on the indication information, which includes a response status identifier. The response status identifier is used to indicate to the processor core that the processor core has successfully accessed the read data of the storage unit in the peer server or peer resource pool, and sends the notification message to the processor core.

[0090] Optionally, the notification message may be sent by the internal controller to the processor core in the form of an internal bus protocol message.

[0091] For example, if the format of the message carrying the notification message generated by the internal controller complies with the message format of the HT protocol, the internal controller may add a response status identifier at byte0_bit[6] and byte1_bit[5] of the message when generating the message carrying the notification message. For example, when the values of byte0_bit[6] and byte1_bit[5] are "00", it indicates that the processor core has successfully accessed the data of the storage unit in the peer server or the peer resource pool.

[0092] The above describes the two response states of the internal controller determining failure to read data and successful reading of target data based on the instruction information sent by the external controller through scenarios 1 and 2. The following describes the method for the internal controller to determine that the response state of the external controller to the read data message is a response timeout.

[0093] Scenario 3: The external controller responds to the converted read data message with a response timeout status.

[0094] The internal controller determines that the response status of the external controller to the read data message is response timeout, and generates a notification message including a response status identifier indicating that the response status of the external controller to the converted read data message is response timeout.

[0095] Specifically, the internal controller starts the timer for timing before, after, or while sending a read data message to the external controller, for example, by increasing the timer from time 0 or decreasing the timer from the maximum time limit. If the value in the timer decreases to 0 or the value in the timer increases to the maximum time limit, the timer is considered to have timed out.

[0096] At this time, if the internal controller still has not received the indication information for the read data message sent by the external controller, the internal controller generates a notification message for the read data message, and the notification message includes a response status identifier. The response status identifier indicates that the response status of the external controller to the converted read data message is a response timeout, that is, it indicates that the processor core's data access to the storage unit in the peer server or the peer resource pool has timed out, and the internal controller sends the notification message to the processor core.

[0097] Optionally, the notification message may be sent by the internal controller to the processor core in the form of an internal bus protocol message.

[0098] For example, if the format of the message carrying the notification message generated by the internal controller complies with the message format of the HT protocol, the internal controller may add a response status identifier at byte0_bit[6] and byte1_bit[5] of the message when generating the message carrying the notification message. For example, when the values of byte0_bit[6] and byte1_bit[5] are "01", it indicates that the processor core has timed out accessing data from the storage unit in the peer server or peer resource pool. It is worth noting that when the response status of the read data message is response timeout, the internal controller may generate invalid data according to a preset rule. This invalid data is sent by the internal controller to the processor core as a response to the read data message, and the processor core then stores the invalid data in the internal storage.

[0099] It is worth noting that the server will perform fault tolerance when the above scenarios 1 and 3 occur. No fault tolerance is required for scenario 2.

[0100] As a possible implementation, in addition to the above-mentioned external controller determining the response status of the external controller to the read data message according to the response fault indication or the response success indication of the indication information, in an embodiment of the present invention, the internal controller can also send the message carrying the indication information in scenario 1 or scenario 2 to the processor core, and the processor core stores the response fault indication carried by the message carrying the indication information in scenario 1 or the response success indication carried by the message carrying the indication information in scenario 2 to the processor core. Figure 1 Processor core cache (cache) Figure 1 In the embodiment (not shown), by adding an instruction to the instructions stored in the internal memory of the server, the processor core can obtain the response failure indication or response success indication included in the message carrying the indication information from the cache.

[0101] After the internal controller receives invalid data generated according to preset rules from the external controller, the internal controller sends the invalid data to the processor core, and the processor core stores the invalid data in the internal memory.

[0102] Before performing operations on invalid data, the processor core first executes instructions stored in the internal memory to obtain the response failure indication or response success indication included in the message carrying the indication information from the cache, and performs fault tolerance processing on the response failure based on the response failure indication.

[0103] In one possible implementation, the method also includes: the internal controller sends the notification message to the processor core, specifically, the processor core obtains the response status identifier from the notification message; saves the response status identifier to the register of the processor core; before the processor core invalidates the data, the processor core obtains the response status identifier from the register; the processor core determines the response status of the external controller to the read data message based on the response status identifier.

[0104] Specifically, after determining the response status of the external controller to the read data message, the internal controller generates a notification message based on the response status and sends the notification message to the processor core. The response status identifier carried in the notification message indicates the response status of the external controller to the read data message. The processor core determines the response status of the external controller to the read data message based on the response status identifier.

[0105] By generating a notification message carrying a response status identifier, which indicates that a response exception has occurred in data access, the processor core requesting data access can determine the response status of the external controller to the read data message based on the response status identifier before performing operations on invalid data, and perform fault-tolerant processing on the response exception when the response status is a response exception, so as to avoid the data access system from failing to restart when performing operations on invalid data without detecting the response exception.

[0106] Next, how the processor core determines the response status of the external controller to the converted read data message according to the notification message and the fault tolerance processing method in the embodiment of the present invention are further explained.

[0107] Specifically, after receiving the notification message from the internal controller, the processor core obtains the response status identifier carried by the notification message (for example, the response status identifier can be any one of the response status identifiers in the above-mentioned scenarios 1 to 3), and stores the response status identifier in a register in the processor core.

[0108] It should be noted that in an embodiment of the present invention, if the notification message is sent by the internal controller to the processor core in the form of an internal bus protocol message, when the processor core receives the message carrying the notification message, it first needs to parse the message, and then obtain the response status identifier carried by the message, and store the response status identifier in a register in the processor core.

[0109] Several ways in which the processor core stores the response status identifier in a register in the processor core are described below.

[0110] Mode 1: Multiple processor cores use only one register to store the response status identifier carried in the notification message.

[0111] The register may be any one of the original registers of the processor core, and only some fields in the register may be used to store the response status identifier carried by the notification message; or, the register may be a newly added register in the processor core, and the register may be dedicated to storing the response status identifier carried by the notification message.

[0112] Specifically, after receiving the notification message sent by the internal controller, the processor core stores the response status identifier carried in the notification message in the register, and then obtains the response status identifier carried in the notification message from the register by executing instructions.

[0113] This register can be used to store multiple response status identifiers carried in multiple notification messages (for example, the multiple notification messages include the notification message in method 200) returned by the external controller to the processor core in response to multiple read data messages (for example, the multiple read data messages include the read data message in method 200). In this case, the multiple response status identifiers can be stored in an overwritten storage manner. After the processor core successfully receives the notification message, the response status identifier obtained from the register is the response status identifier carried in the notification message.

[0114] Optionally, the multiple response status identifiers may not be stored in an overwriting storage manner. For example, fields may be allocated in the register for the multiple response status identifiers corresponding to the multiple read data messages sent by the processor core. The allocated fields are used to store the multiple response status identifiers and create an association relationship between the multiple read data messages and the fields allocated to the response status identifiers corresponding to the multiple read data messages. When the processor core obtains the response status identifier carried by the notification message from the register, it can obtain the response status identifier carried by the notification message from the corresponding field in the register based on the association relationship.

[0115] Mode 2: Multiple processor cores use two or more registers to store the response status identifier carried by the notification message.

[0116] The at least two registers may be original registers of the processor core, and only some fields of the at least two registers may be used to store the response status identifier; or, the at least two registers may be newly added registers in the processor core, and the at least two registers may be dedicated to storing the response status identifier.

[0117] Specifically, after receiving the notification message sent by the internal controller, the processor core stores the response status identifier carried in the notification message in the register, and then obtains the response status identifier carried in the notification message from the register by executing instructions.

[0118] The register can be used to store multiple response status identifiers carried in the notification message (returned by the internal controller for multiple read data messages (for example, the multiple read data messages include converted read data messages) of the processor core. In this case, the multiple response status identifiers are stored in different registers. For example, there can be a one-to-one correspondence between the multiple response status identifiers and the multiple registers, that is, one register is only used to store one response status identifier. In this case, an association relationship between the multiple read data messages and the multiple registers can be established.

[0119] When obtaining the response status identifier carried in the notification message, the processor core may determine the register corresponding to the notification message according to the association relationship between the message and the register, and obtain the response status identifier carried in the notification message from the register.

[0120] For another example, there is a many-to-one relationship between the multiple response status identifiers and the multiple registers. That is, one register stores at least two response status identifiers. In this case, an association relationship can be established between the multiple read data messages, the multiple registers, and the fields in the registers for storing the response status identifiers.

[0121] When the processor core obtains the response status identifier carried by the notification message, it can determine the register corresponding to the notification message based on the association between the message and the register, and further determine the field in the register used to store the response status identifier carried by the notification message, thereby obtaining the response status identifier carried by the notification message in the corresponding storage space in the register.

[0122] It should be noted that the above description uses only the example of establishing a mapping relationship between the multiple read data messages and the fields and / or multiple registers allocated for the response status identifiers corresponding to the multiple read data messages. However, embodiments of the present invention are not limited thereto. For example, a mapping relationship may also be established between multiple notification messages and the fields and / or multiple registers allocated for the response status identifiers carried by the multiple notification messages.

[0123] It should also be noted that, in the embodiment of the present invention, in addition to the above-mentioned method of creating a mapping relationship to enable the processor core to obtain the response status identifier carried in the notification message from the register, the following methods may also be used:

[0124] When the processor core stores the response status identifier carried by the notification message into the register, the storage location of the field in the register used to store the response status identifier can be recorded so that the processor core can obtain the response status identifier carried by the notification message from the register according to the storage location.

[0125] It should also be noted that in an embodiment of the present invention, since the registers are closer to the processor core in the PCIe bus structure, compared to storing the response status identifier in the internal memory (cache), the response status identifier carried by the notification message is stored in the register in the processor core, which enables the processor core to quickly obtain the response status identifier from the register, and determine the response status of the external controller to the converted read data message based on the response status identifier, and quickly perform fault-tolerant processing on the response exception when the response status is a response exception.

[0126] The following describes a method for the processor core to determine the response status of the external controller to the read data message based on the notification message.

[0127] In this embodiment, an instruction is added to the instructions stored in the internal memory of the server. The execution of the instruction enables the processor core to obtain the response status identifier carried in the notification message from the register.

[0128] Therefore, before performing operations on the invalid data, the processor core will first execute the instructions stored in the internal memory to obtain the response status identifier from the register, and determine the response status of the external controller to the read data message based on the response status identifier, and when the response status is a response timeout or a failure to read the target data, fault tolerance processing will be performed for the response timeout or failure to read the target data.

[0129] For example, when the value of the response status identifier obtained by the processor core from the register is 01, the processor core determines that the data access to the storage unit in the peer server or the peer resource pool has timed out based on the specific value of the response status identifier. At this time, the processor determines that the returned data is invalid data, abandons the operation on the invalid data, and realizes data access to the storage unit in the peer server or the peer resource pool through retry, degraded read and replica read.

[0130] For example, when the value of the response status identifier obtained by the processor core from the register is 10, the processor core determines that the external controller has failed to read the target data from the storage space indicated by the destination address carried in the read data message based on the specific value of the response status identifier. At this time, the processor core determines that the returned data is invalid data, abandons performing operations on the invalid data, and implements data access to the storage unit in the peer server or peer resource pool through retry, degraded read or copy read.

[0131] For example, when the value of the response status identifier obtained by the processor core from the register is 00, the processor core determines that the external controller has successfully read the target data from the storage space indicated by the destination address carried in the read data message based on the specific value of the response status identifier. At this time, the processor core then performs operations on the target data returned by the external controller.

[0132] The following describes several methods for fault-tolerant processing when the external controller's response status to the read data message is response timeout or failure to read target data.

[0133] Method 1: Retry processing

[0134] Specifically, when the processor core determines that a timeout failure occurs when reading the target data from the peer server, the processor core abandons the operation on the invalid data. The processor core can send a read data message to the peer server again. The read data message request is used to request the peer server to read the target data from the storage space indicated by the destination address carried by the read data message.

[0135] Method 2: Degraded Read Processing

[0136] Degraded read processing refers to storing the target data and its associated data on separate servers. The associated data of the target data refers to the data used to generate a checksum for the target data as a whole. The checksum can be stored on the same server as the target data or its associated data, or it can be stored separately on a server. If a processor core times out while reading target data from a peer server in this embodiment or fails to read the target data due to a storage medium anomaly, the processor core can read the associated data and checksum of the target data from another server and restore the target data to be read based on the associated data and checksum.

[0137] Method 3: Replica Read Processing

[0138] Replica read processing refers to the target data being stored on multiple servers (e.g., replica servers). If a processor core encounters a timeout while reading the target data from a peer server or fails to read the target data due to a storage medium anomaly, the processor core can read the target data from another replica server that stores the target data.

[0139] Compared with the traditional technical solution in which the processor core assumes that the read access is successful and does not check whether the returned result is invalid data, the embodiment of the present invention enables the processor core to store the response identifier obtained from the notification message in a register, and adds an instruction in the internal memory of the server, so that the processor core executes the instruction to obtain the response status identifier carried by the notification message from the register, so that the processor core can determine the response status of the external controller to the read data message based on the response status identifier before performing operations on the returned data, and perform fault-tolerant processing for the response exception when the response status is a response exception, so as to avoid the data access system from failing to restart when performing operations on invalid data without detecting the response exception.

[0140] Combined with the above Figures 1 to 2 , describes the fault tolerance processing method provided by the embodiment of the present invention, and the following is combined with Figures 3 and 4 The present invention describes a fault-tolerant processing device and server provided by an embodiment of the present invention.

[0141] Figure 3 A schematic block diagram of a fault-tolerant processing device 300 provided in an embodiment of the present invention, wherein the device communicates with an external controller via a memory semantic network protocol, and the external controller is located outside the device. The fault-tolerant processing device 300 includes a first transceiver module 301, a first processing module 302, a second transceiver module 303, a second processing module 304 and a storage module 305.

[0142] A first transceiver module 301 is configured to send a read data message to the external controller, wherein the read data message is used to request the external controller to read data from an indicated storage location, and the message format of the read data message complies with the message format specified by the memory semantic network protocol;

[0143] The first transceiver module 301 is further configured to receive indication information sent by the external controller, where the indication information is used to indicate a response status of the external controller to the read data message;

[0144] The first processing module 302 is configured to determine a response status of the external controller to the read data message according to the indication information, and perform fault tolerance processing when the response status is an abnormal response.

[0145] Optionally, the first transceiver module 301 is further configured to perform format conversion on the message received from the second transceiver module to generate the read data message; and send the read data message to the external controller.

[0146] Optionally, the first processing module 302 is specifically used to determine the read data result of the external controller based on the indication information, and the read data result is used to indicate whether the external controller has successfully read the data; the internal controller generates a notification message based on the read data result, and the notification message includes a response status identifier, and the response status identifier indicates that the external controller failed to read the target data from the storage space indicated by the read data message.

[0147] Optionally, the first transceiver module 301 is also used to send the notification message to the second transceiver module; the second transceiver module 303 is specifically used to obtain the response status identifier from the notification message; and save the response status identifier in the storage module 305 of the device; the device also includes: a second processing module 304, specifically used to obtain the response status identifier from the storage module 305; and determine the response status of the external controller to the read data message based on the response status identifier.

[0148] Optionally, the response status identifier indicates that the external controller fails to read the target data from the storage space indicated by the read data message, or the response status identifier indicates that the external controller successfully reads the target data from the storage space indicated by the read data message.

[0149] Optionally, when the response status identifier indicates that the external controller fails to read the target data from the storage space indicated by the read data message, the fault-tolerant processing includes degraded reading or replica reading.

[0150] The fault-tolerant processing device provided by an embodiment of the present invention determines the response status of the server requested to read data to the read data message before the processor core performs operations on the invalid data returned by the external controller when performing read data access, and performs fault-tolerant processing when the response status is a response exception, thereby avoiding the data access system from failing to restart when performing operations on the invalid data without detecting the response exception.

[0151] It should be understood that the fault-tolerant processing device of the embodiment of the present invention can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), and the PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. It can also be implemented by software. Figure 2When the fault-tolerant processing method is shown, the apparatus 300 and its modules may also be software modules.

[0152] The apparatus 300 for fault tolerance processing according to an embodiment of the present invention may correspond to the method 200 described in the embodiment of the present invention, and the above and other operations and / or functions of each unit in the apparatus 300 are respectively to realize Figure 2 The corresponding process of method 200 in the embodiment, wherein the first transceiver module 301 and the first processing module 302 are modules in the internal controller, and the second transceiver module 303 and the second processing module 304 are modules in the processor core, which will not be described here for the sake of brevity.

[0153] Figure 4 A schematic diagram of a server 500 provided in an embodiment of the present invention is shown as follows: Figure 4 As shown, the server 500 includes a processor 501, a memory 502, a communication interface 503, and a bus 504. The processor 501, the memory 502, and the communication interface 503 communicate via the bus 504, and may also communicate via other means such as wireless transmission.

[0154] The processor 501 includes multiple processor cores 5013 (for example, processor core 0 to processor core L, L ≥ 2) and an internal controller 5011. Each processor core 5013 is equipped with one or more registers ( Figure 4 Only one register is shown in the figure), the internal controller 5011 communicates with multiple processor cores based on the internal bus 5012.

[0155] The internal controller 5011 is used to send a read data message to the external controller, where the read data message is used to request the external controller to read data from the indicated storage location, and the message format of the read data message complies with the message format specified by the memory semantic network protocol; receive indication information sent by the external controller, where the indication information is used to indicate the response status of the external controller to the read data message; determine the response status of the external controller to the read data message based on the indication information, and perform fault tolerance processing when the response status is an abnormal response.

[0156] Optionally, the internal controller 5011 is further configured to perform format conversion on the message from the processor to generate the read data message; and send the read data message to the external controller.

[0157] Optionally, the internal controller 5011 is also used to determine the read data result of the external controller based on the indication information, and the read data result is used to indicate whether the external controller has successfully read the data; based on the read data result, a notification message is generated, and the notification message includes a response status identifier, and the response status identifier indicates that the external controller failed to read the target data from the storage space indicated by the read data message.

[0158] Optionally, the internal controller 5011 is further configured to send the notification message to the processor 501;

[0159] The processor core 5013 in the processor 501 is used to obtain the response status identifier from the notification message; save the response status identifier to the register of the processor; obtain the response status identifier from the register; and determine the response status of the external controller to the read data message based on the response status identifier.

[0160] Optionally, the fault tolerance process includes degraded reads or replica reads.

[0161] The server provided by an embodiment of the present invention, when performing read data access, determines the response status of the server requested to read data to the read data message before the processor core performs operations on the invalid data returned by the external controller, and performs fault tolerance processing when the response status is a response exception, thereby avoiding the data access system from failing to restart when performing operations on the invalid data without detecting the response exception.

[0162] It should be understood that in the embodiment of the present invention, the processor 501 may be a CPU, or other general-purpose processors, SoCs, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0163] The memory 502 may include a read-only memory and a random access memory, and provides instructions and data to the processor 501. The memory 502 may also include a non-volatile random access memory. For example, the memory 502 may also store information about the device type. The memory 502 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0164] In addition to the data bus, the bus 504 may also include a power bus, a control bus, and a status signal bus. Figure 4 Various buses are marked as bus 04.

[0165] The internal bus 5012 may be any one of a quick path interconnect (QPI) bus, a hyper transport (HT) bus, and a HiSilicon cache coherent connect specification (HCCS) bus.

[0166] It should be understood that the server 500 according to the embodiment of the present invention may correspond to the server 400 in the embodiment of the present invention, and may correspond to the corresponding subject in the method 200 according to the embodiment of the present invention, and the above and other operations and / or functions of each module in the server 500 are respectively for the purpose of realizing Figure 2 For the sake of brevity, the corresponding process of method 200 is not repeated here.

[0167] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

[0168] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0169] In the several embodiments provided in the embodiments of the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the unit is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0170] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0171] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0172] The above embodiments can be implemented in whole or in part through software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, hard disk, tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0173] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: The method is applied to a server, wherein the server communicates with an external controller via a memory semantic network protocol, and the external controller is located outside the server. The method includes: The server sends a read data message to the external controller, wherein the read data message is used to request the external controller to read data from an indicated storage location, and a message format of the read data message complies with a message format specified by the memory semantic network protocol; The server receives indication information sent by the external controller, where the indication information is used to indicate a response status of the external controller to the read data message; When the indication information indicates that the response status is a response exception, the server performs fault tolerance processing on the read data message, the response exception includes a data read failure or a data read timeout, and the fault tolerance processing includes degraded reading; The degraded read includes the server reading associated data and a check code of data from another server, and restoring the data based on the associated data and the check code of the data, wherein the associated data of the data and the data are used as a whole to generate the check code.

2. The method according to claim 1, characterized in that When the indication information indicates that the response status is an abnormal response, the server performs fault tolerance processing on the read data message, specifically including: The server determines, according to the indication information, a response status of the external controller to the read data message; When the response status is the response exception, the server performs fault tolerance processing on the read data message.

3. The method according to claim 2, characterized in that The server includes a processor, the processor includes an internal controller and a processor core, and the processor core communicates with the internal controller via an internal bus network protocol; The server sending a read data message to the external controller includes: The internal controller performs format conversion on the message from the processor to generate the read data message; The internal controller sends the read data message to the external controller.

4. The method according to claim 3, characterized in that The server determines a response status of the external controller to the read data message, including: The internal controller determines, according to the indication information, a data reading result of the external controller, wherein the data reading result is used to indicate whether the external controller has successfully read the data; The internal controller generates a notification message according to the data reading result, where the notification message includes a response status identifier, and the response status identifier indicates whether the external controller successfully reads the data from the storage space indicated by the data reading message.

5. The method according to claim 4, characterized in that The method further comprises: The internal controller sends the notification message to the processor core; The processor core obtains the response status identifier from the notification message; The processor core saves the response status identifier into a register of the processor core; The processor core obtains the response status identifier from the register; The server determines, according to the indication information, a response status of the external controller to the read data message, including: The processor core determines a response status of the external controller to the read data message according to the response status identifier.

6. The method according to claim 1 or 2, characterized in that When the indication information is used to indicate that the response status of the external controller to the read data message is that the data is read successfully, the read data is operated.

7. A data processing server, characterized in that: The server communicates with an external controller via a memory semantic network protocol. The external controller is located outside the server. The server includes a processor, which includes a processor core and an internal controller. The processor core and the internal controller are connected via an internal bus. The internal controller is configured to send a read data message to the external controller, wherein the read data message is used to request the external controller to read data from an indicated storage location, and a message format of the read data message complies with a message format specified by the memory semantic network protocol; Receive indication information sent by the external controller, the indication information is used to indicate the response status of the external controller to the read data message; when the indication information indicates that the response status is a response exception, perform fault-tolerant processing on the read data message, the response exception includes a failure to read data or a timeout in reading data, and the fault-tolerant processing includes degraded reading; wherein the processor core is used to read associated data and a check code of data from another server, and recover the data based on the associated data of the data and the check code to perform the degraded read, and the associated data of the data and the data are used as a whole to generate the check code.

8. The server according to claim 7, wherein: The internal controller is further configured to: According to the indication information, a response status of the external controller to the read data message is determined; and when the response status is an abnormal response, fault tolerance processing is performed on the read data message.

9. The server according to claim 8, wherein: The internal controller is further configured to perform format conversion on the message from the processor core to generate the read data message; and send the read data message to the external controller.

10. The server according to claim 9, wherein: The internal controller is also used to determine the read data result of the external controller based on the indication information, and the read data result is used to indicate whether the external controller has successfully read the data; based on the read data result, a notification message is generated, and the notification message includes a response status identifier, and the response status identifier indicates whether the external controller has successfully read the data from the storage space indicated by the read data message.

11. The server according to claim 10, wherein: The internal controller is further configured to send the notification message to the processor core; The processor core is used to obtain the response status identifier from the notification message; save the response status identifier to the register of the processor core; obtain the response status identifier from the register; and determine the response status of the external controller to the read data message based on the response status identifier.

12. The server according to claim 7 or 8, characterized in that: When the indication information is used to indicate that the response status of the external controller to the read data message is that the data is read successfully, the read data is operated.

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