Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present application provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device comprises a transistor array; the method comprises: forming a columnar conductive channel of the transistor array on a wafer surface; wherein an extension direction of the columnar conductive channel is perpendicular to the wafer surface; synchronously forming a gate layer surrounding the columnar conductive channel around each columnar conductive channel of the transistor array; and forming a source and a drain of the transistor at both ends of the extension direction of the columnar conductive channel of the transistor array, respectively.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in dynamic random access memory (DRAM) to control the capacitance in each memory cell, and transistor arrays composed of multiple transistors can be used in semiconductor memory devices.

[0003] In the related art, transistor arrays mainly include planar transistor arrays and buried channel transistor arrays. However, both planar transistor arrays and buried channel transistor arrays occupy a relatively large area. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a transistor array; the method includes:

[0006] Forming a columnar conductive channel of a transistor array on a wafer surface; wherein the extension direction of the columnar conductive channel is perpendicular to the wafer surface;

[0007] Around each columnar conductive channel of the transistor array, a gate layer surrounding the columnar conductive channel is simultaneously formed;

[0008] The source and drain of the transistor are respectively formed at two ends of the extension direction of the columnar conductive channel of the transistor array.

[0009] In some embodiments, the step of forming a columnar conductive channel of a transistor array on a wafer surface includes:

[0010] The wafer surface is etched to form an array of columnar conductive channels and first grooves between the columnar conductive channels; wherein the array of columnar conductive channels includes the columnar conductive channels of each transistor in the transistor array.

[0011] In some embodiments, the gate layer includes: a gate oxide layer and a gate electrode; the gate layer surrounding the columnar conductive channels of the transistor array is formed synchronously, including:

[0012] Around each columnar conductive channel of the transistor array, the gate oxide layer surrounding the columnar conductive channel is simultaneously formed;

[0013] The gate electrode surrounding each of the gate oxide layers is simultaneously formed around the gate oxide layers.

[0014] In some embodiments, the gate oxide layer surrounding each columnar conductive channel of the transistor array is formed synchronously, comprising:

[0015] Depositing an insulating material in the first groove to form an insulating layer;

[0016] The insulating layer is etched to form a second groove; wherein at least a portion of the surrounding sidewall of the columnar conductive channel of each transistor is exposed in the second groove;

[0017] The exposed surrounding sidewalls of the columnar conductive channel are oxidized to form the gate oxide layer surrounding the columnar conductive channel.

[0018] In some embodiments, the gate electrode surrounding each gate oxide layer is formed around the gate oxide layer simultaneously, comprising:

[0019] A conductive material is deposited in the second groove to form the gate electrode surrounding the gate oxide layer.

[0020] In some embodiments, the second groove passes through the columnar conductive channel located in the same column in the transistor array; the conductive materials of the gate electrodes of the transistors located in the same column are interconnected, and the interconnected conductive materials are word lines of the transistors in the same column.

[0021] In some embodiments, forming a source and a drain of a transistor at two ends of the extension direction of the columnar conductive channel of the transistor array respectively includes:

[0022] At one end of each columnar conductive channel of the transistor array away from the bottom of the wafer, a source of each transistor in the transistor array is formed simultaneously;

[0023] At one end of each columnar conductive channel of the transistor array close to the bottom of the wafer, the drain of each transistor in the transistor array is formed simultaneously.

[0024] In some embodiments, at one end of each columnar conductive channel of the transistor array close to the bottom of the wafer, a drain of each transistor in the transistor array is formed simultaneously, including:

[0025] Performing ion implantation on the wafer from the back side of the wafer to form a drain region of the transistor array; wherein the back side of the wafer is the side opposite to the surface of the wafer;

[0026] The drain region is etched to form the drain of each transistor in the transistor array; wherein the drain of each transistor in the transistor array is distributed at intervals at the bottom of the wafer.

[0027] In some embodiments, at one end of each columnar conductive channel of the transistor array close to the bottom of the wafer, a drain of each transistor in the transistor array is formed simultaneously, including:

[0028] Thinning the wafer from the back side of the wafer to expose an end of the columnar conductive channel close to the bottom of the wafer; wherein the back side of the wafer is the side opposite to the surface of the wafer;

[0029] Ion implantation is performed on one end of each of the columnar conductive channels close to the bottom of the wafer to form a drain of each transistor in the transistor array.

[0030] In some embodiments, the ends of the columnar conductive channels in the transistor array away from the bottom of the wafer are used to simultaneously form the source of each transistor in the transistor array, including:

[0031] At one end of each columnar conductive channel of the transistor array away from the bottom of the wafer, ion implantation is performed on each columnar conductive channel to form a source of each transistor in the transistor array.

[0032] In some embodiments, the method further comprises:

[0033] Depositing a metal layer on the source surface of each transistor in the transistor array;

[0034] The metal layer is etched to form a bit line connecting the sources of the transistors in the same row in the transistor array.

[0035] In a second aspect, an embodiment of the present application provides a semiconductor device, characterized in that it includes:

[0036] A transistor array having columnar conductive channels; wherein the extension direction of each of the columnar conductive channels of the transistor array is perpendicular to the surface of the wafer forming the transistor array;

[0037] Each columnar conductive channel of the transistor array is surrounded by a gate layer surrounding the columnar conductive channel;

[0038] The two ends of the extension direction of the columnar conductive channel of the transistor array are respectively provided with a source and a drain of the transistor.

[0039] The embodiment of the present application provides a semiconductor device and a manufacturing method thereof. The source and drain of the transistor array formed by the manufacturing method are respectively located at two ends along the extension direction of the conductive channel, and the extension direction is perpendicular to the wafer surface, and the gate is formed around the conductive channel, so that the area of ​​the transistor array is greatly reduced. In addition, the source of each transistor in the transistor array in the embodiment of the present application can be located in the same plane, and the drain can be located in the same plane, which can simplify the design of the circuit layout inside the semiconductor device and reduce the process difficulty of semiconductor device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0041] Figure 1A It is a schematic diagram of the structure of a planar transistor array in the related art;

[0042] Figure 1B It is a structural schematic diagram of a buried channel transistor array in the related art;

[0043] Figure 2 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present application;

[0044] Figure 3A A top view of a columnar conductive channel provided in an embodiment of the present application;

[0045] Figure 3B A schematic diagram of a structure for forming a columnar conductive channel provided in an embodiment of the present application;

[0046] Figure 4A A schematic diagram of an optional structure for forming a gate layer provided in an embodiment of the present application;

[0047] Figure 4B A schematic diagram of an optional structure for forming a gate layer provided in an embodiment of the present application;

[0048] Figure 5A An optional top view of forming an insulating layer provided in an embodiment of the present application;

[0049] Figure 5B An optional top view of forming a second groove provided in an embodiment of the present application;

[0050] Figure 5C An optional top view of forming a gate oxide layer provided in an embodiment of the present application;

[0051] Figure 6 An optional top view of forming a gate electrode provided in an embodiment of the present application;

[0052] Fig. 7A A schematic diagram of an optional structure for forming a word line provided in an embodiment of the present application;

[0053] Figure 7B A schematic diagram of an optional structure for forming a word line provided in an embodiment of the present application;

[0054] Fig. 8A A schematic diagram of an optional structure for forming a source electrode provided in an embodiment of the present application;

[0055] Figure 8B A schematic diagram of an optional structure for forming a source electrode provided in an embodiment of the present application;

[0056] Fig.9A A schematic diagram of a structure for forming a drain region provided in an embodiment of the present application;

[0057] Fig. 9B A schematic diagram of an optional structure for forming a drain provided in an embodiment of the present application;

[0058] Fig. 10A A schematic diagram of a structure for performing a wafer thinning process provided in an embodiment of the present application;

[0059] Fig. 10B A schematic diagram of an optional structure for forming a drain provided in an embodiment of the present application;

[0060] Fig.11A A schematic diagram of an optional structure for forming a bit line provided in an embodiment of the present application;

[0061] Fig. 11B A schematic diagram of an optional structure for forming a bit line provided in an embodiment of the present application;

[0062] Fig.12 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application; DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the invention will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0064] In the following description, the suffixes such as "module" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module" or "unit" can be used mixedly.

[0065] In the related art, transistor arrays of mainstream memories include planar transistor arrays and buried channel array transistor (BCAT) transistor arrays. However, regardless of whether it is a planar transistor array or a buried channel array, the source and the drain are located on both sides of the gate in their structure. Figure 1A is a schematic diagram of the structure of a planar transistor array in the related art, Figure 1B FIG. 1 is a schematic diagram of a buried channel transistor array in the related art. Figure 1A and 1B As shown, the source 11 and drain 12 of the transistor in the related art are respectively located on both sides of the gate 13. In this structure, the source and drain occupy different positions, so that the area of ​​both the planar transistor array and the buried channel transistor array is larger.

[0066] In addition, since the transistor array can be prepared on a silicon substrate, the transistor array can be used in various memories, such as dynamic random access memory, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc. Since the source and drain of the planar transistor array and the buried channel transistor array are respectively located on both sides of the gate level, the bit line (BL) and the capacitor in the memory cell of the memory will also be located on the same side of the gate, and the subsequent process also needs to realize the connection between the bit line, the transistor and the capacitor, the connection between the word line (WL) and the transistor, etc., which leads to complex circuit wiring in the memory array area of ​​the memory and greater difficulty in the manufacturing process.

[0067] Based on the above-mentioned problems existing in the related art, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof, which can provide a transistor array structure with a smaller area. Moreover, the transistor array structure provided by the embodiments of the present application can simplify the circuit layout inside the memory and reduce the process difficulty of memory manufacturing.

[0068] Figure 2A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application, wherein the semiconductor device comprises a transistor array; the method comprises:

[0069] Step S201, forming a columnar conductive channel of a transistor array on a wafer surface; wherein an extension direction of the columnar conductive channel is perpendicular to the wafer surface;

[0070] Step S202, synchronously forming a gate layer surrounding each columnar conductive channel of the transistor array;

[0071] Step S203 , forming a source and a drain of a transistor at two ends of the extension direction of the columnar conductive channel of the transistor array respectively.

[0072] In the embodiment of the present application, the wafer is a silicon wafer formed by grinding, polishing and slicing cylindrical single crystal silicon for making semiconductor devices. The wafer has two opposite circular surfaces, one of which is the wafer surface, and the other circular surface can be referred to as the wafer back in the embodiment of the present application.

[0073] The transistor involved in the embodiments of the present application may include a field effect transistor or other transistors having a conductive channel. The conductive channel is used to transfer charges or stop the transfer of charges under the action of an external electric field, so that the transistor is turned on or off.

[0074] The embodiment of the present application forms an array of columnar conductive channels on the wafer surface, and the extension direction of each columnar conductive channel is perpendicular to the wafer surface. Here, the extension direction of the columnar conductive channel is the current direction when the transistor is turned on.

[0075] In addition, the cross-section of the columnar conductive channel may be circular, rectangular, diamond-shaped, polygonal, etc., which is not limited in the embodiments of the present application.

[0076] Since the extension direction of each columnar conductive channel of the above transistor array is perpendicular to the wafer surface, the source and drain of the transistor need to be located at both ends of the columnar conductive channel, so the gate layer of each transistor needs to be located next to the surrounding sidewall of the columnar conductive channel. The gate of the transistor is used to provide a gate voltage so that the conductive channel of the transistor is affected by an electric field. The gate voltage can include voltages of different strengths or polarities to control the conductive channel of the transistor to have different degrees of conductivity.

[0077] In the embodiment of the present application, the gate layer surrounding the columnar conductive channel is used as the gate of each transistor. That is to say, the surrounding sidewall of the columnar conductive channel is entirely covered with the annular gate layer. During the manufacturing process, the gate layer can be formed synchronously for the array composed of the columnar conductive channels, and there is no need to align the position of the gate layer relative to the conductive channel, which is convenient for implementation in industrial production.

[0078] In some embodiments, the step of forming a columnar conductive channel of a transistor array on a wafer surface includes:

[0079] The wafer surface is etched to form an array of columnar conductive channels and first grooves between the columnar conductive channels; wherein the array of columnar conductive channels includes the columnar conductive channels of each transistor in the transistor array.

[0080] The wafer surface may be etched using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching or reactive ion etching, which is not limited in the embodiments of the present application.

[0081] like Figure 3A and 3B ( Figure 3A is a top view, Figure 3B As shown in the three-dimensional diagram, during the etching process of the wafer surface, a mask (not shown in the figure) may be used to cover part of the wafer surface, i.e., the regions where the columnar conductive channels 301 need to be formed. Then, the wafer surface is etched, and a part of the semiconductor material on the wafer is etched away outside the region covered by the mask, to form a groove of a certain depth, i.e., the first groove 302 mentioned above.

[0082] The etching depth can be close to the length of the transistor required by the semiconductor device, or slightly less than the length of the transistor. However, the etching depth is less than the initial thickness of the wafer, so that the area covered by the mask layer is not etched away, and columnar conductive channels 301 arranged in an array on the remaining part of the wafer after etching are formed, and the surrounding sidewalls of the columnar conductive channels 301 are exposed in the first groove 302.

[0083] In the embodiment of the present application, by etching the entire wafer surface, an array of columnar conductive channels 301 and first grooves 302 with the same depth are simultaneously formed, which can simplify the manufacturing process and improve efficiency.

[0084] In some embodiments, Figure 4A and Figure 4BAs shown, the gate layer includes: a gate oxide layer 411 and a gate electrode 412; the gate layer surrounding the columnar conductive channels 301 is formed synchronously around each columnar conductive channel 301 of the transistor array, including:

[0085] The gate oxide layer 411 surrounding the columnar conductive channels 301 is formed around each columnar conductive channel 301 of the transistor array simultaneously;

[0086] Around the gate oxide layer 411 , the gate electrode 412 surrounding each of the gate oxide layers 411 is simultaneously formed.

[0087] In the embodiment of the present application, the process of forming the gate layer includes: first forming a gate oxide layer surrounding the columnar conductive channel, and then forming a gate electrode surrounding the gate oxide layer. Wherein, each of the above-mentioned columnar conductive channels is a single crystal silicon material, which is used to transfer charge or stop the transfer of charge under the action of an external electric field; the gate oxide layer is an insulating material, such as silicon dioxide (SiO2), and the gate oxide layer is located between the columnar conductive channel and the gate electrode, which is used for electrical isolation to prevent the gate electrode from directly contacting the columnar conductive channel to generate charge leakage; the gate electrode is a metal material, such as metal tungsten (W), metal nickel (Ni), metal copper (Cu) or metal aluminum (Al), etc., and the gate electrode is formed around the gate oxide layer, which can increase the width of the conductive channel and provide a larger channel current.

[0088] In one embodiment, if Figure 4A As shown, the formed gate oxide layer 411 can cover the surrounding sidewalls of the columnar conductive channel and cover the bottom of the first groove. Exemplarily, the entire wafer after the first groove is formed can be oxidized (at this time, the mask covering the top of the columnar conductive channel when the first groove is formed can be retained to prevent the top of the columnar conductive channel from being oxidized), and then the gate electrode 412 is formed outside the surrounding sidewalls of the columnar conductive channel covered with the gate oxide layer 411.

[0089] In another embodiment, if Figure 4B As shown, the formed gate oxide layer 411 may only cover the surrounding sidewalls of the columnar conductive channel, and then the gate electrode 412 is formed outside the surrounding sidewalls of the columnar conductive channel covered with the gate oxide layer 411 .

[0090] Exemplarily, the gate electrodes 412 of the pillar-shaped conductive channels in the same column may be connected into a straight line as a word line and spaced apart in the row direction, that is, the gate electrodes surrounding the pillar-shaped conductive channels in the same row are separated from each other.

[0091] It should be noted that Figure 4A and Figure 4BThe gate electrode 412 is a perspective effect, which facilitates observation of the structure of the surrounding gate oxide layer covering the surrounding sidewall of the columnar conductive channel, and the structure of the surrounding gate electrode covering the periphery of the gate oxide layer and interconnected in the column direction.

[0092] In some embodiments, Figures 5A to 5C for Figure 4B A top view of the gate oxide layer formed by each conductive channel of the transistor array shown. Figures 5A to 5C As shown, the gate oxide layer 411 surrounding the columnar conductive channels 301 of the transistor array is formed synchronously, including:

[0093] Depositing an insulating material in the first groove 302 to form an insulating layer 521;

[0094] The insulating layer 521 is etched to form a second groove 522 ; wherein at least a portion of the surrounding sidewall of the columnar conductive channel 301 of each transistor is exposed in the second groove 522 ;

[0095] The exposed sidewalls surrounding the columnar conductive channel 301 are oxidized to form the gate oxide layer 523 surrounding the columnar conductive channel 301 .

[0096] The deposition process may include but is not limited to the following methods: chemical vapor deposition (PVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). The insulating material may be silicon dioxide or other insulating materials. Figure 5A As shown, in the embodiment of the present application, the columnar conductive channels can be separated by depositing insulating material SiO2 in the first groove, and the insulating material SiO2 covers the bottom of the first groove and around the columnar conductive channels to form an insulating layer.

[0097] It should be noted that in the actual process of depositing the insulating material, the insulating material SiO2 will cover the surface of the columnar conductive channel. Usually after the deposition is completed, a chemical mechanical polishing (CMP) process can be used to polish and remove excess insulating material SiO2 to expose the surface of the columnar conductive channel.

[0098] like Figure 5BAs shown, when etching the insulating layer around the columnar conductive channel, a mask (not shown) can be used to cover part of the insulating layer 521, exposing only the area where the second groove is to be formed, and then etching is performed. Outside the area covered by the mask, a second groove of a certain depth is formed around the columnar conductive channel. Each second groove has a width greater than the columnar conductive channel in the row direction of the transistor array and extends in the column direction of the transistor array. After etching is completed, the insulating layer is not completely removed, and the remaining insulating layer is located between two adjacent second grooves, and separates the adjacent second grooves in the column direction.

[0099] It should be noted that the transistor array may be arranged in rows and columns, and the row direction may be relatively perpendicular to the column direction, or may have a certain angle therebetween.

[0100] In the extension direction, the second groove may have a depth less than or equal to that of the first groove. When the depth of the second groove is less than that of the first groove, the surrounding sidewall portion of the columnar conductive channel of each transistor is deeply exposed in the second groove, and the remaining portion of the surrounding sidewall is in contact with the bottom insulating layer; when the depth of the second groove is equal to the depth of the first groove, the surrounding sidewall of the columnar conductive channel of each transistor is completely exposed in the second groove.

[0101] like Figure 5C As shown, the process of oxidizing the surrounding sidewalls of the columnar conductive channel exposed in the second groove includes but is not limited to: direct oxidation, alkaline oxidation or acidic oxidation. In the embodiment of the present application, direct oxidation is performed by heating, so that the silicon on the surrounding sidewalls of the columnar conductive channel reacts chemically with the gas containing the oxidizing substance at high temperature, thereby generating a dense silicon dioxide film on the silicon surface, forming a gate oxide layer (SiO2) surrounding the columnar conductive channel.

[0102] In the embodiment of the present application, the depth of the surrounding sidewall of the columnar conductive channel along the extension direction is at least partially exposed in the second groove, which can simplify the process and facilitate the formation of a surrounding gate oxide layer.

[0103] In some embodiments, Figure 6 for Figure 4B The top view of each columnar conductive channel forming a gate electrode of the transistor array shown in FIG. Figure 6 As shown, the gate electrode 634 surrounding each gate oxide layer 523 is formed around the gate oxide layer 523 simultaneously, including:

[0104] A conductive material is deposited in the second groove 522 to form the gate electrode 634 surrounding the gate oxide layer 523 .

[0105] Here, the deposition process includes but is not limited to chemical vapor deposition, physical vapor deposition or atomic layer deposition. The conductive material can be polysilicon, metal or other conductive materials. In the embodiment of the present application, the deposited conductive material is metal tungsten, and the gate electrode is formed by covering the metal tungsten film around the gate oxide layer with tungsten atoms in a low-pressure gas or plasma process.

[0106] Since the gate electrode is formed to surround the columnar conductive channel, the width of the conductive channel can be increased, providing a larger channel current.

[0107] In some embodiments, the second groove passes through the columnar conductive channel located in the same column in the transistor array; the conductive materials of the gate electrodes of the transistors located in the same column are interconnected, and the interconnected conductive materials are word lines of the transistors in the same column.

[0108] In the embodiment of the present application, penetration means that in the column direction of the transistor array, multiple columnar conductive channels are located in the second grooves of the same column, and the depth of the surrounding side wall of each columnar conductive channel along the extension direction is at least partially exposed in the second groove of the same column.

[0109] In the process of depositing the conductive material in the second groove to form the gate electrode, in addition to forming the gate electrode around the gate oxide layer surrounding each transistor, a conductive material is also deposited between two adjacent gate electrodes on the same column for mutual connection to fill the second groove. Fig. 7A and 7B As shown, the gate electrodes 701 extending in the same column direction are electrically connected to an external circuit through external wiring to form a word line, wherein the word line can provide a word line voltage and control the conduction or cutoff of each transistor through the word line voltage.

[0110] Since the gate electrodes are connected to each other in the same column direction to form word lines, the wiring of the word lines in the semiconductor device can be facilitated and the control performance can be optimized.

[0111] In some embodiments, forming a source and a drain of a transistor at two ends of the extension direction of the columnar conductive channel of the transistor array respectively includes:

[0112] At one end of each columnar conductive channel of the transistor array away from the bottom of the wafer, a source of each transistor in the transistor array is formed simultaneously;

[0113] At one end of each columnar conductive channel of the transistor array close to the bottom of the wafer, the drain of each transistor in the transistor array is formed simultaneously.

[0114] In an embodiment of the present application, after etching the first groove and the second groove, a portion of the bottom of the wafer will be exposed at one end of the columnar conductive channel. In the extension direction, the columnar conductive channel has an end away from the bottom of the wafer and an end close to the bottom of the wafer. Among them, the end of each columnar conductive channel away from the bottom of the wafer is located in the same plane, and is spaced apart in the row and column directions of the transistor array, which is used to form the source of each transistor in the subsequent process; the end of each columnar conductive channel close to the bottom of the wafer is located in the same plane, and is spaced apart in the row and column directions of the transistor array, which is used to form the drain of each transistor in the subsequent process.

[0115] Since the source and drain of each transistor are located in the same plane, the circuit layout inside the semiconductor device can be simplified and the process difficulty of manufacturing the semiconductor device can be reduced.

[0116] In some embodiments, Fig. 8A and 8B As shown, the ends of the columnar conductive channels in the transistor array away from the bottom of the wafer simultaneously form the source 801 of each transistor in the transistor array, including:

[0117] At one end of each columnar conductive channel of the transistor array away from the bottom of the wafer, ion implantation is performed on each columnar conductive channel to form a source 801 of each transistor in the transistor array.

[0118] Fig. 8A and Figure 8B The method of forming the source electrode may be the same, wherein, Fig. 8A Corresponding to the above embodiment Fig. 7A situation, Figure 8B Corresponding to the above embodiment Figure 7B situation.

[0119] Before forming the source electrode, an etching process is required in the extension direction, such as photolithography, dry etching or wet etching, to expose the end of each columnar conductive channel away from the bottom of the wafer. During the etching process, the gate layer can be etched to a certain depth along the extension direction, and the conductive material on the top of each columnar conductive channel and the insulating layer can be removed. The etching depth is equal to or slightly less than the thickness of each transistor source electrode along the extension direction, so that the area covered by the mask layer is not etched, forming the end of each columnar conductive channel arranged in an array in the same plane away from the bottom of the wafer.

[0120] During ion implantation, the particles to be doped are injected into the end of each columnar conductive channel away from the bottom of the wafer by means of an ion beam. Through a series of physical and chemical interactions, the doped particles gradually lose energy and remain therein, forming the source of each transistor at the end of each columnar conductive channel away from the bottom of the wafer.

[0121] Since the source electrodes are formed in the extending direction of each transistor, the source electrodes of each transistor are located in the same plane, which can simplify the circuit layout design inside the semiconductor device and reduce the process difficulty of manufacturing the semiconductor device.

[0122] In some embodiments, Fig.9A and 9B As shown, at one end of each columnar conductive channel of the transistor array close to the bottom of the wafer, a drain 902 of each transistor in the transistor array is formed simultaneously, including:

[0123] Performing ion implantation on the wafer from the back side of the wafer (not shown in the figure) to form a drain region 901 of the transistor array; wherein the back side of the wafer is the side opposite to the surface of the wafer;

[0124] The drain region 901 is etched to form a drain 902 of each transistor in the transistor array; wherein the drains 902 of each transistor in the transistor array are spaced apart at the bottom of the wafer, that is, the drains 902 of the transistors in the same row are spaced apart, and the drains 902 of the transistors in the same column are spaced apart.

[0125] The wafer surface is the surface on which the first groove and the columnar conductive channel are etched, and the wafer back side is the side opposite to the wafer surface and is also the bottom surface of the bottom of the wafer.

[0126] here, Figures 9A to 9B The process of forming the drain electrode shown in the figure can be applied to the above-mentioned embodiment with Fig. 8A The array structure shown in FIG. A drain electrode can be formed at the substrate portion connected to the bottom of each columnar conductive channel, that is, an ion implantation process is performed from the back of the wafer, and the drain electrodes of each transistor are further separated from each other by etching or other methods.

[0127] like Fig.9A As shown, during the ion implantation process, the particles to be doped are injected into the bottom of the wafer by means of an ion beam. Through a series of physical and chemical interactions, the doped particles gradually lose energy and stay in the material at the bottom of the wafer, doping the entire bottom of the wafer to form the drain region of the transistor array. The drain region is electrically isolated from the gate electrode by the gate oxide layer, which can effectively protect the gate electrode material.

[0128] It should be noted that a wafer backside thinning process can be performed before ion implantation to reduce the thickness of the bottom of the wafer. In addition, the wafer bonding process is implemented by bonding the second wafer to the wafer to be thinned before the wafer backside thinning process and providing support, thereby preventing the wafer to be thinned from being damaged during the thinning process.

[0129] like Fig. 9B As shown, in the column direction of the transistor array, the drain region is etched by photolithography and dry etching processes. During the etching process, a mask can be used to cover one end of each columnar conductive channel close to the bottom of the wafer, that is, the area where the drain of each transistor needs to be formed, and then the drain region is etched. Outside the area covered by the mask, a portion of the drain region is etched away, and a certain depth is etched along the extension direction to remove the portion of the gate oxide layer. In this way, the drain of each transistor in the transistor array is formed on the area covered by the mask. Among them, the drains of each transistor are located in the same plane and are spaced apart in the row and column directions.

[0130] In some embodiments, Fig. 10A and 10B As shown, at one end of each columnar conductive channel of the transistor array close to the bottom of the wafer, a drain 1002 of each transistor in the transistor array is formed simultaneously, including:

[0131] The wafer is thinned from the back side of the wafer (not shown in the figure) to expose an end of the columnar conductive channel close to the bottom of the wafer; wherein the back side of the wafer is the side opposite to the surface of the wafer;

[0132] Ion implantation is performed on one end of each of the columnar conductive channels close to the bottom of the wafer to form a drain 1002 of each transistor in the transistor array.

[0133] Different from the above Figures 9A to 9B The method shown here Fig. 10A and 10B Is for Figure 8B The process of further forming a drain electrode based on the array structure shown.

[0134] Here, thinning the back side of the wafer requires removing the interconnected wafer portions under the columnar conductive channels of each transistor, and the thinning method may include physical or chemical methods, such as physical thinning by grinding, or thinning by etching the wafer with corrosive liquid or gas.

[0135] Before the thinning process is performed, the wafer may be subjected to a bonding process, that is, a second wafer is bonded to the wafer to be thinned and provides support, thereby preventing the wafer to be thinned from being damaged during the thinning process.

[0136] In the embodiment of the present application, a chemical mechanical polishing process is used to perform thinning and planarization on the back side of the wafer to expose one end of each columnar conductive channel close to the bottom of the wafer.

[0137] During ion implantation, the particles to be doped can be injected into the end of each columnar conductive channel close to the bottom of the wafer by means of an ion beam. Through a series of physical or chemical interactions, the doped particles will gradually lose energy and remain therein, forming the drain of each transistor at the end of each columnar conductive channel close to the bottom of the wafer.

[0138] It should be noted that in the embodiment of the present application, since the drains of each transistor are located in the same plane, they can be uniformly formed through a single ion implantation, thereby simplifying the manufacturing process and improving efficiency.

[0139] In some embodiments, Fig.11A and 11B As shown, the method also includes:

[0140] A metal layer (not shown in the figure) is deposited on the surface of the source 1101 of each transistor in the transistor array; the metal layer is etched to form a bit line 1102 connecting the sources of each transistor in the same row in the transistor array.

[0141] like Fig.11A and 11B As shown, a bit line is formed by depositing a metal layer at a preset bit line position. The material of the deposited metal layer includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al) or other metal materials. The deposition process includes but is not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition or other deposition processes. In the embodiment of the present application, the metal material to be deposited is tungsten, and physical vapor deposition is performed on the source surface of each transistor to deposit tungsten atoms on the source surface in the form of low-pressure gas to form a metal layer.

[0142] In the process of etching the metal layer, a photolithography process or dry etching can be used to cover the metal layer of the source region of each transistor in the same row with a mask, and partially etch the area outside the mask to remove the excess metal layer. After the etching is completed, the area covered by the mask layer is not etched, and a bit line is formed in the same row of the transistor array.

[0143] The present application also provides a semiconductor device, such as Fig.12 As shown, the semiconductor device 1200 includes:

[0144] A transistor array having columnar conductive channels 1201; wherein the extension direction of each of the columnar conductive channels 1201 of the transistor array is perpendicular to the surface of the wafer forming the transistor array;

[0145] Each columnar conductive channel 1201 of the transistor array is surrounded by a gate layer 1202;

[0146] The two ends of the extension direction of the columnar conductive channel 1201 of the transistor array respectively have a source 1203 and a drain 1204 of the transistor.

[0147] In the embodiment of the present application, the gate layer 1202 surrounding the columnar conductive channel 1201 can be used as a word line 1205 of the semiconductor device; the metal layer connecting the source electrodes 1203 of each transistor can be used as a bit line 1206 of the semiconductor device. The word line extends in the column direction of the transistor array, and the bit line extends in the row direction of the transistor array.

[0148] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a transistor array; the method comprises: Forming a columnar conductive channel of a transistor array on a wafer surface; wherein the extension direction of the columnar conductive channel is perpendicular to the wafer surface; A gate layer surrounding each columnar conductive channel of the transistor array is formed synchronously; the gate layer includes a gate oxide layer and a gate electrode; wherein the gate oxide layer is formed by oxidizing the surrounding sidewalls of the columnar conductive channel; After forming the gate layer, forming a source and a drain of a transistor at two ends of the extension direction of the columnar conductive channel of the transistor array respectively, including: Ion implantation is performed on the wafer from the back side of the wafer to form a drain region of the transistor array; the drain region is etched to form drains of each transistor in the transistor array; wherein the drains of each transistor in the transistor array are spaced apart at the bottom of the wafer; or, the wafer is thinned from the back side of the wafer to remove a portion of the wafer connected to each columnar conductive channel and expose an end of the columnar conductive channel close to the bottom of the wafer; ion implantation is performed on an end of each columnar conductive channel close to the bottom of the wafer to form drains of each transistor in the transistor array; The back side of the wafer is the side opposite to the surface of the wafer.

2. The method according to claim 1, characterized in that The columnar conductive channel of the transistor array formed on the surface of the wafer includes: The wafer surface is etched to form an array of columnar conductive channels and first grooves between the columnar conductive channels; wherein the array of columnar conductive channels includes the columnar conductive channels of each transistor in the transistor array.

3. The method according to claim 2, characterized in that The gate layer surrounding each columnar conductive channel of the transistor array is formed synchronously, comprising: Around each columnar conductive channel of the transistor array, the gate oxide layer surrounding the columnar conductive channel is simultaneously formed; The gate electrode surrounding each of the gate oxide layers is simultaneously formed around the gate oxide layers.

4. The method according to claim 3, characterized in that: The gate oxide layer surrounding each columnar conductive channel of the transistor array is formed synchronously, comprising: Depositing an insulating material in the first groove to form an insulating layer; The insulating layer is etched to form a second groove; wherein at least a portion of the surrounding sidewall of the columnar conductive channel of each transistor is exposed in the second groove; The exposed surrounding sidewalls of the columnar conductive channel are oxidized to form the gate oxide layer surrounding the columnar conductive channel.

5. The method according to claim 4, characterized in that The gate electrode surrounding each gate oxide layer is formed synchronously around the gate oxide layer, comprising: A conductive material is deposited in the second groove to form the gate electrode surrounding the gate oxide layer.

6. The method according to claim 5, characterized in that The second groove penetrates the columnar conductive channels in the same column of the transistor array; the conductive materials of the gate electrodes of the transistors in the same column are interconnected, and the interconnected conductive materials are word lines of the transistors in the same column.

7. The method according to claim 1, characterized in that The source and drain of the transistor are respectively formed at both ends of the extension direction of the columnar conductive channel of the transistor array, and further comprises: At one end of each columnar conductive channel of the transistor array away from the bottom of the wafer, the source of each transistor in the transistor array is formed simultaneously.

8. The method according to claim 7, characterized in that The ends of the columnar conductive channels of the transistor array away from the bottom of the wafer are used to simultaneously form the source of each transistor in the transistor array, including: At one end of each columnar conductive channel of the transistor array away from the bottom of the wafer, ion implantation is performed on each columnar conductive channel to form a source of each transistor in the transistor array.

9. The method according to claim 7, characterized in that: The method further comprises: Depositing a metal layer on the source surface of each transistor in the transistor array; The metal layer is etched to form a bit line connecting the sources of the transistors in the same row in the transistor array.

10. A semiconductor device, characterized in that: The manufacturing method according to any one of claims 1 to 9 is used to form the device, comprising: A transistor array having columnar conductive channels; wherein the extension direction of each of the columnar conductive channels of the transistor array is perpendicular to the surface of the wafer forming the transistor array; Each columnar conductive channel of the transistor array is surrounded by a gate layer surrounding the columnar conductive channel; the gate layer includes a gate oxide layer and a gate electrode; wherein the gate oxide layer is formed by oxidizing the surrounding sidewalls of the columnar conductive channel; The two ends of the extension direction of the columnar conductive channel of the transistor array are respectively provided with a source and a drain of the transistor; the drains of the transistors of the transistor array are distributed at intervals.

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