Semiconductor device and manufacturing method thereof
Through the columnar channel structure and metal layer shielding technology, the problems of large transistor array area and word line interference are solved, and semiconductor device manufacturing with high storage density and simplified process is achieved.
Patent Information
- Application Number
- CN202510863051.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-28
- Publication Date
- 2025-10-03
AI Technical Summary
The structure of existing transistor arrays results in a large memory area, complex memory cell wiring, difficult manufacturing process, and interference between adjacent word lines affects device performance.
A columnar channel structure is adopted, with the gate and metal layers distributed along different side walls to form a transistor array perpendicular to the wafer surface. The metal layer is used to shield word line interference, simplifying the manufacturing process.
The area of the transistor array is reduced, the storage density is increased, the difficulty of the manufacturing process is reduced, and the interference effect of the word line on the adjacent channel is reduced, thereby improving the device performance.
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Figure CN120751718A_ABST
Abstract
Description
[0001] Description of the case
[0002] This application is a divisional application of the Chinese patent application with the application date of January 28, 2022, application number 2022101083896, and invention name “A semiconductor device and its manufacturing method”. Technical Field
[0003] The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor device and a method for manufacturing the same. Background Art
[0004] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in dynamic random access memory (DRAM) to control the capacitance of each memory cell, and transistor arrays composed of multiple transistors can be used in semiconductor memory devices.
[0005] Transistor arrays mainly include planar transistor arrays and buried channel transistor arrays. However, both planar transistor arrays and buried channel transistor arrays occupy a large area. Summary of the Invention
[0006] In view of this, the main purpose of this application is to provide a semiconductor device and a manufacturing method thereof.
[0007] To achieve the above objectives, the technical solution of this application is implemented as follows:
[0008] An embodiment of the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a transistor array; the method includes:
[0009] A columnar channel of a transistor array is formed on a wafer surface; wherein the columnar channel extends in a direction perpendicular to the wafer surface; and the columnar channel is distributed in an array along a first direction parallel to the wafer surface and a second direction parallel to the wafer surface;
[0010] forming a gate on a sidewall of each columnar trench of the transistor array, wherein the gate is parallel to the first direction and arranged along the second direction;
[0011] forming a metal layer between adjacent columnar trenches, wherein the metal layer extends along the first direction;
[0012] A source and a drain of a transistor are respectively formed at two ends of the extending direction of each columnar channel of the transistor array.
[0013] In the above solution, the gate and the metal layer are formed simultaneously.
[0014] In the above solution, the columnar trenches of the transistor array formed on the wafer surface include:
[0015] Etching is performed on the wafer surface to form the columnar trenches distributed in an array and first grooves between the columnar trenches.
[0016] In the above solution, the gates on the sidewalls of adjacent columnar trenches are located on different sides.
[0017] In the above solution, the synchronously forming the gate and the metal layer includes:
[0018] depositing an insulating material in the first groove to form an insulating layer surrounding each columnar trench;
[0019] Etching the insulating layer to form a second groove exposing a sidewall of each columnar trench and a third groove located between adjacent columnar trenches; wherein the second grooves of adjacent columnar trenches are located on different sides, and the second groove and the third groove are located on different sides of the columnar trench;
[0020] The second groove and the third groove are filled with metal material to form the gate and the metal layer.
[0021] In the above solution, the gates on the sidewalls of adjacent columnar trenches are located on the same side.
[0022] In the above solution, the synchronously forming the gate and the metal layer includes:
[0023] depositing an insulating material in the first groove to form an insulating layer surrounding each columnar trench;
[0024] Etching the insulating layer to form a second groove exposing a side wall of each columnar trench and a third groove located between adjacent columnar trenches; wherein the second grooves of adjacent columnar trenches are located on the same side, and there is a second groove and a third groove between each adjacent columnar trench;
[0025] The second groove and the third groove are filled with metal material to form the gate and the metal layer.
[0026] In the above solution, before filling the second groove and the third groove with metal material, the method further includes:
[0027] The exposed sidewalls of the columnar trench are oxidized through the second groove to form a gate oxide layer on the sidewalls of the columnar trench.
[0028] In the above solution, the second groove exposes the columnar channels in the same column of the columnar channels distributed in the array; the gates of the columnar channels in the same column are interconnected, and the interconnected gates are word lines of the columnar channels in the same column.
[0029] In the above solution, a bit line is formed, and the bit line is connected to the source or drain of each transistor in the transistor array;
[0030] A storage capacitor is formed, wherein a first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array, and a second electrode of the storage capacitor is connected to a common terminal. The storage capacitor is used to store data written into the semiconductor device.
[0031] In the above solution, the metal layer is connected to the common end.
[0032] In the above solution, the etching depth of the second groove is greater than the etching depth of the third groove.
[0033] In the above solution, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees.
[0034] The present application also provides a semiconductor device, including:
[0035] A transistor array having columnar channels; wherein the columnar channels of the transistor array are distributed in an array along a first direction and a second direction, and the extending direction of the columnar channels is perpendicular to a plane formed by the first direction and the second direction;
[0036] A gate is provided on one sidewall of each columnar channel of the transistor array, wherein the gate extends along the first direction;
[0037] A metal layer is provided between adjacent columnar trenches, wherein the metal layer extends along the first direction;
[0038] The two ends of each columnar channel of the transistor array in the extension direction respectively have a source and a drain of the transistor.
[0039] In the above solution, the length of the metal layer along the extension direction of the columnar channel is smaller than the length of the gate along the extension direction of the columnar channel.
[0040] In the above solution, the gates on the sidewalls of adjacent columnar trenches are located on different sides; the gates and the metal layer are located on different sides of the columnar trenches.
[0041] In the above solution, the gates on the sidewalls of adjacent columnar trenches are located on the same side; and there is a gate and a metal layer between each of the adjacent columnar trenches.
[0042] The above solutions include:
[0043] A bit line connected to a source or a drain of each transistor in the transistor array;
[0044] A storage capacitor, wherein a first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array, a second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store data written into the semiconductor device.
[0045] In the above solution, the metal layer is connected to the common end.
[0046] In the above solution, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees.
[0047] The present invention provides a method for manufacturing a semiconductor device, the semiconductor device including a transistor array; the method comprising: forming a columnar channel of the transistor array on a wafer surface; wherein the columnar channel extends in a direction perpendicular to the wafer surface; the columnar channels are arrayed along a first direction parallel to the wafer surface and a second direction parallel to the wafer surface; forming a gate on a sidewall of each columnar channel of the transistor array, wherein the gate is parallel to the first direction and arranged along the second direction; forming a metal layer between adjacent columnar channels, wherein the metal layer extends in the first direction; and forming a source and a drain of the transistor at both ends of the extension direction of each columnar channel of the transistor array. The present invention provides a semiconductor device and a method for manufacturing the same, wherein the source and drain of the transistor array formed by the manufacturing method are respectively located at both ends along the extension direction of the columnar channel, and the extension direction is perpendicular to the wafer surface, and the gate is located on a sidewall of the columnar channel, thereby greatly reducing the area of the transistor array and improving the storage density of the device. Furthermore, a metal layer is formed between adjacent columnar trenches, and the metal layer can shield the interference caused by the word line on the adjacent columnar trenches. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1A Schematic diagram of the structure of a planar transistor in related art;
[0049] Figure 1B Schematic diagram of the structure of a buried channel transistor in the related art;
[0050] Figure 2 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
[0051] Figure 3 A cross-sectional view of a semiconductor device provided in an embodiment of the present application;
[0052] Figure 4A A schematic diagram of a manufacturing process for a semiconductor device according to an embodiment of the present application;
[0053] Figure 4B A top view of a columnar trench formed according to an embodiment of the present application;
[0054] Figure 4C A three-dimensional diagram of a columnar trench formed according to an embodiment of the present application;
[0055] Figure 4D A top view of an optional insulating layer formed according to an embodiment of the present application;
[0056] Figure 4E A top view of an optional formation of a second groove and a third groove provided in an embodiment of the present application;
[0057] Figure 4F An optional top view of forming a gate oxide layer provided in an embodiment of the present application;
[0058] Figure 4G A top view of an optional formation of a metal layer and a gate provided in an embodiment of the present application;
[0059] Figure 5 A schematic cross-sectional view of an optional semiconductor device provided in an embodiment of the present application;
[0060] Figure 6A A top view of a columnar trench formed according to an embodiment of the present application;
[0061] Figure 6B A top view of an optional insulating layer formed according to an embodiment of the present application;
[0062] Figure 6C A top view of an optional formation of a second groove and a third groove provided in an embodiment of the present application;
[0063] Figure 6D An optional top view of forming a gate oxide layer provided in an embodiment of the present application;
[0064] Figure 6E A top view of an optional formation of a metal layer and a gate provided in an embodiment of the present application;
[0065] Figure 7 A schematic cross-sectional view of an optional semiconductor device provided in an embodiment of the present application;
[0066] Figure 8 An optional top view of forming a lead-out pad provided in an embodiment of the present application;
[0067] Figure 9 Another optional top view of forming a lead-out pad is provided in an embodiment of the present application. DETAILED DESCRIPTION
[0068] The technical solution of the present application will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings show exemplary implementation methods of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.
[0069] The following paragraphs describe the present application in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present application will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present application.
[0070] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0071] In the embodiments of the present application, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent smaller than that of the lower or upper structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface.
[0072] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.
[0073] In the related art, transistor arrays of mainstream memories include planar transistor arrays and buried channel array transistor (BCAT) transistor arrays. However, regardless of whether it is a planar transistor array or a buried channel array, the source and drain are located on both sides of the gate in their structure. Figure 1A is a schematic structural diagram of a planar transistor array in related art. Figure 1B FIG. 1 is a schematic diagram of a buried channel transistor array in related art. Figure 1A and 1BAs shown, the source S and drain D of the transistor in the related art are respectively located on both sides of the horizontal gate G. In this structure, the source and drain occupy different positions, resulting in a larger area for both the planar transistor array and the buried channel transistor array.
[0074] In addition, since the source and drain of the planar transistor array and the buried channel transistor array are located on both sides of the gate, the bit line (BL) and capacitor in the memory cell of the memory are also located on the same side of the gate. In addition, in subsequent processes, it is necessary to realize the connection between the bit line, transistor and capacitor, and the connection between the word line (WL) and transistor, etc., which leads to complex circuit wiring in the memory array area of the memory and greater difficulty in the manufacturing process.
[0075] It should be noted that the number of transistors in the transistor array illustrated in the following embodiments is merely an exemplary description and is not intended to limit the number of transistors in the transistor array of the present application.
[0076] Based on this, a semiconductor device is provided in an embodiment of the present application. Figure 2 , Figure 2 This is a schematic diagram of the structure of the semiconductor device provided in the embodiment of the present application. Figure 2 As shown, the semiconductor device 200 includes a transistor array having columnar channels 211, wherein the columnar channels 211 of the transistor array are arranged in an array along a first direction and a second direction, and the extension direction of the columnar channels is perpendicular to the plane formed by the first direction and the second direction. A gate oxide layer 215 and a gate 214 are provided on one sidewall of each columnar channel of the transistor array, wherein the gate extends along the first direction, and the source 212 and drain 213 of the transistor are provided at both ends of the extension direction of each columnar channel of the transistor array. The transistor array includes transistors 210 arranged in an array. In the embodiment of the present application, the positions of the source 212 and the drain 213 can be interchanged. Here, the X direction is the first direction, and the Y direction is the second direction. The above-mentioned semiconductor device allows the source and drain to be formed at both ends of the columnar channel, thereby avoiding the problem of a large area of the transistor array caused by forming them on both sides of the gate, and can provide a transistor array structure with a smaller area, thereby improving the storage density of the device. However, after further research and analysis of the semiconductor device, the inventors found that when a single-side gate structure is used, the columnar channel CH2 coupled to the unselected word line adjacent to the selected word line is easily affected. This is mainly manifested in that the activity on the adjacent word line can cause the charge in the cell of the unselected word line to change, which poses a risk to the information stored therein. For details, please refer to Figure 3 , Figure 3 for Figure 2As shown in the cross-sectional view of the semiconductor device structure along the AA′ direction, when the selected word line connected to the columnar channel CH1 is active, it will interfere with the adjacent columnar channel CH2, affecting the performance of the device. Therefore, further improvement is needed.
[0077] Based on this, an embodiment of the present application provides a method for manufacturing a semiconductor device. Figure 4A This is a schematic diagram of a process flow for implementing a method for manufacturing a semiconductor device according to an embodiment of the present application. The specific steps of the method for manufacturing a semiconductor device include:
[0078] Step S401: forming columnar channels of a transistor array on a wafer surface; wherein the columnar channels extend in a direction perpendicular to the wafer surface; and the columnar channels are distributed in an array along a first direction parallel to the wafer surface and a second direction parallel to the wafer surface;
[0079] Step S402: forming a gate on a sidewall of each columnar trench of the transistor array, wherein the gate is parallel to the first direction and arranged along the second direction;
[0080] Step S403: forming a metal layer between adjacent columnar trenches, wherein the metal layer extends along the first direction;
[0081] Step S404 : forming a source and a drain of a transistor at two ends of the extension direction of each of the pillar-shaped channels of the transistor array.
[0082] In the embodiments of the present application, a wafer is a silicon wafer formed from cylindrical single-crystal silicon through grinding, polishing, and slicing, used to make semiconductor devices. The wafer has two opposing circular surfaces, one of which is the wafer front surface, while the other circular surface is referred to as the wafer back surface in the embodiments of the present application.
[0083] Figure 4B-4G This is a schematic diagram of a process for manufacturing a semiconductor device provided in an embodiment of the present application. It should be noted that: Figure 4B-4G The gates on the sidewalls of adjacent columnar trenches are located on different sides as an example for description.
[0084] Figure 4B The top view of the columnar trench provided in the embodiment of the present application is as follows: Figure 4BAs shown, an embodiment of the present application forms an array of columnar channels 401 distributed on the surface of the wafer. The channels are used to transfer charge or stop the transfer of charge under the action of an external electric field, so that the transistor is turned on or off. And the extension direction of each columnar channel is perpendicular to the wafer surface. Here, the extension direction of the columnar channel is the direction of current when the transistor is turned on. The columnar channels 401 are distributed in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer. Here, the X direction is the first direction and the Y direction is the second direction.
[0085] In some embodiments, forming a columnar trench of a transistor array on a wafer surface includes:
[0086] The wafer surface is etched to form the columnar trenches distributed in an array and first grooves 402 between the columnar trenches.
[0087] Here, the wafer surface can be etched using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching or reactive ion etching, which is not limited in the embodiments of the present application.
[0088] Figure 4C A three-dimensional diagram of a columnar conductive channel provided in an embodiment of the present application, such as Figure 4B and 4C As shown, during the etching process of the wafer surface, a mask (not shown) can be used to cover part of the wafer surface, i.e., the areas where the columnar trenches 401 need to be formed. The wafer surface is then etched, and a portion of the semiconductor material on the wafer is etched away outside the areas covered by the mask, forming a groove of a certain depth, i.e., the above-mentioned first groove 402.
[0089] The etching depth is less than the initial thickness of the wafer, that is, the etching process will not etch through the wafer. In this way, the area covered by the mask is not etched, and columnar channels 401 are formed in an array on the remaining part of the wafer after etching, and the side walls of the columnar channels 401 are exposed in the above-mentioned first groove 402.
[0090] In addition, the cross-section of the columnar channel 401 may be circular, rectangular, diamond-shaped, polygonal, etc., which is not limited in the embodiment of the present application.
[0091] In the embodiment of the present application, by etching the entire wafer surface, an array of columnar trenches 401 and first grooves 402 having the same depth are simultaneously formed, which can simplify the manufacturing process and improve efficiency.
[0092] In some embodiments, Figures 4D to 4GA top view of the gate and metal layers formed simultaneously for each columnar channel of the transistor array, as shown in FIG. Figures 4D to 4G As shown, the synchronous formation of the gate and the metal layer includes:
[0093] Depositing an insulating material 403 in the first groove 402 to form an insulating layer surrounding each columnar trench;
[0094] The insulating layer is etched to form a second groove 404 exposing a side wall of each columnar trench and a third groove 405 located between adjacent columnar trenches; wherein the second grooves 404 of adjacent columnar trenches are located on different sides, and the second grooves 404 and the third grooves 405 are located on different sides of the columnar trench 401. For details, please refer to Figure 4E ;
[0095] like Figure 4F As shown, the exposed sidewalls of the columnar channel 401 are oxidized through the second groove 404, and a gate oxide layer 406 is formed on the sidewalls of the columnar channel 401. The process of oxidizing the sidewalls of the columnar channel exposed in the second groove includes but is not limited to: direct oxidation, alkaline oxidation or acidic oxidation. In the embodiment of the present application, direct oxidation is performed by heating, so that the silicon on the sidewalls of the columnar channel reacts chemically with the gas containing the oxidizing substance at high temperature, thereby producing a dense silicon dioxide film on the silicon surface, forming a gate oxide layer 406 on the sidewalls of the columnar channel. The gate oxide layer 406 is an insulating material, for example, silicon dioxide (SiO2), and the gate oxide layer 406 is located between the columnar channel 401 and the gate 407 for electrical isolation to prevent the gate from directly contacting the columnar channel to cause charge leakage.
[0096] like Figure 4G As shown, a metal material is filled into the second groove 404 and the third groove 405 to form the gate 407 and the metal layer 408. The metal material used for the filling includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other metal materials. In a preferred embodiment, the metal material is tungsten.
[0097] In the embodiment of the present application, the insulating material may be silicon dioxide or other insulating materials. Figure 4D A top view of depositing insulating material in a first groove provided in an embodiment of the present application, such as Figure 4D As shown, each columnar trench 401 is surrounded by an insulating material SiO2.
[0098] It should be noted that during the actual deposition of the insulating material, the insulating material SiO2 will cover the surface of the columnar trench 401. Usually, after the deposition is completed, a chemical mechanical polishing (CMP) process is used to polish away excess insulating material SiO2 to expose the surface of the columnar trench 401.
[0099] In the embodiments of the present application, a metal layer is formed simultaneously with the gate formation process, thereby eliminating the need for additional process steps to form a metal layer to shield word lines from interfering with adjacent pillar-shaped channels. Thus, without adding additional process steps, the metal layer reduces interference from word lines with adjacent pillar-shaped channels. This improves the coupling effect between word lines and adjacent pillar-shaped channels.
[0100] In the examples of this application, please refer to Figure 4G , the gates on the sidewalls of adjacent columnar channels are located on different sides.
[0101] In the embodiments of this application, Figure 4E As shown, the second groove 402 exposes the columnar channels 401 in the same column of the arrayed columnar channels. The gates of the columnar channels in the same column are interconnected, and the interconnected gates serve as word lines for the columnar channels in the same column. The word lines can provide word line voltages and control the conduction or cutoff of the transistors through the word line voltages.
[0102] In some embodiments, a bit line is formed that is connected to the source or drain of each transistor in the transistor array; a storage capacitor is formed, wherein a first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array, and a second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store data written to the semiconductor device. Here, the common terminal can be connected to a low voltage terminal, and the low voltage can be -0.5V. In some embodiments, the common terminal can also be a ground terminal.
[0103] In some embodiments, the metal layer is connected to a common terminal. In practical applications, the metal layer can be configured to be powered independently and not connected to the common terminal as required. In the embodiments of the present application, a low voltage is applied to the metal layer or the metal layer is grounded so that the metal layer can shield the interference of the word line on the adjacent columnar channel.
[0104] In an embodiment of the present application, the etching depth of the second groove 404 is greater than the etching depth of the third groove 405. The etching depth can be controlled by etching process parameters (for example, etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, when the etching rate is constant, the longer the etching time, the deeper the groove formed in the third direction. In one embodiment of the present application, the etching depth of the second groove 404 can be controlled to be greater than the etching depth of the third groove 405 by adjusting the etching process parameters. The etching method can be dry etching, and the dry etching can be, for example, plasma etching.
[0105] In some embodiments, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees.
[0106] Figure 5 Shown by Figure 4A The cross-sectional structure diagram of the semiconductor device formed by the manufacturing method shown is shown. Figure 5 As shown, the semiconductor device includes: a transistor array having columnar channels 501; wherein the columnar channels of the transistor array are arranged in an array along a first direction and a second direction, and the extension direction of the columnar channels is perpendicular to the plane formed by the first and second directions; a gate 507 is provided on a sidewall of each columnar channel of the transistor array, wherein the gate extends along the first direction; a metal layer 508 is provided between adjacent columnar channels, wherein the metal layer 508 extends along the first direction; and a source 504 and a drain 503 of the transistor are provided at both ends of the extension direction of each columnar channel 501 of the transistor array. Here, the metal layer 508 and the gate 507 are parallel.
[0107] In some embodiments, see Figure 5 The length of the metal layer 508 along the extension direction of the columnar channel is less than the length of the gate along the extension direction of the columnar channel 501. These lengths can be controlled by adjusting the etching depths of the third and second grooves. Etching process parameters include, but are not limited to, etching time, etchant gas flow rate, ratio, pressure, temperature, and the like. In a preferred embodiment, the process parameters are adjusted so that the length of the formed metal layer 508 along the extension direction of the columnar channel 501 is greater than or equal to one-third of the length of the gate 507 along the extension direction of the columnar channel 501.
[0108] In some embodiments, see Figure 5The gates on the sidewalls of adjacent columnar channels 501 are located on different sides; the gates and the metal layer 508 are located on different sides of the columnar channels, wherein the gate oxide layer 506 is located between the columnar channels 501 and the gate 507 for electrical isolation to prevent charge leakage caused by direct contact between the gate and the columnar channels.
[0109] In some embodiments, the semiconductor device includes: a bit line connected to the source or drain of each transistor in the transistor array; a storage capacitor, a first electrode of the storage capacitor connected to the drain or source of each transistor in the transistor array through a storage capacitor contact, and a second electrode of the storage capacitor connected to a common terminal, and the storage capacitor is used to store data written into the semiconductor device.
[0110] See also Figure 5 In a specific embodiment, the bit line 510 is connected to the source of each transistor in the transistor array; the first electrode of the storage capacitor 509 is connected to the drain 503 of each transistor in the transistor array through the storage capacitor contact 505, and the second electrode of the storage capacitor 509 is connected to the common terminal (not shown in the figure). The storage capacitor 509 is used to store data written into the semiconductor device.
[0111] In some embodiments, the metal layer 508 is connected to a common terminal, and a voltage is applied to the metal layer through the common terminal. In practical applications, the metal layer can also be set to be powered separately without being connected to the common terminal according to actual needs.
[0112] In some embodiments, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees.
[0113] Figures 6A-6E This is a schematic diagram of a process of another method for manufacturing a semiconductor device provided in an embodiment of the present application. It should be noted that: Figures 6A-6E The gates on the sidewalls of adjacent columnar trenches are located on the same side as an example for description.
[0114] Figure 6A The top view of the columnar trench provided in the embodiment of the present application is as follows: Figure 6AAs shown, an embodiment of the present application forms an array of columnar channels 601 distributed on the surface of the wafer. The channels are used to transfer charges or stop the transfer of charges under the action of an external electric field, so that the transistor is turned on or off. And the extension direction of each columnar channel is perpendicular to the wafer surface. Here, the extension direction of the columnar channel is the direction of current when the transistor is turned on. The columnar channels 601 are distributed in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer. Here, the X direction is the first direction, and the Y direction is the second direction. In some embodiments, the columnar channels that form the transistor array on the surface of the wafer include:
[0115] The wafer surface is etched to form the columnar trenches 601 distributed in an array and the first grooves 602 between the columnar trenches.
[0116] Here, the wafer surface can be etched using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching or reactive ion etching, which is not limited in the embodiments of the present application.
[0117] In the embodiments of the present application, a metal layer is formed simultaneously with the gate formation process, thereby eliminating the need for additional process steps to form a metal layer to shield word lines from interfering with adjacent pillar-shaped channels. Thus, without adding additional process steps, the metal layer reduces interference from word lines with adjacent pillar-shaped channels. This improves the coupling effect between word lines and adjacent pillar-shaped channels.
[0118] like Figure 6A As shown, during the etching process of the wafer surface, a mask (not shown) can be used to cover part of the wafer surface, i.e., the areas where the columnar trenches 601 need to be formed. The wafer surface is then etched, and a portion of the semiconductor material on the wafer is etched away outside the areas covered by the mask, forming a groove of a certain depth, i.e., the above-mentioned first groove 602.
[0119] In addition, the cross-section of the columnar channel 601 may be circular, rectangular, diamond-shaped, polygonal, etc., which is not limited in the embodiment of the present application.
[0120] In the embodiment of the present application, by etching the entire wafer surface, an array of columnar trenches 601 and first grooves 602 having the same depth are simultaneously formed, which can simplify the manufacturing process and improve efficiency.
[0121] In some embodiments, Figures 6B to 6E A top view of the gate and metal layers formed simultaneously for each columnar channel of the transistor array, as shown in FIG. Figures 6B to 6E As shown, the synchronous formation of the gate and the metal layer includes:
[0122] Depositing an insulating material 603 in the first groove 602 to form an insulating layer surrounding each columnar trench;
[0123] The insulating layer is etched to form a second groove 604 exposing a side wall of each columnar trench and a third groove 605 located between adjacent columnar trenches; wherein the second grooves 604 of adjacent columnar trenches are located on the same side, and there is a second groove 604 and a third groove 605 between each adjacent columnar trench. For details, please refer to Figure 6C ;
[0124] like Figure 6D As shown, the exposed sidewalls of the columnar channel 601 are oxidized by the second groove 604, and a gate oxide layer 606 is formed on the sidewalls of the columnar channel 601. The process of oxidizing the sidewalls of the columnar channel exposed in the second groove includes but is not limited to: direct oxidation, alkaline oxidation or acidic oxidation. In the embodiment of the present application, direct oxidation is performed by heating, so that the silicon on the sidewalls of the columnar channel reacts chemically with the gas containing the oxidizing substance at high temperature, thereby producing a dense silicon dioxide film on the silicon surface, forming a gate oxide layer 606 on the sidewalls of the columnar channel. The gate oxide layer 606 is an insulating material, for example, silicon dioxide (SiO2), and the gate oxide layer 606 is located between the columnar channel 601 and the gate 607 for electrical isolation to prevent the gate from directly contacting the columnar channel to cause charge leakage.
[0125] like Figure 6E As shown, a metal material is filled into the second groove 604 and the third groove 605 to form the gate 607 and the metal layer 608. The metal material used for the filling includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other metal materials. In a preferred embodiment, the metal material is tungsten. In the embodiment of the present application, the insulating material may be silicon dioxide or other insulating materials. Figure 6B A schematic diagram of a top view of the structure of depositing insulating material in the first groove provided in an embodiment of the present application is shown in FIG. Figure 6B As shown, each columnar trench 601 is surrounded by an insulating material SiO2.
[0126] It should be noted that during the actual deposition of the insulating material, the insulating material SiO2 will cover the surface of the columnar trench 601. Usually, after the deposition is completed, a chemical mechanical polishing (CMP) process is used to polish away excess insulating material SiO2 to expose the surface of the columnar trench 601.
[0127] In the examples of this application, please refer to Figure 6E , the gates on the sidewalls of adjacent columnar channels are located on the same side.
[0128] In the embodiments of this application, Figure 6C As shown, the second groove 604 exposes the columnar channels 601 in the same column of the arrayed columnar channels. The gates of the columnar channels in the same column are interconnected, and the interconnected gates serve as word lines for the columnar channels in the same column. The word lines can provide word line voltages and control the conduction or cutoff of each transistor through the word line voltages.
[0129] In some embodiments, a bit line is formed that is connected to the source or drain of each transistor in the transistor array; a storage capacitor is formed, wherein a first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array, and a second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store data written to the semiconductor device. Here, the common terminal can be connected to a low voltage terminal, and the low voltage can be -0.5V. In some embodiments, the common terminal can also be a ground terminal.
[0130] In some embodiments, the metal layer is connected to the common terminal. In practical applications, the metal layer can be set to be powered separately without being connected to the common terminal according to needs.
[0131] In an embodiment of the present application, the etching depth of the second groove 604 is greater than the etching depth of the third groove 605. The etching depth can be controlled by etching process parameters (for example, etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, when the etching rate is constant, the longer the etching time, the deeper the groove formed in the third direction. In one embodiment of the present application, the etching depth of the second groove 604 can be controlled to be greater than the etching depth of the third groove 605 by adjusting the etching process parameters. The etching method can be dry etching, and the dry etching can be, for example, plasma etching.
[0132] In some embodiments, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees.
[0133] Figure 7 Shown by Figure 4A FIG. 1 is a schematic cross-sectional view of another semiconductor device formed by the manufacturing method shown. Figure 7As shown, the semiconductor device includes: a transistor array having columnar channels 701; wherein the columnar channels of the transistor array are arranged in an array along a first direction and a second direction, and the extension direction of the columnar channels is perpendicular to the plane formed by the first and second directions; a gate 707 is provided on a sidewall of each columnar channel of the transistor array, wherein the gate extends along the first direction; a metal layer 708 is provided between adjacent columnar channels, wherein the metal layer 708 extends along the first direction; and a source 704 and a drain 703 of the transistor are provided at both ends of the extension direction of each columnar channel 701 of the transistor array. Here, the metal layer 708 and the gate 707 are parallel.
[0134] In some embodiments, see Figure 7 The length of the metal layer 708 along the extension direction of the columnar channel is less than the length of the gate along the extension direction of the columnar channel 701. This length can be controlled by adjusting the etching depth of the third and second grooves. Etching process parameters include, but are not limited to, etching time, etchant gas flow rate, ratio, pressure, temperature, etc. In a preferred embodiment, the process parameters are adjusted so that the length of the formed metal layer 708 along the extension direction of the columnar channel 701 is greater than or equal to one-third of the length of the gate 707 along the extension direction of the columnar channel 701.
[0135] In some embodiments, see Figure 7 The gates 707 on the sidewalls of adjacent columnar channels 701 are located on the same side; there is a gate 707 and a metal layer 708 between each adjacent columnar channel 701, wherein the gate oxide layer 506 is located between the columnar channel 501 and the gate 507 for electrical isolation to avoid charge leakage caused by direct contact between the gate and the columnar channel.
[0136] In some embodiments, the semiconductor device further includes: a bit line connected to the source or drain of each transistor in the transistor array; a storage capacitor, a first electrode of the storage capacitor connected to the drain or source of each transistor in the transistor array through a storage capacitor contact, and a second electrode of the storage capacitor connected to a common terminal, and the storage capacitor is used to store data written into the semiconductor device.
[0137] In some embodiments, there is an angle between the first direction and the second direction, and the angle range is: less than or equal to 90 degrees.
[0138] See also Figure 7In a specific embodiment, the bit line 710 is connected to the source of each transistor in the transistor array; the first electrode of the storage capacitor 709 is connected to the drain 703 of each transistor in the transistor array through the storage capacitor contact 705, and the second electrode of the storage capacitor 709 is connected to the common terminal (not shown in the figure). The storage capacitor 709 is used to store data written into the semiconductor device.
[0139] In some embodiments, the metal layer 708 is connected to the common terminal. The metal layer can be buried at a suitable location to connect to the common terminal, and a voltage is applied to the metal layer through the common terminal. In actual applications, the metal layer can also be set to be powered separately without being connected to the common terminal according to actual needs.
[0140] Figure 8 An optional top view of forming a lead pad is provided in an embodiment of the present application, wherein the bit line 810 is connected to the source or drain of each transistor in the transistor array, as shown in FIG. Figure 8 As shown, when the distance between the word line and the metal layer is small, the lead-out pad 802 of the metal layer and the lead-out pad 801 of the word line need to be staggered (set on different sides) to avoid short circuit between the word line and the metal layer, while reducing the device size and improving space utilization.
[0141] Figure 9 Another optional top view of forming a lead pad is provided in an embodiment of the present application, wherein the bit line 910 is connected to the source or drain of each transistor in the transistor array, as shown in FIG. Figure 9 As shown, when the distance between the word line and the metal layer allows, the lead-out pad 902 of the metal layer and the lead-out pad 901 of the word line can be arranged on the same side, which is convenient for actual control.
[0142] The present application provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device includes a transistor array; the method comprises: forming a columnar channel of the transistor array on a wafer surface; wherein the columnar channel extends in a direction perpendicular to the wafer surface; the columnar channels are arrayed along a first direction parallel to the wafer surface and a second direction parallel to the wafer surface; forming a gate on a sidewall of each columnar channel of the transistor array, wherein the gate is parallel to the first direction and arranged along the second direction; forming a metal layer between adjacent columnar channels, wherein the metal layer extends in the first direction; and forming a source and a drain of the transistor at both ends of the extension direction of each columnar channel of the transistor array. Through an embodiment of the present application, a semiconductor device and a manufacturing method thereof are provided, wherein the source and drain of the transistor array formed by the manufacturing method are respectively located at both ends of the extension direction of the columnar channel, and the extension direction is perpendicular to the wafer surface, and the gate is located on a sidewall of the columnar channel, thereby greatly reducing the area of the transistor array and improving the storage density of the device. Furthermore, a metal layer is formed between adjacent columnar trenches, and the metal layer can shield the interference caused by the word line on the adjacent columnar trenches.
[0143] It should be understood that “one embodiment” or “some embodiments” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, “in one embodiment” or “in some embodiments” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.
[0144] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.
Claims
1. A semiconductor device, characterized in that: include: A first transistor comprising a first semiconductor pillar extending along a first direction and a first gate located on one side of the first semiconductor pillar along a second direction, wherein the first direction is perpendicular to the second direction; a second transistor, arranged adjacent to the first transistor along the second direction, comprising a second semiconductor column extending along the first direction; a metal layer, the metal layer being located between the first semiconductor pillar and the second semiconductor pillar along the second direction, and the first semiconductor pillar being located between the metal layer and the first gate along the second direction; wherein, A length of the metal layer along the first direction is smaller than a length of the first gate along the first direction.
2. The semiconductor device according to claim 1, wherein The second transistor includes a second gate located at one side of the second semiconductor pillar along the second direction, and the second semiconductor pillar is located between the metal layer and the second gate.
3. The semiconductor device according to claim 2, wherein The first semiconductor pillar and the second semiconductor pillar are both located between the first gate and the second gate.
4. The semiconductor device according to claim 1, wherein The second transistor includes a second gate located at one side of the second semiconductor pillar along the second direction, and the second gate is located between the second semiconductor pillar and the metal layer.
5. The semiconductor device according to claim 4, wherein The second gate and the metal layer are located between the first semiconductor pillar and the second semiconductor pillar.
6. The semiconductor device according to claim 4, wherein An insulating layer is provided between the second gate and the metal layer.
7. The semiconductor device according to claim 1, wherein The first gate extends along a third direction, and the metal layer extends along the third direction. The third direction is perpendicular to the first direction and intersects with the second direction.
8. The semiconductor device according to claim 1, wherein include: a bit line connecting one end of the first semiconductor pillar along the first direction and one end of the second semiconductor pillar along the first direction; a first storage capacitor connected to the other end of the first semiconductor column along the first direction; A second storage capacitor is connected to the other end of the second semiconductor column along the first direction.
9. The semiconductor device according to claim 1, wherein The metal layer is connected to the voltage input terminal.
10. The semiconductor device according to claim 1, wherein An insulating layer is disposed between the first semiconductor column and the second semiconductor column, and the metal layer is disposed in the insulating layer.
11. A semiconductor device, characterized in that: include: A transistor array having columnar channels; wherein the columnar channels of the transistor array are distributed in an array along a first direction and a second direction, and the extending direction of the columnar channels is perpendicular to a plane formed by the first direction and the second direction; A gate is provided on the sidewall of each columnar channel of the transistor array; A metal layer is provided between adjacent columnar trenches, and the metal layer extends along the first direction; A storage capacitor, wherein a first electrode of the storage capacitor is connected to one end of a transistor in the transistor array, and a second electrode of the storage capacitor is connected to a common end.
12. The semiconductor device according to claim 11, wherein The metal layer and the gate are arranged along the second direction.
13. The semiconductor device according to claim 11, wherein A length of the metal layer along an extending direction of the columnar channel is shorter than a length of the gate along the extending direction of the columnar channel.
14. The semiconductor device according to claim 11, wherein The metal layer is connected to the common terminal.
15. A method for manufacturing a semiconductor device, characterized in that: include: forming a first transistor, the first transistor including a first semiconductor pillar extending along a first direction and a first gate located on one side of the first semiconductor pillar along a second direction, the first direction being perpendicular to the second direction; forming a second transistor, the second transistor being arranged adjacent to the first transistor along the second direction and comprising a second semiconductor column extending along the first direction; A metal layer is formed, wherein the metal layer is located between the first semiconductor pillar and the second semiconductor pillar along the second direction, and the first semiconductor pillar is located between the metal layer and the first gate along the second direction; wherein, A length of the metal layer along the first direction is smaller than a length of the first gate along the first direction.
16. The method for manufacturing a semiconductor device according to claim 15, wherein: The forming of the first transistor and the forming of the second transistor include: forming a first groove extending along the second direction and a second groove extending along the third direction on the surface of the wafer to form the first semiconductor column and the second semiconductor column, wherein the second direction intersects the third direction; The first gate is formed in the second groove.
17. The method for manufacturing a semiconductor device according to claim 16, wherein: The forming of the first gate in the second groove includes: forming an insulating layer in the second groove; Etching the insulating layer to form a third groove exposing a side wall of the first semiconductor column; performing oxidation treatment on the exposed sidewall of the first semiconductor column through the third groove to form a gate oxide layer; The first gate is formed on one side of the gate oxide layer in the third groove.
18. The method for manufacturing a semiconductor device according to claim 16, wherein: The forming of the metal layer comprises: The metal layer is formed in the second groove.
19. The method for manufacturing a semiconductor device according to claim 16, wherein: The forming of the second transistor includes: A second gate of the second transistor is formed in the second groove, and the second semiconductor pillar is located between the metal layer and the second gate.
20. The method for manufacturing a semiconductor device according to claim 16, wherein: The forming of the second transistor includes: A second gate of the second transistor is formed in the second groove, and the second gate is located between the second semiconductor pillar and the metal layer.