Thin film transistor array substrate, manufacturing method thereof, repairing method and display panel

Abstract

A thin film transistor array substrate, a manufacturing method and a repairing method thereof, and a display panel are disclosed. The manufacturing method comprises: forming a gate and a bottom layer reserved metal pattern which are spaced apart from each other on a substrate; forming a gate insulating layer; forming an active layer and a semiconductor bridge pattern which are spaced apart from each other on the gate insulating layer; performing ion doping on the semiconductor bridge pattern, so that the semiconductor bridge pattern is changed from a semiconductor to a conductor to form a conductor bridge pattern; forming an etching stop layer; and forming a source, a drain and a data line on the etching stop layer, wherein the conductor bridge pattern is arranged below the data line and in an opening area of a pixel unit, the bottom layer reserved metal pattern is arranged below the data line, and the bottom layer reserved metal pattern is located in an area where the conductor bridge pattern is arranged. According to the embodiment of the present application, the bottom layer reserved metal pattern, the data line and the conductor bridge pattern are fused together, so that the line break repairing of the data line can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a thin film transistor array substrate, a manufacturing method, a repairing method and a display panel. BACKGROUND

[0002] Liquid crystal display panels have the advantages of good picture quality, small volume, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and thus dominate the field of flat panel display.

[0003] A pixel unit of a liquid crystal display panel is generally formed by intersecting a data line and a gate line, and both the data line and the gate line are metal layers. If the line width is too wide, the aperture ratio of the pixel unit will be affected. With the increasing resolution of products, in particular, the line width of the data line is becoming thinner and thinner. Therefore, the problem of broken line is prone to occur in the production process, which affects the yield of products.

[0004] The prior art adopts a line repair circuit to realize broken line repair through a reserved line repair circuit. The current technology has the following disadvantages:

[0005] 1. The number of repairs is limited, and usually one panel can repair one or several lines.

[0006] 2. Because the repair circuit is a redundant design, the wire length is long, the RC loading is large, and a power amplifier integrated circuit is generally used in combination, which increases the product cost.

[0007] 3. The repair redundant circuit is complex, which increases the layout area and is not conducive to reducing the frame size. SUMMARY

[0008] The present application aims to provide a thin film transistor array substrate, a manufacturing method, a repairing method and a display panel, which can repair the broken line of the data line and avoid yield loss.

[0009] The present application provides a thin film transistor array substrate, comprising:

[0010] a substrate;

[0011] a gate and a bottom layer reserved metal pattern formed by etching and patterning a first metal layer and spaced apart from each other on the substrate;

[0012] a gate insulating layer covering the gate and the bottom layer reserved metal pattern;

[0013] active layers and a semiconductor bridge pattern formed by etching patterning of an oxide semiconductor thin film and spaced apart from each other, wherein the active layer is located above the gate electrode, and the semiconductor bridge pattern is formed into a conductor bridge pattern by being ion doped and turned from a semiconductor into a conductor;

[0014] an etching barrier layer located on the active layer and the conductor bridge pattern;

[0015] a source electrode, a drain electrode and a data line formed by etching patterning of a second metal layer and located on the etching barrier layer, wherein the source electrode and the drain electrode are spaced apart from each other and are both electrically connected with the active layer, the source electrode is electrically connected with the data line, the conductor bridge pattern is arranged below the data line and in the opening area of the pixel unit, the bottom layer reserved metal pattern is arranged below the data line, and the bottom layer reserved metal pattern is located in the area where the conductor bridge pattern is located.

[0016] Further, the conductor bridge pattern extends along the direction of the data line, and the conductor bridge pattern extends into the opening area of the adjacent two pixel units on both sides respectively, the length of the conductor bridge pattern along the direction of the data line is close to the length of the opening area of a single pixel unit, at least two bottom layer reserved metal patterns are arranged in the area where the conductor bridge pattern is located, and the two bottom layer reserved metal patterns are located at the positions of the two ends of the conductor bridge pattern along the direction of the data line respectively.

[0017] Further, the conductor bridge pattern forms a through hole at the position corresponding to each bottom layer reserved metal pattern, and the etching barrier layer located above fills the through hole.

[0018] Further, the width of the data line is greater than the width of the bottom layer reserved metal pattern, the data line completely covers the bottom layer reserved metal pattern, and the width of the bottom layer reserved metal pattern is greater than the width of the through hole, the through hole falls into the area where the bottom layer reserved metal pattern is located, and the through hole and the bottom layer reserved metal pattern are vertically and centrally aligned.

[0019] The embodiment of the present application also provides a manufacturing method of a thin film transistor array substrate, comprising:

[0020] forming a first metal layer on a substrate, and etching and patterning the first metal layer to form a gate electrode and a bottom layer reserved metal pattern spaced apart from each other;

[0021] forming a gate insulating layer covering the gate electrode and the bottom layer reserved metal pattern;

[0022] forming an oxide semiconductor thin film on the gate insulating layer, and etching and patterning the oxide semiconductor thin film to form active layers and a semiconductor bridge pattern spaced apart from each other, wherein the active layers are located above the gate electrode;

[0023] ion-doping the semiconductor bridge pattern to change the semiconductor bridge pattern from a semiconductor to a conductor to form a conductor bridge pattern;

[0024] forming an etching stop layer on the active layers and the conductor bridge pattern;

[0025] forming a second metal layer on the etching stop layer, and etching and patterning the second metal layer to form a source electrode, a drain electrode and a data line, wherein the source electrode and the drain electrode are spaced apart from each other and are electrically connected to the active layers, the source electrode is electrically connected to the data line, the conductor bridge pattern is arranged below the data line and in an opening region of a pixel unit, the bottom layer reserved metal pattern is arranged below the data line, and the bottom layer reserved metal pattern is located in a region where the conductor bridge pattern is located.

[0026] Further, the etching and patterning of the oxide semiconductor thin film includes:

[0027] coating a photoresist layer on the oxide semiconductor thin film;

[0028] exposing and developing the photoresist layer using a half-tone mask to leave a first photoresist pattern and a second photoresist pattern on the photoresist layer, and other areas without photoresist are exposed to the oxide semiconductor thin film, wherein the first photoresist pattern corresponds to the position of the active layer, the second photoresist pattern corresponds to the position of the semiconductor bridge pattern, and the thickness of the first photoresist pattern is greater than the thickness of the second photoresist pattern;

[0029] etching the oxide semiconductor thin film to remove the exposed oxide semiconductor thin film, so that the oxide semiconductor thin film forms the active layers and the semiconductor bridge pattern after etching;

[0030] removing the second photoresist pattern by photoresist ashing to expose the semiconductor bridge pattern, so as to ion-dope the semiconductor bridge pattern, and removing the first photoresist pattern after ion-doping the semiconductor bridge pattern.

[0031] Further, the conductor bridging pattern extends along the data line direction, and two sides of the conductor bridging pattern respectively extend into the opening region of two adjacent pixel units, the length of the conductor bridging pattern along the data line direction is close to the length of the opening region of a single pixel unit, at least two bottom layer reserved metal patterns are arranged in the area where the conductor bridging pattern is located, and the two bottom layer reserved metal patterns are respectively located at the two end positions of the conductor bridging pattern along the data line direction.

[0032] Further, the conductor bridging pattern is formed with a via hole at a position corresponding to each bottom layer reserved metal pattern, the via hole is simultaneously formed when etching the oxide semiconductor thin film, and the etching stop layer above fills the via hole.

[0033] The embodiment of the present application also provides a repairing method for the thin film transistor array substrate.

[0034] When the data line is broken, the bottom layer reserved metal pattern, the data line and the conductor bridging pattern are fused together by laser, and the broken data line is conducted through the conductor bridging pattern.

[0035] The embodiment of the present application also provides a display panel comprising the thin film transistor array substrate.

[0036] The thin film transistor array substrate and the manufacturing method thereof provided by the embodiment of the present application have the following advantages when the data line of the array substrate is broken and needs to be repaired:

[0037] 1. The number of repairable data lines is not limited, and the yield can be maximized;

[0038] 2. No redundant data line repair circuit needs to be designed, no power amplifier integrated circuit needs to be added, and no cost is increased;

[0039] 3. No redundant data line repair circuit needs to be designed, which is beneficial to realize a narrow frame.

[0040] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, the following preferred embodiments are described in detail in combination with the drawings, and the other purposes, features and advantages of the present application can be more obvious and easy to understand. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 It is a partial structure plan view of the thin film transistor array substrate in the preferred embodiment of the present application.

[0042] Figure 2 It is a partial structure plan view of the thin film transistor array substrate in the preferred embodiment of the present application. Figure 1 It is a cross-sectional view along the II-II line position.

[0043] Figure 3 For Figure 1 The cross-sectional view along the position of line II-II.

[0044] Figures 4a to 4h For Figure 1 The cross-sectional view along the position of line II-II.

[0045] Figures 5a to 5i For Figure 1 The cross-sectional view along the position of line III-III. DETAILED DESCRIPTION

[0046] To further clarify the technical means and effects taken by the present application to achieve the predetermined purposes, the following describes the specific embodiments, structures, features and effects of the present application in detail in combination with the preferred embodiments and the drawings:

[0047] The foregoing and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of the preferred embodiments in combination with the drawings. Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be understood more deeply and specifically. However, the drawings are provided for reference and illustration only, and are not intended to limit the present application.

[0048] Figure 1 The cross-sectional view along the position of line II-II. Figure 2 For Figure 1 The cross-sectional view along the position of line II-II. Figure 3 For Figure 1 The cross-sectional view along the position of line III-III. Please refer to Figures 1 to 3 The thin film transistor array substrate provided in the preferred embodiments of the present application comprises:

[0049] A substrate 10;

[0050] A plurality of mutually spaced apart gate electrodes 21, a bottom layer reserved metal pattern 22 and a plurality of gate lines 23 formed on the substrate 10 by etching and patterning of the first metal layer 20, wherein the plurality of gate lines 23 extend along a first direction;

[0051] A gate insulating layer 30 covering the gate electrodes 21 and the bottom layer reserved metal pattern 22;

[0052] active layer 41 and a semiconductor bridge pattern 42a formed by etching patterning of the oxide semiconductor thin film 40, wherein the active layer 41 is located above the gate 21, and the semiconductor bridge pattern 42a is located above the bottom layer reserved metal pattern 22; the semiconductor bridge pattern 42a is changed into a conductor bridge pattern 42b by being ion doped and changed from a semiconductor to a conductor;

[0053] an etching barrier layer 50 located on the active layer 41 and the conductor bridge pattern 42b;

[0054] a source electrode 61, a drain electrode 62 and a data line 63 formed by etching patterning of a second metal layer 60 and located on the etching barrier layer 50, and a plurality of data lines 63 extend along a second direction, and the first direction and the second direction are perpendicular to each other. The plurality of gate lines 23 and the plurality of data lines 63 intersect to form a plurality of pixel units.

[0055] wherein the source electrode 61 and the drain electrode 62 are spaced apart from each other and are both electrically connected to the active layer 41, the source electrode 61 is electrically connected to the data line 63, the conductor bridge pattern 42b is arranged below the data line 63 and in the opening area of the pixel unit, the bottom layer reserved metal pattern 22 is arranged below the data line 63, and the bottom layer reserved metal pattern 22 is located in the area where the conductor bridge pattern 42b is located.

[0056] Specifically, please refer to Figure 1 The conductor bridge pattern 42b is located below the data line 63, the conductor bridge pattern 42b extends along the direction of the data line 63, and the two sides of the conductor bridge pattern 42b extend into the opening areas of two adjacent pixel units. By extending the two sides of the conductor bridge pattern 42b into the opening areas of two adjacent pixel units, the width of the conductor bridge pattern 42b can be increased, and when the data line 63 needs to be repaired in the future and the data signal is transmitted through the conductor bridge pattern 42b, the wider conductor bridge pattern 42b can reduce the resistance.

[0057] The conductor bridge pattern 42b extends along the direction of the data line 63, and the length of the conductor bridge pattern 42b along the direction of the data line 63 is close to the length of the opening area of a single pixel unit. By setting the length of the conductor bridge pattern 42b to be close to the length of the opening area of a single pixel unit, the opportunity for repairing the broken data line 63 can be increased, that is, when the data line 63 is broken in each pixel unit area, it can be repaired through the conductor bridge pattern 42b.

[0058] In this embodiment, two bottom layer reserved metal patterns 22 are arranged in the area where the conductor bridge pattern 42b is located, and the two bottom layer reserved metal patterns 22 are respectively located at the two end positions of the conductor bridge pattern 42b along the direction of the data line 63. In this way, Figure 1As shown, when the data line 63 is broken at A, the bottom layer reserved metal pattern 22, the data line 63 and the conductor bridging pattern 42b can be fused together by laser repair at the positions where the two bottom layer reserved metal patterns 22 are located, so that the conductor bridging pattern 42b plays a bridging role to realize the conduction of the broken data line 63. It can be understood that more than two bottom layer reserved metal patterns 22 can also be arranged in the area where each conductor bridging pattern 42b is located, and more bottom layer reserved metal patterns 22 are arranged. When the data line 63 is broken, only the two closest bottom layer reserved metal patterns 22 to the broken position are selected for laser repair.

[0059] It should be noted that when the data line 63 is not broken, the conductor bridging pattern 42b is separated from the data line 63 by the etching stop layer 50 and is not connected, and the existence of the conductor bridging pattern 42b has no other influence.

[0060] Please refer to Figure 1 With Figure 3 Further, the conductor bridging pattern 42b is formed with a through hole 421 at a position corresponding to each bottom layer reserved metal pattern 22, and the etching stop layer 50 located above fills the through hole 421. The conductor bridging pattern 42b is formed with a through hole 421 at a position corresponding to each bottom layer reserved metal pattern 22 to prevent sputtering of the conductor bridging pattern 42b during fusion, so as to achieve better fusion effect.

[0061] Further, the width of the data line 63 located above is greater than the width of the bottom layer reserved metal pattern 22, and the data line 63 completely covers the bottom layer reserved metal pattern 22, and the width of the bottom layer reserved metal pattern 22 is greater than the width of the through hole 421, the through hole 421 falls into the area where the bottom layer reserved metal pattern 22 is located, and the through hole 421 and the bottom layer reserved metal pattern 22 are vertically and centrally aligned. This setting is also to achieve better fusion effect. However, it can be understood that in other embodiments, the widths of the data line 63, the bottom layer reserved metal pattern 22 and the through hole 421 can not be limited by the above, for example, the widths of the data line 63 and the bottom layer reserved metal pattern 22 can be the same and greater than the width of the through hole 421.

[0062] In this embodiment, the material of the oxide semiconductor thin film 40 can be IGZO, but is not limited thereto.

[0063] Further, please refer to Figure 2 With Figure 3 The array substrate further comprises:

[0064] A first passivation layer 70 covering the source electrode 61, the drain electrode 62 and the data line 63;

[0065] A planarization layer 80 covering the first passivation layer 70;

[0066] a common electrode 91 formed on the flat layer 80 and by the first transparent conductive layer 90 through etching patterning;

[0067] a second passivation layer 100 covering the common electrode 91;

[0068] a pixel electrode 111 formed on the second passivation layer 100 and by the second transparent conductive layer 110 through etching patterning, wherein the second passivation layer 100, the flat layer 80 and the first passivation layer 70 are formed with a contact hole 101 corresponding to the drain 62, and the pixel electrode 111 fills in the contact hole 101 and is conductively connected with the drain 62.

[0069] Figures 4a to 4h Fig. 2 is a sectional view of the manufacturing process of the thin film transistor array substrate along the line II-II in Fig. 1. Figure 1 Fig. 3 is a sectional view of the manufacturing process of the thin film transistor array substrate along the line III-III in Fig. 1. Figures 5a to 5i Fig. 4 is a sectional view of the manufacturing process of the thin film transistor array substrate along the line IV-IV in Fig. 1. Figure 1 Fig. 5 is a sectional view of the manufacturing process of the thin film transistor array substrate along the line V-V in Fig. 1.

[0070] The preferred embodiment of the present application further provides a manufacturing method of a thin film transistor array substrate, which combines Figure 1 、 Figure 2 、 Figure 3 and Figures 4a to 5i A manufacturing method of a thin film transistor array substrate comprises:

[0071] Please refer to Figure 4a and Figure 5a , a first metal layer 20 is formed on a substrate 10, and the first metal layer 20 is etched and patterned, so that the first metal layer 20 is formed with mutually spaced apart gate electrodes 21, a bottom layer reserved metal pattern 22 and gate lines 23 (as shown in Figure 1 , wherein the plurality of gate lines 23 extend along a first direction. Etching and patterning of the film layer mainly adopts the process steps of coating photoresist, exposure, development, etching and removing photoresist, and is prior art, which is not described here.

[0072] After the gate electrodes 21 and the bottom layer reserved metal pattern 22 are formed, a gate insulating layer 30 covering the gate electrodes 21 and the bottom layer reserved metal pattern 22 is formed on the substrate 10, as shown in Figure 4a and Figure 5a .

[0073] Then, an oxide semiconductor thin film 40 is formed on the gate insulating layer 30, and the oxide semiconductor thin film 40 is etched and patterned so that the oxide semiconductor thin film 40 forms active layers 41 and a semiconductor bridge pattern 42a, wherein the active layers 41 are located above the gates 21, and the semiconductor bridge pattern 42a is located above the bottom layer reserved metal pattern 22; then, the semiconductor bridge pattern 42a is ion-doped so that the semiconductor bridge pattern 42a is changed from a semiconductor to a conductor to form a conductor bridge pattern 42b.

[0074] Preferably, the etching and patterning of the oxide semiconductor thin film 40 includes the following steps:

[0075] Please refer to Figure 4b and Figure 5b A photoresist layer 120 is coated on the oxide semiconductor thin film 40.

[0076] Please refer to Figure 4c and Figure 5c The photoresist layer 120 is exposed and developed using a half-tone mask 130 so that the photoresist layer 120 leaves a first photoresist pattern 121 and a second photoresist pattern 122, and other areas without photoresist are exposed to the oxide semiconductor thin film 40, wherein the first photoresist pattern 121 corresponds to the position of the active layers 41, the second photoresist pattern 122 corresponds to the position of the semiconductor bridge pattern 42a, and the thickness of the first photoresist pattern 121 is greater than that of the second photoresist pattern 122.

[0077] Specifically, the half-tone mask 130 includes an opaque area 131, a semi-transparent area 132 and a fully transparent area 133, wherein the opaque area 131, the semi-transparent area 132 and the fully transparent area 133 correspond to the first photoresist pattern 121, the second photoresist pattern 122 and the area without photoresist, respectively. After exposure and development, the photoresist layer 120 leaves the first photoresist pattern 121 and the second photoresist pattern 122, and the thickness of the first photoresist pattern 121 is greater than that of the second photoresist pattern 122.

[0078] Please refer to Figure 4c and Figure 5c The exposed oxide semiconductor thin film 40 is etched to remove the exposed oxide semiconductor thin film 40, so that the oxide semiconductor thin film 40 forms the active layers 41 and the semiconductor bridge pattern 42a after etching.

[0079] Please refer to Figure 5dAfter the active layer 41 and the semiconductor bridge pattern 42a are formed, the second photoresist pattern 122 is removed by photoresist ashing to expose the semiconductor bridge pattern 42a, so that the semiconductor bridge pattern 42a is ion doped. After the semiconductor bridge pattern 42a is exposed, the semiconductor bridge pattern 42a is subjected to a conductorization process, in this embodiment, the semiconductor bridge pattern 42a is ion doped (e.g. treated with H2gas). It is worth mentioning that during the photoresist ashing process, the first photoresist pattern 121 is also thinned, but since the first photoresist pattern 121 is thicker than the second photoresist pattern 122 as a whole, the first photoresist pattern 121 still covers the active layer 41 after being thinned, so that the active layer 41 is not affected when the semiconductor bridge pattern 42a is ion doped.

[0080] Please refer to Figure 4d After the semiconductor bridge pattern 42a is ion doped to change the semiconductor bridge pattern 42a from a semiconductor to a conductor to form a conductor bridge pattern 42b, the first photoresist pattern 121 is removed.

[0081] In this embodiment, the halftone mask 130 can be used to complete the patterning of the active layer 41 and the semiconductor bridge pattern 42a, and at the same time, the ion doping of the semiconductor bridge pattern 42a can also be completed, without the need to use multiple masks, saving the process steps, reducing the manufacturing cost, and improving the production efficiency.

[0082] It can be understood that in other embodiments, multiple masks (mask) can also be used, for example, one mask is used to complete the patterning of the active layer 41 and the semiconductor bridge pattern 42a, and another mask is used to complete the ion doping of the semiconductor bridge pattern 42a, which is also feasible, but the production efficiency may be reduced.

[0083] Please refer to Figure 4e And Figure 5f After the conductor bridge pattern 42b is formed, an etching stop layer 50 is formed on the active layer 41 and the conductor bridge pattern 42b.

[0084] Please refer to Figure 4f And Figure 5g Then, a second metal layer 60 is formed on the etching stop layer 50, and the second metal layer 60 is etched and patterned to form a source electrode 61, a drain electrode 62 and a data line 63. The plurality of data lines 63 extend along a second direction, and the first direction and the second direction are perpendicular. The plurality of gate lines 23 and the plurality of data lines 63 intersect to form a plurality of pixel units.

[0085] The source electrode 61 and the drain electrode 62 are spaced apart from each other and are electrically connected to the active layer 41, the source electrode 61 is electrically connected to the data line 63, the conductor bridging pattern 42b is arranged below the data line 63 and in the opening region of the pixel unit, the bottom layer reserved metal pattern 22 is arranged below the data line 63, and the bottom layer reserved metal pattern 22 is located in the region where the conductor bridging pattern 42b is located.

[0086] Specifically, the source electrode 61 can be integrated with the data line 63. In addition, it is worth mentioning that, in order to make the two ends of the active layer 41 contact and connect with the source electrode 61 and the drain electrode 62 respectively, the etching stop layer 50 needs to be etched and patterned after being formed, and the positions corresponding to the two ends of the active layer 41 are removed to expose the two ends of the active layer 41, so that the source electrode 61 and the drain electrode 62 can be directly in contact with the two ends of the active layer 41 and be electrically connected, but the middle channel region of the active layer 41 is covered by the etching stop layer 50 to achieve protection of the channel region. By covering the etching stop layer 50 on the active layer 41, the channel region is protected by the etching stop layer 50, which prevents the etching process in the subsequent manufacturing of the source electrode 61, the drain electrode 62 and the data line 63 from damaging the active layer 41, which helps to improve the stability of the TFT.

[0087] Please refer to Figure 1 and Figure 5g , the conductor bridging pattern 42b is located below the data line 63, the conductor bridging pattern 42b extends along the direction of the data line 63, and the two sides of the conductor bridging pattern 42b extend into the opening regions of two adjacent pixel units respectively. By extending the two sides of the conductor bridging pattern 42b into the opening regions of two adjacent pixel units, the width of the conductor bridging pattern 42b can be increased, and when the data line 63 needs to be repaired in the future and the data signal is transmitted through the conductor bridging pattern 42b, the wider conductor bridging pattern 42b can reduce the resistance.

[0088] The conductor bridging pattern 42b extends along the direction of the data line 63, and the length of the conductor bridging pattern 42b along the direction of the data line 63 is close to the length of the opening region of a single pixel unit. By setting the length of the conductor bridging pattern 42b to be close to the length of the opening region of a single pixel unit, the opportunity for repairing the broken data line 63 can be increased, that is, the broken data line 63 in each pixel unit region can be repaired through the conductor bridging pattern 42b.

[0089] In the embodiment, two bottom layer reserved metal patterns 22 are arranged in the region where the conductor bridging pattern 42b is located, and the two bottom layer reserved metal patterns 22 are respectively located at the two ends of the conductor bridging pattern 42b along the direction of the data line 63. In this way, as Figure 1As shown, when the data line 63 is broken at A, the bottom layer reserved metal pattern 22, the data line 63 and the conductor bridging pattern 42b can be fused together by laser repair at the positions of the two bottom layer reserved metal patterns 22, so that the conductor bridging pattern 42b plays a bridging role to realize the conduction of the broken data line 63. It can be understood that more than two bottom layer reserved metal patterns 22 can be arranged in the area where each conductor bridging pattern 42b is located, and more bottom layer reserved metal patterns 22 are arranged, so that when the data line 63 is broken, only the two closest bottom layer reserved metal patterns 22 to the broken position are selected for laser repair. Figure 1 Only one conductor bridging pattern 42b is schematically shown in the figure, and it can be understood that such a conductor bridging pattern 42b and a bottom layer reserved metal pattern 22 can be arranged at the position of the data line 63 between each adjacent two pixel units, so that the data line 63 can be repaired no matter where it is broken.

[0090] It should be noted that when the data line 63 is not broken, the conductor bridging pattern 42b is separated from the data line 63 by the etching stop layer 50 and is not connected, and the existence of the conductor bridging pattern 42b has no other effect.

[0091] Please refer to Figure 1 , Figure 3 and Figure 5c , further, the conductor bridging pattern 42b is formed with a through hole 421 at a position corresponding to each bottom layer reserved metal pattern 22, the through hole 421 can be formed at the same time when the oxide semiconductor thin film 40 is etched, and the etching stop layer 50 above is filled in the through hole 421. The conductor bridging pattern 42b can achieve better fusion effect by forming a through hole 421 at a position corresponding to each bottom layer reserved metal pattern 22, to prevent sputtering of the conductor bridging pattern 42b during fusion.

[0092] In the embodiment, the material of the oxide semiconductor thin film 40 can be IGZO, but is not limited thereto. The oxide semiconductor material has the characteristics of high mobility, low off-state current and simple process, and ion doping (such as treatment with H2 gas) of the oxide semiconductor material can convert it from a semiconductor to a conductor. In the embodiment, the oxide semiconductor thin film 40 is divided into two parts by the half-tone mask 130, one part is not doped to become the active layer 41 of the TFT, and the other part is doped to become a transparent conductor layer, i.e. the conductor bridging pattern 42b. The transparent conductor bridging pattern 42b is arranged below the data line 63 and in the opening area of the pixel unit, which does not affect normal display, and the laser repair method can realize the repair of the broken data line 63.

[0093] Further, the manufacturing method further comprises:

[0094] Please refer to Figure 4g and Figure 5h forming a first passivation layer 70 covering the source 61, the drain 62 and the data line 63;

[0095] forming a planar layer 80 covering the first passivation layer 70;

[0096] forming a first transparent conductive layer 90 on the planar layer 80, and etching and patterning the first transparent conductive layer 90, so that the first transparent conductive layer 90 forms a common electrode 91;

[0097] Please refer to Figure 4h and Figure 5i forming a second passivation layer 100 covering the common electrode 91, and etching and patterning the second passivation layer 100, the planar layer 80 and the first passivation layer 70, so that a contact hole 101 is formed in the second passivation layer 100, the planar layer 80 and the first passivation layer 70 at a position corresponding to the drain 62, wherein the drain 62 is exposed through the contact hole 101;

[0098] Please refer to Figure 2 and Figure 3 forming a second transparent conductive layer 110 on the second passivation layer 100, and etching and patterning the second transparent conductive layer 110, so that the second transparent conductive layer 110 forms a pixel electrode 111, wherein the pixel electrode 111 fills in the contact hole 101 and is in conductive connection with the drain 62.

[0099] The preferred embodiment of the present application further provides a repairing method for the thin film transistor array substrate as described above, comprising:

[0100] When the data line 63 is broken, the bottom layer reserved metal pattern 22, the data line 63 and the conductor bridging pattern 42b are fused together by laser, and since the conductor bridging pattern 42b is a conductor, the broken data line 63 can be conducted through the conductor bridging pattern 42b.

[0101] In the embodiment, in order to prevent sputtering of the conductor bridging pattern 42b during fusion, the conductor bridging pattern 42b is hollowed out at a local position to form a through hole 421 at the fusion position of the bottom layer reserved metal pattern 22 and the data line 63, and the width of the data line 63 is greater than the width of the bottom layer reserved metal pattern 22, and the width of the bottom layer reserved metal pattern 22 is greater than the width of the through hole 421, so as to achieve better fusion effect. However, it can be understood that in other embodiments, the widths among the data line 63, the bottom layer reserved metal pattern 22 and the through hole 421 can not be limited by the above, for example, the widths of the data line 63 and the bottom layer reserved metal pattern 22 can be the same and greater than the width of the through hole 421.

[0102] The display panel can be a liquid crystal display panel.

[0103] The thin film transistor array substrate and the manufacturing method thereof have the following advantages when the data line of the array substrate is broken and needs to be repaired:

[0104] 1. The number of repairable data lines is not limited, and the yield can be maximized;

[0105] 2. No redundant data line repair circuit needs to be designed, no power amplifier integrated circuit needs to be added, and no cost is increased;

[0106] 3. No redundant data line repair circuit needs to be designed, which is conducive to realizing a narrow frame.

[0107] The above application specific examples describe the principles and implementation modes of the present application, and the above examples are only used to help understand the method and core idea of the present application; for those skilled in the art, the specific implementation mode and application range can be changed according to the idea of the present application; in summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A thin-film transistor array substrate, characterized in that, include: Substrate; The gate and the underlying reserved metal pattern are spaced apart and formed by etching the first metal layer on the substrate; A gate insulating layer covering the gate and the underlying reserved metal pattern; An active layer and a semiconductor bridging pattern are spaced apart on the gate insulating layer and formed by etching a thin oxide semiconductor film, wherein the active layer is located above the gate and the semiconductor bridging pattern is formed into a conductor bridging pattern by ion doping and transforming it from a semiconductor to a conductor. An etch barrier layer located on the active layer and the conductor bridging pattern; The source, drain, and data lines are formed on the etch barrier layer by etching patterning of the second metal layer. The source and drain are spaced apart from each other and are both electrically connected to the active layer. The source is electrically connected to the data line. The conductor bridging pattern is disposed below the data line, extends along the direction of the data line, and extends into the opening areas of two adjacent pixel units on both sides of the conductor bridging pattern. The conductor bridging pattern forms vias at positions corresponding to each of the underlying reserved metal patterns. The etch barrier layer above fills the vias. The underlying reserved metal pattern is disposed below the data line and is located within the area where the conductor bridging pattern is located. The underlying reserved metal pattern and the conductor bridging pattern are separated by the gate insulating layer, and the conductor bridging pattern and the data line are separated by the etch barrier layer.

2. The thin-film transistor array substrate as described in claim 1, characterized in that, The length of the conductor bridging pattern along the data line direction is close to the length of the opening area of ​​a single pixel unit. At least two of the underlying reserved metal patterns are provided in the area where the conductor bridging pattern is located, and the two underlying reserved metal patterns are respectively located at the two ends of the conductor bridging pattern along the data line direction.

3. The thin-film transistor array substrate as described in claim 2, characterized in that, The width of the data cable is greater than the width of the underlying reserved metal pattern. The data cable completely covers the underlying reserved metal pattern, and the width of the underlying reserved metal pattern is greater than the width of the through hole. The through hole falls within the area where the underlying reserved metal pattern is located, and the through hole is vertically and centrally aligned with the underlying reserved metal pattern.

4. A method for fabricating a thin-film transistor array substrate, characterized in that, include: A first metal layer is formed on a substrate, and the first metal layer is etched and patterned to form a gate and a reserved bottom metal pattern spaced apart from each other. A gate insulating layer is formed covering the gate and the reserved metal pattern on the bottom layer; An oxide semiconductor thin film is formed on the gate insulating layer, and the oxide semiconductor thin film is etched and patterned to form an active layer and a semiconductor bridging pattern spaced apart from each other, wherein the active layer is located above the gate. The semiconductor bridging pattern is ion-doped to transform it from a semiconductor to a conductor, thus forming a conductor bridging pattern. An etch barrier layer is formed on the active layer and the conductor bridging pattern; A second metal layer is formed on the etch barrier layer, and the second metal layer is etched and patterned to form a source, a drain, and a data line. The source and drain are spaced apart from each other and are both electrically connected to the active layer. The source is electrically connected to the data line. A conductor bridging pattern is disposed below the data line and extends along the direction of the data line. The two sides of the conductor bridging pattern extend into the opening areas of two adjacent pixel units. The conductor bridging pattern forms vias at positions corresponding to each of the underlying reserved metal patterns. The etch barrier layer above fills the vias. The underlying reserved metal pattern is disposed below the data line and is located within the area where the conductor bridging pattern is located. The underlying reserved metal pattern and the conductor bridging pattern are separated by the gate insulating layer, and the conductor bridging pattern and the data line are separated by the etch barrier layer.

5. The method for fabricating a thin-film transistor array substrate as described in claim 4, characterized in that, The above-mentioned etching patterning of the oxide semiconductor thin film includes: A photoresist layer is coated on the oxide semiconductor thin film; The photoresist layer is exposed and developed using a halftone mask to leave a first photoresist pattern and a second photoresist pattern on the photoresist layer. Other areas where no photoresist is left expose the oxide semiconductor film. The first photoresist pattern corresponds to the position of the active layer, and the second photoresist pattern corresponds to the position of the semiconductor bridging pattern. The thickness of the first photoresist pattern is greater than the thickness of the second photoresist pattern. The oxide semiconductor film is etched to remove the exposed oxide semiconductor film, so that the oxide semiconductor film forms the active layer and the semiconductor bridging pattern after etching. The second photoresist pattern is removed by photoresist ashing to expose the semiconductor bridging pattern, so that the semiconductor bridging pattern can be ion-doped, and the first photoresist pattern is removed after the semiconductor bridging pattern has been ion-doped.

6. The method for fabricating a thin-film transistor array substrate as described in claim 4, characterized in that, The length of the conductor bridging pattern along the data line direction is close to the length of the opening area of ​​a single pixel unit. At least two of the underlying reserved metal patterns are provided in the area where the conductor bridging pattern is located, and the two underlying reserved metal patterns are respectively located at the two ends of the conductor bridging pattern along the data line direction.

7. The method for fabricating a thin-film transistor array substrate as described in claim 6, characterized in that, The via was created simultaneously during the etching of the oxide semiconductor thin film.

8. A method for repairing a thin-film transistor array substrate as described in any one of claims 1-3, characterized in that, include: When the data cable breaks, the underlying reserved metal pattern, the data cable, and the conductor bridging pattern are fused together using laser technology, and the broken data cable is made conductive through the conductor bridging pattern.

9. A display panel, characterized in that, Includes the thin-film transistor array substrate as described in any one of claims 1-3.

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