Array gate driving circuit, display panel and display device

Abstract

The application discloses an array gate driving circuit, a display panel and a display device. The array gate driving circuit comprises a plurality of array gate driving units connected in cascade, the array gate driving unit comprises a reset transistor for resetting the array gate driving unit, the array gate driving unit comprises a first array gate driving unit, the reset transistor of the first array gate driving unit is connected with a first reset signal source, the first reset signal source is not connected with a rear-stage array gate driving unit, and the array gate driving circuit further comprises a shunt module connected with the first reset signal source for shunting the reset transistor of the first array gate driving unit. The array gate driving circuit of the application is connected with the reset transistor of the first array gate driving unit through the shunt module, so that the reset transistor is shunted, damage of the reset transistor caused by no shunting of other rear-stage array gate driving units is avoided, and the phenomenon of horizontal stripe defects is avoided.

Description

Technical Field

[0001] This invention relates to the field of display device technology, and more specifically, to an array gate driving circuit, a display panel, and a display device. Background Technology

[0002] With the development of electronic technology, displays are widely used in various industries, and liquid crystal display technology has become the mainstream display technology. Among them, TFT-LCD (Thin Film Transistor Liquid Crystal Display) has been widely adopted and become the mainstream product due to its small size, low power consumption, no radiation, and high display resolution. Currently, most TFT-LCDs use Gate Driver On Array (GOA) technology to fabricate the gate driving circuits used to drive the liquid crystal display pixels on the array substrate, resulting in fewer manufacturing processes and lower costs. However, TFT-LCD products suffer from the problem of horizontal stripes appearing in fixed positions. Summary of the Invention

[0003] The present invention provides an array gate driving circuit, a display panel, and a display device.

[0004] This invention provides an array gate driving circuit, comprising a plurality of cascaded array gate driving units. Each array gate driving unit includes a reset transistor for resetting the array gate driving unit. Each array gate driving unit includes a first array gate driving unit, the reset transistor of which is connected to a first reset signal source. The output signal of the first reset signal source is not used as an input signal. The input signal is used to drive either the array gate driving unit or the first reset signal source. The array gate driving circuit further includes a shunt module connected to one end of the first reset signal source for shunting current to the reset transistor of the first array gate driving unit.

[0005] In some embodiments, the current shunt module includes a current shunt transistor and a current shunt capacitor. The current shunt transistor is used to connect to one end of the first reset signal source. The current shunt capacitor is used to connect to the current shunt transistor. The current shunt transistor and the current shunt capacitor are used to shunt the reset transistor of the first array gate driving unit.

[0006] In some embodiments, the number of shunt transistors and shunt capacitors is the same as the number of the first array gate driving units, and the first reset signal source connected to one of the first array gate driving units is connected to one shunt transistor and one of the shunt capacitors.

[0007] In some embodiments, the reset transistor and the shunt transistor are thin-film transistors, and the gate of the shunt transistor is connected to the gate of the reset transistor.

[0008] In some embodiments, the array gate driving unit includes a second array gate driving unit, which does not have a connected subsequent array gate driving unit that provides a reset signal. The second array gate driving unit includes the first array gate driving unit. The array gate driving circuit includes a redundancy unit and a reset module. The redundancy unit is used to provide a reset signal to the second array gate driving unit, and the first reset signal source is the redundancy unit. The reset module is connected to the redundancy unit and is used to provide the reset signal to the redundancy unit. The shunt module is connected to the reset module.

[0009] In some embodiments, the array gate driving circuit includes a clock signal line and a redundant unit. The clock signal line is used to provide a clock signal to the array gate driving unit. The array gate driving unit includes at least two first array gate driving units, each including a first unit and a second unit. The first unit and at least one of the redundant units are connected to the same clock signal line. The second unit and the redundant unit are connected to different clock signal lines. The shunt module is connected to one end of a first reset signal source connected to the first unit, and the other end of the first reset signal source connected to the second unit is left floating.

[0010] In some embodiments, the array gate driving unit includes at least two first array gate driving units and at least two shunt modules, wherein one first array gate driving unit is connected to one first reset signal source, and one first reset signal source is connected to one shunt module.

[0011] In some embodiments, the array gate driving circuit further includes a redundant unit, and the array gate driving unit further includes a third array gate driving unit. The third array gate driving unit is connected to a second reset signal source, and the output signal of the second reset signal source is used as the input signal. The second reset signal source is either the array gate driving unit or the redundant unit.

[0012] In some embodiments, the array gate driving circuit includes clock signal lines, and the number of clock signal lines includes multiple lines. The number of the first array gate driving units is determined according to the number of clock signal lines.

[0013] This invention provides a display panel, which includes a light-emitting unit and an array gate driving circuit according to any of the above embodiments, wherein the array gate driving circuit is used to drive the light-emitting unit.

[0014] An embodiment of the present invention provides a display device, the display device including a housing and a display panel as described above, the display panel being disposed within the housing.

[0015] The array gate driving circuit of the present invention connects a current shunt module to one end of the first reset signal source connected to the reset transistor of the first array gate driving unit, so that the current shunt module can shunt the current of the reset transistor of the first array gate driving unit, thereby avoiding damage to the reset transistor of the first array gate driving unit due to the lack of other subsequent array gate driving units to shunt the current of the first reset signal source, and thus avoiding the occurrence of horizontal stripe defects.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0018] Figure 1 This is a schematic diagram of the connection of a portion of the array gate driving circuit according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the connection of a portion of the array gate driving circuit according to an embodiment of the present invention;

[0020] Figure 3 This is a circuit diagram of an array gate driving unit in a related technology. Detailed Implementation

[0021] Embodiments of the present invention are described in detail below. These embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0022] With the development of electronic technology, displays are widely used in various industries, and liquid crystal display technology has become the mainstream display technology. Among them, TFT-LCD (Thin Film Transistor Liquid Crystal Display) has been widely adopted and become the mainstream product due to its small size, low power consumption, no radiation, and high display resolution. Currently, most TFT-LCDs use Gate Driver On Array (GOA) technology to fabricate the gate driving circuits used to drive the liquid crystal display pixels on the array substrate, resulting in fewer manufacturing processes and lower costs. However, TFT-LCD products suffer from the problem of horizontal stripes appearing in fixed positions.

[0023] Please see Figure 1 This invention provides an array gate driving circuit 1000, which includes a plurality of cascaded array gate driving units. Each array gate driving unit includes a reset transistor for resetting the array gate driving unit. The array gate driving unit includes a first array gate driving unit 101, whose reset transistor is connected to a first reset signal source 102. The output signal of the first reset signal source 102 is not used as an input signal, but is used to drive the array gate driving unit or the first reset signal source 102. The array gate driving circuit 1000 also includes a shunt module 200, which is connected to one end of the first reset signal source 102 and is used to shunt the reset transistor of the first array gate driving unit 101.

[0024] Specifically, the array gate driving circuit 1000 is a GOA (Gate driver On Array) circuit, the array gate driving unit is a GOA unit, and the first array gate driving unit 101 is the first GOA unit. The GOA circuit is composed of multiple cascaded GOA units. The gate lines of the GOA units and the light-emitting units are connected one-to-one. One GOA unit drives the corresponding connected light-emitting unit to emit light. The output signal of the GOA unit can be used as a reset signal for the preceding GOA unit to control the reset transistor of the GOA unit to turn off, thus turning off the GOA unit; it can also be used as an input signal for the following GOA unit. The GOA unit also outputs a driving signal to drive the corresponding connected light-emitting unit. A first reset signal source 102 is set to provide a reset signal for the first GOA unit that does not have a reset signal, and the output signal of the first reset signal source 102 is not used as an input signal for other units, but only as a reset signal for the GOA unit. That is, the first reset signal source 102 is only connected to the first GOA unit that does not have a reset signal. Since the first reset signal source 102 is not connected to other GOA units or the first reset signal source 102, all the output signals of the first reset signal source 102 are used as reset signal outputs connected to the reset transistor of the first GOA unit, which can easily damage the reset transistor and cause it to be unable to disconnect. Therefore, a shunt module 200 is set to connect to the first GOA unit. The shunt module 200 is connected to the reset transistor of the first GOA unit to shunt the current to the reset transistor and avoid damage to the reset transistor.

[0025] Thus, the array gate driving circuit 1000 of this embodiment connects a shunt module 200 to one end of the first reset signal source 102 connected to the reset transistor of the first array gate driving unit 101, so that the shunt module 200 can shunt the reset transistor of the first array gate driving unit 101, thereby avoiding damage to the reset transistor of the first array gate driving unit 101 due to the lack of other downstream array gate driving units to shunt the first reset signal source 102, and thus avoiding the occurrence of horizontal stripe defects.

[0026] Please see Figure 1 In some embodiments, the shunt module 200 includes a shunt transistor and a shunt capacitor. The shunt transistor is used to connect to one end of the first reset signal source 102, and the shunt capacitor is used to connect to the shunt transistor. The shunt transistor and the shunt capacitor are used to shunt the reset transistor of the first array gate drive unit 101.

[0027] Specifically, the shunt module 200 may further include components such as resistors to shunt current to the reset transistor of the first GOA unit. The reset transistor of the first GOA unit is connected to one end of the first reset signal source 102. Simultaneously, the shunt transistor M1 of the shunt module 200 is connected to the same end of the first reset signal source 102, and the shunt capacitor C is connected to the shunt transistor M1. When the first reset signal source 102 outputs the signal OUT_C, the shunt transistor M1 and the shunt capacitor C jointly shunt current to the reset transistor of the first GOA unit. The array gate drive circuit 1000 can be applied to schemes with resolutions such as WQXGA (2560×1600) and QSXGA (2560×2048), and the position of the first GOA unit can be determined according to the resolution. This embodiment is described using a scheme with a resolution of WQXGA (2560×1600). Figure 1 In the diagram, 1596 to 1600 represent GOA units from row 1596 to row 1600. The GOA unit in row 1597 is the first GOA unit. Dummy2 is the first reset signal source 102 connected to the GOA unit in row 1597, meaning the output signal of Dummy2 serves as the reset signal for the GOA unit in row 1597. The shunt transistor M1 of the shunt module 200 is connected to the reset transistor M2 of the GOA unit in row 1597, and the shunt capacitor C is connected to the shunt transistor M1. When Dummy2 outputs an output signal, the electrical signal serving as the output signal simultaneously flows to both the reset transistor M2 of the GOA unit in row 1597 and the shunt transistor M1 of the shunt module 200, thereby shunting the reset transistor M2 and preventing it from being damaged by a large current, thus avoiding the occurrence of horizontal stripe defects.

[0028] Thus, by connecting the shunt transistor and the shunt capacitor, the output signal of the first reset signal source 102 can simultaneously enter the reset transistor of the first array gate drive unit 101 and the shunt transistor of the shunt module 200, thereby achieving shunt current to the reset transistor to avoid damage to the reset transistor due to large current, thus avoiding the occurrence of horizontal stripe defects.

[0029] In some implementations, the number of shunt transistors and shunt capacitors is the same as the number of first array gate drive units 101, and a first reset signal source 102 connected to a first array gate drive unit 101 is connected to a shunt transistor and a shunt capacitor.

[0030] Specifically, in other GOA units, the reset transistor M2 is connected to the input transistor M1 of the GOA unit that provides the reset signal. In this GOA unit, the input transistor M1 is connected to a capacitor C. Therefore, when the shunt module 200 includes a shunt transistor M1 and a shunt capacitor, the connection relationship is the same as that of the preceding GOA unit. No special processing of the circuit for the shunt module 200 is required, making the implementation simple. Please refer to [link to relevant documentation]. Figure 2 The current shunt module 200 includes a current shunt transistor M1 and a current shunt capacitor C. A first GOA unit is connected to a current shunt transistor M1 and a current shunt capacitor C. The current shunt transistor M1 is connected to the reset transistor M2 of the first GOA unit, and the current shunt capacitor C is connected to the current shunt transistor M1. The current shunt transistor M1 and the current shunt capacitor C together shunt current to the first GOA unit.

[0031] Thus, by using a shunt transistor and a shunt capacitor to connect the reset transistor of a first array gate drive unit 101, the circuit implementation process can be simplified while shunting the reset transistor to avoid horizontal stripe defects.

[0032] In some implementations, the shunt module 200 includes a shunt transistor or a shunt capacitor, thereby simplifying the circuit structure while shunting the reset transistor.

[0033] In some implementations, the reset transistor and the shunt transistor are thin-film transistors, with the gate of the shunt transistor connected to the gate of the reset transistor.

[0034] Specifically, please refer to Figure 3 Thin-film transistors (TFTs) are used in GOA (Gateway Amplifier) ​​systems. A GOA unit can include four TFTs and one capacitor, where M2 is a reset transistor and M1 is an input transistor. In cascaded GOA units, the gate of the reset transistor M2 in the preceding GOA unit is connected to the gate of the input transistor M1 in the following GOA unit. Therefore, the gate of the shunt transistor is connected to the gate of the reset transistor M2 to maintain the same connection method as the preceding GOA unit, simplifying the circuit structure and design flow.

[0035] Thus, both the reset transistor and the shunt transistor are thin-film transistors, making the connection between the first array gate driving unit 101 and the shunt transistor through the first reset signal source 102 the same as the connection relationship of the preceding array gate driving unit, simplifying the circuit structure and design process.

[0036] Please see Figure 2In some embodiments, the array gate driving unit includes a second array gate driving unit 103. The second array gate driving unit 103 does not have a connected subsequent array gate driving unit that provides a reset signal. The second array gate driving unit 103 includes a first array gate driving unit 101. The array gate driving circuit 1000 includes a redundancy unit 300 and a reset module 400. The redundancy unit 300 is used to provide a reset signal to the second array gate driving unit 103. The first reset signal source 102 is the redundancy unit 300. The reset module 400 is connected to the redundancy unit 300 and is used to provide a reset signal to the redundancy unit 300. The shunt module 200 is connected to the reset module 400.

[0037] Specifically, the second array gate driving unit 103 is the second GOA unit. Since the output signal of the GOA unit serves as the reset signal for the preceding GOA unit, and the last one or more GOA units in a cascaded network do not provide a reset signal (i.e., the second GOA unit is the last one or more GOA units in the cascaded network), a redundant unit 300 is provided to enable the provision of a reset signal to the last one or more GOA units. The redundant unit 300 can be a dummy GOA unit, which does not output a drive signal. Multiple first reset signal sources 102 are cascaded together, with one redundant GOA unit connected to one GOA unit and providing it with a reset signal. Since the output signal of the redundant GOA unit serves as both the reset signal and the input signal for the subsequent redundant GOA unit, the output of the last one or more redundant GOA units is not used as the input for the subsequent redundant GOA units; these GOA units are the first reset signal sources 102.

[0038] In one embodiment, Figure 2 Dummy1 to Dummy5 are redundant GOA units, and OUT_C ​​is the output signal. GOA units in rows 1596 to 1600 are the second GOA units. The output signal of Dummy1 serves as the reset signal for the GOA unit in row 1596 and also as the input signal for Dummy5. The output signals of Dummy2 to Dummy5 serve as the reset signals for the GOA units in rows 1597 to 1600, respectively, but not as the input signals for other units. Therefore, Dummy2 to Dummy5 constitute the first reset signal source 102. Figure 2 TRST in the diagram represents reset module 400. The redundancy module is connected to reset module 400. Reset module 400 provides a reset signal to redundancy unit 300. One end of shunt module 200 is connected to TRST.

[0039] Thus, by connecting the reset transistor of the second array gate driving unit 103 to the redundant unit 300, the redundant unit 300 can provide a reset signal to the reset transistor, so that the second array gate driving unit 103 can stop working when it receives the reset signal; and a reset module 400 is provided to provide a reset signal to the redundant unit 300, and a shunt module 200 is connected to the reset transistor of the second array gate driving unit 103 and the reset module 400 to shunt the current to the reset transistor and avoid the occurrence of horizontal stripe defects.

[0040] Please see Figure 1 In some embodiments, the array gate driving circuit 1000 includes a clock signal line 500 and a redundant unit 300. The clock signal line 500 is used to provide a clock signal to the array gate driving unit. The array gate driving unit includes at least two first array gate driving units 101. The first array gate driving unit 101 includes a first unit and a second unit. The first unit and at least one redundant unit 300 are connected to the same clock signal line 500. The second unit and the redundant unit 300 are connected to different clock signal lines 500. The shunt module 200 is connected to one end of the first reset signal source 102 connected to the first unit, and one end of the first reset signal source 102 connected to the second unit is left floating.

[0041] Specifically, the output signal of the GOA unit serves as the input signal of the preceding GOA unit, and the output signal of the GOA unit is delayed by 1H as the reset signal of the subsequent GOA unit. Therefore, there is a redundant unit 300 that shares the same clock signal line 500 as the first GOA unit. In one embodiment, the output signal of the nth-stage GOA unit serves as the input signal of the (n+4)th-stage GOA unit and as the reset signal of the (n-5)th-stage GOA unit. Since the first reset signal source 102 connected to the first GOA unit is not connected to other GOA units or the first reset signal source 102, the output signal of the first reset signal source 102 only serves as the reset signal of the first GOA unit. When the first reset signal source 102 outputs current as the output signal, the reset transistor of the first GOA unit may be damaged due to a large current surge, causing the reset transistor to fail to turn off, thus preventing the first GOA unit from stopping operation. At the same time, the first unit and at least one redundant unit 300 are connected to the same clock signal line 500. When the clock signal line 500 outputs a high level, the output of the redundant unit 300 causes the first unit to produce an abnormal output, resulting in horizontal stripe defects. Therefore, a shunt module 200 is connected to one end of the first reset signal source 102 connected to the first unit, so that the output signal of the first reset signal source 102 can flow to the reset transistor of the first unit and the shunt transistor of the shunt module 200 at the same time, thereby realizing the shunt of the reset transistor.

[0042] In one embodiment, see Figure 1 GOA units in rows 1597 to 1600 are the first GOA units. GOA unit in row 1597 and redundant unit Dummy5 are connected to clock signal line CLK5. Therefore, GOA unit in row 1597 is the first unit. Redundant unit Dummy2, as the first reset signal source 102, provides a reset signal to GOA unit in row 1597. GOA units in rows 1598 to 1600 are connected to clock signal lines CLK6, CLK7 and CLK8 respectively. These three clock signal lines 500 are not connected to redundant unit 300. Therefore, GOA units in rows 1598 to 1600 are all the second units. The reset transistor M2 of the GOA unit in line 1597 is connected to the shunt transistor M1 of the shunt module 200. The shunt capacitor C is connected to the shunt transistor M1 and the reset module 400. The shunt transistor M1 and the shunt capacitor C together shunt the reset transistor M2. One end of the first reset signal source 102 connected to the GOA units in lines 1598 to 1600 is left floating and is not connected to other GOA units or the first reset current source 102.

[0043] Since the first unit has a redundant unit 300 connected to the same clock signal line 500, it may cause horizontal stripe defects. Therefore, a shunt module 200 is set for the first unit. The shunt module 200 is connected to the first reset signal source 102 connected to the first unit, thereby shunting the reset transistor of the first unit. Since the second unit does not have a redundant unit 300 connected to the same clock signal line 500, one end of the first reset signal source 102 of the second unit can be left floating to simplify the circuit structure.

[0044] Please see Figure 2 In some embodiments, the array gate driving unit includes at least two first array gate driving units 101 and at least two shunt modules 200, with one first array gate driving unit 101 connected to a first reset signal source 102 and one first reset signal source 102 connected to a shunt module 200.

[0045] Specifically, to prevent damage to the reset transistor from high current surges, a shunt module 200 is provided for shunt protection in all GOA units that do not offer shunt protection. In one embodiment, please refer to... Figure 2GOA units from row 1597 to row 1600 are all first GOA units. Redundant units Dummy2 to Dummy5 are the first reset signal sources 102 for GOA units from row 1596 to row 1597, respectively. Each of the redundant Dummy2 to Dummy5 is connected to a shunt transistor M1 of a shunt module 200. Each shunt transistor M1 in the shunt module 200 is connected to a shunt capacitor C, and each shunt capacitor C is connected to TRST. Each shunt module 200 shunts the reset transistor connected to the first current source, thereby avoiding the occurrence of horizontal stripe defects due to reset transistor damage.

[0046] Thus, the first reset signal source 102 connected to each first array gate drive unit 101 is connected to the shunt module 200, so that the electrical signal of the first reset signal source 102 as the output signal can flow to the reset transistor and the shunt module 200 at the same time, so as to avoid the reset transistor being damaged by the large current surge.

[0047] Please see Figure 1 In some embodiments, the array gate driving circuit 1000 further includes a redundant unit 300, and the array gate driving unit further includes a third array gate driving unit 104. The third array gate driving unit 104 is connected to a second reset signal source 105, and the output signal of the second reset signal source 105 is used as an input signal. The second reset signal source 105 is either the array gate driving unit or the redundant unit 300.

[0048] Specifically, M1 represents the input transistor, and M2 represents the reset transistor. The third array gate driving unit 104 is the third GOA unit. The output signal of the second reset signal source 105 connected to the third GOA unit can be used as the reset signal of the third GOA unit or as the input signal of the connected subsequent GOA unit. The second reset signal source 105 can be a GOA unit, and the input transistor M1 can be a TFT. Then, one end of the output signal OUT_C ​​in the GOA unit of the second reset signal source 105 is connected to the gate of the reset transistor M2 of the third GOA unit and the gate of the input transistor M1 of the subsequent GOA unit. When the GOA unit of the second reset signal source 105 outputs the output signal OUT_C, the output signal OUT_C ​​simultaneously flows into the connected reset transistor M2 and the input transistor M1. Therefore, the input transistor M1 of the subsequent GOA unit can shunt the reset transistor M2 of the third GOA unit. In one embodiment, please refer to Figure 1 The GOA cell in row 1596 is the third array gate drive unit 104, and the redundant unit 300 is the second reset signal source 105 that provides a reset signal to the GOA cell in row 1596.

[0049] Thus, the reset transistor of the third array gate driving unit 104 can be shunted by the input transistor of the subsequent array gate driving unit or the second reset signal source 105 connected to the second reset signal source 105, and the reset transistor of the first array gate driving unit 101 can be shunted by the shunt module 200, so as to shunt the reset transistor of the array gate driving unit, avoid the reset transistor from being damaged by large current impact, and thus avoid the phenomenon of horizontal stripe defects.

[0050] In some embodiments, the array gate driving circuit 1000 includes clock signal lines 500, and the number of clock signal lines 500 includes multiple lines. The number of first array gate driving units 101 is determined according to the number of clock signal lines 500.

[0051] Specifically, the number of clock signal lines 500 can be 2, 4, 6, 8, 10, etc. This embodiment uses 8 clock signal lines 500 for explanation. The number of first GOA units is determined based on the clock signal lines 500, the GOA unit arrangement, and whether the reset signal is delayed. When the GOA unit is reset 1H later, it means that if the output signal of the nth level GOA unit is used as the input signal of the (n+i)th level GOA unit, it is also used as the reset signal of the (ni-1)th level GOA unit. In one embodiment, there are 8 clock signal lines 500, the GOA units are arranged in a double-sided driving manner (i.e., arranged in two columns), and the GOA units are reset 1H later. In this case, the number of first GOA units is 4, including 1 first unit and 3 second units. In addition, the number of redundant units 300 is also determined based on the number of clock signal lines 500.

[0052] Thus, the number of the first array gate drive units 101 is determined according to the number of clock signal lines 500, thereby determining the number of shunt modules 200 to simplify the circuit design process, and the shunt modules 200 are used to shunt the reset transistors of the first array gate drive units 101.

[0053] The present invention provides a display panel, which includes a light-emitting unit and an array gate driving circuit 1000 according to any of the above embodiments. The array gate driving circuit 1000 is used to drive the light-emitting unit.

[0054] Thus, in this embodiment, the display panel connects a current shunt module 200 to one end of the first reset signal source 102 connected to the reset transistor of the first array gate driving unit 101. This allows the current shunt module 200 to shunt the reset transistor of the first array gate driving unit 101, thereby preventing damage to the reset transistor of the first array gate driving unit 101 due to the lack of other downstream array gate driving units to shunt the first reset signal source 102, and thus avoiding the occurrence of horizontal stripe defects.

[0055] The present invention provides a display device, which includes a housing and a display panel as described in the above embodiments, the display panel being disposed within the housing.

[0056] Thus, the display device of this embodiment connects a current shunt module 200 to one end of the first reset signal source 102 connected to the reset transistor of the first array gate driving unit 101, so that the current shunt module 200 can shunt the reset transistor of the first array gate driving unit 101, thereby avoiding damage to the reset transistor of the first array gate driving unit 101 due to the lack of other downstream array gate driving units to shunt the first reset signal source 102, and thus avoiding the occurrence of horizontal stripe defects.

[0057] In the description of this specification, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0058] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connections, detachable connections, or integral connections; it can include direct connections or indirect connections through an intermediate medium; and it can also include internal communication between two elements. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0061] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An array gate drive circuit, characterized by comprising: The array gate driving circuit includes multiple cascaded array gate driving units. Each array gate driving unit includes a reset transistor for resetting the array gate driving unit. Each array gate driving unit includes a first array gate driving unit, where the reset transistor is connected to a first reset signal source. The output signal of the first reset signal source serves as the reset signal for the first array gate driving unit. The output signal of the first reset signal source is not used as an input signal. The input signal is used to drive either the array gate driving unit or the first reset signal source. The array gate driving circuit further includes: A current shunting module is connected to the first reset signal source. The electrical signal from the first reset signal source flows simultaneously to the reset transistor of the first array gate driving unit and the current shunting module. The current shunting module is used to shunt the reset transistor of the first array gate driving unit. The traffic splitting module includes: A shunt transistor is connected to the first reset signal source; A shunt capacitor is connected to the shunt transistor, and the shunt transistor and the shunt capacitor are used to shunt the reset transistor of the first array gate drive unit.

2. The array gate drive circuit according to claim 1, characterized by, The number of shunt transistors, the number of shunt capacitors, and the number of the first array gate driving units are the same. The first reset signal source connected to one of the first array gate driving units is connected to one of the shunt transistors and one of the shunt capacitors.

3. The array gate drive circuit of claim 1, wherein, The reset transistor and the shunt transistor are thin-film transistors, and the gate of the shunt transistor is connected to the gate of the reset transistor.

4. The array gate driving circuit according to claim 1, characterized in that, The array gate driving unit includes a second array gate driving unit, which does not have a subsequent array gate driving unit that provides a reset signal. The second array gate driving unit includes the first array gate driving unit. The array gate driving circuit further includes: A redundancy unit is provided for providing a reset signal to the second array gate driving unit, and the redundancy unit includes the first reset signal source; A reset module is connected to the redundant unit and is used to provide the reset signal to the redundant unit. The shunt module is connected to the reset module.

5. The array gate drive circuit of claim 1, wherein, The array gate driving circuit further includes a clock signal line and a redundant unit. The clock signal line is used to provide a clock signal to the array gate driving unit. The array gate driving unit includes at least two first array gate driving units. The first array gate driving unit includes a first unit and a second unit. The first unit and at least one of the redundant units are connected to the same clock signal line. The clock signal line connected to the second unit is different from the clock signal line connected to the redundant unit. The shunt module is connected to the first reset signal source connected to the first unit, and one end of the first reset signal source connected to the second unit is left floating.

6. The array gate drive circuit of claim 1, wherein, The array gate driving unit includes at least two first array gate driving units and at least two shunt modules, with one first array gate driving unit connected to one first reset signal source and one first reset signal source connected to one shunt module.

7. The array gate drive circuit of claim 1, wherein, The array gate driving circuit further includes a redundant unit, and the array gate driving unit further includes a third array gate driving unit. The third array gate driving unit is connected to a second reset signal source, and the output signal of the second reset signal source is used as the input signal. The second reset signal source is either the array gate driving unit or the redundant unit.

8. The array gate drive circuit of claim 1, wherein, The array gate driving circuit includes clock signal lines, and the number of clock signal lines includes multiple lines. The number of the first array gate driving units is determined according to the number of clock signal lines.

9. A display panel, characterized by, The display panel includes a light-emitting unit and an array gate driving circuit as described in any one of claims 1-8, wherein the array gate driving circuit is used to drive the light-emitting unit.

10. A display device, characterized by comprising: The display device includes a housing and a display panel as described in claim 9, wherein the display panel is disposed within the housing.

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