A switching circuit and method that suppresses hot carrier injection effects

Abstract

This invention relates to the field of integrated circuit technology, and discloses a switching circuit and method for suppressing the hot carrier injection effect. The switching circuit includes a first switching transistor and a second switching transistor array. The second switching transistor array includes multiple switching transistors connected in parallel. The first switching transistor is connected in parallel with the second switching transistor array, and the conduction area of ​​the first switching transistor is smaller than the total conduction area of ​​the second switching transistor array. The first switching transistor is configured to turn on before the second switching transistor array. This invention can effectively suppress the hot carrier injection effect while achieving high current transmission.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a switching circuit and method for suppressing the hot carrier injection effect. Background Technology

[0002] Hot carrier injection (HCI effect) refers to the phenomenon where charge carriers, under the influence of a strong electric field, continuously drift and accelerate along the field direction, gaining significant kinetic energy; these carriers are then called hot carriers. The degradation of MOS devices induced by hot carrier injection is caused by the injection of high-energy electrons and holes into the gate oxide layer. During injection, interface states and trapped charges in the oxide layer are generated, causing damage. As the degree of damage increases, the current-voltage characteristics of the device change. When the device parameters change beyond a certain limit, the device will fail. The degree and mechanism of device damage depend on the device's operating conditions.

[0003] Under normal circumstances, when a large current needs to pass through the MOSFET switch, a very large source-drain voltage difference will be generated at the instant the switch is closed and the MOSFET is turned on, resulting in the HCI effect, which has a significant impact on various parameters of the MOSFET.

[0004] Therefore, it is urgent to propose a switching circuit and method to suppress the hot carrier injection effect in order to solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to propose a switching circuit and method for suppressing the hot carrier injection effect, which can effectively suppress the hot carrier injection effect while realizing high current transmission.

[0006] To solve the above-mentioned technical problems, the present invention provides a switching circuit for suppressing hot carrier injection effect, including a first switching transistor and a second switching transistor array; the second switching transistor array includes a plurality of switching transistors connected in parallel, the first switching transistor is connected in parallel with the second switching transistor array, the conduction area of ​​the first switching transistor is smaller than the total conduction area of ​​the second switching transistor array, and the first switching transistor is configured to conduct before the second switching transistor array.

[0007] Furthermore, both the first switching transistor and the switching transistor are NMOS transistors.

[0008] Furthermore, the first switching transistor is a long-channel NMOS transistor.

[0009] Furthermore, the channel length of the first switching transistor ranges from 0.5 μm to 1.0 μm, and the channel width ranges from 10 μm to 50 μm.

[0010] Furthermore, the switching transistor is a short-channel NMOS transistor.

[0011] Furthermore, the channel length of the switching transistor ranges from 0.3 μm to 0.5 μm, and the channel width ranges from 10 μm to 50 μm.

[0012] Furthermore, the ratio of the conduction area of ​​the first switch to the total conduction area of ​​the second switch array is 1:10 to 1:1000.

[0013] Furthermore, this invention also proposes a method for suppressing the hot carrier injection effect, using a switching circuit for suppressing the hot carrier injection effect as described above, specifically including the following:

[0014] When current needs to be conducted, the first switch is first controlled to be turned on, so that the current flows through the first switch and the voltage difference between the source and drain of the second switch array is reduced.

[0015] After a preset delay time after the first switch is turned on, the second switch array is then turned on, allowing current to flow through the second switch array.

[0016] Furthermore, the turn-on time of the first switch is 0.5 ns to 10 ns earlier than the turn-on time of the second switch array.

[0017] Furthermore, the switching circuit is used to output the current to the chip pins or the IP module inside the chip.

[0018] Through the above technical solution, the present invention has the following beneficial effects:

[0019] By employing a first-turn-on approach, a current path can be established before the second-turn-on array is turned on, reducing the voltage difference across the switch. This effectively lowers the source-drain voltage across the second-turn-on array at the moment of turn-on, suppressing the hot carrier injection effect. Simultaneously, due to the large total conduction area of ​​the second-turn-on array, it provides a sufficiently small on-resistance after turn-on, meeting the requirements for high current transmission and maintaining good current transmission performance while suppressing the hot carrier injection effect.

[0020] Furthermore, by employing a long-channel NMOS transistor as the first switch, the channel electric field strength during the first switch's conduction can be further reduced, improving circuit reliability. Using short-channel NMOS transistors to form the second switch array reduces on-resistance, power consumption, and voltage drop. By optimizing the conduction area ratio and conduction timing of the first and second switch arrays, performance balance can be achieved in different application scenarios, enhancing the circuit's applicability and flexibility. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall structure of a switching circuit for suppressing the hot carrier injection effect in one embodiment of the present invention;

[0022] Figure 2 This is a flowchart of a method for suppressing the hot carrier injection effect in one embodiment of the present invention;

[0023] Figure 3 This is a timing diagram of a method for suppressing the hot carrier injection effect in one embodiment of the present invention. Detailed Implementation

[0024] Based on the teachings of this specification, those skilled in the art can form new technical solutions through cross-combination of different implementation methods without creating technical contradictions. Such variations should all be considered to fall within the protection scope of this invention.

[0025] The following description, in conjunction with the accompanying drawings, provides a more detailed account of a switching circuit and method for suppressing hot carrier injection effects according to the present invention, which illustrates preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0026] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0027] like Figure 1 As shown, an embodiment of the present invention proposes a switching circuit for suppressing the hot carrier injection effect, comprising a first switching transistor and a second switching transistor array.

[0028] Specifically, the second switch array includes multiple parallel-connected switching transistors. The first switch is connected in parallel with the second switch array. The conduction area of ​​the first switch is smaller than the total conduction area of ​​the second switch array. The first switch is configured to turn on before the second switch array. This embodiment, by employing the method of turning on the first switch first, establishes a current path before the second switch array turns on, reducing the voltage difference across the switch. This effectively reduces the source-drain voltage experienced by the second switch array at the moment of turn-on, suppressing the hot carrier injection effect. Simultaneously, because the second switch array has a large total conduction area, it can provide a sufficiently small on-resistance after turn-on, meeting the requirements of high current transmission and maintaining good current transmission performance while suppressing the hot carrier injection effect.

[0029] Preferably, both the first switching transistor and the switching transistor are NMOS transistors. The use of NMOS transistors in this embodiment provides better conduction characteristics and switching speed, making them suitable for high-current transmission scenarios.

[0030] In one embodiment, the first switch is a long-channel NMOS transistor. Long-channel NMOS transistors have a longer channel length, which effectively reduces the electric field strength within the channel, thereby improving the device's resistance to hot carrier injection effects. At the moment of turn-on, even with a large source-drain voltage difference, the long-channel structure can prevent hot carriers from gaining sufficiently high energy to inject into the gate oxide layer, helping to maintain the stability of device parameters.

[0031] In this embodiment, the channel length of the first switching transistor ranges from 0.5 μm to 1.0 μm, and the channel width ranges from 10 μm to 50 μm. Those skilled in the art will understand that these parameters can be adjusted according to actual needs, and other embodiments besides this one are also possible. In a specific example, when the channel length is selected as 0.6 μm and the channel width as 20 μm, the conduction area of ​​the first switching transistor is 12 μm. 2 This size provides sufficient resistance to the HCI effect while also establishing an effective current path during the initial conduction phase. The channel length, ranging from 0.5 μm to 1.0 μm, achieves a good balance between long-channel characteristics and area efficiency, enhancing the suppression of hot carrier injection effects while avoiding excessive area occupation.

[0032] Preferably, the switching transistor is a short-channel NMOS transistor. Short-channel NMOS transistors have a smaller channel length, providing lower on-resistance, thereby reducing power consumption and voltage drop during current transfer. Although short-channel devices are more susceptible to hot carrier injection effects, the timing control strategy of turning on the first switch in this embodiment effectively suppresses the HCI effect generated at the moment of turn-on of the short-channel NMOS transistor, enabling it to operate safely and reliably in high-current transfer scenarios.

[0033] In one embodiment, the channel length of the switching transistor ranges from 0.3 μm to 0.5 μm, and the channel width ranges from 10 μm to 50 μm. Those skilled in the art will understand that these parameters can be set according to actual application scenarios and current requirements, and other embodiments besides this one are also possible. In a specific example, when the channel length of a single switching transistor is 0.4 μm and the channel width is 20 μm, its conduction area is 8 μm². 2By connecting multiple such switching transistors in parallel to form a second switching array, for example, 100 transistors in parallel, the total conduction area can reach 800 μm. 2 This allows it to meet the high current transmission requirements of 100mA. The short-channel design reduces on-resistance, improves current transmission efficiency, and reduces power consumption.

[0034] In this embodiment, the ratio of the conduction area of ​​the first switch to the total conduction area of ​​the second switch array is 1:10 to 1:1000. Those skilled in the art will understand that this ratio can be adjusted according to the specific current magnitude and application requirements, and other embodiments besides this one are also possible.

[0035] In a specific example, when the conduction area of ​​the first switching transistor is 12 μm 2 The total conduction area of ​​the second switch array is 800 μm. 2 At this point, the area ratio of the two transistors is approximately 1:67. This area ratio setting can provide sufficient pre-conduction capability while saving chip area. Although the first switching transistor has a smaller area, its long-channel characteristics enable it to establish a stable current path in the early stages of conduction, reducing the voltage difference across the second switching transistor array and effectively suppressing the HCI effect. When a larger current needs to be transmitted, the number of transistors in the second switching transistor array can be appropriately increased to achieve an area ratio of 1:100 or even higher to meet the needs of larger current transmission. Conversely, for low-current applications, the number of transistors in the second switching transistor array can be reduced to achieve an area ratio close to 1:10, further reducing chip area while meeting performance requirements.

[0036] In addition, such as Figure 2 As shown, this embodiment also proposes a method for suppressing the hot carrier injection effect, using a switching circuit for suppressing the hot carrier injection effect as described above, specifically including the following steps:

[0037] S1. When current needs to be conducted, first control the first switch to be turned on so that the current flows through the first switch and reduces the voltage difference between the source and drain of the second switch array.

[0038] S2. After a preset delay time after the first switch is turned on, the second switch array is turned on, so that current flows through the second switch array.

[0039] In this embodiment, the turn-on time of the first switch is 0.5 ns to 10 ns earlier than the turn-on time of the second switch array. In a specific example, when the time difference is set to 5 ns, the first switch can establish an effective current path between the source and drain within these 5 ns, allowing partial conduction of the charge and significantly reducing the source-drain voltage difference. If the time difference is too short, for example, less than 0.5 ns, the first switch may not have enough time to reduce the voltage difference, and the suppression effect will be weakened; if the time difference is too long, for example, more than 10 ns, although it can further reduce the voltage difference, it will prolong the overall current settling time and affect the circuit response speed. Therefore, choosing a time difference of 0.5 ns to 10 ns can achieve a good balance between HCI suppression effect and circuit response speed. For applications with large current, the time difference can be appropriately extended to 8-10 ns to enhance the suppression effect; for applications with high response speed requirements, the time difference can be shortened to 1-2 ns to improve the switching speed while meeting basic suppression requirements.

[0040] In one embodiment, the control signals for the first switch and the second switch array can be generated by a timing control circuit. Specifically, the timing control circuit receives an enable signal, and when it detects that current needs to be turned on, it first generates a first control signal to turn on the first switch. After a preset delay time, it then generates a second control signal to turn on the second switch array. The timing control circuit can be implemented using various methods such as a delay chain, a counter, or a programmable delay unit. In a specific example, a digital delay chain can be used, which achieves precise nanosecond-level delay control by connecting multiple inverters in series. The delay time of each inverter is approximately 0.1-0.2 ns, and an adjustable delay from 0.5 ns to 10 ns can be achieved by selecting different numbers of inverters. This timing control method is simple to implement, occupies a small area, and helps reduce circuit costs.

[0041] In one embodiment, the switching circuit is used to output the current to a chip pin or an internal IP module. This switching circuit is suitable for various integrated circuit applications requiring high current output. When used to output current to a chip pin, it can provide a stable and reliable high-current power supply to an external load, while suppressing the damage of the HCI effect to the output switch, thus improving the long-term reliability of the chip. When used to power an internal IP module, it enables efficient current transfer between modules, reducing power consumption and voltage drop during the transfer process, and improving the overall circuit performance.

[0042] More specifically, in this embodiment, the first switch NM1 and the second switch array (NM0) <1> ~NM0 <n>The two are connected in parallel, with their sources connected to the output of the high current generation module and their drains connected to the current output node Iout, which outputs to the chip pins or other IP modules. On the gate side, NM1 is controlled by the pilot control signal φ1_early, and the second switch array is controlled by the control signal φ1. φ1_early is turned on before φ1 to achieve timing control.

[0043] In this embodiment, when a large current in the mA range needs to pass through the switching transistor array, the current charge generated by the current generation module will accumulate at the sources of the first and second switching transistor arrays. At this time, if the second switching transistor array is directly turned on, because it is a short-channel NMOS transistor, it will experience a large source-drain voltage difference at the moment of turn-on. Combined with the large amount of charge accumulating at the source, this will cause hot carriers to gain high energy, resulting in a severe HCI effect. Hot carriers will then rush into the gate, affecting important parameters such as the threshold voltage of the transistor. To suppress this phenomenon, this embodiment employs a timing control strategy, turning on the first switching transistor first. Since the first switching transistor is a long-channel NMOS transistor, it has strong resistance to the HCI effect and can safely transmit current in the initial stage of turn-on. Although the conduction area of ​​the first switching transistor is small and the current flow rate is relatively slow, it can effectively reduce the voltage difference between the source and drain. After the first switch has been turned on for a period of time, some of the charge accumulated at the source has flowed to the drain through the first switch. When the second switch array is turned on at this time, the voltage difference between its source and drain has been greatly reduced, and the hot carrier injection phenomenon is effectively suppressed, thereby improving the reliability and service life of the second switch array.

[0044] like Figure 2 and Figure 3 As shown, for example, the size of the switching transistor (i.e., NM0) in the second switching transistor array is set to 20μm / 0.4μm, with a multiplier of 100, meaning the actual total conduction area is 800μm. 2 The first switching transistor (NM1) has dimensions of 20μm / 0.6μm and a conduction area of ​​12μm. 2 The required current Iout is set to 100mA. The specific working steps are as follows:

[0045] First, a large current of 100mA is generated through a current generation module. This current needs to be output to the chip pins or other internal IP modules via a switching transistor to provide operating current. In the initial state, neither NM0 nor NM1 is turned on, and the charge generated by the current accumulates at the sources of NM0 and NM1. At this time, there is a large potential difference between the source and drain.

[0046] After a 1μs delay, the timing control circuit first turns on NM1, and current begins to flow through NM1 to the drain. Because NM1 is a long-channel transistor with a large channel length, it effectively reduces the electric field strength within the channel, thus avoiding the effects of the HCl effect and ensuring safe and stable operation. However, the conduction area of ​​NM1 is relatively small, only 12μm. 2 Its on-resistance is relatively large, and the current flow rate is slow, which cannot immediately meet the fast transmission requirements of a large current of 100mA. However, during the conduction of NM1, some of the charge accumulated at the source has already flowed to the drain through NM1, causing the voltage difference between the source and drain of NM0 to gradually decrease.

[0047] After NM1 is turned on for 5ns, the timing control circuit turns on the large array of NM0 switches. Since NM0 has an 800μm... 2 With its large conduction area and short-channel characteristic of 0.4μm, the NM0 has very low on-resistance, allowing current to pass through quickly and rapidly complete the 100mA current transfer task. Although the NM0 is a short-channel NMOS transistor, it will experience a severe hot carrier injection effect when subjected to a large current surge during normal conduction. However, because the NM1 has already turned on and established a current path, the voltage difference between the source and drain of the NM0 is significantly reduced. Under the condition of a lower source-drain voltage difference, the energy gained by carriers drifting in the channel is reduced, and the phenomenon of hot carrier injection into the gate oxide layer is effectively suppressed. This suppresses the HCI effect, and the threshold voltage, transconductance, and other important parameters of the NM0 do not change significantly, improving the reliability and lifespan of the device. The entire current transfer process is completed smoothly, meeting the requirements of high-current rapid transfer while avoiding the damage to device performance caused by the HCI effect.

[0048] In summary, the switching circuit and method for suppressing the hot carrier injection effect proposed in this invention have the following advantages:

[0049] By employing a first-turn-on approach, a current path can be established before the second-turn-on array is turned on, reducing the voltage difference across the switch. This effectively lowers the source-drain voltage across the second-turn-on array at the moment of turn-on, suppressing the hot carrier injection effect. Simultaneously, due to the large total conduction area of ​​the second-turn-on array, it provides a sufficiently small on-resistance after turn-on, meeting the requirements for high current transmission and maintaining good current transmission performance while suppressing the hot carrier injection effect.

[0050] Furthermore, by employing a long-channel NMOS transistor as the first switch, the channel electric field strength during the first switch's conduction can be further reduced, improving circuit reliability. Using short-channel NMOS transistors to form the second switch array reduces on-resistance, power consumption, and voltage drop. By optimizing the conduction area ratio and conduction timing of the first and second switch arrays, performance balance can be achieved in different application scenarios, enhancing the circuit's applicability and flexibility.

[0051] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.< / n>

Claims

1. A switching circuit for suppressing hot carrier injection effect, characterized in that, It includes a first switching transistor and a second switching transistor array; the second switching transistor array includes a plurality of switching transistors connected in parallel, the first switching transistor is connected in parallel with the second switching transistor array, the conduction area of ​​the first switching transistor is smaller than the total conduction area of ​​the second switching transistor array, and the first switching transistor is configured to conduct before the second switching transistor array. Both the first switching transistor and the second switching transistor are NMOS transistors. The first switching transistor is a long-channel NMOS transistor, and the second switching transistor is a short-channel NMOS transistor. The control signals for the first switching transistor and the second switching transistor array are generated by a timing control circuit. The timing control circuit receives an enable signal, generates a first control signal to turn on the first switching transistor, and after a preset delay time, generates a second control signal to turn on the second switching transistor array.

2. The switching circuit for suppressing hot carrier injection effect as described in claim 1, characterized in that, The channel length of the first switching transistor ranges from 0.5 μm to 1.0 μm, and the channel width ranges from 10 μm to 50 μm.

3. The switching circuit for suppressing hot carrier injection effect as described in claim 1, characterized in that, The channel length of the switching transistor ranges from 0.3 μm to 0.5 μm, and the channel width ranges from 10 μm to 50 μm.

4. The switching circuit for suppressing hot carrier injection effect as described in claim 1, characterized in that, The ratio of the conduction area of ​​the first switch to the total conduction area of ​​the second switch array is 1:10 to 1:1000.

5. A method for suppressing the hot carrier injection effect, using a switching circuit for suppressing the hot carrier injection effect as described in any one of claims 1-4, characterized in that, Specifically, it includes the following: When current needs to be conducted, the first switch is first turned on to allow current to flow through the first switch, thereby reducing the voltage difference between the source and drain of the second switch array. After a preset delay time after the first switch is turned on, the second switch array is then turned on, allowing current to flow through the second switch array.

6. The method for suppressing the hot carrier injection effect as described in claim 5, characterized in that, The turn-on time of the first switch is 0.5 ns to 10 ns earlier than the turn-on time of the second switch array.

7. The method for suppressing the hot carrier injection effect as described in claim 5, characterized in that, The switching circuit is used to output the current to the chip pins or the IP module inside the chip.

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