Display panel and display device

Abstract

A display panel and a display device are provided, the display panel including: a first bypass wiring electrically coupled to a main pixel circuit in a first direction and bypassing along a side of a pixel group at an outermost of an assembly area; a horizontal wiring electrically coupled to the main pixel circuit and an auxiliary pixel circuit and extending in the first direction; and an extension wiring between two pixel groups adjacent to each other along the first direction and extending in the first direction, wherein the extension wiring is electrically coupled to the horizontal wiring included in each of the two pixel groups, and a number of the extension wiring is less than a number of the horizontal wiring.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0056149, filed on May 11, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display panel and a display device including the display panel, and for example to a display panel including an extended display area so as to display images even in an area where components as electronic elements are placed, and a display device including the display panel. Background Technology

[0004] In recent years, the use of display devices has become more diversified and increased. Furthermore, as display devices have become thinner and lighter, their applications are expanding.

[0005] As display devices are used in various ways, there are various methods for designing the shape of display devices, and the functions that are combined with or linked to display devices are increasing. Summary of the Invention

[0006] One or more embodiments provide a display panel and a display device including the display panel, the display panel including an extended display area to display images even in areas where components, as electronic elements, are placed. However, these features are exemplary, and the scope of this disclosure is not limited by these features.

[0007] Additional aspects of the embodiments will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented.

[0008] According to one aspect of an embodiment of the present disclosure, a display panel may include: a substrate; a main display element and a main pixel circuit, the main display element being on the substrate and corresponding to a main display area, the main pixel circuit being coupled to the main display element; an auxiliary display element and an auxiliary pixel circuit, the auxiliary display element being on the substrate and corresponding to a pixel group, the auxiliary pixel circuit being coupled to the auxiliary display element; a first bypass wiring electrically coupled to the main pixel circuit in a first direction and bypassing one side of a pixel group in the pixel group at the outermost part of a component region, the component region including the pixel groups spaced apart from each other and including a transmissive region between the pixel groups; a horizontal wiring electrically coupled to the main pixel circuit and the auxiliary pixel circuit and extending in the first direction; and an extension wiring between two adjacent pixel groups along the first direction and extending in the first direction, wherein the extension wiring is electrically coupled to the horizontal wiring included in each of the two pixel groups, and the number of extension wirings is less than the number of horizontal wirings.

[0009] In one embodiment, the first bypass wiring may be bent into a stepped shape along the periphery of the pixel group at the outermost part of the component region.

[0010] In one embodiment, the first bypass wiring may be bent into a stepped shape along the inner side of the pixel group at the outermost part of the component region.

[0011] In one embodiment, on a plane, the width of the area where the extended wiring is arranged along a second direction perpendicular (e.g., substantially perpendicular) to the first direction is smaller than the width of the area where the horizontal wiring is arranged along the second direction.

[0012] In an embodiment, each auxiliary pixel circuit in the auxiliary pixel circuit may include a driving thin-film transistor, a first initialization thin-film transistor, and a second initialization thin-film transistor. The first initialization thin-film transistor initializes the voltage of the driving gate electrode of the driving thin-film transistor, and the second initialization thin-film transistor initializes the pixel electrode of the auxiliary display element. The horizontal wiring may include a first initialization voltage line and a second initialization voltage line. The first initialization voltage line transmits the initialization voltage to the first initialization thin-film transistor, and the second initialization voltage line transmits the initialization voltage to the second initialization thin-film transistor. The first initialization voltage line and the second initialization voltage line may be electrically coupled to each other through a first connection line.

[0013] In one embodiment, the first connecting line may be on a different layer than the horizontal wiring.

[0014] In an embodiment, each pixel group in the pixel group may include a first row and a second row, in which auxiliary sub-pixels are arranged along the first direction, the first auxiliary sub-pixel included in the first row and the second auxiliary sub-pixel included in the second row may be adjacent to each other along a second direction perpendicular to (e.g., substantially perpendicular to) the first direction, and the second initialization voltage line may be shared by the first auxiliary sub-pixel and the second auxiliary sub-pixel.

[0015] In one embodiment, the second initialization voltage line can be electrically coupled to the first initialization thin-film transistor of the second auxiliary sub-pixel.

[0016] In an embodiment, the horizontal wiring may further include: a third initialization voltage line, which intersects the second row in the first direction, and the third initialization voltage line applies an initialization voltage to the second initialization thin-film transistor of the second auxiliary sub-pixel, and the third initialization voltage line may be electrically coupled to the first connection line.

[0017] In an embodiment, the display panel may further include: a second bypass wiring, which is electrically coupled to the main pixel circuit in a second direction intersecting the first direction and bypasses one side of the pixel group at the outermost part of the component region.

[0018] In one embodiment, the second bypass wiring may be bent into a stepped shape.

[0019] In an embodiment, the display panel may further include a lower metal layer in the component region and between the substrate and the auxiliary pixel circuit driving the auxiliary sub-pixels, wherein the lower metal layer includes a lower aperture corresponding to the transmissive region.

[0020] According to one aspect of an embodiment of the present disclosure, a display device may include: a display panel including a main display area and a component area, the main display area including a main sub-pixel, the component area including a plurality of pixel groups and a transmissive area; and a component below the display panel corresponding to the component area, wherein the display panel includes: a substrate; a first bypass wiring electrically coupled to the main sub-pixel in a first direction and bypassing one side of a pixel group at the outermost edge of the component area; a horizontal wiring electrically coupled to the main sub-pixel and the plurality of pixel groups and extending in the first direction; and an extension wiring between two adjacent pixel groups in the plurality of pixel groups along the first direction and extending in the first direction, wherein the extension wiring is electrically coupled to the horizontal wiring included in each of the two pixel groups, and the number of extension wirings is less than the number of horizontal wirings.

[0021] In one embodiment, the first bypass wiring may be bent into a stepped shape along the periphery of the pixel group at the outermost part of the component region.

[0022] In one embodiment, the first bypass wiring may be bent into a stepped shape along the inner side of the pixel group at the outermost part of the component region.

[0023] In one embodiment, on a plane, the width of the area where the extended wiring is arranged along a second direction perpendicular (e.g., substantially perpendicular) to the first direction is smaller than the width of the area where the horizontal wiring is arranged along the second direction.

[0024] In an embodiment, the display panel may further include: auxiliary display elements and auxiliary pixel circuits. The auxiliary display elements are on the substrate and correspond to the pixel groups respectively, and the auxiliary pixel circuits are respectively coupled to the auxiliary display elements. Each auxiliary pixel circuit may include a driving thin-film transistor, a first initialization thin-film transistor, and a second initialization thin-film transistor. The first initialization thin-film transistor initializes the voltage of the driving gate electrode of the driving thin-film transistor, and the second initialization thin-film transistor initializes the pixel electrode of the auxiliary display element. The horizontal wiring includes a first initialization voltage line and a second initialization voltage line. The first initialization voltage line transmits the initialization voltage to the first initialization thin-film transistor, and the second initialization voltage line transmits the initialization voltage to the second initialization thin-film transistor. The first initialization voltage line and the second initialization voltage line are electrically coupled to each other through a first connection line.

[0025] In one embodiment, the first connecting line may be on a different layer than the horizontal wiring.

[0026] In an embodiment, each of the plurality of pixel groups may include a first row and a second row, in which a plurality of auxiliary sub-pixels are arranged along the first direction, the first auxiliary sub-pixel included in the first row and the second auxiliary sub-pixel included in the second row may be adjacent to each other along a second direction perpendicular to (e.g., substantially perpendicular to) the first direction, and the second initialization voltage line may be shared by the first auxiliary sub-pixel and the second auxiliary sub-pixel.

[0027] In an embodiment, the horizontal wiring may further include a third initialization voltage line that intersects the second row in the first direction, and the third initialization voltage line applies an initialization voltage to the second initialization thin-film transistor of the second auxiliary sub-pixel, and the third initialization voltage line may be electrically coupled to the first connection line. Attached Figure Description

[0028] The above and other aspects and features of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a schematic diagram illustrating a perspective view of a display device according to an embodiment;

[0030] Figure 2 This is a schematic cross-sectional view illustrating a portion of a display device according to an embodiment;

[0031] Figure 3 These are schematic illustrations and may include, according to embodiments, the following: Figure 1 A plan view of the display panel in the display device;

[0032] Figure 4 This is an equivalent circuit diagram of a pixel circuit for driving sub-pixels according to an embodiment;

[0033] Figure 5 This is a plan view of the pixel circuit of a pixel according to an embodiment;

[0034] Figure 6 This is a schematic diagram illustrating the pixel arrangement structure in the main display area according to an embodiment;

[0035] Figure 7A and Figure 7B It is a schematic diagram illustrating the layout of the pixel arrangement structure in the component area according to an embodiment;

[0036] Figure 8These are schematic cross-sectional views illustrating a portion of the display panel according to an embodiment, and schematic cross-sectional views illustrating the main display area and component areas;

[0037] Figure 9 This is a schematic diagram illustrating the arrangement of sub-pixels and some wiring of the main display area according to an embodiment.

[0038] Figure 10 This is a schematic diagram illustrating the arrangement of sub-pixels and some wiring of the main display area according to an embodiment.

[0039] Figure 11 It is a schematic plan view illustrating the arrangement of wiring coupled to a pixel group according to an embodiment; and

[0040] Figure 12 This is a schematic diagram illustrating the arrangement of sub-pixels and some wiring of the main display area of ​​the display panel according to an embodiment. Detailed Implementation

[0041] Reference will now be made in more detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals consistently denote the same elements. In this regard, embodiments may take different forms and will not be construed as limited to the description set forth herein. Accordingly, embodiments are described below only by reference to the accompanying drawings to explain aspects of the embodiments described herein. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0042] This disclosure may include various modifications and may include various embodiments, and specific embodiments will be illustrated in the accompanying drawings and described in more detail in the detailed description. The effects and features of this disclosure, as well as methods for achieving these effects and features, will be illustrated by referring to the embodiments described below in more detail with reference to the accompanying drawings. However, the subject matter of this disclosure is not limited to the embodiments disclosed below, but can be implemented in various suitable forms.

[0043] In the following description, embodiments will be described in more detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components will be given the same reference numerals, and redundant descriptions of the same or corresponding components may be avoided.

[0044] In the following embodiments, when various components such as layers, films, regions, plates, etc., are referred to as being "on" another component, this includes not only when the component is "directly" on another component, but also when an intermediate component exists between the component and another component. Additionally, for ease of description, the dimensions of components may be enlarged or reduced in the drawings. For example, since the dimensions and thicknesses of each component shown in the drawings may be arbitrarily shown for ease of description, the embodiments are not necessarily limited to what is shown.

[0045] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can refer to different directions that are not orthogonal to each other.

[0046] Figure 1 This is a schematic perspective view of a display device 1 according to an embodiment.

[0047] refer to Figure 1 The display device 1 includes a display area DA and a peripheral area DPA outside the display area DA. The display area DA includes a component area CA and a main display area MDA that at least partially surrounds the component area CA. For example, each of the component area CA and the main display area MDA can display an image individually or together. The peripheral area DPA can be a non-display area without display elements. The display area DA can be completely surrounded by the peripheral area DPA.

[0048] Figure 1 A component region CA is shown in the main display area MDA. In another embodiment, the display device 1 may include two or more component regions CA, and the multiple component regions CA may have different shapes and sizes from each other. When viewed in a direction substantially perpendicular to the upper surface of the display device 1, the component region CA may have a variety of suitable shapes, including circles, ellipses, polygons such as rectangles, stars, or rhombuses. Figure 1 In the present invention, when viewed in a direction substantially perpendicular to the upper surface of the display device 1, the component region CA is located at the upper center (+ second direction y) of the main display area MDA, which is substantially rectangular in shape. However, the component region CA may be on one side of the rectangular main display area MDA, for example, on the upper right or upper left side of the rectangular main display area MDA.

[0049] Display device 1 can provide an image using multiple primary sub-pixels Pm in the main display area MDA and multiple auxiliary sub-pixels Pa in the component area CA.

[0050] In the component area CA, as referenced below in this article. Figure 2As described, component 40, as an electronic element, may correspond to component region CA below display panel 10. Component 40 may be a camera using infrared and / or visible light and may include an imaging device. In some embodiments, component 40 may be a solar cell, a flash, an illuminance sensor, a proximity sensor, and / or an iris sensor. In some embodiments, component 40 may provide the function of receiving audio. To reduce limitations on the functionality of component 40, component region CA includes a transmission region TA through which light and / or audio, etc., output from component 40 to the outside or traveling from the outside toward component 40, may be transmitted. In the case of display panel and display device including display panel according to embodiments, when light is transmitted through component region CA, the light transmittance may be approximately 10% or greater, approximately 40% or greater, approximately 25% or greater, approximately 50% or greater, approximately 85% or greater, or approximately 90% or greater.

[0051] Multiple auxiliary subpixels Pa can exist in the component region CA. These auxiliary subpixels Pa emit light to provide a preset image. The image displayed in the component region CA is an auxiliary image and may have a lower resolution than the image displayed in the main display region MDA. For example, the component region CA includes a transmissive region TA through which light and audio can pass, and when a subpixel is not on or in the transmissive region TA, the number of auxiliary subpixels Pa that can be included per unit area may be less than the number of primary subpixels Pm included per unit area in or in the main display region MDA.

[0052] Figure 2 This is a schematic cross-sectional view of a portion of the display device 1 according to an embodiment.

[0053] refer to Figure 2 The display device 1 may include a display panel 10 and a component 40, wherein the component 40 overlaps with or is overlapped by the display panel 10. A cover window protecting the display panel 10 may be further located on the display panel 10.

[0054] The display panel 10 includes a component area CA and a main display area MDA for displaying the main image. The component area CA is the area that overlaps with the component 40. The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical functional layer OFL, and a panel protection member PB below the substrate 100.

[0055] The display layer DISL may include: a circuit layer PCL comprising thin-film transistors TFTs and TFT'; a display element layer EDL comprising light-emitting elements EDs and ED' as display elements; and a sealing member ENCM such as a thin-film encapsulation layer TFEL or a sealing substrate. An insulating layer IL may be in the display layer DISL, and an insulating layer IL' may be between the substrate 100 and the display layer DISL.

[0056] The substrate 100 may include insulating materials such as glass, quartz, and / or polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate capable of being bent, folded, and / or rolled.

[0057] The main thin-film transistor (TFT) and the main light-emitting element (ED) coupled to the main TFT can be located in the main display area MDA of the display panel 10 to realize the main sub-pixel Pm. In the component area CA, an auxiliary thin-film transistor (TFT) and an auxiliary light-emitting element (ED) coupled to the auxiliary TFT can be included to realize the auxiliary sub-pixel Pa. The area containing the auxiliary sub-pixel Pa in the component area CA can be referred to as the auxiliary display area ADA.

[0058] Additionally, a transmissive region TA without a display element may be located within the component region CA. The transmissive region TA can be the area through which light / signals emitted from the component 40 corresponding to the component region CA and / or incident on the component 40 are transmitted. The auxiliary display region ADA and the transmissive region TA may be arranged alternately within the component region CA.

[0059] A lower metal layer (BML) may be located within the component region CA. The lower metal layer (BML) may be positioned corresponding to the lower portion of the auxiliary thin-film transistor (TFT) '. For example, the lower metal layer (BML) may be located between the auxiliary thin-film transistor (TFT) ' and the substrate 100. This lower metal layer (BML) may prevent or reduce external light penetration into the auxiliary thin-film transistor (TFT) '. In some embodiments, a constant voltage and / or signal may be applied to the lower metal layer (BML) to prevent or reduce damage to the pixel circuitry due to electrostatic discharge.

[0060] The display element layer (EDL) can be covered by a thin-film encapsulation layer (TFEL) and / or a sealing substrate. In some embodiments, such as Figure 2 As shown, the thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer 131, a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133.

[0061] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may include one or more inorganic insulating materials, such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The organic encapsulation layer 132 may include polymer-based materials. Polymer-based materials may include acrylic resins, epoxy resins, polyimides, and / or polyethylene.

[0062] When the display element layer EDL is sealed with a sealing substrate, the sealing substrate may face the substrate 100, and the display element layer EDL is located between the sealing substrate and the substrate 100. A gap may exist between the sealing substrate and the display element layer EDL. The sealing substrate may include glass. A sealant including glass frit, etc., may be present between the substrate 100 and the sealing substrate, and the sealant may be in the peripheral area DPA as described above. The sealant placed in the peripheral area DPA can prevent or reduce moisture penetration through the side surfaces while surrounding the display area DA.

[0063] A touchscreen layer (TSL) can obtain or determine coordinate information based on external inputs such as touch events. A TSL may include touch electrodes and touch wiring coupled to the touch electrodes. The TSL can detect external inputs using self-capacitance or mutual capacitance methods.

[0064] The touchscreen layer TSL can be formed on the thin-film encapsulation layer TFEL. In some embodiments, the touchscreen layer TSL can be formed separately on the touch substrate and then bonded to the thin-film encapsulation layer TFEL by an adhesive layer such as, for example, optically clear adhesive (OCA). As an embodiment, the touchscreen layer TSL can be formed directly on the thin-film encapsulation layer TFEL, and in this case, the adhesive layer may not be between the touchscreen layer TSL and the thin-film encapsulation layer TFEL.

[0065] The optical functional layer OFL may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (external light) incident from the outside toward the display device 1.

[0066] In some embodiments, the optical functional layer OFL can be a polarizing film. The optical functional layer OFL may include an opening OFL_OP corresponding to the transmission region TA. Accordingly, the light transmittance of the transmission region TA can be significantly improved. A transparent material, such as, for example, optically transparent resin (OCR), can fill the opening OFL_OP.

[0067] In some embodiments, the optical functional layer OFL may include a filter plate, which includes a black matrix and color filters.

[0068] A cover window can be placed on top of the display panel 10 to protect it. The optical functional layer OFL can be attached to the cover window using an optically clear adhesive, or it can be attached to the touchscreen layer TSL using an optically clear adhesive.

[0069] The panel protection member PB can be attached to the lower part of the substrate 100 and can support and protect the substrate 100. The panel protection member PB may include an opening PB_OP corresponding to the component region CA. By including the opening PB_OP in the panel protection member PB, it is possible to improve the light transmittance of the component region CA. The panel protection member PB may include polyethylene terephthalate (PET) and / or polyimide (PI).

[0070] The area of ​​component region CA can be larger than the area of ​​the region where component 40 is located. Correspondingly, the area of ​​the opening PB_OP provided in the panel protection component PB can be mismatched with the area of ​​component region CA.

[0071] Additionally, multiple components 40 may be located in the component area CA. These multiple components 40 may be functionally different from each other. For example, the multiple components 40 may include at least two of a camera (imaging device), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor.

[0072] Figure 3 These are schematic illustrations and may include, according to embodiments, the following: Figure 1 A plan view of the display panel 10 in the display device 1.

[0073] refer to Figure 3 The various components included in the display panel 10 are mounted on a substrate 100. The substrate 100 includes a display area DA and a peripheral area DPA surrounding the display area DA. The display area DA includes a main display area MDA and a component area CA. The main image is displayed in the main display area MDA, and the component area CA includes a transmissive area TA and an auxiliary image is displayed in the component area CA. The auxiliary image may form a single image together with the main image, and / or the auxiliary image may be an image independent of the main image.

[0074] The main display area (MDA) includes multiple main sub-pixels (Pm). Each of the main sub-pixels (Pm) can be implemented as a display element such as, for example, an organic light-emitting diode (OLED). For example, each main sub-pixel (Pm) can emit red, green, blue, or white light. The main display area (MDA) is covered by a sealing member and can be protected from external air or moisture by the sealing member.

[0075] The component region CA can be located on one side of the main display region MDA as described above, or it can be inside the display region DA and surrounded by the main display region MDA. Multiple auxiliary sub-pixels Pa are located within the component region CA. Each of the multiple auxiliary sub-pixels Pa can be implemented by (or included in) a display element such as an organic light-emitting diode (OLED). For example, each auxiliary sub-pixel Pa can emit red, green, blue, or white light. The component region CA is covered by a sealing component and can be protected from external air or moisture by the sealing component.

[0076] In some embodiments, the component region CA may include a transmission region TA. The transmission region TA may surround a plurality of auxiliary sub-pixels Pa. In some embodiments, the transmission region TA may be in a grid shape with the plurality of auxiliary sub-pixels Pa.

[0077] Because the component area CA includes the transmission area TA, the resolution of the component area CA will be lower than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, 1 / 16, etc., of the resolution of the main display area MDA. For example, the resolution of the main display area MDA can be approximately 400 ppi or greater, and the resolution of the component area CA can be approximately 200 ppi or approximately 100 ppi (e.g., approximately 200 ppi or less, or approximately 100 ppi or less).

[0078] The pixel circuits driving sub-pixels Pm and Pa can be electrically coupled to external circuits in the peripheral region DPA. The peripheral region DPA may include a first scan drive circuit SDRV1, a second scan drive circuit SDRV2, a terminal unit PAD, a drive voltage supply line 11, and a common voltage supply line 13.

[0079] The first scan driving circuit SDRV1 can apply a scan signal to each of the pixel circuits driving sub-pixels Pm and Pa via the second scan line SL. The first scan driving circuit SDRV1 can apply an emission control signal to each pixel circuit via the emission control line EL. The second scan driving circuit SDRV2 can be located on the opposite side of the first scan driving circuit SDRV1 around the main display area MDA, and can be substantially parallel to the first scan driving circuit SDRV1. Some pixel circuits in the pixel circuit of the main sub-pixel Pm of the main display area MDA can be electrically coupled to the first scan driving circuit SDRV1, and other pixel circuits can be electrically coupled to the second scan driving circuit SDRV2. Some pixel circuits in the pixel circuit of the auxiliary sub-pixel Pa of the component area CA can be electrically coupled to the first scan driving circuit SDRV1, and other pixel circuits can be electrically coupled to the second scan driving circuit SDRV2. In some embodiments, the second scan driving circuit SDRV2 can be omitted.

[0080] The terminal unit PAD can be located on one side of the substrate 100. The terminal unit PAD is exposed and not covered by an insulating layer, and is coupled to the display circuit board 30. The display driver 32 can be located on the display circuit board 30.

[0081] The display driver 32 can generate control signals to be transmitted to the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. The display driver 32 generates data signals, and the generated data signals can be transmitted to the pixel circuits of sub-pixels Pm and Pa through the fan-out wiring FW and the data line DL coupled to the fan-out wiring FW.

[0082] The display driver 32 can drive voltage ELVDD (see...) Figure 4 ) is supplied to drive voltage supply line 11, and the common voltage ELVSS (see Figure 4 Supply to common voltage supply line 13. Drive voltage ELVDD (see...) Figure 4 The pixel circuits of sub-pixels Pm and Pa are applied through the drive voltage line PL coupled to the drive voltage supply line 11, and the common voltage ELVSS (see...) Figure 4 It can be supplied to the common voltage supply line 13 and applied to the counter electrode of the display element.

[0083] The driving voltage supply line 11 may extend at the bottom of the main display area MDA in the first direction x. The common voltage supply line 13 is a ring-shaped line with one side open and may partially surround the main display area MDA.

[0084] although Figure 3The illustration shows a scenario with one component region CA, but multiple component regions CA can be provided. In this case, the multiple component regions CA can be spaced apart from each other, and a first camera can be positioned corresponding to one component region CA, and a second camera can be positioned corresponding to another component region CA. In some embodiments, a camera can be positioned corresponding to one component region CA, and an infrared sensor can be positioned corresponding to another component region CA. The multiple component regions CA can be provided in different shapes and sizes.

[0085] In some embodiments, the component area CA can be provided as a polygon. For example, the component area CA can be provided in an octagonal shape. The component area CA can be provided in a polygonal shape of various suitable shapes such as, for example, squares or hexagons, but this disclosure is not limited thereto. The component area CA can be surrounded by a main display area MDA.

[0086] Figure 4 This is an equivalent circuit diagram of a pixel circuit PC for driving sub-pixels according to an embodiment.

[0087] refer to Figure 4 The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, a second initialization thin-film transistor T7, and a storage capacitor Cst.

[0088] exist Figure 4 In this embodiment, each pixel circuit PC includes signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL, but the example is not limited thereto. As another embodiment, at least one selected from signal lines SL, SL-1, SL+1, EL, and DL and / or the initialization voltage line VL may be shared with adjacent pixel circuit PCs.

[0089] The drain electrode of the driving thin-film transistor T1 can be electrically coupled to the emitting device (also known as the light-emitting element) ED via the emitter control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2 to supply drive current to the emitting device ED.

[0090] The gate electrode of the switching thin-film transistor T2 is coupled to the second scan line SL, and the source electrode is coupled to the data line DL. The drain electrode of the switching thin-film transistor T2 can be coupled to the drive voltage line PL via the operation control thin-film transistor T5, and is also coupled to the source electrode of the drive thin-film transistor T1.

[0091] The switching thin-film transistor T2 is turned on according to the scan signal Sn transmitted through the second scan line SL to perform a switching operation, thereby transmitting the data signal Dm transmitted to the data line DL to the source electrode of the driving thin-film transistor T1.

[0092] The gate electrode of the compensation thin-film transistor T3 can be coupled to the second scan line SL. The source electrode of the compensation thin-film transistor T3 can be coupled to the pixel electrode of the emitter device ED via the emitter control thin-film transistor T6, and simultaneously coupled to the drain electrode of the driving thin-film transistor T1. The drain electrode of the compensation thin-film transistor T3 can be coupled together to any electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn received via the second scan line SL, and is coupled to the gate and drain electrodes of the driving thin-film transistor T1 to connect the diode of the driving thin-film transistor T1.

[0093] The gate electrode of the first initialization thin-film transistor T4 can be coupled to the first scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be coupled to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be coupled together to any electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on according to the previous scan signal Sn-1 received through the first scan line SL-1, and transmits the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1 to perform an initialization operation for initializing the voltage of the gate electrode of the driving thin-film transistor T1.

[0094] The gate electrode of the operation control thin-film transistor T5 can be coupled to the emitter control line EL. The source electrode of the operation control thin-film transistor T5 can be coupled to the drive voltage line PL. The drain electrode of the operation control thin-film transistor T5 is coupled to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0095] The gate electrode of the emitter control thin-film transistor T6 can be coupled to the emitter control line EL. The source electrode of the emitter control thin-film transistor T6 can be coupled to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emitter control thin-film transistor T6 can be electrically coupled to the pixel electrode of the emitter device ED. The operation control thin-film transistor T5 and the emitter control thin-film transistor T6 are turned on concurrently (e.g., simultaneously) according to the emitter control signal En received through the emitter control line EL, and the drive voltage ELVDD is transmitted to the emitter device ED, and the drive current flows in the emitter device ED.

[0096] The gate electrode of the second initialization thin-film transistor T7 can be coupled to the third scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be coupled to the pixel electrode of the emitter ED. The drain electrode of the second initialization thin-film transistor T7 can be coupled to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the subsequent scan signal Sn+1 received through the third scan line SL+1, and initialize the pixel electrode of the emitter ED.

[0097] exist Figure 4 In this embodiment, the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are coupled to the first scan line SL-1 and the third scan line SL+1, respectively, but are not limited thereto. As another embodiment, the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can both be coupled to the first scan line SL-1 and can be driven according to the previous scan signal Sn-1.

[0098] The other electrode of the storage capacitor Cst can be coupled to the drive voltage line PL. One electrode of the storage capacitor Cst can also be coupled to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0099] The counter electrode (e.g., cathode) of the emitting device ED receives a common voltage ELVSS. The emitting device ED emits light by receiving a drive current from the driving thin-film transistor T1.

[0100] Pixel circuit PC is not limited to reference Figure 4 The number of thin-film transistors and storage capacitors, as well as the circuit design, are described, and the number and circuit design can be varied. The pixel circuits PC driving the main sub-pixel Pm and the auxiliary sub-pixel Pa can be provided identically (e.g., substantially identical to each other) or differently (e.g., different from each other).

[0101] Figure 5 This is a plan view of the pixel circuit PC of one pixel according to an embodiment.

[0102] refer to Figure 5 A driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7 are arranged along the semiconductor layer 1130. The semiconductor layer 1130 is on a substrate on which a buffer layer is formed, and the buffer layer comprises an inorganic insulating material.

[0103] Some regions of semiconductor layer 1130 correspond to the semiconductor layers of driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7. For example, it should be understood that the semiconductor layers of driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7 are coupled to each other and bent in various suitable shapes.

[0104] The semiconductor layer 1130 includes a channel region and source and drain regions on opposite sides of the channel region, and the source and drain regions can be understood as the source electrode and drain electrode of the corresponding thin-film transistor. For convenience, the source and drain regions are referred to as source electrode and drain electrode, respectively.

[0105] The driving thin-film transistor T1 includes a driving gate electrode G1 that overlaps with the driving channel region, and driving source electrode S1 and driving drain electrode D1 on opposite sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 has a curved shape, such as an omega (Ω) shape, allowing for the formation of a long channel length in a narrow space. When the driving channel region is long, the driving range of the gate voltage becomes wider, allowing for more precise control of the level of light emitted from the organic light-emitting diode (OLED) as an emission device, and thus improving display quality.

[0106] The switching thin-film transistor T2 includes a switching gate electrode G2 that overlaps with the switching channel region, and a switching source electrode S2 and a switching drain electrode D2 on opposite sides of the switching channel region. The switching drain electrode D2 can be coupled to the driving source electrode S1.

[0107] The compensation thin-film transistor T3 is a dual thin-film transistor and may include a compensation gate electrode G3 overlapping with two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 on opposite sides of each of the compensation gate electrodes G3. The compensation thin-film transistor T3 can be coupled to the driving gate electrode G1 of the driving thin-film transistor T1 via the node connection line 1174 described later.

[0108] The first initialization thin-film transistor T4 is a dual thin-film transistor and may include a first initialization gate electrode G4 that overlaps with two first initialization channel regions, and may include a first initialization source electrode S4 and a first initialization drain electrode D4 on opposite sides of the first initialization gate electrode G4.

[0109] The operation control thin-film transistor T5 may include an operation control gate electrode G5 overlapping with the operation control channel region, and may include an operation control source electrode S5 and an operation control drain electrode D5 on the opposite side of the operation control gate electrode G5. The operation control drain electrode D5 may be coupled to the drive source electrode S1.

[0110] The emitter control thin-film transistor T6 may include an emitter control gate electrode G6 overlapping with the emitter control channel region, and may include an emitter control source electrode S6 and an emitter control drain electrode D6 on the opposite side of the emitter control gate electrode G6. The emitter control source electrode S6 may be coupled to the drive drain electrode D1.

[0111] The second initialization thin-film transistor T7 may include a second initialization gate electrode G7 that overlaps with the second initialization channel region, and may include a second initialization source electrode S7 and a second initialization drain electrode D7 on the opposite side of the second initialization gate electrode G7.

[0112] The thin-film transistors described above can be coupled to signal lines SL, SL-1, SL+1, EL and DL, initialization voltage lines VL1 and VL2, and drive voltage line PL.

[0113] The second scan line SL, the first scan line SL-1, the third scan line SL+1, the emission control line EL, and the driving gate electrode G1 can be on the semiconductor layer 1130 as described above, with multiple insulating layers between the second scan line SL, the first scan line SL-1, the third scan line SL+1, the emission control line EL, and the driving gate electrode G1 and the semiconductor layer 1130.

[0114] The second scan line SL can extend along the first direction x. Some regions of the second scan line SL can correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, the regions of the second scan line SL that overlap with the channel regions of the switching thin-film transistor T2 and the compensation thin-film transistor T3 can be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0115] The first scan line SL-1 extends along the first direction x, but some regions may correspond to the first initialization gate electrode G4. For example, each region of the first scan line SL-1 that overlaps with the channel region of the first initialization thin-film transistor T4 may be the first initialization gate electrode G4.

[0116] The third scan line SL+1 extends along the first direction x, but some regions may correspond to the second initialization gate electrode G7. For example, each of the regions of the third scan line SL+1 that overlap with the channel region of the second initialization thin-film transistor T7 may be the second initialization gate electrode G7.

[0117] The emitter control line EL extends along a first direction x. One or more regions of the emitter control line EL may correspond to the operation control gate electrode G5 and the emitter control gate electrode G6, respectively. For example, the regions of the emitter control line EL that overlap with the channel regions of the operation control thin-film transistor T5 and the emitter control thin-film transistor T6 may be the operation control gate electrode G5 and the emitter control gate electrode G6, respectively.

[0118] The driving gate electrode G1 is a floating electrode and can be coupled to the compensation thin-film transistor T3 via the node connection line 1174 as described above.

[0119] The electrode voltage line HL can be arranged on the first scan line SL-1, the second scan line SL, the third scan line SL+1, the emission control line EL, and the driving gate electrode G1 as described above, with (multiple) insulating layers between the first scan line SL-1, the second scan line SL, the third scan line SL+1, the emission control line EL, the driving gate electrode G1, and the electrode voltage line HL.

[0120] The electrode voltage line HL may extend along a first direction x to intersect the data line DL and the drive voltage line PL. A portion of the electrode voltage line HL covers at least a portion of the drive gate electrode G1 and may form a storage capacitor Cst together with the drive gate electrode G1. For example, the drive gate electrode G1 may be the lower electrode CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may be the upper electrode CE2 of the storage capacitor Cst.

[0121] The upper electrode CE2 of the storage capacitor Cst is electrically coupled to the drive voltage line PL. In this regard, the electrode voltage line HL can be coupled to the drive voltage line PL via contact hole 1158. Therefore, the electrode voltage line HL can have the same (e.g., substantially the same) voltage level (constant voltage) as the drive voltage line PL. For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be understood as a lateral drive voltage line.

[0122] The driving voltage line PL extends along the second direction y, and the electrode voltage line HL electrically coupled to the driving voltage line PL extends along the first direction x, which intersects the second direction y. Therefore, multiple driving voltage lines PL and electrode voltage lines HL in the display area can realize a grid structure.

[0123] Data line DL, drive voltage line PL, initialization connection lines 1173a and 1173b, and node connection line 1174 can be on electrode voltage line HL, and (multiple) insulating layers are between data line DL, drive voltage line PL, initialization connection lines 1173a and 1173b, node connection line 1174 and electrode voltage line HL.

[0124] The data line DL extends in the second direction y and can be coupled to the switching source electrode S2 of the switching thin-film transistor T2 through the contact hole 1154. The portion of the data line DL can be understood as the switching source electrode.

[0125] The driving voltage line PL extends in the second direction y and is coupled to the electrode voltage line HL via contact hole 1158 as described above. Additionally, the driving voltage line PL can be coupled to the operation control thin-film transistor T5 via contact hole 1155. The driving voltage line PL can also be coupled to the operation control drain electrode D5 via contact hole 1155.

[0126] The first initialization voltage line VL1 can be coupled to the first initialization thin-film transistor T4 via the first initialization connection line 1173a, and the second initialization voltage line VL2 can be coupled to the second initialization thin-film transistor T7 via the second initialization connection line 1173b. For example, one end of the second initialization connection line 1173b can be coupled to the second initialization voltage line VL2 via contact hole 1151, and the other end can be coupled to the second initialization drain electrode D7 via contact hole 1152. Simultaneously, the first initialization voltage line VL1 and the second initialization voltage line VL2 can be electrically coupled to each other via coupling members and can have a constant voltage (e.g., -2V, etc.).

[0127] One end of the node connection line 1174 can be coupled to the compensation drain electrode D3 through the contact hole 1156, and the other end can be coupled to the drive gate electrode G1 through the contact hole 1157.

[0128] Initialization voltage lines VL1 and VL2 can be on data line DL, drive voltage line PL, initialization connection lines 1173a and 1173b, and node connection line 1174, with (multiple) insulating layers between the data line DL, drive voltage line PL, initialization connection lines 1173a and 1173b, node connection line 1174 and initialization voltage lines VL1 and VL2.

[0129] Initialization voltage lines VL1 and VL2 are connected to the pixel electrode 121 of the organic light-emitting diode OLED (see...) Figure 8 The pixel electrodes are on the same layer and may comprise the same (e.g., substantially the same) material. The pixel electrodes may be coupled to the emitter control thin-film transistor T6. The pixel electrodes may be coupled to the connection electrode 1175 via contact hole 1163, and the connection electrode 1175 may be coupled to the emitter control drain electrode D6 via contact hole 1153. In some embodiments, initialization voltage lines VL1 and VL2 may be on the same layer as the electrode voltage line HL.

[0130] Figure 6This is a schematic diagram illustrating the pixel arrangement structure in the main display area MDA according to an embodiment.

[0131] Multiple master subpixels Pm can exist in the main display area MDA. In this specification, a subpixel refers to an emission region that serves as a basic unit (e.g., the smallest unit) for realizing an image (or for emitting light). Alternatively, when an organic light-emitting diode (OLED) is used as a display element, the emission region can be defined by an opening in the pixel-defining layer. This will be further described below.

[0132] like Figure 6 As shown, the main sub-pixel Pm in the main display area MDA can be arranged in a pentile structure. The red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb can respectively realize red, green, and blue.

[0133] Multiple red sub-pixels Pr and multiple blue sub-pixels Pb are alternately arranged in the first row 1N. In the adjacent second row 2N, multiple green sub-pixels Pg are separated by a preset interval. In the adjacent third row 3N, blue sub-pixels Pb and red sub-pixels Pr are alternately arranged. In the adjacent fourth row 4N, multiple green sub-pixels Pg are separated by a predetermined interval. This arrangement of pixels is repeated until the Nth row N. In some embodiments, the blue sub-pixels Pb and red sub-pixels Pr may be provided as larger than the green sub-pixels Pg.

[0134] Multiple red sub-pixels Pr and blue sub-pixels Pb in the first row 1N and multiple green sub-pixels Pg in the second row 2N are alternated. Therefore, red sub-pixels Pr and blue sub-pixels Pb are arranged alternately in the first column 1M, and multiple green sub-pixels Pg are arranged at a predetermined interval in the adjacent second column 2M. Blue sub-pixels Pb and red sub-pixels Pr are arranged alternately in the adjacent third column 3M, and multiple green sub-pixels Pg are arranged at a predetermined interval in the adjacent fourth column 4M. This arrangement of pixels is repeated until the Mth column M.

[0135] When the pixel arrangement structure is represented differently, the red sub-pixel Pr is the first and third vertex facing each other in the vertices of the virtual square VS, which is a rectangle with the center point of the green sub-pixel Pg as its center point, and the blue sub-pixel Pb is the second and fourth vertex, which are the remaining vertices. In this case, the virtual square VS can be modified in various ways to form shapes such as rectangles, rhombuses, or squares.

[0136] This pixel arrangement structure is called a waveform tile matrix structure or waveform tile structure, and high resolution can be achieved with a small number of pixels by applying a rendering-driven method, which expresses color by sharing adjacent pixels.

[0137] exist Figure 6 In this embodiment, multiple principal sub-pixels Pm are arranged in a waveform tile matrix structure, but this disclosure is not limited thereto. For example, multiple principal sub-pixels Pm can be arranged in various suitable shapes such as, for example, stripe structures, mosaic array structures, or triangular array structures.

[0138] Figure 7A and Figure 7B This is a schematic diagram illustrating the layout of the pixel arrangement structure in the component region CA according to an embodiment.

[0139] refer to Figure 7A Multiple auxiliary sub-pixels Pa can be located within the component region CA. Each of the auxiliary sub-pixels Pa can emit light of any color selected from red, green, blue, and white.

[0140] The component region CA may include a pixel group PG and a transmission region TA, wherein the pixel group PG includes at least one auxiliary sub-pixel Pa. The pixel group PG and the transmission region TA are arranged alternately along a first direction x and a second direction y, and may be arranged, for example, in a lattice shape. In some embodiments, the component region CA may include multiple pixel groups PG and multiple transmission regions TA.

[0141] A pixel group PG can be defined as a set of subpixels, in which multiple auxiliary subpixels Pa are grouped in a preset unit. For example, ... Figure 7A As shown, a pixel group PG may include eight auxiliary sub-pixels Pa arranged in a wave-shaped structure. In some embodiments, a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb.

[0142] In the component region CA, basic units U can be repeatedly arranged in the first direction x and the second direction y, and a preset number of pixel groups PG and a preset number of transmission regions TA are bound in the basic unit U. Figure 7A In this context, the basic unit U can be a shape in which two pixel groups PG and two transmissive regions TA arranged around the two pixel groups PG are bound together in a square shape. The basic unit U is a division of a repeating shape and does not imply a break in composition.

[0143] In the main display area MDA, the corresponding unit U' can be set (see...). Figure 6 ), corresponding to unit U' (see Figure 6 The corresponding unit U' is provided with an area that is the same (e.g., substantially the same) as the area of ​​the basic unit U. In some embodiments, it includes the corresponding unit U' (see Figure 6The number of principal sub-pixels Pm in a basic unit U can be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. For example, the basic unit U includes 16 auxiliary sub-pixels Pa, and includes 16 auxiliary sub-pixels Pa in the corresponding unit U' (see [link to basic unit U]). Figure 6 The number of principal sub-pixels Pm in the array is 32, and the number of auxiliary sub-pixels Pa and the number of principal sub-pixels Pm can be provided in a 1:2 ratio.

[0144] like Figure 7A The arrangement structure of the auxiliary sub-pixels Pa shown is a waveform tile structure, and the pixel arrangement structure of the component area CA, whose resolution is provided to be half the resolution of the main display area MDA, is called a 1 / 2 waveform tile structure. The number or arrangement of auxiliary sub-pixels Pa included in the pixel group PG can be modified according to the resolution of the component area CA.

[0145] refer to Figure 7B The pixel arrangement structure of the component region CA can be provided as a 1 / 4 wave tile structure. In this embodiment, eight auxiliary sub-pixels Pa are arranged in a wave tile structure in pixel group PG, but only one pixel group PG may be included in the basic unit U. The remaining area of ​​the basic unit U can be provided as a transmission region TA. Therefore, the number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm arranged in the same (e.g., substantially the same) area can be provided in a 1:4 ratio. In some embodiments, a pixel group PG may be surrounded by a transmission region TA.

[0146] Figure 7A and Figure 7B The illustration shows multiple auxiliary subpixels Pa arranged in a waveform tile matrix structure, but this disclosure is not limited thereto. For example, the multiple auxiliary subpixels Pa can be arranged in various suitable shapes such as, for example, stripe structures, mosaic array structures, or triangular array structures.

[0147] In addition, although in Figure 7A and Figure 7B The size of the auxiliary sub-pixel Pa in Figure 6 The primary sub-pixels Pm in the display area are of the same size (e.g., substantially the same), but this disclosure is not limited thereto. The secondary sub-pixels Pa can be of a size larger than the primary sub-pixels Pm that give the same (e.g., substantially the same) color. For example, the size of the blue sub-pixel Pb of the secondary sub-pixel Pa can be larger than the size of the blue sub-pixel Pb of the primary sub-pixel Pm. Differences in size can be considered in the design due to differences in brightness and / or resolution between the component area CA and the main display area MDA.

[0148] Figure 8 This is a schematic cross-sectional view of a portion of the display panel 10 according to an embodiment, and a schematic illustration of the main display area MDA and the component area CA.

[0149] refer to Figure 8 The display panel 10 includes a main display area MDA and a component area CA. A main sub-pixel Pm is included in the main display area MDA, and the component area CA includes an auxiliary sub-pixel Pa and a transmissive area TA. The main display area MDA includes: a main pixel circuit PC, which includes a main thin-film transistor TFT and a main storage capacitor Cst; and a main organic light-emitting diode OLED, which serves as a display element coupled to the main pixel circuit PC. The component area CA includes: an auxiliary pixel circuit PC', which includes an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst'; and an auxiliary organic light-emitting diode OLED', which serves as a display element coupled to the auxiliary pixel circuit PC'.

[0150] Although organic light-emitting diodes are used as display elements in this embodiment, inorganic light-emitting elements and / or quantum dot light-emitting elements may be used as display elements, for example, in embodiments of this disclosure.

[0151] The stacked structure of the components included in the display panel 10 will be described below. The display panel 10 can be provided by stacking a substrate 100, a buffer layer 111, a circuit layer PCL, a display element layer EDL, a sealing member ENCM, and an optical functional layer OFL.

[0152] As described above, substrate 100 may include insulating materials such as glass, quartz, and / or polymer resin. Substrate 100 may be a rigid substrate or a flexible substrate capable of bending, folding, and / or rolling.

[0153] A buffer layer 111 may be present on the substrate 100 to reduce or prevent the penetration of foreign matter, moisture, and / or external air from the bottom of the substrate 100, and / or to provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials, organic materials, and / or organic-inorganic composites such as oxides and / or nitrides, and may comprise a single-layer or multi-layer structure of inorganic and organic materials. A barrier layer may also be included between the substrate 100 and the buffer layer 111 to prevent or reduce the infiltration of external air. In some embodiments, the buffer layer 111 may comprise silicon oxide (SiO2) and / or silicon nitride (SiN2). X A buffer layer 111 can be provided, such that the first buffer layer 111a and the second buffer layer 111b are stacked.

[0154] In the component region CA, the lower metal layer BML may be located between the first buffer layer 111a and the second buffer layer 111b. In another embodiment, the lower metal layer BML may be located between the substrate 100 and the first buffer layer 111a. The lower metal layer BML is located below the auxiliary pixel circuit PC', thereby preventing or reducing the degradation of the characteristics of the auxiliary thin-film transistor TFT' due to light emitted from the component, etc. Furthermore, the lower metal layer BML can prevent (or reduce) diffraction of light emitted from the component and directed to the component through the narrow gap between the wiring coupled to the auxiliary pixel circuit PC'. The lower metal layer BML is not present in the transmission region TA.

[0155] A bias voltage can be applied to the underlying metal layer (BML). When a bias voltage is applied, the underlying metal layer (BML) can significantly reduce the likelihood of electrostatic discharge. The underlying metal layer (BML) is made of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The underlying metal layer (BML) can be provided as a single layer or multiple layers of the aforementioned materials.

[0156] The circuit layer PCL is on the buffer layer 111 and may include pixel circuits PC and PC', a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 115, and / or a planarization layer 117. The main pixel circuit PC may include a main thin-film transistor TFT and a main storage capacitor Cst, and the auxiliary pixel circuit PC' may include an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst'.

[0157] The main thin-film transistor (TFT) and the auxiliary thin-film transistor (TFT) can be located on the buffer layer 111. The main TFT includes a first semiconductor layer AA, a first gate electrode GG, a first source electrode SS, and a first drain electrode DD, and the auxiliary TFT includes a second semiconductor layer AA', a second gate electrode GG', a second source electrode SS', and a second drain electrode DD'. The main TFT can be coupled to the main organic light-emitting diode (OLED) to drive the OLED. The auxiliary TFT can be coupled to the auxiliary organic light-emitting diode (OLED) to drive the OLED.

[0158] The first semiconductor layer AA and the second semiconductor layer AA' are on the buffer layer 111 and may include polycrystalline silicon. In another embodiment, the first semiconductor layer AA and the second semiconductor layer AA' may include amorphous silicon. In another embodiment, the first semiconductor layer AA and the second semiconductor layer AA' may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer AA and the second semiconductor layer AA' may include a channel region and impurity-doped source and drain regions.

[0159] The second semiconductor layer AA' can overlap with the lower metal layer BML, and the second buffer layer 111b is located between the second semiconductor layer AA' and the lower metal layer BML. As an embodiment, the width of the second semiconductor layer AA' can be formed to be smaller than the width of the lower metal layer BML, so that when projected in a direction perpendicular (e.g., substantially perpendicular) to the substrate 100, the second semiconductor layer AA' can overlap the lower metal layer BML entirely.

[0160] A first gate insulating layer 112 may be provided to cover the first semiconductor layer AA and the second semiconductor layer AA'. The first gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). X The materials used may be silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). The first gate insulating layer 112 may be a single layer or multiple layers comprising the inorganic insulating materials described above.

[0161] The first gate electrode GG and the second gate electrode GG' are respectively overlapped on the first gate insulating layer 112 with the first semiconductor layer AA and the second semiconductor layer AA'. The first gate electrode GG and the second gate electrode GG' include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed as a single layer or multiple layers. For example, the first gate electrode GG and the second gate electrode GG' can be a single layer of Mo.

[0162] The second gate insulating layer 113 may cover the first gate electrode GG and the second gate electrode GG'. The second gate insulating layer 113 may include inorganic insulating materials, such as silicon oxide (SiO2) and silicon nitride (SiN). X The inorganic insulating layer 113 may be a single layer or multiple layers comprising the inorganic insulating materials described above.

[0163] The second gate insulating layer 113 may include the first upper electrode CE2 of the main storage capacitor Cst and the second upper electrode CE2' of the auxiliary storage capacitor Cst'.

[0164] In the main display area MDA, the first upper electrode CE2 may overlap with the first gate electrode GG below the first upper electrode CE2. The overlapping first gate electrode GG and the first upper electrode CE2 may form the main storage capacitor Cst, and the second gate insulating layer 113 is between the first gate electrode GG and the first upper electrode CE2. The first gate electrode GG may be the first lower electrode CE1 of the main storage capacitor Cst.

[0165] In the component region CA, the second upper electrode CE2' may overlap with the second gate electrode GG' below the second upper electrode CE2'. The overlapping second gate electrode GG' and the second upper electrode CE2' may form an auxiliary storage capacitor Cst', with the second gate insulating layer 113 between the second gate electrode GG' and the second upper electrode CE2'. The second gate electrode GG' may be the second lower electrode CE1' of the auxiliary storage capacitor Cst'.

[0166] The first upper electrode CE2 and the second upper electrode CE2' may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may be a single layer or multiple layers of the aforementioned materials.

[0167] The interlayer insulating layer 115 may cover the first upper electrode CE2 and the second upper electrode CE2'. The interlayer insulating layer 115 may include silicon oxide (SiO2) or silicon nitride (SiN). X The materials used may be silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). The interlayer insulation layer 115 may be a single layer or multiple layers comprising the inorganic insulating materials described above.

[0168] When the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may include a first aperture H1 corresponding to the transmission region TA. The first aperture H1 may expose a portion of the upper surface of the buffer layer 111 or the substrate 100. The first aperture H1 may be formed by overlapping with the openings of the first gate insulating layer 112 (corresponding to the transmission region TA), the second gate insulating layer 113, and the interlayer insulating layer 115. These openings may be formed separately by individual processes, or they may be formed concurrently (e.g., simultaneously) by the same (e.g., substantially the same) processes. When these openings are formed in individual processes, the inner surface of the first aperture H1 may not be smooth and may include stepped steps.

[0169] Of course, in contrast, the inorganic insulating layer IL may include grooves other than the first hole H1 exposing the buffer layer 111. In some embodiments, the inorganic insulating layer IL may not include the first hole H1 or groove corresponding to the transmission region TA. The inorganic insulating layer IL typically comprises an inorganic insulating material with excellent light transmittance, and thus even without the hole or groove corresponding to the transmission region TA, the inorganic insulating layer IL has suitable or sufficient transmittance, such that component 40 (see...) Figure 2 Transmit / receive appropriate or sufficient light.

[0170] The source electrodes SS and SS' and the drain electrodes DD and DD' can be located on the interlayer insulating layer 115. The source electrodes SS and SS' and the drain electrodes DD and DD' can include conductive materials, such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can be multilayers or single layers comprising the aforementioned materials. For example, the source electrodes SS and SS' and the drain electrodes DD and DD' can be a Ti / Al / Ti multilayer structure.

[0171] The planarization layer 117 may cover the source electrodes SS and SS' and the drain electrodes DD and DD'. The planarization layer 117 may include a flat upper surface, such that the first pixel electrode 121 and the second pixel electrode 121' on the planarization layer 117 can be formed flat.

[0172] The planarization layer 117 may comprise organic and / or inorganic materials, and may be a single-layer or multi-layer structure. The planarization layer 117 may comprise a first planarization layer 117a and a second planarization layer 117b. Accordingly, conductive patterns, such as wiring, may be formed between the first planarization layer 117a and the second planarization layer 117b, which can be beneficial for high integration.

[0173] Planarization layer 117 may comprise a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), and / or polystyrene (PS), including phenolic polymer derivatives, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, and / or vinyl alcohol polymers. In some embodiments, planarization layer 117 may comprise an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN). X The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). When the planarization layer 117 is formed, chemical mechanical polishing can be performed on the upper surface of the layer to provide a flat upper surface after the layer is formed.

[0174] The first planarization layer 117a may cover the pixel circuits PC and PC'. The second planarization layer 117b is on the first planarization layer 117a and may include a flat upper surface, such that the pixel electrodes 121 and 121' can be formed flat.

[0175] Organic light-emitting diodes (OLEDs) and OLED' are located on the second planarization layer 117b. The pixel electrodes 121 and 121' of the organic light-emitting diodes OLEDs and OLED' can be coupled to the pixel circuits PC and PC' via the connection electrodes CM and CM' on the planarization layer 117b.

[0176] The connecting electrodes CM and CM' can be located between the first planarization layer 117a and the second planarization layer 117b. The connecting electrodes CM and CM' can include conductive materials, such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can be a multilayer or a single layer comprising the aforementioned materials. For example, the connecting electrodes CM and CM' can be formed from a Ti / Al / Ti multilayer structure.

[0177] The planarization layer 117 may include a second aperture H2 corresponding to the transmission region TA. The second aperture H2 may overlap with the first aperture H1. Figure 8 In the diagram, the second hole H2 is shown to be larger than the first hole H1. In another embodiment, the planarization layer 117 covers the edge of the first hole H1 in the inorganic insulating layer IL, such that the area of ​​the second hole H2 can be formed to be smaller than the area of ​​the first hole H1.

[0178] The planarization layer 117 includes vias that expose either a first source electrode SS or a first drain electrode DD of the main thin-film transistor TFT, and the first pixel electrode 121 can be electrically coupled to the main thin-film transistor TFT by contacting (e.g., physically contacting) the first source electrode SS or the first drain electrode DD through these vias. Additionally, the planarization layer 117 includes vias that expose either a second source electrode SS' or a second drain electrode DD' of the auxiliary thin-film transistor TFT', and the second pixel electrode 121' can be electrically coupled to the auxiliary thin-film transistor TFT' by contacting (e.g., physically contacting) the second source electrode SS' or the second drain electrode DD' through these vias.

[0179] The first pixel electrode 121 and the second pixel electrode 121' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). The first pixel electrode 121 and the second pixel electrode 121' may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or compounds thereof. For example, the first pixel electrode 121 and the second pixel electrode 121' may include structures on and under the reflective film as described above, the structures comprising films containing ITO, IZO, ZnO, and / or In2O3. In some embodiments, the first pixel electrode 121 and the second pixel electrode 121' may include a stacked structure of ITO / Ag / ITO.

[0180] The pixel defining layer 119 may cover each of the edges of the first pixel electrode 121 and the second pixel electrode 121' on the planarization layer 117, and may include a first opening OP1 and a second opening OP2 that respectively expose the central portions of the first pixel electrode 121 and the second pixel electrode 121'. The first opening OP1 and the second opening OP2 define the size and shape of the emission regions of the organic light-emitting diode OLED and OLED' (e.g., sub-pixels Pm and Pa).

[0181] The pixel defining layer 119 increases the distance between the edges of the pixel electrodes 121 and 121' and the counter electrode 123 on the pixel electrodes 121 and 121', thereby preventing or reducing the occurrence of electric arcs or the like at the edges of the pixel electrodes 121 and 121'. The pixel defining layer 119 is an organic insulating material, such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and / or phenolic resin, and can be formed by methods such as spin coating.

[0182] The pixel defining layer 119 may include a third aperture H3 in the transmission region TA. The third aperture H3 may overlap with the first aperture H1 and the second aperture H2. Through the first aperture H1 to the third aperture H3, the light transmittance in the transmission region TA can be improved. In some embodiments, in Figure 8 In this diagram, the buffer layer 111 is shown as being continuously arranged corresponding to the transmission region TA; however, it should be noted that the buffer layer 111 may include holes in the transmission region TA. (As will be further described herein) portions of the counter electrode 123 may be on the inner surfaces of the first hole H1 to the third hole H3.

[0183] The first emitting layer 122b and the second emitting layer 122b' are located within the first opening OP1 and the second opening OP2 of the pixel defining layer 119, and the first emitting layer 122b and the second emitting layer 122b' are respectively formed to correspond to the first pixel electrode 121 and the second pixel electrode 121'. The first emitting layer 122b and the second emitting layer 122b' may include high molecular weight materials and / or low molecular weight materials, and may emit red, green, blue or white light.

[0184] The organic functional layer 122e may be on and / or below the first emission layer 122b and the second emission layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. The first functional layer 122a or the second functional layer 122c may be omitted.

[0185] The first functional layer 122a may be located below the first emission layer 122b and the second emission layer 122b'. The first functional layer 122a may be a single layer or multiple layers comprising organic materials. The first functional layer 122a may be a single-layer hole transport layer (HTL). In some embodiments, the first functional layer 122a may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 122a may be integrally formed to correspond to the organic light-emitting diodes OLED and OLED' respectively included in the main display area MDA and the component area CA.

[0186] The second functional layer 122c may be located on the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may be a single layer or multiple layers comprising organic materials. The second functional layer 122c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may be integrally formed to correspond to organic light-emitting diodes OLED and OLED' respectively included in the main display area MDA and the component area CA.

[0187] Counter electrode 123 is located on the second functional layer 122c. Counter electrode 123 may comprise a conductive material with a low work function. For example, counter electrode 123 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or alloys thereof. In some embodiments, counter electrode 123 may also comprise a layer such as ITO, IZO, ZnO, and / or In2O3 on the (semi-)transparent layer containing the aforementioned materials. Counter electrode 123 may be integrally formed to correspond to organic light-emitting diodes OLED and OLED' respectively included in the main display region MDA and component region CA.

[0188] The layer formed in the main display area MDA, from the first pixel electrode 121 to the counter electrode 123, can form a main organic light-emitting diode (OLED). The layer formed in the component area CA, from the second pixel electrode 121' to the counter electrode 123, can form an auxiliary organic light-emitting diode (OLED').

[0189] An upper layer 150 comprising an organic material may be formed on the counter electrode 123. The upper layer 150 may be a layer provided to protect the counter electrode 123 and improve light extraction efficiency. The upper layer 150 may include an organic material having a higher refractive index than the counter electrode 123. In some embodiments, the upper layer 150 may be provided by stacking layers with different refractive indices. For example, the upper layer 150 may be provided by stacking a high refractive index layer / a low refractive index layer / a high refractive index layer. In some embodiments, the refractive index of the high refractive index layer may be 1.7 or greater, and the refractive index of the low refractive index layer may be 1.3 or less.

[0190] The upper layer 150 may also include LiF. In some embodiments, the upper layer 150 may also include an inorganic insulating material, such as silicon oxide (SiO2) and / or silicon nitride (SiN). X ).

[0191] The first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may include a transmission aperture TAH corresponding to the transmission region TA. For example, each of the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may include an opening corresponding to the transmission region TA. The areas of such openings can be substantially the same. For example, the area of ​​the opening of the counter electrode 123 can be substantially the same as the area of ​​the transmission aperture TAH.

[0192] It is understandable that the correspondence between the transmission aperture TAH and the transmission region TA means that the transmission aperture TAH and the transmission region TA overlap. In this case, the area of ​​the transmission aperture TAH can be made narrower than the area of ​​the first aperture H1 formed in the inorganic insulating layer IL. Therefore, Figure 8 The width Wt of the transmission aperture TAH is shown to be smaller than the width of the first aperture H1. Here, the area of ​​the transmission aperture TAH can be defined as the area of ​​the opening with the smallest area among the openings constituting the transmission aperture TAH. The area of ​​the first aperture H1 can also be defined as the area of ​​the opening with the smallest area among the openings constituting the first aperture H1.

[0193] Because of the transmission aperture TAH, a portion of the counter electrode 123 is not present in the transmission region TA, thereby significantly improving the light transmittance in the transmission region TA. The counter electrode 123 equipped with this transmission aperture TAH can be formed by various suitable methods. In one embodiment, after forming the material for the electrode 123 on the front surface of the substrate 100, the portion corresponding to the transmission region TA is removed by laser ablation, thereby forming the counter electrode 123 including the transmission aperture TAH. In another embodiment, the counter electrode 123 including the transmission aperture TAH can be formed by a metal self-patterning (MSP) method. In yet another embodiment, the counter electrode 123 including the transmission aperture TAH can be formed by depositing the counter electrode 123 using a fine metal mask (FMM).

[0194] The lower metal layer BML of component region CA may correspond to the entire component region CA. In some embodiments, the lower metal layer BML may include a lower aperture BMLH that overlaps with the transmission region TA. In some embodiments, the shape and size of the transmission region TA may be defined by the shape and size of the lower aperture BMLH.

[0195] Figure 9 This is a schematic plan view of the main display area MDA, illustrating the arrangement of subpixels and some wiring of a display panel according to an embodiment. This plan view shows only a portion of the display panel and omits additional subpixels. Furthermore, since this plan view only shows the wiring required for illustration, additional wiring is omitted. This plan view shows the component area CA and a portion of the main display area MDA outside the component area CA. Figure 10 This is a schematic diagram illustrating the arrangement of sub-pixels and some wiring of the main display area MDA according to an embodiment.

[0196] refer to Figure 9 Multiple pixel groups PG are spaced apart from each other in the component region CA, and a transmission region TA is located between the multiple pixel groups PG. A preset number of auxiliary subpixels Pa can be located in each of the multiple pixel groups PG.

[0197] In this embodiment, the first bypass wiring DTL1 and the horizontal wiring HSL extend in the first direction x.

[0198] The first bypass wiring DTL1 extends in the first direction x to electrically couple to the pixel circuit of the main sub-pixel Pm in the same row of the main display area MDA, but may be bent to bypass along the outermost edge (outermost) of the component area CA, without coupling to the pixel circuit of the auxiliary sub-pixel Pa. Some of the first bypass wiring DTL1 may bypass along the upper side (+ second direction y) of the component area CA, and other first bypass wiring DTL1 may bypass along the lower side (- second direction y) of the component area CA.

[0199] The first bypass wiring DTL1 may be bent along one side of the pixel group PG at the outermost edge (outermost) of the pixel group PG in the component region CA. In some embodiments, on a plane, the first bypass wiring DTL1 may be bent into a stepped or sawtooth shape.

[0200] Figure 9 The first bypass wiring DTL1 in the diagram bends along the outside of pixel group PG at the outermost edge (outermost) of component region CA (e.g., between component region CA and main display region MDA), but this disclosure is not limited thereto. Figure 10 As illustrated, the first bypass wiring DTL1 can bend along the inside of the pixel group PG at the outermost edge (outermost) of the component region CA.

[0201] In this way, the wiring of the pixel circuit that is not coupled to the auxiliary sub-pixel Pa runs around the periphery of the component region CA without crossing the transmission region TA, thus ensuring a high aperture ratio of the transmission region TA.

[0202] The horizontal wiring HSL extends in the first direction x and can electrically couple the pixel circuits of the main sub-pixel Pm and the pixel circuits of the auxiliary sub-pixel Pa. In at least some regions, the horizontal wiring HSL can be located on a different layer from the first bypass wiring DTL1.

[0203] In some embodiments, some of the horizontal wirings HSL in the multiple pixel groups PG of the component region CA can be connected via the connecting line CL (see Figure 9 They are coupled to each other. Accordingly, the number of wirings extending between multiple pixel groups PG in the first direction x is reduced, so that the transmittance of the transmission region TA can be ensured. The connecting line CL is on a different layer than the horizontal wiring HSL and can be coupled to the horizontal wiring HSL through contact holes.

[0204] In the following text, reference will be made to Figure 11 The connection relationships of horizontal wiring HSL in multiple pixel groups PG are further described.

[0205] Figure 11 This is a schematic plan view illustrating the arrangement of wiring coupled to a pixel group PG according to an embodiment. In other words, Figure 11 It is a schematic diagram of the layout of the wiring in a pixel group PG of the component area.

[0206] refer to Figure 11 Pixel group PG can be surrounded by transmission region TA. In an embodiment, eight auxiliary sub-pixels Pa can be in one pixel group PG, and the eight auxiliary sub-pixels Pa can be referenced. Figure 7A and Figure 7B The corrugated tile structure arrangement is described.

[0207] When the auxiliary sub-pixel Pa is arranged in a wave pattern (e.g., arranged in a wave pattern), the first initialization voltage line VL1, the first scan line SL-1, the second scan line SL, the first electrode voltage line HL1, the first emission control line EL1, the second initialization voltage line VL2, and the third scan line SL+1 can be electrically coupled to the pixel circuit of the first auxiliary sub-pixel Pa1, while transversely cutting the first auxiliary sub-pixel Pa1 included in the first row in the first direction x.

[0208] Additionally, the second initialization voltage line VL2, the third scan line SL+1, the fourth scan line SL+2, the second electrode voltage line HL2, the second emission control line EL2, the third initialization voltage line VL3, and the fifth scan line SL+3 can be electrically coupled to the pixel circuit of the second auxiliary sub-pixel Pa2, and simultaneously intersect with the pixel circuit of the second auxiliary sub-pixel Pa2 in the first direction x. In some embodiments, the second auxiliary sub-pixel Pa2 can be adjacent to the first auxiliary sub-pixel Pa1 in the second direction y.

[0209] In some embodiments, the second initialization voltage line VL2 and the third scan line SL+1 can be shared by the first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2.

[0210] Therefore, the second initialization voltage line VL2 can be electrically coupled to the second initialization thin-film transistor of the first auxiliary sub-pixel Pa1 (see...). Figure 4 The first initialization thin-film transistor (see T7 in the middle) and the second auxiliary sub-pixel Pa2 (see T7 in the middle) is a thin-film transistor. Figure 4 (T4 in the text). Additionally, the third scan line SL+1 is electrically coupled to the first initialization thin-film transistor of the second auxiliary sub-pixel Pa2 (see T4 in the text). Figure 4 In T4), and the scan signal applied to the third scan line SL+1 can be passed as the previous scan signal to the first initialization thin-film transistor of the second auxiliary sub-pixel Pa2 (see T4). Figure 4 (T4 in the middle).

[0211] In some embodiments, Figure 11 In the first direction x, the horizontal wiring HSL extending and transversely cutting a pixel group PG may include twelve lines, including a first initialization voltage line VL1, a first scan line SL-1, a second scan line SL, a first electrode voltage line HL1, a first emission control line EL1, a second initialization voltage line VL2, a third scan line SL+1, a fourth scan line SL+2, a second electrode voltage line HL2, a second emission control line EL2, a third initialization voltage line VL3, and a fifth scan line SL+3.

[0212] Each of the pixel group PG includes a horizontal wiring HSL electrically coupled by extension wirings 1001 to 1007 extending in the first direction x in the transmission region TA, and the number of extension wirings 1001 to 1007 may be less than the number of horizontal wirings HSL, and extension wirings 1001, 1002, 1003, 1004 and 1005 may be provided integrally with some of the horizontal wirings HSL.

[0213] As an example, in a horizontal wiring HSL, the first initialization voltage line VL1 and the second initialization voltage line VL2, as described above, can be electrically coupled to a third initialization voltage line VL3. The third initialization voltage line VL3 intersects the second row in the first direction x via a first connection line CL1. The third initialization voltage line VL3 can apply an initialization voltage to the second initialization thin-film transistor of the second auxiliary sub-pixel Pa2 (see...). Figure 9 (T7 in the example). In some embodiments, as an example, only the second initialization voltage line VL2 among the first initialization voltage line VL1, the second initialization voltage line VL2, and the third initialization voltage line VL3 can extend to the transmission region TA to form the fourth extension wiring 1004.

[0214] Furthermore, the second scan line SL and the third scan line SL+1 can be coupled through the second connecting line CL2 to receive the same scan signal, and only the third scan line SL+1 can extend to the transmission region TA to form the fifth extension wiring 1005.

[0215] Additionally, the fourth scan line SL+2 and the fifth scan line SL+3, which cross the second row in the first direction x, can be coupled by the third connecting line CL3, and only the fourth scan line SL+2 can extend to the transmission region TA to form the seventh extension wiring 1007.

[0216] Additionally, the first transmit control line EL1, which intersects the first row in the first direction x, and the second transmit control line EL2, which intersects the second row in the first direction x, can be coupled via a fourth connecting line CL4 and electrically coupled to the third extension wiring 1003. Accordingly, the same transmit control signal can be transmitted to the first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2. In some embodiments, the third extension wiring 1003 can be formed by extending the first transmit control line EL1, or it can be configured as a separate wiring on a different layer than the first transmit control line EL1.

[0217] As described above, the first connecting line CL1, the second connecting line CL2, the third connecting line CL3, and the fourth connecting line CL4 can be on a different layer than the horizontal wiring HSL. For example, the first connecting line CL1, the second connecting line CL2, the third connecting line CL3, and the fourth connecting line CL4 can be on the interlayer insulation layer 115.

[0218] In some embodiments, the first extension wiring 1001 may be integrally formed with the first scan line SL-1, the second extension wiring 1002 may be integrally provided with the first electrode voltage line HL1, and the sixth extension wiring 1006 may be integrally formed with the second electrode voltage line HL2.

[0219] Therefore, since the twelve horizontal wirings HSL intersecting a pixel group PG are coupled to seven extension wirings 1001 to 1007, the number of wirings in the transmission region TA is reduced, thereby improving the transmittance of the transmission region TA. Furthermore, the extension wirings 1001 to 1007 can be adjacent to each other in the central portion of the pixel group PG. For example, on a plane, the width of the area where the extension wirings 1001 to 1007 are arranged along the second direction y is smaller than the width of the area where the horizontal wirings HSL are arranged along the second direction y. As a result, compared to the case where the extension wirings 1001 to 1007 are widely distributed in the transmission region TA, when the component (see...)... Figure 2 When transmitting and receiving signals, 40) can reduce interference caused by extension wiring 1001 to 1007.

[0220] Figure 12 This is a schematic plan view of the main display area MDA, illustrating the arrangement of subpixels and some wiring of a display panel according to an embodiment. This plan view only shows a portion of the display panel, therefore omitting more subpixels. Additionally, since this plan view only shows the wiring necessary for illustration, further wiring is omitted. This plan view shows the component area CA and a portion of the main display area MDA outside the component area CA.

[0221] refer to Figure 12Multiple pixel groups PG are spaced apart from each other in the component region CA, and a transmission region TA is located between the multiple pixel groups PG. A preset number of auxiliary subpixels Pa can be located in each of the multiple pixel groups PG.

[0222] In this embodiment, the second bypass wiring DTL2 and the vertical wiring VSL extend in the second direction y.

[0223] The second bypass wiring DTL2 extends in the second direction y to electrically couple to the pixel circuitry of the primary sub-pixel Pm in the same row of the main display area MDA, but may be bent to bypass along the outermost edge of the component area CA, without coupling to the pixel circuitry of the auxiliary sub-pixel Pa. Some of the second bypass wirings DTL2 may bypass along the left side of the component area CA, while others may bypass along the right side of the component area CA.

[0224] The second bypass wiring DTL2 can be bent along one side of the pixel group PG at the outermost edge of the pixel group PG in the component region CA. In some embodiments, the second bypass wiring DTL2 can be bent into a planar stepped shape or a zigzag shape.

[0225] exist Figure 12 In the diagram, the second bypass wiring DTL2 is shown as bending outward along the outermost edge of the component region CA (e.g., between the component region CA and the main display region MDA) of the pixel group PG, but this disclosure is not limited thereto. The second bypass wiring DTL2 may also bend inward along the inner side of the pixel group PG at the outermost edge of the component region CA.

[0226] In this way, the wiring of the pixel circuit that is not coupled to the auxiliary sub-pixel Pa runs around the periphery of the component region CA without crossing the transmission region TA, thus ensuring a high aperture ratio of the transmission region TA.

[0227] The vertical routing VSL can extend in the second direction y and can electrically couple the pixel circuits of the main sub-pixel Pm and the pixel circuits of the auxiliary sub-pixel Pa. The vertical routing VSL can be located on a different layer from the second bypass routing DTL2 in at least some areas. The second bypass routing DTL2 and the vertical routing VSL can be data lines for transmitting data signals.

[0228] The spacing between vertical wiring VSLs located between multiple pixel groups PG can be smaller than the spacing between vertical wiring VSLs located within pixel group PG.

[0229] This wiring arrangement can improve the light transmittance of the transmission region TA and the overall light transmittance of the module region CA. On the other hand, as the distance between the wirings in the module region CA narrows, light diffraction may occur, potentially causing the lower metal layer BML to overlap with the wirings in the module region CA.

[0230] As described above, the display panel and display device according to embodiments of the present disclosure employ a structure that reduces the number of wires passing between pixel groups in the component area, thereby improving transmittance by ensuring or obtaining a wider transmittance area.

[0231] Of course, the scope of this disclosure is not limited by these effects.

[0232] It will be understood that the embodiments described herein are to be considered descriptive only and are not intended to be limiting. The description of features or aspects within each embodiment will be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A display panel, wherein, The display panel includes: Base; A main display element and a main pixel circuit, wherein the main display element is on the substrate and corresponds to the main display area, and the main pixel circuit is coupled to the main display element; An auxiliary display element and an auxiliary pixel circuit, wherein the auxiliary display element is on the substrate and corresponds to a pixel group respectively, and the auxiliary pixel circuit is coupled to the auxiliary display element respectively; A first bypass wiring is electrically coupled to the main pixel circuit in a first direction and bypasses one side of a pixel group in the pixel group at the outermost part of the component region, the component region including the pixel groups spaced apart from each other and including a transmissive region between the pixel groups; Horizontal wiring, said horizontal wiring being electrically coupled to the main pixel circuit and the auxiliary pixel circuit and extending in the first direction; and The extended wiring is between two adjacent pixel groups along the first direction and extends in the first direction. The extended wiring is electrically coupled to the horizontal wiring included in each of the two pixel groups, and the number of extended wirings is less than the number of horizontal wirings.

2. The display panel according to claim 1, wherein, The first bypass wiring is curved into a stepped shape along the periphery of the pixel group at the outermost part of the component region.

3. The display panel according to claim 1, wherein, The first bypass wiring bends into a stepped shape along the inner side of the pixel group at the outermost part of the component region.

4. The display panel according to claim 1, wherein, On a plane, the width of the area where the extended wiring is arranged along a second direction perpendicular to the first direction is smaller than the width of the area where the horizontal wiring is arranged along the second direction.

5. The display panel according to claim 1, wherein, Each auxiliary pixel circuit in the auxiliary pixel circuit includes a driving thin-film transistor, a first initialization thin-film transistor, and a second initialization thin-film transistor. The first initialization thin-film transistor initializes the voltage of the driving gate electrode of the driving thin-film transistor, and the second initialization thin-film transistor initializes the pixel electrode of the auxiliary display element. The horizontal wiring includes a first initialization voltage line and a second initialization voltage line. The first initialization voltage line transmits the initialization voltage to the first initialization thin-film transistor, and the second initialization voltage line transmits the initialization voltage to the second initialization thin-film transistor. The first initialization voltage line and the second initialization voltage line are electrically coupled to each other through a first connection line.

6. The display panel according to claim 5, wherein, The first connecting line is on a different layer than the horizontal wiring.

7. The display panel according to claim 5, wherein, Each pixel group comprises a first row and a second row, wherein auxiliary sub-pixels are arranged along the first direction in the first row and the second row. The first auxiliary sub-pixel included in the first row and the second auxiliary sub-pixel included in the second row are adjacent to each other along a second direction perpendicular to the first direction, and The second initialization voltage line is shared by the first auxiliary sub-pixel and the second auxiliary sub-pixel.

8. The display panel according to claim 7, wherein, The second initialization voltage line is electrically coupled to the first initialization thin-film transistor of the second auxiliary sub-pixel.

9. The display panel according to claim 7, wherein, The horizontal wiring further includes: a third initialization voltage line, which intersects the second row in the first direction, and the third initialization voltage line applies an initialization voltage to the second initialization thin-film transistor of the second auxiliary sub-pixel. The third initialization voltage line is electrically coupled to the first connection line.

10. The display panel according to claim 1, wherein, The display panel further includes a second bypass wiring, which is electrically coupled to the main pixel circuit in a second direction intersecting the first direction and bypasses one side of the pixel group at the outermost part of the component region.

11. The display panel according to claim 10, wherein, The second bypass wiring is bent into a stepped shape.

12. The display panel according to claim 1, wherein, The display panel further includes a lower metal layer, the lower metal layer being located in the component region and situated between the substrate and the auxiliary pixel circuitry driving the auxiliary sub-pixels. The lower metal layer includes a lower hole corresponding to the transmission region.

13. A display device, wherein, The display device includes: A display panel, comprising a main display area and a component area, wherein the main display area includes main sub-pixels, and the component area includes multiple pixel groups and a transmissive area; and Components, the components being located below the display panel and corresponding to the component area, wherein the display panel includes: Base; A first bypass wiring is electrically coupled to the main sub-pixel in a first direction and bypasses one side of the pixel group at the outermost part of the component region. Horizontal wiring, said horizontal wiring being electrically coupled to the main sub-pixel and the plurality of pixel groups and extending in the first direction; and The extended wiring extends between two adjacent pixel groups along the first direction within the plurality of pixel groups. The extended wiring is electrically coupled to the horizontal wiring included in each of the two pixel groups, and the number of extended wirings is less than the number of horizontal wirings.

14. The display device according to claim 13, wherein, The first bypass wiring is curved into a stepped shape along the periphery of the pixel group at the outermost part of the component region.

15. The display device according to claim 13, wherein, The first bypass wiring bends into a stepped shape along the inner side of the pixel group at the outermost part of the component region.

16. The display device according to claim 13, wherein, The width of the area where the extended wiring is arranged along a second direction perpendicular to the first direction is smaller than the width of the area where the horizontal wiring is arranged along the second direction.

17. The display device according to claim 13, wherein, The display panel further includes: auxiliary display elements and auxiliary pixel circuits, wherein the auxiliary display elements are on the substrate and correspond to the pixel groups respectively, and the auxiliary pixel circuits are respectively coupled to the auxiliary display elements. Each auxiliary pixel circuit in the auxiliary pixel circuit includes a driving thin-film transistor, a first initialization thin-film transistor, and a second initialization thin-film transistor. The first initialization thin-film transistor initializes the voltage of the driving gate electrode of the driving thin-film transistor, and the second initialization thin-film transistor initializes the pixel electrode of the auxiliary display element. The horizontal wiring includes a first initialization voltage line and a second initialization voltage line. The first initialization voltage line transmits the initialization voltage to the first initialization thin-film transistor, and the second initialization voltage line transmits the initialization voltage to the second initialization thin-film transistor. The first initialization voltage line and the second initialization voltage line are electrically coupled to each other through a first connection line.

18. The display device according to claim 17, wherein, The first connecting line is on a different layer than the horizontal wiring.

19. The display device according to claim 17, wherein, Each of the plurality of pixel groups includes a first row and a second row, in which a plurality of auxiliary sub-pixels are arranged along the first direction. The first auxiliary sub-pixel included in the first row and the second auxiliary sub-pixel included in the second row are adjacent to each other along a second direction perpendicular to the first direction, and The second initialization voltage line is shared by the first auxiliary sub-pixel and the second auxiliary sub-pixel.

20. The display device according to claim 19, wherein, The horizontal wiring also includes a third initialization voltage line, which intersects the second row in the first direction and applies an initialization voltage to the second initialization thin-film transistor of the second auxiliary sub-pixel, wherein the third initialization voltage line is electrically coupled to the first connection line.

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