Receiver front-end architecture for in-band carrier aggregation

Abstract

A receiver front-end architecture for in-band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal for receiving an input signal, a drain terminal for outputting an amplified signal, and a source terminal connected to signal ground via a source degradation inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus further includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load, and a source terminal connected to signal ground.

Description

[0001] This application is a divisional application of the invention patent application filed on September 30, 2015, with application number 201580061296.0 and invention title "Receiver Front-End Architecture for In-Band Carrier Aggregation". Technical Field

[0002] This disclosure generally relates to electronic technology, and more specifically to the configurable routing of radio frequency signals in wireless devices. Background Technology

[0003] Wireless devices in a wireless communication system (e.g., cellular phones or smartphones) can transmit and receive data for two-way communication. For example, the wireless device can operate in a frequency division duplex (FDD) system or a time division duplex (TDD) system. The wireless device can include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter can use data to modulate a radio frequency (RF) carrier signal to obtain a modulated RF signal, amplify and filter the modulated RF signal to obtain an amplified RF signal with an appropriate output power level, and transmit the amplified RF signal to a base station via an antenna. For data reception, the receiver can obtain the received RF signal via an antenna and can amplify, filter, and process the received RF signal to recover the data transmitted by the base station.

[0004] Wireless devices can support operation over a wide frequency range. For example, a wireless device can operate in a carrier aggregation (CA) communication system, where the device includes a front-end that receives multiple downlink (DL) carrier signals over a wide frequency range. The front-end operates by amplifying the received carrier signals and routing them to appropriate demodulators for demodulation. Unfortunately, conventional front-ends may utilize multiple amplifiers, each with a degeneration inductor. The large size of these inductors means that conventional front-ends utilize significant circuit area. Furthermore, if the amplifiers used to amplify multiple carrier signals are distributed across multiple chips, it may be difficult to compensate for the various gain and circuit routing losses that may result.

[0005] Therefore, it is desirable for carrier aggregation receivers to have a front-end architecture that provides efficient amplification and routing of the received signal. The front-end should operate to maintain excellent linearity, provide compensation for gain and routing losses, and reduce or minimize circuit area requirements compared to conventional front-ends. Attached Figure Description

[0006] Figure 1 An exemplary embodiment of a front-end architecture used in a wireless device for communication within a wireless system is shown.

[0007] Figure 2 It shows Figure 1 An exemplary embodiment of the front-end architecture shown can operate in three exemplary frequency band groups therein.

[0008] Figure 3 A receiver is shown that includes an exemplary embodiment of a front-end architecture that provides configurable RF signal amplification and routing.

[0009] Figure 4 It shows Figure 3 A detailed exemplary embodiment of the front-end architecture shown is illustrated.

[0010] Figure 5 It shows Figure 3 Detailed alternative exemplary embodiments of the front-end architecture shown are illustrated.

[0011] Figure 6 It shows the use of with Figure 4 An exemplary embodiment of the controller used in conjunction with the front-end architecture shown.

[0012] Figure 7 Exemplary operations are shown, performed by an exemplary embodiment of the front-end architecture, to provide RF signal amplification and routing in the receiver front end.

[0013] Figure 8 An exemplary embodiment of a table is shown, which illustrates a table for use with... Figure 4 and Figure 5 The control signal settings for various signal amplification and routing configurations used together in the front-end architecture shown are illustrated.

[0014] Figure 9 An exemplary embodiment of an apparatus for amplifying and routing RF signals in a carrier aggregation receiver is shown. Detailed Implementation

[0015] The detailed description set forth below is intended as a description of exemplary designs of this disclosure and is not intended to represent the only designs in which this disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous relative to other designs. This detailed description includes specific details for the purpose of providing a thorough understanding of exemplary designs of this disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.

[0016] This paper discloses a novel receiver front-end architecture that provides configurable RF signal amplification and routing within a device to demodulate multiple carrier signals over a wide frequency range covering multiple frequency bands. This receiver front-end architecture is suitable for use in various types of electronic devices, such as wireless communication devices.

[0017] Figure 1 An exemplary embodiment of a front-end architecture 112 used in a wireless device 110 for communication within a wireless system 120 is shown. The wireless system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, or some other wireless system. The CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Generally, the wireless system 120 may include any number of base stations and any set of network entities.

[0018] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, cordless phone, wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 can communicate with devices in wireless system 120. Wireless device 110 can also receive signals from a broadcast station (e.g., broadcast station 134) or from satellites (e.g., satellite 150) in one or more Global Navigation Satellite Systems (GNSS). Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11. In an exemplary embodiment, wireless device 110 includes a receiver front-end (FE) architecture 112 to provide RF carrier signal amplification and routing when multiple carriers are received in a carrier aggregation communication system. The FE 112 is designed to use fewer amplifier degradation inductors compared to conventional front-end designs, in order to reduce circuit area requirements and provide better compensation for gain / routing losses.

[0019] Figure 2 It shows Figure 1An exemplary embodiment of the FE 112 shown can operate in one of three exemplary frequency band groups. The wireless device 110 can operate in a low-frequency band (LB) covering frequencies below 1000 MHz, a mid-frequency band (MB) covering frequencies from 1000 MHz to 2300 MHz, and / or a high-frequency band (HB) covering frequencies above 2300 MHz. For example, as... Figure 2 As shown, the low-frequency band can cover 698 to 960 MHz, the mid-frequency band can cover 1475 to 2170 MHz, and the high-frequency band can cover 2300 to 2690 MHz and 3400 to 3800 MHz. The low-frequency, mid-frequency, and high-frequency bands refer to three groups (or band sets) of frequency bands, each band set comprising multiple frequency bands (or simply "bands"). Each band can cover up to 200 MHz. LTE Release 11 supports 35 frequency bands, which are referred to as LTE / UMTS bands and are listed in 3GPP TS 36.101.

[0020] Generally, any number of frequency bands can be defined. Each frequency band can cover any range of frequencies, which may or may not match the frequencies specified in the original text. Figure 2 Any of the frequency ranges shown. Each band group may also include any number of bands. In various exemplary embodiments, FE 112 is adapted to receive, amplify, and demodulate carrier signals in any band of the frequency band in which the device 110 may operate.

[0021] Figure 3 A receiver 300 is shown, including an exemplary embodiment of a front-end architecture that provides configurable RF signal path amplification and routing. For example, the receiver 300 is adapted for amplifying and routing received carrier signals in a carrier aggregation communication system. The receiver 300 includes a receiving antenna 302, a matching circuit 304, a signal amplification and routing circuit (SARC) 306, a controller 308, a main load circuit 310, a first carrier aggregation (“CA1”) load circuit 312, one or more additional carrier aggregation load circuits (not shown), and an nth carrier aggregation (“CAn”) load circuit 314. In an exemplary embodiment, each load circuit 310-314 includes a separate demodulation circuit.

[0022] During operation, the RF signal is received by the receiving antenna 302. For example, the RF signal may include... Figure 2Any of the frequency bands or frequency band groups illustrated herein. The received RF signals are routed by SARC 306 to any combination of output loads 310-314 according to control signals 316 provided to SARC 306 from controller 308. In an exemplary embodiment, control signal 316 is set to a first logic voltage level for a first signal path routing configuration, and control signal 316 is set to a second logic voltage level for a second signal path routing configuration.

[0023] although Figure 3 Not shown in the diagram, however, controller 308 can be dynamically programmed by a baseband processor within the wireless device. For example, the baseband processor provides configuration parameters 318 to controller 308 to program the operation of controller 308. In an exemplary embodiment, the baseband processor included in the wireless device will use controller 308 to modify the signal routing of received RF signals depending on the carrier aggregation mode in which the wireless device is operating.

[0024] Figure 4 It shows in Figure 3 A detailed exemplary embodiment of the SARC 306 used in the front-end architecture shown is illustrated. The SARC 306 includes a first common-source amplifier 402, which includes a transistor (T1) having a gate terminal 404 that receives an input signal 406 via an inductor 448, a source terminal 408 connected to a source degraded inductor 410 further connected to signal ground, and a drain terminal 412 that outputs an amplified version of the input signal. Therefore, the first common-source amplifier 402 is implemented using transistor T1 and source degraded inductor L1.

[0025] SARC 306 also includes a first cascode amplifier 414, which includes a transistor (T3) having a source terminal 416 connected to a drain terminal 412 and a drain terminal 418 connected to a main load 420 via a main signal path. The first cascode amplifier 414 also includes a gate terminal 422 selectively connected to a voltage level (VBC) via a switch 424. Therefore, the first cascode amplifier 414 is implemented using transistor T3. Switch 424 receives a control signal Sa from controller 308, which controls switch 424 to selectively input either a zero voltage level or a VBC voltage level to the gate terminal 422. In an exemplary embodiment, the VBC voltage level is typically 1.2 volts. In another exemplary embodiment, the VBC voltage level is configured to bias either of the transistor devices to any desired bias setting or for DC coupling.

[0026] SARC 306 further includes a second common-source amplifier 426, which includes a transistor (T21) having a gate terminal 428 connected to a drain terminal 412 and a drain terminal 430 connected to a source terminal 458 of a switch 432 via a CA1 signal path. Switch 432 includes a transistor (T51) and has a drain terminal 456 connected to a second load 434. Therefore, the second common-source amplifier 426 is implemented using transistor T21. It should be noted that, unlike the first common-source amplifier 402 which uses a source degradation inductor 410, the second common-source amplifier 426 is configured without a source degradation inductor. Therefore, the source terminal of transistor T21 is directly connected to signal ground. Switch 432 includes a gate terminal 460 selectively connected to a voltage level vbc via a switch 462.

[0027] SARC 306 also includes a second cascode amplifier 436, which includes a transistor (T3') having a source terminal 438 connected to a first drain terminal 412 and a drain terminal 440 connected to the drain terminal 418 of transistor T3 and to a drain terminal 450 of switch 442. The second cascode amplifier 436 has a gate terminal 446 selectively connected to a voltage level vbc via switch 444. Therefore, the second cascode amplifier 436 is implemented using transistor T3'. In an exemplary embodiment, the first cascode amplifier 414 is configured to conduct more current than the second cascode amplifier 436, which is accomplished by appropriately sizing transistors T3 and T3' to achieve the desired current conduction characteristics. Switch 442 includes a transistor (T41) with a source terminal 452 connected to the CA1 signal path and thereby connected to the drain terminal 430 of transistor T21 and the source terminal 458 of transistor T51. Switch 442 includes a gate terminal 464 selectively connected to a voltage level vbc via a switch 454. In an exemplary embodiment, transistor T3 is partitioned into transistors (T3+T3') such that, in carrier aggregation mode, transistor T3' can be turned off to increase the impedance seen at the drain of transistor T1. This increases the gain at the drain of transistor T1, which is input to transistor (T2n). This helps reduce the noise contribution from transistor (T2n).

[0028] In addition to amplifying the received RF signal and routing it to the main load 420 and CA1 load 434, the SARC 306 can be configured to amplify the received RF signal and route it to any number of additional CA loads. The following is a description of the configuration of the SARC 306 amplifying the received RF signal and routing it to the nth CA load. It should be noted that a similar circuit structure can be used to amplify the received RF signal and route it to any number of CA loads between the first CA load and the nth CA load.

[0029] The SARC 306 includes an nth common-source amplifier 466, which includes a transistor (T2). n ), transistor (T2) n It has a gate terminal 468 connected to the drain terminal 412, and is connected via CA n The signal path is connected to the drain terminal 470 of the source terminal 472 of switch 474. Switch 474 includes a transistor (T5). n It also has a drain terminal 476 connected to the nth load 478. Therefore, the nth common-source amplifier 466 uses transistor T2. n Implemented. It should be noted that up to and including the nth common-source amplifier 466, the additional common-source amplifiers do not utilize source degenerate inductors as the first common-source amplifier 402, which uses degenerate inductor 410. Switch 474 includes a gate terminal 480 selectively connected to a voltage level (VBC) via switch 482.

[0030] The SARC 306 includes a switch 484, which includes a transistor (T4). n ), transistor (T4) n It has a source terminal 486, which is connected to the CA. n The signal path is thus connected to the drain terminal 470 and the source terminal 472. The drain terminal 488 of switch 484 is connected to the drain terminal 418. The gate terminal 490 of switch 484 is selectively connected to the voltage level vbc via switch 492.

[0031] During operation, controller 308 generates multiple control signals. In an exemplary embodiment, each control signal is either a logic low voltage level or a logic high voltage level. The control signal “Sa” output from controller 308 is coupled to switch 424 and controls the voltage level at gate terminal 422 of transistor T3. When control signal “Sa” is a logic low voltage level, a zero-volt signal is input to gate terminal 422 and the first cascode amplifier 414 is turned off. As a result, input signal 406 is not coupled to drain terminal 418 through transistor T3. Alternatively, when control signal “Sa” is a logic high voltage level, a VBC voltage level is input to gate terminal 422 and the first cascode amplifier 414 is turned on. As a result, input signal 406 is coupled to drain terminal 418 through transistor T3. The signal at drain terminal 418 is then passed to main load 420 via the main signal path. At the main load 420, the signal is coupled to a demodulator via a transformer, which demodulates the signal based on a selected local oscillator signal to generate the main baseband (BB) signal.

[0032] A control signal “Sb” generated by controller 308 is coupled to control switch 444, which controls the voltage level at gate terminal 446 of transistor T3'. When control signal “Sb” is at a logic low voltage level, switch 444 inputs zero volts to gate terminal 446 and the second cascode amplifier 436 is turned off, so the amplified input signal at terminal 412 is not coupled to drain terminal 440 of transistor T3'. Alternatively, when control signal “Sb” is at a logic high voltage level, switch 444 inputs vbc volts to gate terminal 446, so the second cascode amplifier 436 is turned on. As a result, the amplified input signal at terminal 412 is coupled to drain terminal 440 of transistor T3' and coupled to the main signal path.

[0033] The controller 308 generates a control signal "S(n)". Signal S1 is coupled to control switch 454 associated with the CA1 signal path. Control signal S(n) is also coupled to control additional corresponding switches associated with other signal paths. For example, signal S... n Coupled to control with CA nThe signal path is associated with switch 492. Therefore, the control signal S(n) controls the voltage level at the gate terminal of the corresponding transistor T4(n) in the CA signal path. For example, when the control signal "S1" is at a logic low voltage level, switch 442 is turned off (i.e., open-circuited) and there is no connection between the CA1 signal path and the main signal path. Alternatively, when the control signal "S1" is at a logic high voltage level, switch 442 is turned on (i.e., closed) and a connection is established between the CA1 signal path and the main signal path. This operation of the S(n) control signal is the same for any other CA signal path that may be utilized. For example, if the control signal S... n If the logic voltage level is high, then switch 484 is turned on (i.e., closed) and CA... n The connection between the signal path and the main signal path is established.

[0034] A control signal “SE(n)” is generated by controller 308. The control signal SE(n) is coupled to control switches to determine the input voltage to the gate terminals of the switches that connect the CA signal paths to their associated output loads. For example, a control signal SE1 is coupled to control switch 462 to determine the voltage level input to the gate terminal 460 of switch 432. When the control signal “SE1” is a logic low voltage level, zero volts are input to gate terminal 460 to turn off switch 432 (e.g., open circuit) and the path between the CA1 signal path and the output load 434 is opened. Alternatively, when the control signal “SE1” is a logic high voltage level, vbc volts are input to gate terminal 460 of switch 432 (e.g., close circuit) and the path between the CA1 signal path and the output load 434 is opened. The control signal SE(n) operates similarly to control other corresponding switches in any other CA signal paths.

[0035] First operating mode—Main load only

[0036] It may be advantageous to couple the input signal 406 only to the main output load 420 during carrier aggregation. To couple the input signal 406 only to the main load 420, one or both of the first cascode amplifier 414 and the second cascode amplifier 436 are turned on via the operation of the Sa and Sb control signals. Furthermore, the control signal SE(n) is set such that zero volts are input to the gate terminal of the associated (T5(n)) switch, thereby opening those switches to prevent coupling of the input signal 406 to other CA loads. Turning on one or the other of the first cascode amplifier 414 and the second cascode amplifier 436 sets the selected gain level. Turning on both the first cascode amplifier 414 and the second cascode amplifier 436 maximizes the gain applied to the input signal 406 before it is coupled to the main load 420.

[0037] Second operating mode—Main load and one or more CA loads

[0038] It may be advantageous to couple the input signal 406 to the main output load 420 and one or more CA loads during carrier aggregation. For example, the main load operates to demodulate the first carrier signal, and the one or more additional CA loads operate to demodulate one or more additional carrier signals. To couple the input signal 406 to the main load 420, at least one of the first cascode amplifier 414 and the second cascode amplifier 436 is turned on by the operation of the Sa and Sb control signals. To couple the input signal to one or more CA loads, the control signal SE(n) is set such that volts vbc are input to the gate terminal of the associated (T5(n)) switch, thereby closing those switches to allow coupling of the input signal 406 to the associated CA load. Turning on both the first cascode amplifier 414 and the second cascode amplifier 436 will maximize the gain applied to the input signal 406 before the input signal 406 is coupled to the main load 420.

[0039] Third operating mode—first load connected to the main load

[0040] It may be advantageous to couple the first output load 434 to the main output load 420 during carrier aggregation. To couple the first output load 434 to the main output load 420, control signals S1 and SE1 are set such that both the first switch 432 and the second switch 442 are closed. If either the first switch 432 or the second switch 442 is open, the first output load 434 will be disconnected from the main output load 420. While coupling the first output load 434 to the main output load 420, it may be advantageous to decouple the input signal from the main output load 420. To prevent coupling of the input signal to the main output load 420, the first cascode amplifier 414 and the second cascode amplifier 436 are turned off.

[0041] Figure 4 Further illustration shows how switches 474 and 484 can be operated in a similar manner to couple the Nth output load 478 to the main output load 420. Therefore, utilizing... Figure 4 In the exemplary embodiment illustrated, the SARC 306 can amplify a signal and route the signal to N output loads as well as route the signal among the N output loads. As described above, the amplification and routing of the signal are dynamically controlled by the controller 308 for each path.

[0042] When routing the RF input signal to the CA load, the output of transistor T1 is used by transistor T2(n) to generate current signals, which are coupled to the CA(n) output for in-carrier aggregation mode. The voltage gain at the drain of transistor T1 for a common-source LNA topology will be “Q_matching * (gm_T1 / gm_T3)”. For a common-source amplifier, the Q of the input network is defined by the ratio of reactive impedance to resistive impedance.

[0043] Figure 4 The SARC 306 shown provides good linearity for each carrier aggregation (CA) path. The linearity for each carrier aggregation path is close to that of the main path. The linearity of each carrier aggregation path is set by the current and voltage gains of transistor T3 and transistor T2. The first cascode amplifier is adjusted depending on whether the operation is in carrier aggregation mode or non-carrier aggregation mode to reduce noise contribution and improve linearity during operation. It should also be noted that... Figure 4 The front-end architecture shown can be implemented on one or more integrated circuits. For example, in an exemplary embodiment, components on one side of circuit boundary 494 can be implemented in a first integrated circuit, and components on the opposite side of circuit boundary 494 can be implemented in a second integrated circuit. Therefore, the exemplary embodiment can be implemented in any number of integrated circuits.

[0044] Figure 5 The following are examples including SARC 502. Figure 3 The diagram illustrates a detailed alternative exemplary embodiment of the front-end architecture. The SARC 502 includes... Figure 4 The circuit components shown in SARC 306 are identical but connected in a different configuration. In SARC 502, the gate terminal 468 of the third common-source amplifier 466 is coupled to the first CA1 path at terminal 506 via signal line 504. Therefore, the third common-source amplifier 466 receives its input from the output of the second common-source amplifier 426. As a further extension, a subsequent common-source amplifier associated with another CA signal path can be connected to the CA2 signal path at terminal 508. By linking the outputs of the common-source amplifiers in this way, any number of CA signal paths can be generated. It should also be noted that the second common-source amplifier 426 and the third common-source amplifier 466 are also configured without degenerate inductors, which reduces the circuit area requirements of SARC 502.

[0045] Figure 6 It shows the use of with Figure 4 An exemplary embodiment of the controller 600 used in conjunction with the front-end architecture shown is illustrated. In the exemplary embodiment, the controller 600 is adapted to function as... Figure 4 or Figure 5 The controller 308 shown is included. The controller 600 includes a processor 602, a memory 604, a main control signal generator 606, and an auxiliary control signal generator 608, all coupled to communicate via a bus 610.

[0046] Processor 602 includes at least one of the following: CPU, processor, gate array, hardware logic, discrete circuitry, memory elements, and / or hardware for executing software. Processor 602 operates to control other functional elements of controller 600 using bus 610. Processor 602 is also configured to communicate with other entities at a wireless device using communication line 612. For example, processor 602 can receive instructions, control information, configuration information, data, measurements, or other information via communication line 612.

[0047] Memory 604 includes any suitable memory or storage device that allows for the storage, retrieval, and maintenance of instructions and / or data associated with the operation of controller 600. In an exemplary embodiment, memory 604 stores algorithm instructions that can be executed by memory 602 to perform the signal amplification and routing functions described herein.

[0048] The main control signal generator 606 includes hardware such as amplifiers, buffers, registers, gates, analog-to-digital converters, digital-to-analog converters, or any other suitable hardware or discrete components and / or hardware that operates to generate the main control signals Sa and Sb. In an exemplary embodiment, the processor 602 operates to determine the configuration of the SARC 306 based on configuration parameters received via signal line 612. The processor then uses bus 610 to control the main control signal generator 606 to generate and output the Sa and Sb control signals to achieve the desired configuration. In an exemplary embodiment, the Sa and Sb control signals are set to enable, disable, or bias any of the transistor devices to which they are coupled. For example, the Sa and Sb control signals may operate to bias the transistor devices to any desired bias setting or for DC coupling.

[0049] The auxiliary control signal generator 608 includes hardware such as amplifiers, buffers, registers, gates, analog-to-digital converters, digital-to-analog converters, or any other suitable hardware or discrete components and / or hardware that operates to generate auxiliary control signals S(n) and SE(n) for execution software. In an exemplary embodiment, the processor 602 operates to determine the configuration of the SARC 306 based on configuration parameters received via signal line 612. The processor then controls the auxiliary control signal generator 608 to generate the S(n) and SE(n) control lines to achieve the desired configuration. In an exemplary embodiment, the S(n) and SE(n) control signals are set to enable, disable, or bias any of the transistor devices to which they are coupled. For example, the S(n) and SE(n) control signals may operate to bias the transistor devices to any desired bias setting or for DC coupling.

[0050] In an exemplary embodiment, processor 602 executes code stored in memory 604 to control main control signal generator 606 and auxiliary control signal generator 608 to generate control signals to obtain the desired signal routing configuration.

[0051] It should be noted that controller 600 represents only one implementation and other implementations are possible. For example, controller 600 may be implemented in discrete logic that eliminates the need for a processor or memory device. In another implementation, the functionality and / or implementation of controller 600 may be incorporated into or integrated into other entities at the baseband processor or wireless device.

[0052] Figure 7 An exemplary operation 700 for RF signal amplification and routing in a receiver front end is illustrated. For example, in an exemplary embodiment, Figure 4 The SARC 306 and controller 308 shown are configured to perform operation 700 to obtain desired RF signal amplification and routing at the receiver front end. In an exemplary embodiment, controller 308 is controller 600, and processor 602 executes instructions stored in memory 604 to control the components of controller 600 to control SARC 306 to perform the operations described below.

[0053] At block 702, configuration parameters are received. For example, configuration parameters are received by processor 602 from an entity at the wireless device via communication line 612. The configuration parameters describe how the received RF signal will be amplified and routed to the primary load and carrier aggregation load in the receiver. In an exemplary embodiment, processor 602 operates to store the configuration parameters in memory 604.

[0054] At box 704, the RF signal is received. For example, the RF signal is received by antenna 302 and... Figure 4The flow on the input line 406 shown is transmitted through the matching circuit 304 before passing through.

[0055] At block 706, the received RF signal is amplified. In an exemplary embodiment, the received RF signal is input to a first common-source amplifier 402. The first common-source amplifier 402 includes a degraded inductor 410. An amplified version of the received RF signal appears at the drain terminal 412. Therefore, the received RF signal is amplified by a common-source amplifier with source degradedness to generate an amplified version of the received RF signal.

[0056] At block 708, an amplified version of the received RF signal is selectively connected to the main load based on configuration parameters. In an exemplary embodiment, processor 602 processes the configuration parameters to determine the control signal settings required to obtain the desired configuration. Processor 602 uses bus 610 to communicate the control signal settings to main control signal generator 606. Main control signal generator 606 operates to generate and output Sa and Sb control signals to obtain the desired signal amplification and routing to the main load as identified by the configuration parameters. For example, if the Sa control signal is logic high (1) and the Sb control signal is logic low (0), amplifier 414 provides cascode amplification to amplify the signal at terminal 412 to generate an amplified output signal at terminal 418, which is input to the main load. In various exemplary embodiments, main control signal generator 606 generates, as shown in the example... Figure 8 The control signals Sa and Sb provided in Table 800 shown here are used to selectively connect the amplified RF signal to the main load.

[0057] At block 710, an amplified version of the received RF signal is selectively connected to one or more CA loads based on configuration parameters. In an exemplary embodiment, processor 602 processes the configuration parameters to determine the control signal settings required to obtain the desired configuration. Processor 602 uses bus 610 to communicate the control signal settings to auxiliary control signal generator 608. Auxiliary control signal generator 608 operates to generate and output S(n) and SE(n) control signals to obtain the desired signal amplification and routing to one or more CA loads as identified by the configuration parameters. For example, if the SE1 control signal is logic high (1), switch 432 is enabled to input the amplified signal at terminal 430 to the first CA load 434. As a result, the received RF signal is amplified and routed to the selected CA load based on the SE(n) control signal to obtain the desired signal amplification and routing configuration. When amplifying and routing the received RF signal to the selected CA load, the additional common-source amplifiers (T2(n)) (e.g., amplifiers 426 to 466) do not include (or are configured to have no) source degradation inductors, which results in a reduced circuit area compared to conventional systems.

[0058] Therefore, SARC 306 and controller 308 are configured to perform the operations described above. It should be noted that operation 700 is exemplary and minor changes, modifications, rearrangements, and other alterations to operation 700 are within the scope of the exemplary embodiments.

[0059] Figure 8 An exemplary embodiment of Table 800 is shown, which illustrates methods for use with... Figure 4 The control signal settings for various amplification and routing configurations used in the front-end architecture shown are illustrated. Table 800 includes configuration information 802, control signal Sa setting 804, control signal Sb setting 806, control signal S1 setting 808, and control signal SE1 setting 810. For clarity, Table 800 only shows the signal settings for the S1 and SE1 signals. It should be noted that similar settings can be used for control signals S(n) and SE(n) to connect additional loads to input signals or main loads. In various exemplary embodiments, the controller 600 operates to generate and output the illustrated control signals to obtain the selected configuration.

[0060] In an operating mode where the input signal is routed only to the main load, the control signal SA is set to logic high, the control signal SB is set to logic high, the control signal S1 is set to logic low, and the control signal SE1 is set to logic low.

[0061] In another operating mode that routes the input signals to the main load and the first load (CA1), the control signal SA is set to logic low, the control signal SB is set to logic low, the control signal S1 is set to logic low, and the control signal SE1 is set to logic high.

[0062] In another operating mode that routes the first load signal to the main load, control signal SA is set to logic low, control signal SB is set to logic low, control signal S1 is set to logic high, and control signal SE1 is set to logic low.

[0063] Figure 9 An exemplary embodiment of an apparatus 900 for RF signal amplification and routing in a carrier aggregation receiver is shown. In the exemplary embodiment, the apparatus 900 is adapted to be used as... Figure 4 The SARC 306 shown is an example. The device 900 includes a first component 902 for generating control signals that control how a signal will be amplified and routed to one or more loads. This signal is output from a first transistor having a source terminal connected to signal ground via a source degradation inductor, which in an exemplary embodiment includes... Figure 6The controller 600 shown is Figure 4 The amplifier 402 shown is included. The device 900 also includes a second component 904 for selectively connecting a signal to a first load via a first signal path based on a control signal, which in an exemplary embodiment includes... Figure 4 Transistors T3 and T3' are shown. The device 900 also includes a third component 906 for selectively connecting a signal to a second load based on a control signal. This component includes a transistor that receives the signal and has a source terminal connected to signal ground, which in an exemplary embodiment includes transistor T21.

[0064] The exemplary embodiments of the signal amplifier and routing circuit (SARC) described herein can be implemented in ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. SARCs can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0065] The apparatus for implementing the Signal Amplifier and Router Circuit (SARC) described herein may be a standalone device or may be part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RF IC, such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC, such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a mobile phone, or a mobile unit, (vii) and so on.

[0066] In one or more exemplary designs, the described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored or transmitted as one or more instructions or code on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, with communication media including any medium that facilitates the transfer of a computer program from one place to another. A storage medium can be any available medium accessible to a computer. By way of example, and not limitation, such a computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is properly referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave) is included in the definition of medium. As used in this article, discs and platters include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where discs typically reproduce data magnetically, while platters optically reproduce data using lasers. The combinations described above should also be included within the scope of computer-readable media.

[0067] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but rather will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic device comprising: The first transistor has a gate terminal configured to receive an input signal, a drain terminal configured to output an amplified signal, and a source terminal connected to signal ground via a source degenerate inductor. The second transistor has a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first signal path; as well as The third transistor has a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to the second signal path, and a source terminal connected to the signal ground. The drain terminal of the third transistor is selectively connected to the first signal path via a switch.

2. The electronic device according to claim 1, further comprising: A fourth transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first signal path, the fourth transistor being configured to conduct the same or different amount of current as the second transistor.

3. The electronic device of claim 2, wherein the fourth transistor is selectively enabled or biased by a control signal for DC coupling to control the current to a first load connected to the first signal path.

4. The electronic device of claim 1, further comprising one or more additional transistors having one or more gate terminals respectively connected to the drain terminal of the first transistor, one or more drain terminals respectively connected to one or more signal paths, and one or more source terminals connected to the signal ground.

5. The electronic device of claim 4, wherein the one or more drain terminals are selectively connected to the one or more signal paths via one or more switches.

6. The electronic device of claim 5, wherein the one or more switches are selectively activated by one or more control signals.

7. The electronic device of claim 4, wherein the drain terminal of the one or more additional transistors is selectively connected to the first signal path via one or more switches.

8. The electronic device of claim 7, wherein the one or more switches are selectively activated by one or more control signals.

9. The electronic device of claim 1, wherein the second transistor is selectively enabled or biased by a control signal for DC coupling.

10. The electronic device of claim 1, wherein the drain terminal of the third transistor is selectively connected to the second signal path via a switch.

11. The electronic device of claim 10, wherein the switch is selectively enabled or biased for DC coupling by a control signal.

12. The electronic device of claim 4, wherein the first signal path connects the drain terminal of the second transistor to a first load, the second signal path connects the drain terminal of the third transistor to a second load, and the one or more signal paths respectively connect the drain terminals of the one or more additional transistors to one or more loads, wherein, The first load includes a primary load, and the second load and the one or more loads include carrier aggregation loads.

13. The electronic device of claim 4, wherein the first signal path includes a main signal path, and the second signal path and one or more signal paths include carrier aggregation signal paths.

14. The electronic device of claim 1, wherein the switch is selectively activated by a control signal.

15. The electronic device of claim 1, further comprising a controller for generating control signals to selectively enable the second transistor and the third transistor or bias the second transistor and the third transistor for DC coupling.

16. The electronic device of claim 1, wherein the electronic device is configured to perform configurable amplification and routing of a carrier aggregation signal in a receiver.

17. The electronic device of claim 1, wherein the electronic device is formed on an integrated circuit.

18. The electronic device of claim 1, further comprising an additional transistor having a gate terminal connected to the drain terminal of the third transistor, a drain terminal connected to an additional signal path, and a source terminal connected to the signal ground.

19. The electronic device of claim 18, wherein the drain terminal of the additional transistor is selectively connected to the first signal path via a switch.

20. The electronic device of claim 19, wherein the switch is selectively activated by a control signal.

21. The electronic device of claim 18, wherein the additional transistor is one of a plurality of additional transistors, each of the plurality of additional transistors having a gate terminal, a source terminal and a drain terminal, wherein the plurality of additional transistors form a chain such that the gate terminal of the plurality of transistors is coupled to the drain terminal of a corresponding preceding transistor, wherein the drain terminal of the plurality of transistors is coupled to a corresponding signal path, and wherein the source terminal of the plurality of transistors is connected to the signal ground.

22. The electronic device of claim 21, wherein the first signal path includes a main signal path, and the second signal path and the corresponding signal path include carrier aggregation signal paths.

23. An electronic device comprising: A component for generating a control signal that controls how a signal is amplified and routed to one or more signal paths, the signal being output from a first transistor having a source terminal connected to signal ground by a source degenerate inductor; A component for selectively connecting the signal to a first signal path based on the control signal; as well as A component for connecting the signal to a second signal path includes a transistor that receives the signal at a gate terminal and has a source terminal connected to the signal ground.

24. The electronic device of claim 23, further comprising: A second component for selectively connecting the signal to the first signal path based on the control signal is configured to conduct the same or different current amount as the component for selectively connecting the signal to the first signal path.

25. The electronic device of claim 23, further comprising: A component for connecting the signal to one or more additional signal paths includes one or more additional transistors connected to receive the signal at one or more gate terminals and having one or more source terminals connected to the signal ground.

26. The electronic device of claim 25, further comprising: A component for selectively connecting one or more additional signal paths to the first signal path based on the control signal.

27. The electronic device of claim 25, further comprising: A component for selectively connecting the second signal path to a load based on the control signal, and one or more components for selectively connecting the one or more additional signal paths to one or more loads respectively.

28. The electronic device of claim 23, further comprising: A component for connecting the second signal path to a third signal path includes a transistor having a gate terminal connected to the second signal path and a source terminal connected to the signal ground.

29. The electronic device of claim 23, wherein the first signal path includes a main signal path, and the second signal path includes a carrier aggregation signal path.

30. A method for operating an electronic device, comprising: A control signal is generated that controls how a signal is amplified and routed to one or more signal paths. The signal is output from a first transistor having a source terminal connected to signal ground by a source degenerate inductor. The signal is selectively connected to the first signal path based on the control signal; as well as Based on the control signal, the signal is selectively connected to a second signal path via a transistor, the transistor receiving the signal at its gate terminal and having a source terminal connected to the signal ground.

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