Adaptive error correction in quantum computing

Abstract

A method for adaptive error correction in quantum computing includes performing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In one embodiment, the method includes estimating a runtime duration of a quantum circuit design corresponding to a quantum algorithm in response to determining the initial state of the quantum processor, the quantum processor being configured to execute the quantum circuit design. In one embodiment, the method includes calculating an error scenario for the quantum circuit design. In one embodiment, the method includes selecting a quantum error correction method for the quantum circuit design using the error scenario and the initial state of the quantum processor. In one embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

Description

Technical Field

[0001] The present invention generally relates to methods for quantum computing. More specifically, the present invention relates to an adaptive error correction method in quantum computing. Background Art

[0002] In the following, unless explicitly distinguished in usage, a "Q" prefix in a word of a phrase indicates that the word or phrase is referenced in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, the branch of physics that explores how the physical world works at its most fundamental level. At this level, particles behave in strange ways, assume more than one state at the same time, and interact with other particles that are very far away. Quantum computing exploits these quantum phenomena to process information.

[0004] The computers we commonly use today are called classical computers (also referred to herein as "conventional" computers or conventional nodes, or "CN"). Conventional computers use conventional processors, which are manufactured using semiconductor materials and technologies, semiconductor memory, and magnetic or solid-state storage devices, which is called the Von Neumann architecture. In particular, the processors in conventional computers are binary processors, that is, they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (q-processors) use the unique properties of entangled quantum bit devices (compactly referred to herein as "qubits", multiple "qubits") to perform computing tasks. In a specific area of ​​quantum mechanics work, matter particles can exist in multiple states, such as an "on" state, an "off" state, and a simultaneous "on" and "off" state. Where binary computing using semiconductor processors is limited to using only ON and OFF states (equivalent to 1 and 0 in binary code), quantum processors exploit these quantum states of matter to output signals that can be used for data computing.

[0006] Traditional computers encode information in bits. Each bit can take on a value of 1 or 0, and these 1s and 0s act as on / off switches that ultimately drive the computer's functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent a 1 and 0 reasoning between possible outcomes of an event. Entanglement means that qubits in superposition can be related to each other in a nonclassical way; that is, the state of one qubit (it is either 1 or 0 or both) can depend on the state of another qubit, and when they are entangled, more information is contained in the two qubits than in two separate qubits.

[0007] Using these two principles, qubits operate as processors of information, allowing quantum computers to operate in a way that allows them to solve certain difficult problems that are intractable using conventional computers.

[0008] Superconducting qubits include a Josephson junction. A Josephson junction is formed by separating two thin-film superconducting metal layers with a non-superconducting material. When the metal in the superconducting layer becomes superconducting, for example by lowering the temperature of the metal to a specific cryogenic temperature, electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In a qubit, a Josephson junction - which acts as a dispersive nonlinear inductor - is electrically coupled in parallel with one or more capacitive devices that form a nonlinear microwave oscillator. The oscillator has a resonant / transition frequency determined by the values ​​of the inductance and capacitance in the qubit circuit.

[0009] The information processed by the qubit is carried or transmitted in the form of microwave signals / photons in the microwave frequency range. The microwave signals are captured, processed and analyzed in order to decrypt the quantum information encoded therein. The readout circuit is a circuit coupled to the qubit that is used to capture, read and measure the quantum state of the qubit. The output of the readout circuit is information that can be used by the q-processor to perform calculations.

[0010] Superconducting qubits have two quantum states - |0> and |1>. These two states can be two energy states of an atom, for example, the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of a nuclear or electron spin, two positions of a crystal defect, and two states of a quantum dot. Because the system has quantum properties, any combination of the two states is allowed and valid.

[0011] In order for quantum computations using qubits to be reliable, quantum circuits, such as the qubits themselves, readout circuits associated with the qubits, and other parts of the quantum processor, must not change the energy state of the qubits in any significant way, such as by injecting or dissipating energy, or affecting the relative phase between the |0> and |1> states of the qubit. This operational constraint on any circuit that operates with quantum information requires special considerations in the fabrication of semiconductor and superconducting structures used in such circuits.

[0012] In conventional circuits, Boolean logic gates arranged in series manipulate a series of bits. Techniques for optimizing gate logic for binary computations are well known. Circuit optimization software for conventional circuits is intended to improve efficiency and reduce the complexity of conventional circuits. Circuit optimization software for conventional circuits operates in part by breaking down the overall desired behavior of conventional circuits into simpler functions. Conventional circuit optimization software more easily manipulates and processes simpler functions. Circuit optimization software generates an efficient layout of design elements on conventional circuits. As a result, circuit optimization software for conventional circuits significantly reduces resource requirements, thereby improving efficiency and reducing complexity.

[0013] The illustrative embodiments recognize that in a quantum circuit, quantum gates manipulate qubits to perform quantum computations. A quantum gate is a unitary matrix transformation that acts on a qubit. Due to the superposition and entanglement of qubits, a quantum gate represents a 2n×2n matrix, where n is the number of qubits manipulated by the quantum gate. The illustrative embodiments recognize that because the size of the matrix transformation increases exponentially with the number of qubits, the decomposition of such a matrix transformation quickly becomes too complex to perform manually. For example, a quantum computer with 2 qubits requires 4 by 4 matrix operators for the quantum gate representation. As a result of the exponential increase, manual quantum logic gate matrix transformations quickly become unmanageable as the number of qubits increases. The depth of a quantum circuit is the total number of time steps. Each time step corresponds to a quantum logic gate acting on a set of qubits.

[0014] The illustrative embodiments recognize that quantum processors exhibit varying physical properties over time. The illustrative embodiments recognize that the calibration of a quantum processor determines the error rates of the associated qubits and quantum gates of the quantum processor. The illustrative embodiments further recognize that a quantum processor is typically calibrated only once or twice a day.

[0015] The illustrative embodiments recognize that quantum computers are more prone to errors than classical computers due to the sensitivity of quantum computers causing undesired interactions with the environment. The illustrative embodiments recognize that quantum states and quantum operations are continuous, i.e., belong to continuous intervals, which allows small errors to accumulate over the entire quantum circuit. The illustrative embodiments also recognize that classical error correction schemes perform measurements to query the nature and type of errors. The illustrative embodiments recognize that performing measurements on a quantum system collapses the quantum system and can result in the loss of information encoded in the quantum state from the quantum state to the classical state.

[0016] The illustrative embodiments recognize that currently available quantum error correction techniques require varying amounts of quantum computing resources to operate. A three-qubit bit-flip code uses three qubits to determine and correct an error in one of the three qubits. A first or target qubit is transmitted through a noisy channel that either flips the state of the first qubit with probability p or leaves the state of the first qubit unchanged. Thus, the state of the first qubit is correctly transmitted with probability 1-p.

[0017] To improve this probability, the state of the first qubit is encoded into multiple additional qubits. The first qubit is entangled with two auxiliary qubits, and all three qubits are initialized to the state |0>. When the encoded state of the three qubits is transmitted through a noisy channel, the channel acts on the encoded state and flips a subset of the three qubits. The probability that no qubit is flipped is (1-p)^3. The probability that a single qubit is flipped is 3p*(1-p)^2. Two qubits are flipped with probability 3*p^2*(1-p), and all three qubits are flipped with probability p^3.

[0018] The illustrative embodiments recognize that p is typically a very small number. By determining whether one qubit is different from the other qubits, a detection is made to determine whether one of the qubits is flipped. Since all qubits start out in the same state, if any qubit is different from the other qubits, the qubit is flipped when transmitted through the channel. If the qubit is flipped, a Pauli X gate or qubit-flip gate is applied to the flipped qubit.

[0019] The illustrative embodiments also recognize that sign flipping creates another error in a quantum computer. The Hadamard gate maps the ground state |0> to And map the ground state |1> to Using the three-qubit flip code described above, and adding a layer of Hadamard gates on each qubit before and after transmission through the noisy channel, the three-qubit bit-flip code is converted into a three-qubit sign-flip code.

[0020] The illustrative embodiments also recognize that more complex quantum error correction techniques require additional quantum computing resources. Shor codes require nine total qubits, one target qubit, and eight auxiliary qubits. Shor codes correct bit slips, sign flips, and any arbitrary single qubit errors. Steane codes require a total of seven qubits, one target qubit, and six auxiliary qubits to correct any arbitrary single qubit errors. Calderbank-Shor-Steane (CSS) codes require a total of a minimum of five qubits, one target qubit, and four auxiliary qubits to correct any arbitrary single qubit errors. The illustrative embodiments recognize that choosing an appropriate error correction technique depends on the available quantum computing resources. Summary of the invention

[0021] The illustrative embodiments provide a method for adaptive error correction in quantum computing. In one embodiment, the method includes performing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In one embodiment, the method includes estimating a runtime duration of a quantum circuit design corresponding to a quantum algorithm in response to determining the initial state of the quantum processor, the quantum processor being configured to execute the quantum circuit design.

[0022] In one embodiment, a method comprises calculating error scenarios for the quantum circuit design. In one embodiment, a method comprises using the error scenarios and the initial state of the quantum processor to select a quantum error correction method for the quantum circuit design. In one embodiment, a method comprises transforming the quantum algorithm into a quantum circuit design, the quantum circuit design comprising a set of quantum logic gates.

[0023] In one embodiment, a subset of the set of quantum logic gates corresponds to the selected quantum error correction method. In one embodiment, the initial state of the quantum processor includes the total number of qubits of the quantum processor. In one embodiment, the method includes determining the depth of the quantum circuit design.

[0024] In one embodiment, the method comprises assigning a set of weights to the set of quantum logic gates. In one embodiment, the method comprises comparing the quantum circuit design to a set of previously executed quantum circuit designs. In one embodiment, the method comprises determining a first computational cost of the selected quantum error correction method.

[0025] In one embodiment, the method includes determining a second computational cost of a probabilistic quantum error correction method. In one embodiment, the method includes comparing the quantum circuit design to a set of previously executed quantum circuit designs. In one embodiment, the method includes selecting a quantum error correction method for a first quantum circuit design in the set of previously executed quantum circuit designs. In one embodiment, the method includes transforming the quantum algorithm into a new quantum circuit design, the new quantum circuit design including a set of quantum logic gates corresponding to the first quantum circuit design.

[0026] One embodiment includes a computer usable program product. The computer usable program product includes a computer readable storage device and program instructions stored on the storage device.

[0027] In one embodiment, the computer usable code is stored in a computer readable storage device in a data processing system and wherein the computer usable code is transmitted from a remote data processing system over a network. In one embodiment, the computer usable code is stored in a computer readable storage device in a server data processing system and wherein the computer usable code is downloaded to the remote data processing system over a network for use in a computer readable storage device associated with the remote data processing system.

[0028] An embodiment includes a computer system. The computer system includes a processor, a computer-readable memory, a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The novel features which are believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, together with its preferred mode of use, further objects and advantages will be best understood by reference to the following detailed description of illustrative embodiments taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 A block diagram showing a network of data processing systems in which the illustrative embodiments may be implemented;

[0031] Figure 2 shows a block diagram of a data processing system in which the illustrative embodiments may be implemented;

[0032] Figure 3 shows an example configuration for adaptive error correction in quantum computing in accordance with an illustrative embodiment;

[0033] Figure 4 shows an exemplary configuration for calibrating a quantum processor in accordance with an illustrative embodiment;

[0034] Figure 5 shows an example configuration of a quantum circuit construction according to an illustrative embodiment;

[0035] Figure 6 A flow chart showing an example method for adaptive error correction in quantum computing according to an illustrative embodiment is shown;

[0036] Figure 7 A flow chart showing an example method for estimating the running time of a quantum circuit design corresponding to a quantum algorithm in accordance with an illustrative embodiment is shown;

[0037] Figure 8 A flowchart illustrating an example method for calculating error scenarios according to an illustrative embodiment; and

[0038] Fig. 9 A flowchart of an example method for selecting an error correction method is shown in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0039] The illustrative embodiments used to describe the present invention generally illustrate and address the above-mentioned need for reducing the error rate of qubits and quantum gates in quantum processors.The illustrative embodiments provide a method for adaptive error correction in quantum computing.

[0040] In one embodiment, initialization of a quantum algorithm on a quantum computer is detected. In this embodiment, an initial degenerate state of the quantum computer is determined. In a specific embodiment, a randomized benchmark is used to determine the initial degenerate state of the quantum computer. In a specific embodiment, a predetermined set of operations is performed on a plurality of qubits on the quantum computer. The predetermined set of operations generates a set of values ​​for each qubit in response to performing the predetermined set of operations. In one embodiment, at least one of the set of values ​​for each qubit is compared to an expected answer of at least one of the predetermined set of operations.

[0041] In one embodiment, a time period of the quantum algorithm is estimated. In a specific embodiment, a depth of the quantum circuit is determined. In one embodiment, an application determines a frequency of a plurality of gates executed on a set of qubits. In a specific embodiment, weights are assigned to quantum logic gates of a quantum circuit corresponding to the quantum algorithm. In a specific embodiment, quantum logic gates with greater error rates are assigned greater weights. In one embodiment, an application compares the estimated time period to a decoherence time of a set of qubits of the quantum processor.

[0042] In one embodiment, the quantum algorithm is compared to a second quantum algorithm, the second quantum algorithm corresponding to a compiled quantum circuit. In a specific embodiment, the initial state of the quantum computer is compared to a second initial state corresponding to the second quantum algorithm.

[0043] In one embodiment, an error correction method is selected in response to the comparison. In a specific embodiment, the error correction method includes executing multiple iterations of the quantum algorithm, the multiple iterations producing multiple outputs. In a specific embodiment, the multiple outputs are averaged. In a specific embodiment, a second time period of the selected error correction method is selected.

[0044] The operations described herein with respect to a frequency or multiple frequencies should be interpreted as signal generation with respect to the frequency or multiple frequencies. Unless clearly distinguished when used, all references to "signals" are references to microwave signals.

[0045] For the sake of clarity of description, and without implying any limitation thereto, some example configurations are used to describe the illustrative embodiments. Based on this disclosure, those skilled in the art will be able to conceive of many changes, adaptations and modifications of the configurations for achieving the described purposes, and these are considered to be within the scope of the exemplary embodiments.

[0046] In addition, simplified diagrams of example resistors, inductors, capacitors, and other circuit components are used in the drawings and illustrative embodiments. In actual manufacturing or circuits, there may be additional structures or components not shown or described herein, or structures or components that are different from the structures or components shown but have similar functions as described herein, without departing from the scope of the illustrative embodiments.

[0047] The illustrative embodiments are described with respect to certain types of materials, electrical characteristics, steps, quantities, frequencies, circuits, components, and applications by way of example only. Any particular manifestation of these and other similar artifacts is not intended to limit the present invention. Any suitable manifestation of these and other similar artifacts may be selected within the scope of the exemplary embodiments.

[0048] The examples in this disclosure are only for clear description and are not intended to limit the illustrative embodiments. Any advantages listed herein are only examples and are not intended to limit the illustrative embodiments. Additional or different advantages can be achieved through specific illustrative embodiments. In addition, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0049] With reference to the accompanying drawings, and with particular reference to Figure 1 and 2 , these figures are exemplary diagrams of data processing environments in which illustrative embodiments may be implemented. Figure 1 and Figure 2 This is merely an example and is not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Specific implementations may make many modifications to the illustrated environment based on the following description.

[0050] Figure 1A block diagram of a network of data processing systems in which the illustrative embodiments may be implemented is shown. Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between various devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0051] Client or server are merely example roles for certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles for these data processing systems. Classical processing system 104 is coupled to network 102. Classical processing system 104 is a classical processing system. Software applications can be executed on any quantum data processing system in data processing environment 100. Figure 1 Any software application executed in the classic processing system 104 in can be configured to execute in another data processing system in a similar manner. Figure 1 Any data or information stored or generated in the classical processing system 104 in the can be configured to be stored or generated in another data processing system in a similar manner. A classical data processing system such as the classical processing system 104 can contain data and can have software applications or software tools that perform classical computing processes thereon.

[0052] Server 106 is coupled to network 102 along with storage unit 108. Server 106 is a conventional data processing system. Storage unit 108 may store a set of quantum algorithms, a set of quantum circuits, a set of quantum logic gates, and a set of quantum error correction codes as described herein. Quantum processing system 140 is coupled to network 102. Quantum processing system 140 is a quantum data processing system. The software application may be executed on any quantum data processing system in data processing environment 100. Figure 1 Any software application executed in the quantum processing system 140 in can be configured to execute in another quantum data processing system in a similar manner. Figure 1 Any data or information stored or generated in a quantum processing system 140 in the can be configured to be stored or generated in another quantum data processing system in a similar manner. A quantum data processing system such as quantum processing system 140 can contain data and can have a software application or software tool that performs quantum computing processes on it.

[0053] Clients 110, 112, and 114 are also coupled to network 102. Conventional data processing systems, such as server 106 or clients 110, 112, or 114, may contain data and may have software applications or software tools that perform conventional computing processes thereon.

[0054] This is for example purposes only and does not imply any limitation on such architecture. Figure 1 Certain components that can be used in the example implementation of the embodiment are shown. For example, server 106 and client 110, 112, 114 are described as servers, while the client is only used as an example and does not imply limitation of the client-server architecture. As another example, the embodiment can be distributed over several conventional data processing systems, quantum data processing systems, and data networks as shown, while another embodiment can be implemented on a single conventional data processing system or a single quantum data processing system within the scope of the illustrative embodiment. Conventional data processing systems 106, 110, 112 and 114 also represent example nodes in clusters, partitions, and other configurations suitable for implementing the embodiment.

[0055] Device 132 is an example of a conventional computing device as described herein. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a fixed or portable form factor of client 110, a wearable computing device, or any other suitable device. Figure 1 Any software application that is executed in another conventional data processing system in the can be configured to be executed in the device 132 in a similar manner. Figure 1 Any data or information stored or generated in another conventional data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0056] Server 106, storage unit 108, classical processing system 104, quantum processing system 140, and clients 110, 112, and 114, and device 132 may be coupled to network 102 using wired connections, wireless communication protocols, or other suitable data connections. Clients 110, 112, and 114 may be, for example, personal computers or network computers.

[0057] In the depicted example, server 106 may provide data, such as boot files, operating system images, and applications to clients 110, 112, and 114. In this example, clients 110, 112, and 114 may be clients to server 106. Clients 110, 112, 114, or some combination thereof, may include their own data, boot files, operating system images, and applications. Data processing environment 100 may include additional servers, clients, and other devices not shown.

[0058] In the described example, memory 144 can provide data to quantum processor 142, such as previously compiled quantum algorithms, quantum logic gates, quantum error correction codes, boot files, operating system images, and applications. Quantum processor 142 can include its own data, boot files, operating system images, and applications. Data processing environment 100 may include additional memory, quantum processors, and other devices not shown. Memory 144 includes application 105, which can be configured to implement one or more of the quantum processor functions described herein according to one or more embodiments.

[0059] In the described example, data processing environment 100 can be the Internet. Network 102 can represent a collection of networks and gateways that use transmission control protocol / Internet protocol (TCP / IP) and other protocols to communicate with each other. At the core of the Internet is the backbone of data communication links between master nodes or host computers, including thousands of commercial, government, educational and other computer systems that route data and messages. Of course, data processing environment 100 can also be implemented as many different types of networks, such as intranets, local area networks (LANs) or wide area networks (WANs). Figure 1 It is intended as an example and not as an architectural limitation to the different illustrative embodiments.

[0060] Among other uses, data processing environment 100 can be used to implement a client-server environment in which exemplary embodiments can be implemented. A client-server environment enables software applications and data to be distributed on a network so that applications work by using the interactivity between a conventional client data processing system and a conventional server data processing system. Data processing environment 100 can also adopt a service-oriented architecture in which interoperable software components distributed on a network can be packaged together as consistent business applications. Data processing environment 100 can also take the form of a cloud, and adopt a cloud computing model of service delivery to realize convenient on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), which can be quickly supplied and released with minimal management effort or interaction with the provider of the service.

[0061] refer to Figure 2 , which shows a block diagram of a data processing system in which the illustrative embodiments may be implemented. Data processing system 200 is an example of a computer, such as Figure 1 Servers 104 and 106, or clients 110, 112, and 114, or another type of device, in which computer usable program code or instructions implementing the processes may be provided for exemplary embodiments.

[0062] Data processing system 200 also represents a data processing system or configuration thereof, such as Figure 1 Data processing system 132 in which computer usable program code or instructions implementing the processes of the exemplary embodiments may be placed. Data processing system 200 is described as a computer only as an example and is not limited thereto. Without departing from the general description of the operation and functionality of data processing system 200 described herein, the computer may be represented by a computer program such as a computer program. Figure 1 Implementation in the form of other devices of device 132 may modify data processing system 200 , such as by adding a touch interface, and even removing certain illustrated components from data processing system 200 .

[0063] In the illustrated example, data processing system 200 employs a hub architecture including north bridge and memory controller hub (NB / MCH) 202 and south bridge and input / output (I / O) controller hub (SB / ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled to north bridge and memory controller hub (NB / MCH) 202. Processing unit 206 may include one or more processors and may be implemented using one or more heterogeneous processor systems. Processing unit 206 may be a multi-core processor. In some implementations, graphics processor 210 may be coupled to NB / MCH 202 via an accelerated graphics port (AGP).

[0064] In the example shown, a local area network (LAN) adapter 212 is coupled to the south bridge and I / O controller hub (SB / ICH) 204. An audio adapter 216, a keyboard and mouse adapter 220, a modem 222, a read-only memory (ROM) 224, a universal serial bus (USB) and other ports 232, and a PCI / PCIe device 234 are coupled to the south bridge and I / O controller hub 204 via bus 238. A hard disk drive (HDD) or solid-state drive (SSD) 226 and a CD-ROM 230 are coupled to the south bridge and I / O controller hub 204 via bus 240. PCI / PCIe devices 234 may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not. ROM 224 may be, for example, a flash binary input / output system (BIOS). Hard disk drive 226 and CD-ROM 230 may use, for example, an integrated drive electronics (IDE), a serial advanced technology attachment (SATA) interface, or variations such as external SATA (eSATA) and micro SATA (mSATA). Super I / O (SIO) device 236 may be coupled to south bridge and I / O controller hub (SB / ICH) 204 via bus 238.

[0065] Memories, such as main memory 208, ROM 224, or flash memory (not shown), are some examples of computer usable storage devices. Hard disk drives or solid state drives 226, CD-ROM 230, and other similarly available devices are some examples of computer usable storage devices that include computer usable storage media.

[0066] An operating system runs on processing unit 206. The operating system coordinates and provides Figure 2 The operating system may be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices. An object-oriented or other type of programming system may operate with the operating system and provide calls to the operating system from programs or applications executing on data processing system 200.

[0067] for operating systems, object-oriented programming systems, and such Figure 1 Instructions for an application or program, such as application 105 in , are located on a storage device, such as in the form of code 226A on hard drive 226, and may be loaded into at least one of one or more memories, such as main memory 208, for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer-implemented instructions, which may be located in a memory, such as main memory 208, read-only memory 224, or in one or more peripheral devices.

[0068] In addition, in one case, code 226A can be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another case, code 226A can be downloaded to remote system 201B via network 201A, where downloaded code 201C is stored on storage device 201D.

[0069] Figure 1-Figure 2 The hardware in can vary depending on the implementation. Figure 1-Figure 2 In addition to or in place of the hardware described in , other internal hardware or peripheral devices such as flash memory, equivalent non-volatile memory, or optical drives may be used.

[0070] In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA), which is typically configured with flash memory to provide non-volatile memory for storing operating system files and / or user-generated data. The bus system may include one or more buses, such as a system bus, an I / O bus, and a PCI bus. Of course, the bus system may be implemented using any type of communication structure or architecture that provides data transfer between different components or devices attached to the structure or architecture.

[0071] The communication unit may include one or more devices for sending and receiving data, such as a modem or a network adapter. A memory may be, for example, main memory 208 or a cache, such as that found in north bridge and memory controller hub 202. A processing unit may include one or more processors or CPUs.

[0072] Figure 1-Figure 2 The examples described in and above are not meant to imply architectural limitations.For example, data processing system 200 may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile or wearable device.

[0073] Where a computer or data processing system is depicted as a virtual machine, virtual device, or virtual component, the virtual machine, virtual device, or virtual component uses virtualized representations of some or all of the components shown in data processing system 200 to operate in the manner of data processing system 200. For example, in the virtual machine, virtual device, or virtual component, processing unit 206 is represented as a virtualized instance of all or some number of hardware processing units 206 available in a host data processing system, main memory 208 is represented as a virtualized instance of all or some portion of main memory 208 available in the host data processing system, and disk 226 is represented as a virtualized instance of all or some portion of disk 226 available in the host data processing system. In this case, the host data processing system is represented by data processing system 200.

[0074] refer to Figure 3 , which shows an example configuration of adaptive error correction in quantum computing according to an illustrative embodiment. The example embodiment includes an application 302. In a particular embodiment, the application 302 is Figure 1 , the application 302 includes a calibration component 304 and a quantum circuit construction component 306. The calibration component 304 calibrates an input quantum processor 308 according to the exemplary methods described herein. The quantum circuit construction component 306 compiles an output quantum circuit design 310 according to the exemplary methods described herein.

[0075] refer to Figure 4, which shows an example configuration for calibrating a quantum processor according to an illustrative embodiment. The example embodiment includes an application 402. In a particular embodiment, the application 402 is Figure 1 An example of application 105 in FIG.

[0076] Application 402 includes a calibration component 404. In one embodiment, component 404 is Figure 3 As an example of components 304 in FIG. 4 , components 404 include calibration operator component 406 , qubit parameter analysis component 408 , and quantum gate parameter analysis component 410 . Application 402 receives calibration operation 412 .

[0077] The calibration operator 406 performs a calibration operation 412. In one embodiment, the calibration operation 412 performs a set of operations on a plurality of qubits Q1, Q2, Q3, ..., Qn of a quantum processor 414. In an embodiment, the calibration operation 412 performs a method of randomized benchmarking. For example, the calibration operation 412 may perform a predetermined set of operations on a plurality of qubits of the quantum processor 414. The predetermined set of operations generates a set of values ​​for each qubit in response to performing the predetermined set of operations. In one embodiment, the calibration operation 412 compares the set of values ​​for each qubit to an expected answer of at least one of the predetermined set of operations.

[0078] In one embodiment, calibration operation 412 returns a set 416 of qubit parameter values ​​for a plurality of qubits of quantum processor 414. For example, qubit coherence time, qubit relaxation time, measurement error, and other qubit parameter values ​​may be determined by the calibration operation. Each qubit of quantum processor 414 may include a subset of the set of parameter values. For example, qubit Q1 may include associated parameter values ​​P1, P2, ..., Pn, etc. These examples of qubit parameter values ​​are not limiting. In light of this disclosure, one of ordinary skill in the art will be able to envision many other qubit parameter values ​​suitable for calibrating a set of qubits, and the same is contemplated within the scope of the illustrative embodiments.

[0079] In one embodiment, calibration operation 412 returns a set of quantum gate parameters. For example, calibration operation 412 may return a parameter corresponding to the error rate of each quantum gate in quantum processor 414. In one embodiment, calibration operation 412 returns a parameter corresponding to the error rate of each and two qubit gates (primitive gates) in quantum processor 414.

[0080] Component 408 analyzes set of qubit parameter values ​​416. In one embodiment, component 408 analyzes set of qubit parameter values ​​416 according to at least one of set of qubit acceptability criteria 418. For example, component 408 can compare the parameter value of the qubit to the qubit acceptability criteria. For example, component 408 can determine that the coherence time of the qubit fails to meet the threshold coherence time to perform a set of operations. As another example, component 408 can determine that the coherence time of another qubit meets the threshold coherence time to perform the set of operations.

[0081] Component 410 analyzes a set of quantum gate parameters. In one embodiment, the quantum gate parameters correspond to a set of qubits that form the quantum gate and the layout of these qubits on the quantum processor. In one embodiment, calibration operation 412 returns a set of quantum gate parameter values ​​for multiple quantum gates of quantum processor 414. For example, gate error rate, gate speed, gate crosstalk matrix, and other quantum gate parameter values ​​can be determined by calibration operation. Each quantum gate of quantum processor 414 can include a subset of the set of quantum gate parameter values. These examples of quantum gate parameters are not limiting. In light of this disclosure, one of ordinary skill in the art will be able to envision many other quantum gate parameter values ​​suitable for calibrating a set of quantum gates, and these parameter values ​​can be envisioned within the scope of exemplary embodiments.

[0082] Component 410 analyzes the set of quantum gate parameter values. In one embodiment, component 410 analyzes the set of quantum gate parameter values ​​according to at least one criterion in a set of quantum gate acceptability criteria 420. For example, component 410 can compare the parameter values ​​of the quantum gate to the quantum gate acceptability criteria. For example, component 410 can determine that the gate error rate of the quantum gate fails to meet a threshold error rate to execute the quantum gate.

[0083] In one embodiment, component 410 generates a composite gate error rate for a composite gate based on a set of raw gate error rates, the composite gate being formed from a set of raw gates corresponding to the raw gate error rates. In one embodiment, component 410 generates a composite gate error rate for a composite gate formed using three qubits from the formula

[0084]

[0085] Among them A xy and B xy is the raw gate error rate of the quantum gates formed by qubits x and y during the first and second calibration operations, respectively.

[0086] refer to Figure 5 , which shows an example configuration of a quantum circuit construction according to an illustrative embodiment. The example embodiment includes an application 502. In a specific embodiment, the application 502 is Figure 1 An example of application 105 in FIG.

[0087] Application 502 includes a quantum circuit construction component 504. In a specific embodiment, component 504 is Figure 3 , component 504 includes a quantum circuit compiler component 506. Component 506 is configured to transform an input quantum algorithm 514 into a quantum circuit design 530. Component 516 includes an algorithm transformation component 508.

[0088] Component 508 transforms the quantum algorithm code into a first quantum circuit design corresponding to the operations performed by the quantum algorithm. Application 502 receives a set of quantum circuit designs 528 stored in database 524. In a specific embodiment, each quantum circuit design 528 includes a previously determined runtime estimate. In a specific embodiment, the runtime estimate for each of the stored set of quantum circuit designs is determined based on previously executing each of the set of quantum circuit designs on a quantum processor. Database 524 is Figure 1 In one embodiment, the running time estimation component 510 determines the running time of the quantum algorithm 522. In one embodiment, the component 510 compares the quantum algorithm 522 to a set of quantum algorithms corresponding to the quantum circuit design set 528. In a specific embodiment, the component 510 compares the total number of quantum logic gates in the quantum circuit design 530 to the total number of quantum logic gates in at least one of the stored quantum circuit design sets.

[0089] Component 510 includes circuit depth component 512 and gate weight factors 514. In one embodiment, circuit depth component 514 determines the depth of quantum circuit design 530. In one embodiment, gate weight factors 514 assign a set of weights to a set of quantum logic gates in quantum circuit design 530. In a specific embodiment, a subset of a set of quantum logic gates having a relatively high error rate has a larger weight factor than a subset of quantum logic gates having a lower error rate.

[0090] Error scenario component 516 determines a worst-case error scenario for quantum circuit design 530. In one embodiment, circuit comparison component 518 analyzes quantum circuit design 530 to determine the number of quantum logic gates, the type of quantum logic gates, and the state of a quantum processor configured to execute quantum circuit design 530. In a specific embodiment, circuit comparison component 518 determines the decoherence time of a set of qubits of the quantum processor. In a specific embodiment, each of quantum circuit design set 528 includes a state of the quantum processor determined prior to executing the corresponding quantum circuit design.

[0091] In one embodiment, circuit comparison component 518 compares the quantum circuit design 530 and the state of the quantum processor with a set of quantum logic gates and a corresponding set of states of the quantum processor. In one embodiment, component 518 selects a quantum circuit design similar to quantum circuit design 530 from quantum circuit design set 528. In a specific embodiment, component 518 compares the total number of quantum logic gates, the type of quantum logic gates, and the initial state of the quantum processor between the quantum circuit designs.

[0092] In one embodiment, the error correction selection component 520 analyzes the quantum circuit design 530, the runtime estimate, and the state of the quantum processor to select an appropriate error correction method. In one embodiment, the component 520 analyzes the number of qubits required to execute the quantum circuit design 530. In one embodiment, the component 520 analyzes the total number of qubits available for performing calculations on the quantum processor. In a specific embodiment, the component 520 determines the remaining set of qubits available for quantum error correction on the quantum processor. For example, the component 520 may determine that five qubits are required to execute the quantum circuit design 530. The component 520 may determine that a total of eight qubits are available for calculations on the quantum processor. The component 520 may determine that the remaining three qubits are available for quantum error correction.

[0093] In one embodiment, component 520 selects an appropriate quantum error correction technique in response to determining a subset of the set of qubits available for quantum error correction on the quantum processor. In a specific embodiment, component 520 selects a quantum error correction technique that produces the highest level of accuracy while also making the available qubits suitable for quantum error correction. In a specific embodiment, component 520 selects a quantum error correction technique based on the type of quantum logic gates in quantum circuit design 530.

[0094] The probability comparison component 520 determines the number of iterations of executing the quantum circuit design 530 on the quantum processor that is necessary to reach a threshold level of accuracy. For example, the component 520 may determine that 120 iterations are required to produce a 99% level of accuracy. The component 520 determines the running time of the selected quantum error correction method. The component 520 compares the running time of the selected quantum error correction method with the running time for performing additional iterations to reach the threshold level of accuracy. For example, the component 520 may determine that performing additional iterations produces a similar level of accuracy in less time than the selected quantum error correction method. The application 502 outputs the quantum circuit design 530 with the corresponding selected quantum error correction method 532.

[0095] refer to Figure 6, which shows a flow chart of an example method for adaptive error correction in quantum computing according to an illustrative embodiment. In one embodiment, application 105 performs method 600.

[0096] In block 602, application 105 determines an initial state of the quantum processor. In one embodiment, application 105 performs a calibration operation on a set of qubits in a first iteration. In one embodiment, the calibration operation produces a set of parameters, a first subset of the set of parameters corresponding to a first qubit of the set of qubits, and a second subset of the set of parameters corresponding to a second qubit of the set of qubits. In one embodiment, application 105 performs a predetermined operation on the first qubit. In one embodiment, application 105 compares an output of the predetermined operation to an expected output.

[0097] In box 604, application 105 estimates the runtime duration of the quantum circuit design corresponding to the quantum algorithm. In box 606, application 105 calculates error scenarios for the quantum circuit design corresponding to the quantum algorithm. In box 608, application 105 selects an appropriate error correction method for the quantum circuit design corresponding to the quantum algorithm. In box 610, application 105 transforms the quantum algorithm into a quantum circuit design, which includes a set of quantum logic gates. In one embodiment, a subset of the set of quantum logic gates corresponds to the selected error correction method. Thereafter, application 105 ends process 600.

[0098] refer to Figure 7 , which shows a flow chart of an example method for estimating the running time of a quantum circuit design corresponding to a quantum algorithm according to an illustrative embodiment. In one embodiment, application 105 performs method 700 at block 604. In block 702, application 105 determines the depth of a quantum circuit corresponding to a quantum algorithm. In block 704, application 105 assigns a set of weights to a set of quantum logic gates in the quantum circuit design. Thereafter, application 105 ends process 700.

[0099] refer to Figure 8 , which shows a flow chart of an example method for computing error scenarios according to an illustrative embodiment. In one embodiment, application 105 performs method 800 at block 606. In block 802, application 105 assigns a set of weights to a set of error scenarios. In block 804, application 105 compares the quantum circuit design to a set of previously executed quantum circuit designs stored in a database. Application 105 thereafter ends process 800.

[0100] refer to Fig. 9, which shows a flow chart of an example method for selecting an error correction method according to an illustrative embodiment. In one embodiment, the application 105 performs the method 900 at block 608. In block 902, the application 105 determines a first computational (evaluated) cost of the selected error correction method. In block 904, the application 105 determines a second computational (evaluated) cost of the probabilistic error correction method. In block 906, the application 105 compares the first computational cost and the second computational cost. In one embodiment, the application 105 selects the error correction method with the lower computational cost. Thereafter, the application 105 ends the process 900.

[0101] Various embodiments of the present invention are described herein with reference to the relevant drawings. Without departing from the scope of the present invention, alternative embodiments may be designed. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and drawings, it will be appreciated by those skilled in the art that many positional relationships described herein are orientation-independent when the described functions are maintained even when the orientation is changed. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this regard. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, it is mentioned in this specification that forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant characteristics and functions of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0102] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0103] Additionally, the term "illustrative" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" may include both indirect "connections" and direct "connections."

[0104] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0105] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time this application was filed. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0106] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

[0107] Thus, in illustrative embodiments, a computer-implemented method, system or apparatus, and computer program product are provided for managing participation in an online community and other related features, functions, or operations. Where embodiments or portions thereof are described with respect to one type of device, the computer-implemented method, system or apparatus, computer program product, or portions thereof, is adapted or configured for use with appropriate and comparable representations of that type of device.

[0108] Where embodiments are described as being implemented in an application, delivery of the application in a software as a service (SaaS) model may be envisioned within the scope of the illustrative embodiments. In the SaaS model, the ability to implement the application of the embodiments is provided to the user by executing the application in a cloud infrastructure. The user may access the application using a variety of client devices through a thin client interface such as a web browser (e.g., web-based email) or other lightweight client applications. The user does not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage of the cloud infrastructure. In some cases, the user may not even manage or control the capabilities of the SaaS application. In some other cases, a SaaS implementation of the application may allow limited possible exceptions to user-specific application configuration settings.

[0109] The present invention may be a system, method and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, and the computer-readable program instructions are used to cause a processor to perform various aspects of the present invention.

[0110] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0111] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0112] The computer program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0113] Various aspects of the present invention are described herein with reference to the flow charts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flow chart and / or block diagram and the combination of each box in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0114] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0115] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0116] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

Claims

1. A computer-implemented method comprising: determining a set of parameters of the quantum processor by performing a calibration operation on the quantum processor, the calibration operation performing a set of operations on a plurality of qubits of the quantum processor, the parameter set characterizing states of components of the quantum processor, the parameter set including an initial state of the quantum processor; determining a number of qubits that can be used for error correction when the quantum processor executes the quantum circuit design by analyzing the quantum circuit design to be executed by the quantum processor using the initial state of the quantum processor; selecting a first error correction technique from a library of error correction techniques, the first error correction technique being implemented using the number of qubits available for error correction, the first error correction technique having a first level of accuracy and a first runtime required for the quantum processor to execute the first error correction technique; probabilistically determining, by analyzing the quantum circuit design and the parameter set, a number of iterations of the quantum circuit design required to obtain a threshold accuracy when the quantum processor executes the quantum circuit design with an error rate determined by a calibration operation and averaging output sets over multiple iterations; determining a second running time required for the quantum processor to execute the number of iterations by analyzing the quantum circuit design and the parameter set; as well as In response to determining that the first runtime is shorter than the second runtime, executing, by the quantum processor, an error-corrected quantum circuit design, the error-corrected quantum circuit design comprising the quantum circuit design and the first error correction technique.

2. The computer-implemented method of claim 1 , further comprising: In response to determining that the second runtime is shorter than or equal to the first runtime, executing the quantum circuit design by the quantum processor for the number of iterations. 3 . The computer-implemented method of claim 1 , wherein the calibration operation comprises generating the set of parameters by comparing results of operations in the set of operations with expected results.

4. The computer-implemented method of claim 1 , wherein the calibration operation determines a set of qubit parameter values ​​for the plurality of qubits of the quantum processor.

5. The computer-implemented method of claim 1, wherein the calibration operation determines a set of quantum gate parameters of the quantum processor.

6. The computer-implemented method of claim 1 , wherein the number of qubits available for error correction comprises the total number of qubits of the quantum processor minus the number of qubits required for the quantum processor to execute the quantum circuit design.

7. The method of claim 1, wherein the first error correction technique is selected based on a first accuracy level that is equal to or greater than a threshold accuracy level.

8. A computer usable program product, comprising a computer readable storage device and program instructions stored on the storage device, the stored program instructions comprising program instructions for implementing the method according to any one of claims 1 to 7.

9. A computer system comprising a processor, a computer-readable memory and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory, the stored program instructions comprising program instructions for implementing the method according to any one of claims 1 to 7.

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