A system of electrically isolated, data coupled microcontrollers

Abstract

System consisting of electrically isolated, data-coupled microcontrollers. The invention relates to a system consisting of microcontrollers, having a first microcontroller (100) and a second microcontroller (200), wherein the first microcontroller (100) and the second microcontroller (200) are electrically isolated (400) from one another, wherein the first microcontroller (100) has a first processor unit (110) and a first communication interface (120) connected to the first processor unit (110), the first communication interface being set up to enable direct memory access to a memory unit (140, 141, 142) of the first processor unit, wherein the second microcontroller (200) has a second processor unit (210) and a second communication interface (220) connected to the second processor unit (210), the second communication interface being set up to enable direct memory access to a memory unit (240, 241, 242) of the second processor unit, and wherein the first communication interface (120) and the second communication interface (220) are coupled (300) to one another.

Description

Technical Field

[0001] This invention relates to a system consisting of electrically isolated microcontrollers. Background Technology

[0002] For example, modern microcontrollers used in (motor) vehicles mostly include additional peripheral devices in addition to the processor unit or microprocessor and storage unit (flash memory, EEPROM memory, RAM memory, etc.), such as network interface, ADC, DAC, timer, CAN, I / O, etc. These peripheral devices are connected to each other and maintain communication with each other through internal communication systems, such as internal buses.

[0003] Such processor units or microprocessors are mostly constructed as multi-core processors with multiple (at least two) processor cores. A processor core includes an arithmetic logic unit (ALU), which is the actual electronic arithmetic unit used to execute tasks, programs, calculation instructions, etc.; and also includes one or more local memories. Such local memories can be constructed, for example, as cache memory, a register bank consisting of one or more registers, or as RAM memory.

[0004] In technological applications such as (motor) vehicles, a large number of different microcontrollers are often used, and these microcontrollers can often be positioned in different voltage domains. Thus, different on-board electrical networks can be configured in a vehicle, with different supply or on-board voltages, such as a low-voltage on-board electrical network with a low supply voltage, for example, 12V or 24V; and a high-voltage on-board electrical network with a high supply voltage, for example, 48V or even 800V. For safety reasons, such as to prevent feedback in fault conditions and to avoid crosstalk and voltage spikes, such on-board electrical networks with different voltage levels are mostly electrically isolated and do not share a common reference potential. Therefore, the microcontrollers located in these on-board electrical networks are also electrically isolated from each other. Exchanging data or signals between such electrically isolated microcontrollers often proves to be complex and expensive. Exemplary implementations that couple different microcontrollers via a vehicle bus system (such as CAN) are thus limited in terms of data rate and latency. Summary of the Invention

[0005] According to the present invention, a system comprising electrically isolated microcontrollers having the features of claim 1 is proposed. Advantageous designs are the subject of the dependent claims and the following description.

[0006] The system has a first microcontroller and a second microcontroller, which are electrically isolated from each other. Therefore, there is no common reference potential between the two microcontrollers. The first microcontroller is specifically configured to be connected to a first supply voltage source, and the second microcontroller is specifically configured to be connected to a second supply voltage source, wherein the first and second supply voltage sources are electrically isolated. Furthermore, the first and second supply voltage sources suitably provide different levels of supply voltage. The first and second microcontrollers are respectively located in different voltage domains, and there is no common reference potential for these two voltage domains. It is readily understood that other components, besides the respective microcontrollers, can be located in these voltage domains. It is also readily understood that the system may also have other microcontrollers and other components.

[0007] The present invention now provides the possibility of coupling these electrically isolated microcontrollers or their processor units to each other in a data transmission manner, so that the microcontrollers or their processor units can communicate directly with each other.

[0008] The first microcontroller has a first processor unit and a first communication interface connected to the first processor unit. This first communication interface is configured to enable direct memory access (DMA) of the memory units of the first processor unit, particularly working memory such as RAM or registers. Correspondingly, the second microcontroller has a second processor unit and a second communication interface connected to the second processor unit. This second communication interface is configured to enable direct memory access of the memory units of the second processor unit, particularly working memory such as RAM or registers. The first and second communication interfaces are connected for data transmission via an isolation coupler, for example, via an optocoupler, magnetic coupler, or capacitive coupler.

[0009] The first and second processor units can be configured as single-core processors with one processor core, or suitably as multi-core processors with multiple processor cores. Specifically, the first processor unit and the first communication interface are connected to the internal communication or connection system of the first microcontroller, for example, to the internal bus of the first microcontroller or to an internal crossbar connection. Correspondingly, the second processor unit and the second communication interface are also connected to the corresponding internal communication or connection system of the second microcontroller. Furthermore, in the first or second microcontroller, other components can suitably be connected to the respective processor unit and the respective communication interface via corresponding communication or connection systems, particularly memory units such as flash memory, EEPROM memory, RAM memory, etc., and additional peripheral devices such as network interfaces, ADCs, DACs, timers, CAN, I / O, etc.

[0010] By means of coupling between the first and second communication interfaces, a virtual connection can be appropriately established between the communication or connection systems of the first and second microcontrollers. In particular, this can create a virtual, cross-microcontroller communication or connection system through which the first and second processor units can communicate directly with each other.

[0011] Furthermore, these processor units can particularly suitably access components of another microcontroller directly via coupled communication interfaces, especially components that are connected to the internal communication or connection system of the other microcontroller. Thus, for example, a processor unit of one of the two microcontrollers can directly access the memory or peripheral devices of the other microcontroller via coupling.

[0012] This invention provides a tightly coupled multi-core processor system in which each processor unit is positioned on a different electrically isolated voltage domain. By coupling these two microcontrollers via these communication interfaces, the number of signals that must cross the voltage domains of these microcontrollers can be significantly reduced. For example, fast signals or regulation loops can be processed locally.

[0013] In the implementation of a system with microcontrollers from the same processor family, the program code can be allocated most rationally from the perspectives of resource allocation, runtime characteristics, and access to interfaces of the corresponding voltage domains. This allocation of program code can be specifically defined once during the initial programming process.

[0014] Due to the high performance of the communication interface, especially its high data rate and low latency, it is suitable to bundle code portions onto a microcontroller, with only specific portions implemented in another microcontroller. This allows for flexible allocation of similar software code portions.

[0015] Furthermore, for example, a greater selection of resources or peripherals can be achieved by having one microcontroller's processor unit access the peripherals of another microcontroller through a coupled communication interface.

[0016] These communication interfaces are specifically used to couple the internal communication system of the microcontroller and thus the processor units. Particularly advantageously, these processor units maintain bidirectional or full-duplex communication connections via these communication interfaces. In particular, data can be transmitted simultaneously in both directions between the two processor units. Therefore, each of these processor units can particularly suitably send data to and receive data from the other processor unit simultaneously.

[0017] Preferably, the first and second communication interfaces are optically coupled. Signals are transmitted optically between these communication interfaces. In particular, electrical and optical signals are converted for this purpose. For data transmission, electrical signals are suitably converted into optical signals at the respective transmitting communication interface, and these optical signals are transmitted via coupling to another receiving communication interface. There, the optical signals are suitably converted back into electrical signals. Therefore, for data or signals to be transmitted between these microcontrollers, it is particularly suitable that no electrical connection is required between these microcontrollers.

[0018] Particularly preferably, the first and second communication interfaces are coupled via at least one optocoupler. Specifically, the different transmitting and receiving units (transceivers) of these two communication interfaces are coupled to each other via optocouplers. Optocouplers are particularly used as coupling mechanisms or optoelectronic device elements for optically transmitting signals between electrically isolated elements. For this purpose, the optocoupler particularly comprises: an optical transmitter, such as a light-emitting diode (LED) or a laser diode (LD); and an optical receiver, such as a photodiode, phototransistor, triac, etc., wherein the transmitter and receiver are optically coupled and connected, for example, via a light conductor.

[0019] Preferably, the first and second communication interfaces are configured as full-duplex interfaces, particularly as high-speed full-duplex interfaces, and are preferably configured for simultaneous bidirectional transmission. Therefore, simultaneous data transmission between the first and second processor units can be particularly achieved. Suitably, the two processor units can simultaneously send and receive data.

[0020] Advantageously, the first and second communication interfaces are respectively configured as LVDS interfaces ("Low Voltage Differential Signalling"). LVDS is an interface standard for high-speed data transmission standardized according to ANSI / TIA / EIA-644-1995. Such LVDS interfaces feature low voltage levels and differential voltage levels. Furthermore, a constant current source is used to generate the signal. Such LVDS interfaces can be configured, for example, as a so-called LFAST / SIPI interface ("LVDS Fast Asynchronous Serial Transmission Interface", LFAST, or "Serial Inter-Processor Interface", SIPI) or, for example, as a so-called HSCT / HSSL interface ("High Speed ​​Serial Link", HSSL).

[0021] According to a preferred design, at least five signal terminals of the first communication interface and at least five signal terminals of the second communication interface are coupled to each other. Particularly suitably, these signal terminals are coupled optically, especially via one or more optocouplers. These signal terminals are particularly used for coupling signal input or output.

[0022] Particularly preferably, the at least five signal connection terminals of the first communication interface and the at least five signal connection terminals of the second communication interface each include: at least one signal connection terminal for transmitting time or clock signals; at least two signal connection terminals for outputting data signals; and at least two signal connection terminals for receiving data signals. Therefore, two signal connection terminals of one communication interface suitably serve as output connection terminals to transmit data signals to the other communication interface. Correspondingly, two of these signal connection terminals serve as input connection terminals for receiving data signals from the other communication interface. The clock signal is particularly used to synchronize the microcontroller or its internal clock generation. In particular, one of these microcontrollers is configured as a master, which pre-determines a time base for another microcontroller configured as a slave.

[0023] Particularly suitably, the signal terminals for clock signals of the two communication interfaces are coupled via a first optocoupler. At least two input terminals of the first communication interface are coupled to at least two output terminals of the second communication interface, particularly via a second optocoupler. Correspondingly, at least two output terminals of the first communication interface are coupled to at least two input terminals of the second communication interface via a third optocoupler.

[0024] The first processor unit is preferably configured to access memory cells connected to the second processor unit during a Direct Memory Access (DMA) process via a coupled communication interface. Correspondingly, the second processor unit is preferably configured to access memory cells connected to the first processor unit during a Direct Memory Access (DMA) process via a coupled communication interface. In particular, these memory cells are connected to the respective processor units via corresponding microcontroller internal communication systems. These memory cells can be, for example, flash memory, EEPROM memory, or RAM memory. Therefore, these processor units can particularly suitably communicate with each other via the coupled communication interface during DMA access. Through such Direct Memory Access (DMA), these processor units can suitably achieve direct access to memory cells connected to the corresponding other processor unit without communicating with the other processor unit.

[0025] According to a particularly advantageous design, systems composed of microcontrollers are used in (motorized) vehicles. These microcontrollers can be used, in particular, in the vehicle's electrically isolated control devices.

[0026] A first microcontroller is advantageously disposed in a first on-board electrical network, in which a first supply voltage source provides the first on-board electrical network voltage. A second microcontroller is advantageously disposed in a second on-board electrical network, in which a second supply voltage source provides the second on-board electrical network voltage. These two on-board electrical networks are suitably electrically isolated from each other and do not share a common reference potential. Suitably, the two on-board electrical network voltages are different. One of these two on-board electrical networks is particularly configured as a low-voltage on-board electrical network, having a low on-board electrical network voltage of, for example, 12V. The other on-board electrical network is suitably configured as a high-voltage on-board electrical network, having a high on-board electrical network voltage of, for example, between 48V and 800V. Communication between these electrically isolated on-board electrical networks or their control devices is particularly possible, as the signals do not share a common reference potential.

[0027] Other advantages and designs of the present invention will become apparent from the description and the accompanying drawings.

[0028] The present invention is schematically illustrated in the accompanying drawings according to embodiments and is described below with reference to the accompanying drawings. Attached Figure Description

[0029] Figure 1 The illustration schematically shows a preferred design of a system composed of microcontrollers according to the present invention.

[0030] Figure 2 A fragment of a preferred design of a system composed of microcontrollers according to the present invention is illustrated schematically. Detailed Implementation

[0031] Figure 1 The schematic illustration shows a preferred design of a system comprising a first microcontroller 100 and a second microcontroller 200 according to the present invention.

[0032] Microcontrollers 100 and 200 are respectively installed in the vehicle's control equipment and also in different vehicle electrical networks 410 and 420.

[0033] For example, a first microcontroller 100 is disposed in a first vehicle electrical network 410, in which a first supply voltage source 411 provides the first vehicle electrical network voltage, and a second microcontroller 200 is disposed in a second vehicle electrical network 420, in which a second supply voltage source 421 provides the second vehicle electrical network voltage. For example, the first vehicle electrical network 410 is a low-voltage vehicle electrical network with a vehicle electrical network voltage of 12V, and the vehicle electrical network 420 is a high-voltage vehicle electrical network with a vehicle electrical network voltage of 48V. For safety reasons, such as to prevent feedback in fault conditions and to avoid crosstalk and voltage spikes, the vehicle electrical networks 410, 420 and therefore the microcontrollers 100, 200 are electrically isolated and do not share a common reference potential. Each vehicle electrical network in the vehicle electrical networks 410, 420 has its own independent reference potential 412 or 422. Figure 1 The diagram also schematically illustrates the electrical isolation between microcontrollers 100 and 200 using a dashed line 400.

[0034] The first microcontroller 100 has a first processor unit 110, which has two processor cores 111 and 112. For example, each processor core 111 and 112 may have an arithmetic logic unit and internal RAM memory, and an interface for connecting the processor cores 111 and 112 to a microcontroller internal communication system 101 of the first microcontroller 100. The microcontroller internal communication system 101 may be configured, for example, as a crossbar connection.

[0035] The communication system 101 is specifically configured as a processor core communication system so that other components of the microcontroller 100 can be directly connected to processor cores 111 and 112. In particular, different memory units are connected to crossbar connection 101, such as flash memory 140, EEPROM memory 141, and RAM memory 142.

[0036] Furthermore, a second microcontroller internal communication system 102, such as another crossbar connection 102, is provided within the microcontroller 100. This other crossbar connection 102 can be specifically configured for peripheral units. For example, multiple different interfaces 150, 151, 152, 153, 154, and 155 can be provided to allow the microcontroller 100 to connect to vehicle components such as sensors, actuators, fieldbuses, etc. For example, a message buffer or buffer 160 is connected to the other crossbar connection 102, which can be connected to the vehicle's fieldbus (e.g., CAN or the like) for receiving or sending messages via two connection terminals 161 and 162. Additionally, an analog-to-digital converter 170 is connected to the crossbar connection 102.

[0037] The two crossbar switches 101 and 102 of the first microcontroller 100 are also interconnected via a unit 103 for Direct Memory Access (DMA). In this way, the peripheral units can appropriately access the memory units 140, 141, and 142 directly without communicating with the processor cores 111 and 112.

[0038] The first microcontroller 100 also has a first communication interface 120, which is connected to the processor unit 110 or to the processor cores 111 and 112 via a crossbar switch connection 102. In addition, the first microcontroller 100 may also have other communication interfaces 130 and 131, which may be constructed, for example, corresponding to the communication interface 120.

[0039] The communication interface 120 is configured to couple the first microcontroller 100 or its processor unit to the second microcontroller 200.

[0040] The second microcontroller 200 is designed, for example, in the same manner as the first microcontroller 100. The components of the second microcontroller 200 are characterized by reference numerals with the added value 100, and these components are the same as or have the same structure as the components of the first microcontroller 100.

[0041] The first communication interface 120 and the second communication interface 220 are coupled to each other in a data transmission manner via an isolation coupler, and particularly suitably in an optical manner via a coupling mechanism 300 for optically transmitting signals between electrically isolated elements.

[0042] Through the coupling 300 of the communication interfaces 120 and 220, the first processor unit 110 or processor cores 111 and 112 and the second processor unit 210 or its processor cores 211 and 212 maintain a direct communication connection with each other.

[0043] By means of the coupling 300 between communication interfaces 120 and 220, a virtual connection can be suitably established between the processor core communication systems or cross-connections 101 and 201 of the first and second microcontrollers 100 and 200. Particularly suitably, this creates a virtual, cross-microcontroller communication system for the processor cores 111, 112, 211, and 212 of the two microcontrollers 100 and 200, through which the first and second processor units 110 and 210 can communicate directly with each other.

[0044] Furthermore, this virtual, cross-microcontroller communication system enables direct memory access from the processor unit of one microcontroller to the memory unit of the corresponding microcontroller. For example, the first processor unit 110 or its cores 111, 112 can directly access the memory units 240, 241, 242 of the second microcontroller 200 during direct memory access via coupled communication interfaces 120, 220. Correspondingly, the second processor unit 210 or its cores 211, 212 can directly access the memory units 140, 141, 142 of the first microcontroller 100 during direct memory access via coupled communication interfaces 120, 220.

[0045] Communication interfaces 130 and 230 are configured, for example, as full-duplex interfaces for simultaneous bidirectional data transmission, enabling the two processor units of microcontrollers 110 and 120 to exchange data with each other simultaneously. Furthermore, communication interfaces 130 and 230 are configured, for example, as LVDS interfaces with low voltage differential signaling (LVDS).

[0046] In particular, this communication is implemented via communication interfaces 130 and 230 according to the HSSL (High Speed ​​Serial Link) protocol. However, the invention is not limited to this and can be applied in conjunction with any other suitable type of interface.

[0047] Figure 2 A fragment of a preferred design of a system composed of microcontrollers according to the invention is illustrated schematically. Figure 2 The diagram schematically illustrates the communication interfaces 120 and 220 of microcontrollers 110 and 210, as well as the coupling mechanism 300. Here, Figure 1 and 2 The same reference numerals in the figures indicate the same or structurally identical elements.

[0048] The first communication interface 120 has a first signal connection terminal 121 for transmitting time signals. Correspondingly, the second communication interface 220 has a signal connection terminal 221 for receiving time signals. For example, the first microcontroller 100 can act as a master and the second microcontroller 200 can act as a slave, wherein the master microcontroller 100 sends a corresponding time signal to the slave microcontroller 200 to establish a common time base.

[0049] The second communication interface 220 also includes two signal connection terminals 222 and 223 for outputting data signals, particularly a positive connection terminal 222 and a negative connection terminal 223. Correspondingly, the first communication interface 120 also includes a positive signal connection terminal 124 and a negative signal connection terminal 125 for outputting data signals.

[0050] The first communication interface 120 also has positive and negative signal connection terminals 122 or 123 for receiving data signals, and the second communication interface 220 correspondingly has a positive signal connection terminal 224 and a negative signal connection terminal 225 for receiving data signals.

[0051] The signal connection terminals 121, 122, 123, 124, and 125 of the first communication interface 120 are connected to the corresponding transceivers 126, 127, and 128. Correspondingly, the signal connection terminals 221, 222, 223, 224, and 225 of the second communication interface 220 are also connected to the corresponding transceivers 226, 227, and 228.

[0052] By using these different connection points for sending and receiving data signals, bidirectional full-duplex data transmission can be achieved, that is, data can be sent and received simultaneously.

[0053] The coupling mechanism has three optocouplers through which the signal connection terminals 121 to 125 and 221 to 225 of the communication interfaces 120 and 220 are optically coupled to each other.

[0054] For example, a first optocoupler 310 is provided with an optical transmitter 311 and an optical receiver 312 so that signal connection terminals 121 and 221 for use with time signals are coupled.

[0055] A second optocoupler 320 is provided, having an optical transmitter 321 and an optical receiver 322, so that the signal connection terminals 222 and 223 of the second communication interface 220 for transmitting data signals are optically coupled to the signal connection terminals 122 and 123 of the first communication interface 120 for receiving data signals.

[0056] A third optocoupler 330 with an optical transmitter 331 and an optical receiver 332 is also provided. The signal connection terminals 124 and 125 of the first communication interface 120 for transmitting data signals are optically coupled to the signal connection terminals 224 and 225 of the second communication interface 220 for receiving data signals through the optical transmitter and the optical receiver.

[0057] For example, the optical transmitters 311, 321, and 331 of optocouplers 310, 320, and 330 can be configured as light-emitting diodes (LEDs) or laser diodes (LDs), respectively. The optical receivers 312, 322, and 332 can be configured as photodiodes, phototransistors, three-terminal bidirectional AC switches, etc., for example.

Claims

1. A system composed of microcontrollers, the system having a first microcontroller (100) and a second microcontroller (200). The first microcontroller (100) and the second microcontroller (200) are electrically isolated from each other (400). The first microcontroller (100) has a first processor unit (110) and a first communication interface (120) connected to the first processor unit (110). The first communication interface is configured to enable direct memory access to the memory units (140, 141, 142) of the first processor unit. The second microcontroller (200) has a second processor unit (210) and a second communication interface (220) connected to the second processor unit (210). The second communication interface is configured to enable direct memory access to the memory units (240, 241, 242) of the second processor unit. The first communication interface (120) and the second communication interface (220) are coupled in a data transmission manner by means of isolation couplers (300, 310, 320, 330). The first processor unit (110) is configured to access memory units (240, 241, 242) connected to the second processor unit (210) during direct memory access via coupled communication interfaces (110, 220, 300), and the second processor unit (210) is configured to access memory units (140, 141, 142) connected to the first processor unit (110) during direct memory access via the coupled communication interfaces (110, 220, 300).

2. The system according to claim 1, wherein the first communication interface (120) and the second communication interface (220) are respectively configured as full-duplex interfaces and are set up for simultaneous bidirectional transmission.

3. The system according to claim 1 or 2, wherein the first communication interface (120) and the second communication interface (220) are respectively configured as LVDS interfaces.

4. The system according to any one of claims 1 to 2, wherein the first communication interface (120) and the second communication interface (220) are optically coupled (300).

5. The system according to any one of claims 1 to 2, wherein at least five signal connection terminals (121, 122, 123, 124, 125) of the first communication interface (120) and at least five signal connection terminals (221, 222, 223, 224, 225) of the second communication interface (220) are coupled to each other.

6. The system according to claim 5, wherein the at least five signal connection terminals (121, 122, 123, 124, 125) of the first communication interface (120) and the at least five signal connection terminals (221, 222, 223, 224, 225) of the second communication interface (220) respectively comprise: At least one signal connection terminal (121, 221) for transmitting clock signals. At least two signal connection terminals (124, 125, 222, 223) for outputting data signals; and at least two signal connection terminals (122, 123, 224, 225) for receiving data signals.

7. The system according to any one of claims 1 to 2, wherein the system is used in a vehicle.

8. The system according to claim 7, wherein the first microcontroller (100) is disposed in a first vehicle electrical network (410), wherein a first power supply voltage source (411) provides a first vehicle electrical network voltage in the first vehicle electrical network, and wherein the second microcontroller (200) is disposed in a second vehicle electrical network (420), wherein a second power supply voltage source (421) provides a second vehicle electrical network voltage in the second vehicle electrical network.

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