A watchdog control method and system based on dual CPU multi-core system

Abstract

The present application relates to a watchdog control method and system based on a dual-CPU multi-core system. The virtual watchdog data of the cores in each processor is obtained through the main cores of each processor in the target device system, and the virtual watchdog data of the cores in each processor are analyzed. If there is a core in each processor that does not perform a preset watchdog refresh operation, a control signal is sent to the hardware watchdog to instruct the hardware watchdog to reset each processor. The method can realize the reset operation of the entire target device system, thereby effectively monitoring the multi-processor device system.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a watchdog control method and system based on a dual-CPU multi-core system. Background Art

[0002] In embedded systems, for device systems with strict requirements on response and execution time, in order to ensure long-term stable operation of the system, a hardware watchdog is usually used to monitor the operation of the device system to ensure that the system can be restarted through the hardware watchdog circuit when an abnormal situation occurs, thereby ensuring the continuous operation of the device system.

[0003] In the related art, when a hardware watchdog is used to monitor the operation of a device system, it is first necessary to enable the hardware watchdog, and then perform a dog-flash operation at fixed time intervals. If the dog-flash time interval is greater than a certain time, the hardware watchdog will reset the device system's processor by operating the reset pin of the device system's processor.

[0004] However, the related art cannot perform a reset operation on the entire device system, resulting in a defect that the multi-processor device system cannot be effectively monitored. Summary of the invention

[0005] Based on this, it is necessary to provide a watchdog control method and system based on a dual CPU multi-core system that can reset the entire device system and effectively monitor the multi-processor device system in order to solve the above technical problems.

[0006] In a first aspect, an embodiment of the present application provides a device system monitoring method, the method comprising:

[0007] Acquire virtual watchdog data of the core of each processor in the target device system, where the virtual watchdog data represents the refresh status of the virtual watchdog of the core of each processor;

[0008] Analyze the virtual watchdog data of the cores in each processor;

[0009] If there is a core in each processor that does not execute the preset watchdog operation, a control signal is sent to the hardware watchdog, and the control signal is used to instruct the hardware watchdog to perform a reset operation on each processor.

[0010] In one embodiment, the process of generating virtual watchdog data of the core of each processor includes:

[0011] The core of each processor creates a corresponding virtual watchdog data structure in the shared memory of the processor to which it belongs; the virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag;

[0012] According to each virtual watchdog data structure, the core of each processor performs a dog flushing operation on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each processor.

[0013] In one embodiment, the watchdog brushing operation includes the cores of each processor enabling the corresponding virtual watchdog respectively, and outputting a kicking signal to the corresponding virtual watchdog according to a preset interval time.

[0014] In one embodiment, the step of obtaining virtual watchdog data of a core in each processor in a target device system includes:

[0015] In the shared memory of the processor to which it belongs, first virtual watchdog data of the core in the processor to which it belongs is obtained, and second virtual watchdog data of the core in other processors transmitted by the core in other processors except the processor to which it belongs is received; the other processors include at least one processor;

[0016] The virtual watchdog data of the cores in each processor in the target device system is obtained according to the first virtual watchdog data and the second virtual watchdog data.

[0017] In one embodiment, the method further comprises:

[0018] If the cores in each processor have executed the refresh operation, a refresh signal is sent to the hardware watchdog, and the refresh signal is used to refresh the hardware watchdog.

[0019] In a second aspect, an embodiment of the present application provides a device system monitoring system, the system comprising: multiple processors and a hardware watchdog of a target device system, each processor comprising at least one core; a target processor among the multiple processors is connected to the hardware watchdog;

[0020] The target core in the target processor is used to obtain the virtual watchdog data of the core in each processor, and when there is a core in each processor that has not performed the preset watchdog refresh operation, a control signal is sent to the hardware watchdog. The control signal is used to instruct the hardware watchdog to reset each processor.

[0021] In one embodiment, a shared memory is pre-built in each processor, and the shared memory is used to store virtual watchdog data of the core in the corresponding processor.

[0022] In a third aspect, an embodiment of the present application provides a device system monitoring apparatus, the device comprising:

[0023] An acquisition module is used to acquire virtual watchdog data of the core of each processor in the target device system, where the virtual watchdog data represents the refresh state of the virtual watchdog of the core of each processor;

[0024] An analysis module, used for analyzing the virtual watchdog data of the cores in each processor;

[0025] The reset module is used to send a control signal to the hardware watchdog if there is a core in each processor that does not execute the preset watchdog operation. The control signal is used to instruct the hardware watchdog to perform a reset operation on each processor.

[0026] In a fourth aspect, an embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method provided in any embodiment of the first aspect are implemented.

[0027] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method provided in any embodiment of the first aspect above.

[0028] The embodiment of the present application provides a watchdog control method and system based on a dual-CPU multi-core system. The virtual watchdog data of the cores in each processor is obtained through the main cores of each processor in the target device system, and the virtual watchdog data of the cores in each processor is analyzed. If there is a core in each processor that does not perform the preset watchdog operation, a control signal is sent to the hardware watchdog to instruct the hardware watchdog to reset each processor. In this method, since the virtual watchdog data can characterize the operating status of each core of each processor, after comprehensively analyzing the virtual watchdog data of each core in each processor, it can be determined whether there is an abnormally operating core in the target device system based on the analysis results. When there is an abnormally operating core in the device system, all processors in the target device system will be reset through the hardware watchdog, so as to achieve a reset operation on the entire target device system, thereby effectively monitoring the multi-processor device system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An application environment diagram of a device system monitoring method in one embodiment;

[0030] Figure 2 A schematic diagram of a flow chart of a device system monitoring method in one embodiment;

[0031] Figure 3 A structural diagram of a device system monitoring method in one embodiment;

[0032] Figure 4 is a flow chart of a device system monitoring method in another embodiment;

[0033] Figure 5A structural diagram of a device system monitoring method in another embodiment;

[0034] Figure 6 A structural diagram of a device system monitoring method in another embodiment;

[0035] Figure 7 A schematic flow chart of a device system monitoring method in another embodiment;

[0036] Figure 8 A schematic diagram of a process flow of a device system monitoring method in another embodiment;

[0037] Fig. 9 A structural diagram of a device system monitoring system in one embodiment;

[0038] Fig.10 is a structural block diagram of a device system monitoring apparatus in one embodiment;

[0039] Fig.11 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] The device system monitoring method provided in this application can be applied to Figure 1 In the application environment shown in the figure, Figure 1 The target device 100 can be a device or terminal in any field. For example, the target device 100 is an electric power device in a substation. The embodiment of the present application does not limit the type of the target device. The target device 100 includes multiple processors 1001 and a hardware watchdog 1002, and each processor 1001 is connected to the hardware watchdog 1002. Among them, each processor 1001 can be the same processor or a different processor. For example, the processor 1001 is a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPFA), a microcontroller unit (MCU), etc. The embodiment of the present application does not limit the type of processor. The embodiment of the present application does not limit the implementation structure of the hardware watchdog 1002. Based on Figure 1The hardware watchdog 1002 can reset each processor 1001 according to the control signal output by the processor 1.

[0042] In the related art, when a device system is monitored by a hardware watchdog, the hardware watchdog can monitor the processor of the device system. During monitoring, the hardware watchdog needs to be flushed at fixed time intervals. For example, taking the processor as a CPU, assuming the fixed time interval is 1.6 seconds, then the CPU is flushed once every 1.6 seconds. If the time interval for flushing the dog is greater than 1.6 seconds, the hardware watchdog will reset the CPU by operating the reset pin of the CPU.

[0043] However, for the Asymmetric Multi-Processing (AMP) system architecture of multiple CPUs, the flashing program of the hardware watchdog can only monitor a single core in a CPU, and the running status of other cores in the CPU and the running status of cores in other CPUs cannot be known. Once the program of other cores is abnormal, the hardware watchdog cannot reset the processor corresponding to the abnormal core, and cannot effectively reset the entire system. For example, in the main transformer system of a 220KV substation, most systems require a dual protection system for main transformer protection to ensure the safety and stability of the protection system. This makes it common for two or more independent CPUs to exist in the equipment system in the power field, and each CPU has one core or multiple cores. In this way, when the hardware watchdog circuit in the related technology is used to monitor the power equipment system, it will not be possible to monitor the operation of all cores in each CPU in the equipment system at the same time, and it will not be possible to effectively monitor the multi-CPU equipment system, resulting in the defect of being unable to reset the entire equipment system.

[0044] Based on this, the embodiment of the present application provides a watchdog control method and system based on a dual-CPU multi-core system, which can realize the reset operation of the entire system of the device system, thereby effectively monitoring the multi-processor device system.

[0045] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems will be described in detail below through embodiments and in combination with the accompanying drawings. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. It should be noted that the device system monitoring method provided by the present application, the execution subject of which can be a processor, can also be a device system monitoring device, and the device can be implemented as part or all of the processor through software, hardware, or a combination of software and hardware. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments.

[0046] In one embodiment, Figure 2 As shown, a device system monitoring method is provided. This embodiment involves analyzing the virtual watchdog data of the cores in each processor in the target device system. If there is a core in each processor that does not perform a preset reset operation, a control signal is sent to the hardware watchdog to instruct the hardware watchdog to perform a reset operation on each processor. The embodiment includes the following steps:

[0047] S201, obtaining virtual watchdog data of a core in each processor in a target device system, where the virtual watchdog data represents a refresh state of a virtual watchdog of a core in each processor.

[0048] Among them, the processor takes the CPU as an example. The CPU core is also called the kernel, which is the most important component of the CPU. Generally, all CPU calculations, command acceptance / storage, and data processing are completed by the core. Different CPUs (different series or the same series) will have different core types, and no matter what type of CPU core, it has a fixed logical structure, as well as logical units such as the first-level cache, second-level cache, execution unit, instruction-level unit, and bus interface.

[0049] The types of CPUs mentioned in the embodiments of the present application include but are not limited to multiple CPUs with a single core, a single CPU with multiple cores, or multiple CPUs with multiple cores.

[0050] See also Figure 3 As shown, Figure 3 A dual-CPU multi-core situation is illustrated, where the two CPUs are called CPU1 and CPU2, and both CPU1 and CPU2 have three cores: 810_1 core, 860 core, and 810_0 core. For the convenience of explanation, the 810_0 core in CPU1 is called the main core. Based on this, the main core is used to execute when obtaining the virtual watchdog data of all cores in CPU1 and CPU2, that is, all steps in the device system monitoring method provided in the embodiment of the present application can be regarded as being executed by the main core. It should be noted that using the 810_0 core in CPU1 as the main core is only an example. In actual applications, other cores of the CPU can also be used as the main core in combination with actual conditions. The embodiment of the present application does not limit the selection of the main core.

[0051] A watchdog is essentially a timer circuit, which generally has one input and one output. The input is called the dog feed, and the output is generally connected to the reset terminal of another part. For example, the output can be connected to the reset terminal of a microcontroller. In this way, the watchdog circuit can be used to regularly check the internal status of the microcontroller. Once an error occurs in the program running inside the microcontroller, a reset / restart signal will be sent to the microcontroller.

[0052] The virtual watchdog in the embodiment of the present application refers to a virtual watchdog that simulates a real object and implements the function of a watchdog circuit through a program, and the virtual watchdog data represents the state data of the virtual watchdog after the refresh operation is performed, which can be used to characterize the refresh state of the core in each processor. In the embodiment of the present application, by setting a virtual watchdog and obtaining the virtual watchdog data, it is beneficial to monitor whether the operating state of the core in each processor in the target device system is normal.

[0053] For each core of each processor in the target device system, a virtual watchdog needs to be established in advance. Therefore, when obtaining the virtual watchdog data of the cores in each processor in the target device system, the virtual watchdog data of each core in all processors needs to be obtained.

[0054] For example, the method for obtaining virtual watchdog data may be that the main core sends indication information to other cores so that other cores can feed back their respective virtual watchdog data; or, other cores actively send their respective virtual watchdog data to the main core according to a preset program, which is not limited to this in the embodiments of the present application.

[0055] For example, see above Figure 3 , the 810_0 core in CPU1 needs to obtain the virtual watchdog data of all cores in CPU1 and CPU2. When obtaining, the 810_0 core in CPU1 can send indication information to the five cores, namely, the 810_1 core of CPU1, the 860 core of CPU1, the 810_0 core of CPU2, the 810_1 core of CPU2, and the 860 core of CPU2. After receiving the indication information, the five cores feedback their own virtual watchdog data to the 810_0 core in CPU1, so that the 810_0 core in CPU1 obtains the virtual watchdog data of all cores. It can be understood that all cores include the virtual watchdog data of the 810_0 core in CPU1 itself.

[0056] S202, analyzing the virtual watchdog data of the core in each processor.

[0057] The watchdog circuit can monitor the operating status of the processor, and the purpose of monitoring is to ensure that the program of each core in the processor is reset in time when an abnormality occurs. In actual application, the purpose of monitoring can be achieved through a watchdog operation. For example, each core of the processor periodically sends a signal to the watchdog circuit, and the signal can make the watchdog circuit perform a watchdog operation. Whether the watchdog operation is performed on time indicates whether the operating status of the processor core is normal.

[0058] Therefore, based on the virtual watchdog data of the cores in each processor, the main core needs to analyze the virtual watchdog data of all cores to determine the watchdog brushing operation status of each core of each processor according to the analysis results of the virtual watchdog data. The operating status of each core of each processor can be known through the watchdog brushing operation status.

[0059] In one embodiment, when the main core analyzes the virtual watchdog data of all cores, it can be implemented through a pre-trained neural network model. For example, the virtual watchdog data of all cores is used as the input of the pre-trained neural network model, and the watchdog operation status and running status of each core can be directly output after passing through the neural network model.

[0060] In another embodiment, when the main core analyzes the virtual watchdog data of all cores, it can judge through the data information in the virtual watchdog data. For example, if the data information in the virtual watchdog data contains a flag indicating that the watchdog brushing operation has been executed, it means that the corresponding core has executed the watchdog brushing operation. Otherwise, it means that the core has not executed the watchdog brushing operation, and executing the watchdog brushing operation means that the core is running normally. Thus, by judging the data information in the virtual watchdog data of each core in turn in this way, the running status of each core in each processor can be determined.

[0061] S203: If there is a core in each processor that does not execute the preset watchdog reset operation, a control signal is sent to the hardware watchdog, where the control signal is used to instruct the hardware watchdog to reset each processor.

[0062] After the above analysis, if the virtual watchdog of the processor core does not perform the above-mentioned watchdog flushing operation, it means that there is a program running abnormality in the core of the processor, and at this time, the processor needs to be reset. It should be noted that for multi-processor multi-core device systems, in order to ensure the normal operation of the device system as a whole, once there is a program running abnormality in one core, all processors need to be reset at the same time.

[0063] In view of this, in an embodiment of the present application, the above reset operation can be implemented by a separate hardware watchdog circuit connected to each processor at the same time.

[0064] Specifically, when the above-mentioned main core analyzes that there is a core in each processor that has not executed the preset watchdog operation, it is necessary to send a control signal to the hardware watchdog. The control signal is used to instruct the hardware watchdog to reset each processor in the device system at the same time. That is, once the main core sends a control signal to the hardware watchdog, it indicates that the running program of the device system has crashed and the device system needs to be restarted. In this way, the running status of the device system can be monitored accurately and quickly.

[0065] For example, see Figure 3, the 810_0 core of CPU1 analyzes the obtained virtual watchdog data of each core of each processor. After analysis, it is found that the 860 core in CPU2 has not performed the dog brushing operation, and the 810_1 core, 860 core, 810_0 core in CPU1 and the 810_0 core and 810_1 core in CPU2 have all performed the dog brushing operation, which means that there are cores in each processor that have not performed the preset dog brushing operation. Then, the 810_0 core of CPU1 will send a control signal to the hardware watchdog. After receiving the control signal, the hardware watchdog will perform a reset operation on CPU1 and CPU2 at the same time.

[0066] The device system monitoring method provided in this embodiment obtains the virtual watchdog data of the cores in each processor through the main cores of each processor in the target device system, and analyzes the virtual watchdog data of the cores in each processor. If there is a core in each processor that does not perform the preset watchdog operation, a control signal is sent to the hardware watchdog to instruct the hardware watchdog to reset each processor. In this method, since the virtual watchdog data can characterize the operating status of each core of each processor, after comprehensively analyzing the virtual watchdog data of each core in each processor, it can be determined whether there is a core with abnormal operation in the target device system based on the analysis results, and when there is a core with abnormal operation in the device system, all processors in the target device system will be reset through the hardware watchdog, so as to achieve a reset operation on the entire target device system, thereby effectively monitoring the multi-processor device system.

[0067] The virtual watchdog data of the core of each processor in the previous embodiment is described in detail below through an embodiment. Figure 4 As shown, the process of generating the virtual watchdog data of the core of each processor includes the following steps:

[0068] S401, the cores of each processor respectively create corresponding virtual watchdog data structures in the shared memory of the respective processors; the virtual watchdog data structures include a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag.

[0069] This embodiment may be performed before the above-mentioned acquisition of the virtual watchdog data of the cores in each processor in the target device system, that is, it is necessary to create a corresponding virtual watchdog for each core in each processor in advance.

[0070] Specifically, for a single core, when creating a corresponding virtual watchdog for each core, the virtual watchdog of the core is created in the shared memory of the processor to which the core belongs. For example, see Figure 5 As shown, the processor to which the 860 cores in CPU1 belong is CPU1, and the processor to which the 860 cores in CPU2 belong is CPU2.

[0071] The shared memory refers to a memory area pre-created for each processor, which is shared by all cores of the processor. For example, Figure 5 The shared memory in CPU1 is accessible to the three cores 810_1, 860, and 810_0 in CPU1; the shared memory in CPU2 is accessible to the three cores 810_1, 860, and 810_0 in CPU2. However, it should be noted that the core in CPU1 cannot access the shared memory in CPU2, and the core in CPU2 cannot access the shared memory in CPU1.

[0072] When creating a shared memory in a processor, an area may be created in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR) in the processor and the area may be used as the shared memory of the corresponding processor.

[0073] In the shared memory, when a corresponding virtual watchdog is created for each core, it is created in the form of a virtual watchdog data structure, and the virtual watchdog data structure includes an enable flag, a timeout time, and a kick-dog flag.

[0074] Among them, the enable flag of the virtual watchdog data structure indicates the operating state of the system. When the virtual watchdog is initialized, the virtual watchdog enable flag is set to the enabled state, that is, the normal operating state of the system. If the system operating state is abnormal, the virtual watchdog enable flag is disabled. The timeout period of the virtual watchdog data structure indicates the time when the virtual watchdog does not perform the kicking operation within the specified time. If the kicking operation is not performed after this time, the enable flag of the virtual watchdog data structure becomes disabled, and it indicates that the program of the core to which it belongs has crashed. The kicking flag of the virtual watchdog data structure indicates that within the timeout period of the virtual watchdog data structure, the processor core will send a signal to the virtual watchdog of the core, causing the virtual watchdog to perform the kicking operation.

[0075] In the above manner, a corresponding virtual watchdog data structure is created for each core.

[0076] S402 , according to each virtual watchdog data structure, the core of each processor performs a dog flushing operation on the corresponding virtual watchdog to obtain virtual watchdog data of the core of each processor.

[0077] When performing the watchdog flushing operation, each core in each processor performs the watchdog flushing operation on its own virtual watchdog.

[0078] Optionally, the watchdog brushing operation includes the cores of each processor enabling the corresponding virtual watchdog respectively, and outputting a kicking signal to the corresponding virtual watchdog according to a preset interval time.

[0079] For each core, see Figure 6 , taking the 860 cores of CPU1 as an example, the virtual watchdog of the 860 cores of CPU1 is the virtual watchdog 12, then at a fixed time interval, the 860 cores of CPU1 perform a dog-flush operation on the virtual watchdog 12. Specifically, the 860 cores of CPU1 can enable the virtual watchdog 12, and output a dog-kick signal to the virtual watchdog 12 at every preset time interval. After receiving the dog-kick signal, the virtual watchdog 12 will update the dog-kick flag. For example, before the dog-kick signal is received, the dog-kick flag is 0, and after the dog-kick signal is received, the dog-kick flag is updated to 1. In addition, after the 860 cores of CPU1 enable the virtual watchdog 12, the enable flag in the virtual watchdog 12 also needs to be updated. For example, before the virtual watchdog 12 is enabled, the enable flag in the virtual watchdog 12 is empty, and after the virtual watchdog 12 is enabled, the enable flag of the virtual watchdog 12 is updated to 1. However, it should be noted that if the 860 cores of CPU1 do not perform the watchdog refresh operation within a fixed time interval, that is, if the virtual watchdog 12 is not enabled, the enable flag in the virtual watchdog 12 is not updated.

[0080] Among them, the above-mentioned preset time interval can be set according to actual needs. In one embodiment, the preset interval time can be set to 1.6s. The dog-flush operation means that each core of each processor needs to output a dog-kick signal within 1.6s when the virtual watchdog is enabled. The embodiment of the present application does not limit the specific value of the preset time interval.

[0081] For example, when the 860 cores of the above-mentioned CPU1 enable the virtual watchdog 12, it is necessary to output a kicking signal to the virtual watchdog 12 every 1.6 seconds, indicating that the 860 cores of CPU1 are operating normally. Once the kicking signal is not output to the virtual watchdog 12 according to the 1.6 seconds, it means that the 860 cores of CPU1 are operating abnormally. At this time, the virtual watchdog timeout time in the virtual watchdog 12 needs to be updated to the timeout time when the kicking signal is not output according to 1.6 seconds. Of course, the specific time may also be not displayed, and a timeout mark may be used to display that the 860 cores of CPU1 have not output a kicking signal to the virtual watchdog 12 at a fixed time interval. The embodiments of the present application do not limit this.

[0082] The device system monitoring method provided in this embodiment is that each core of each processor creates a corresponding virtual watchdog data structure in the shared memory of the processor to which it belongs, and according to each virtual watchdog data structure, the core of each processor performs a dog brushing operation on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each processor, wherein the virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a dog kicking flag, and the dog brushing operation includes the core of each processor enabling the corresponding virtual watchdog respectively, and outputting a dog kicking signal to the corresponding virtual watchdog according to a preset interval time. In this method, each core creates a corresponding virtual watchdog data structure in the shared memory of the processor to which it belongs, and the core of each processor performs a dog brushing operation on the corresponding virtual watchdog to obtain the virtual watchdog data of each core of each processor. Since the virtual watchdog data can represent the running status of each core program of each processor, creating a virtual watchdog data structure in each core of each processor can effectively monitor each core of the entire device system.

[0083] Based on any of the foregoing embodiments, in one embodiment, if Figure 7 As shown, the acquisition of virtual watchdog data of the cores of each processor in the target device system in S201 above includes the following steps:

[0084] S601, in the shared memory of the processor to which it belongs, obtain first virtual watchdog data of the core in the processor to which it belongs, and receive second virtual watchdog data of the core in other processors transmitted by the core in other processors except the processor to which it belongs; the other processors include at least one processor.

[0085] The main core obtains the virtual watchdog data of each core of the processor to which it belongs. The data obtained from the processor to which it belongs is called the first virtual watchdog data. The first virtual watchdog data includes both the virtual watchdog data corresponding to the main core and the virtual watchdog data of other cores in the processor to which it belongs except the main core. For example, Figure 6 In the example, the main core is the 810_0 core in CPU1, so the processor to which the main core belongs is CPU1. The first virtual watchdog data here includes the virtual watchdog data of the virtual watchdog 13 corresponding to the 810_0 core, the virtual watchdog data of the virtual watchdog 11 corresponding to the 810_1 core in CPU1, and the virtual watchdog data of the virtual watchdog 12 corresponding to the 860 core.

[0086] The main core receives virtual watchdog data of each core in other processors except the processor to which it belongs, and all virtual watchdog data received from other processors are called second virtual watchdog data. The other processors can be one processor or multiple processors, which is not limited in the embodiment of the present application.

[0087] The other processors are considered as one processor, and Figure 6 Take CPU2 in as an example, Figure 6 In the example, CPU1 is the processor of the main core, and CPU2 is the processor other than the processor. Then the second virtual watchdog data received by the main core (core 810_0 in CPU1) includes the virtual watchdog data of virtual watchdog 21 corresponding to core 810_1 in CPU2, the virtual watchdog data of virtual watchdog 22 corresponding to core 860 in CPU2, and the virtual watchdog data of virtual watchdog 23 corresponding to core 810_0 in CPU2.

[0088] In one embodiment, the way in which the core 810_0 of CPU1 receives the virtual watchdog data of the cores 810_1, 860 and 810_0 in CPU2 may be that CPU2 transmits the data to the core 810_0 of CPU1 through GMAC Gigabit Ethernet.

[0089] In another embodiment, the way in which the core 810_0 of CPU1 receives the virtual watchdog data of the cores 810_1, 860 and 810_0 in CPU2 may be that CPU2 transmits the data to the core 810_0 of CPU1 through a serial peripheral interface (Serial Peripheral Interface, SPI).

[0090] S602: Obtain virtual watchdog data of a core in each processor in the target device system according to the first virtual watchdog data and the second virtual watchdog data.

[0091] According to the first virtual watchdog data and the second virtual watchdog data obtained above, the virtual watchdog data of each core of each processor in the target device system can be obtained.

[0092] For example, see Figure 5 , the 810_0 core of CPU1 obtains the first virtual watchdog data of the 810_1 core, 860 core and 810_0 core in CPU1 from the shared memory of CPU1, and the 810_0 core of CPU1 receives the second virtual watchdog data of the 810_1 core, 860 core and 810_0 core in CPU2. The first watchdog data and the second virtual watchdog data are the virtual watchdog data of CPU1 and CPU2 in the device system.

[0093] The first and second in the first virtual watchdog data and the second virtual watchdog data involved in the embodiment of the present application are only used to distinguish different data and do not limit other information.

[0094] The device system monitoring method provided in this embodiment obtains the first virtual watchdog data of the core in the processor to which it belongs in the shared memory of the processor to which it belongs, and receives the second virtual watchdog data of the cores in other processors transmitted by the cores in other processors except the processor to which it belongs, and then obtains the virtual watchdog data of the cores in each processor in the target device system according to the first virtual watchdog data and the second virtual watchdog data. In this method, the main core obtains the virtual watchdog data of each core of the processor to which it belongs, and receives the virtual watchdog data of each core of other processors, so that the main core can obtain the virtual watchdog data of each core of each processor in the target device system, and the virtual watchdog data represents the running status of the core program, so that the virtual watchdog data of each core of each processor in the target device system is obtained, and the purpose of monitoring the entire target device system of multiple processors can be achieved.

[0095] In the foregoing, a case where a core with abnormal operation exists in the target device system is described. In actual application, there is also a case where the target device system does not have a core with abnormal operation, that is, all cores are normal. This case is described below through an embodiment, which includes: if the cores in each processor have executed the watchdog refresh operation, a refresh signal is sent to the hardware watchdog, and the refresh signal is used to refresh the hardware watchdog.

[0096] The existence of cores that have not been flashed indicates that there are cores in each processor that are operating abnormally; and the flashing operation has been performed on each core, indicating that there are no cores in each processor that are operating abnormally. For details, please continue to refer to Figure 3 , if the 810_1 core, 860 core, 810_0 core in CPU1 and the 810_1 core, 860 core, 810_0 core in CPU2 have all performed the dog-flush operation, then it is considered that each core in CPU1 and CPU2 has performed the dog-flush operation, and a refresh signal is sent to the hardware watchdog. Among them, the refresh signal is to refresh the hardware watchdog when the programs of each processor and each core of the target device system are running normally. In this way, when all cores are normal, the main core still sends a refresh signal to the hardware watchdog, which can ensure the normal operation of the hardware watchdog and continue to monitor the target device system.

[0097] like Figure 8 As shown, in one embodiment, a device system monitoring method is further provided. In this embodiment, the processor is a CPU, the target device system includes CPU1 and CPU2, and CPU1 and CPU2 each include multiple cores. The embodiment includes:

[0098] S701, each core in CPU1 creates its own corresponding virtual watchdog data structure in the shared memory of CPU1, and each core in CPU2 creates its own corresponding virtual watchdog data structure in the shared memory of CPU2.

[0099] The virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag.

[0100] S702, the main core performs a dog flushing operation on the corresponding virtual watchdogs according to the virtual watchdog data structures of each core, CPU1 and CPU2, to obtain virtual watchdog data of each core.

[0101] S703, the main core obtains the first virtual watchdog data of each core in CPU1, and receives the second virtual watchdog data transmitted by each core in CPU2.

[0102] S704: The main core analyzes the virtual watchdog data of each core in CPU1 and CPU2 according to the first virtual watchdog data and the second virtual watchdog data.

[0103] S705: If there is a core that does not perform the preset watchdog operation, the main core sends a control signal to the hardware watchdog to instruct the hardware watchdog to reset both CPU1 and CPU2.

[0104] S706: If all cores have executed the refresh operation, the main core sends a refresh signal to the hardware watchdog to perform a refresh operation on the hardware watchdog.

[0105] The implementation principles and technical effects of each step in the device system monitoring method provided in this embodiment are similar to those in the previous device system monitoring method embodiments, and will not be repeated here.

[0106] It should be understood that, although the various steps in the flowchart in the above-described embodiment are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart in the above-described embodiment may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0107] In addition, the present application also provides a device system monitoring system, see Fig. 9As shown, the system includes: multiple processors and hardware watchdogs of the target device system, each processor includes at least one core; the target processor among the multiple processors is connected to the hardware watchdog; the target core in the target processor is used to obtain the virtual watchdog data of the core in each of the processors, and when there is a core in each processor that does not perform a preset watchdog refresh operation, a control signal is sent to the hardware watchdog, and the control signal is used to instruct the hardware watchdog to reset each processor.

[0108] In one embodiment, a shared memory is pre-built in each processor, and the shared memory is used to store virtual watchdog data of the core in the corresponding processor.

[0109] The implementation principles and technical effects of each step in the equipment system monitoring system provided in this embodiment are similar to those in the previous equipment system monitoring system embodiments, and will not be repeated here.

[0110] In addition, the present application also provides a device system monitoring device, such as Fig.10 As shown, in one embodiment, the equipment system monitoring device 900 includes: an acquisition module 901, an analysis module 902 and a reset module 903, wherein:

[0111] An acquisition module 901 is used to acquire virtual watchdog data of the core of each processor in the target device system, where the virtual watchdog data represents a refresh state of the virtual watchdog of the core of each processor;

[0112] An analysis module 902 is used to analyze the virtual watchdog data of the core in each processor;

[0113] The reset module 903 sends a control signal to the hardware watchdog if there is a core in each processor that does not perform the preset watchdog operation. The control signal is used to instruct the hardware watchdog to perform a reset operation on each processor.

[0114] In one embodiment, a device system monitoring device is also provided, the device comprising:

[0115] A creation module is used to create corresponding virtual watchdog data structures in the shared memory of each processor; the virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag;

[0116] The data generation module is used to perform a dog flushing operation on the corresponding virtual watchdog according to each virtual watchdog data structure, so as to obtain the virtual watchdog data of the core of each processor.

[0117] In one of the embodiments, the above-mentioned watchdog brushing operation includes the cores of each processor respectively enabling the corresponding virtual watchdog, and outputting a kicking signal to the corresponding virtual watchdog according to a preset interval time.

[0118] In one embodiment, the acquisition module 901 includes:

[0119] an acquisition unit, configured to acquire, in a shared memory of the processor to which it belongs, first virtual watchdog data of a core in the processor to which it belongs, and receive second virtual watchdog data of a core in other processors transmitted by a core in other processors except the processor to which it belongs; the other processors include at least one processor;

[0120] The determination unit is used to obtain virtual watchdog data of the cores in each processor in the target device system according to the first virtual watchdog data and the second virtual watchdog data.

[0121] In one embodiment, a device system monitoring apparatus is also provided, the apparatus further comprising:

[0122] The refresh module is used to send a refresh signal to the hardware watchdog if the cores in each processor have executed the refresh operation. The refresh signal is used to refresh the hardware watchdog.

[0123] For the specific definition of the equipment system monitoring device, please refer to the definition of the equipment system monitoring method above, which will not be repeated here. Each module in the above-mentioned equipment system monitoring device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0124] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.11As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a device system monitoring method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0125] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0126] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0127] Acquire virtual watchdog data of the core of each processor in the target device system, where the virtual watchdog data represents the refresh status of the virtual watchdog of the core of each processor;

[0128] Analyze the virtual watchdog data of the cores in each processor;

[0129] If there is a core in each processor that does not execute the preset watchdog operation, a control signal is sent to the hardware watchdog, and the control signal is used to instruct the hardware watchdog to perform a reset operation on each processor.

[0130] In one embodiment, the processor implements the following steps when executing the computer program:

[0131] Create corresponding virtual watchdog data structures in the shared memory of the respective processors; the virtual watchdog data structures include a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag;

[0132] According to each virtual watchdog data structure, a dog flushing operation is performed on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each processor.

[0133] In one embodiment, the watchdog brushing operation includes the cores of each processor enabling the corresponding virtual watchdog respectively, and outputting a kicking signal to the corresponding virtual watchdog according to a preset interval time.

[0134] In one embodiment, the processor implements the following steps when executing the computer program:

[0135] In the shared memory of the processor to which it belongs, first virtual watchdog data of the core in the processor to which it belongs is obtained, and second virtual watchdog data of the core in other processors transmitted by the core in other processors except the processor to which it belongs is received; the other processors include at least one processor;

[0136] The virtual watchdog data of the cores in each processor in the target device system is obtained according to the first virtual watchdog data and the second virtual watchdog data.

[0137] In one embodiment, the processor implements the following steps when executing the computer program:

[0138] If the cores in each processor have executed the refresh operation, a refresh signal is sent to the hardware watchdog, and the refresh signal is used to refresh the hardware watchdog.

[0139] The above embodiment provides a computer device, whose implementation principle and technical effect are similar to those of the above method embodiment, and will not be repeated here.

[0140] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0141] Acquire virtual watchdog data of the core of each processor in the target device system, where the virtual watchdog data represents the refresh status of the virtual watchdog of the core of each processor;

[0142] Analyze the virtual watchdog data of the cores in each processor;

[0143] If there is a core in each processor that does not execute the preset watchdog operation, a control signal is sent to the hardware watchdog, and the control signal is used to instruct the hardware watchdog to perform a reset operation on each processor.

[0144] In one embodiment, the computer program, when executed by a processor, implements the following steps:

[0145] Create corresponding virtual watchdog data structures in the shared memory of the respective processors; the virtual watchdog data structures include a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag;

[0146] According to each virtual watchdog data structure, a dog flushing operation is performed on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each processor.

[0147] In one embodiment, the watchdog brushing operation includes the cores of each processor enabling the corresponding virtual watchdog respectively, and outputting a kicking signal to the corresponding virtual watchdog according to a preset interval time.

[0148] In one embodiment, the computer program, when executed by a processor, implements the following steps:

[0149] In the shared memory of the processor to which it belongs, first virtual watchdog data of the core in the processor to which it belongs is obtained, and second virtual watchdog data of the core in other processors transmitted by the core in other processors except the processor to which it belongs is received; the other processors include at least one processor;

[0150] The virtual watchdog data of the cores in each processor in the target device system is obtained according to the first virtual watchdog data and the second virtual watchdog data.

[0151] In one embodiment, the computer program, when executed by a processor, implements the following steps:

[0152] If the cores in each processor have executed the refresh operation, a refresh signal is sent to the hardware watchdog, and the refresh signal is used to refresh the hardware watchdog.

[0153] The above embodiment provides a computer-readable storage medium, whose implementation principle and technical effect are similar to those of the above method embodiment, and will not be repeated here.

[0154] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0155] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A device system monitoring method, characterized in that: The method is applied to a main core in a processor, and the method comprises: Acquire virtual watchdog data of the core of each processor in the target device system, wherein the virtual watchdog data represents the refresh status of the virtual watchdog of the core of each processor; the virtual watchdog is a virtual watchdog that simulates a real object and implements the function of the watchdog circuit through a program; Analyzing the virtual watchdog data of the cores in each of the processors based on a pre-trained neural network model and / or data information in the virtual watchdog data; If there is a core in each of the processors that does not perform the preset watchdog operation, a control signal is sent to the hardware watchdog, wherein the control signal is used to instruct the hardware watchdog to perform a reset operation on each of the processors at the same time; The process of generating the virtual watchdog data of the core of each processor includes: The cores of each processor respectively create a corresponding virtual watchdog data structure in the shared memory of the processor to which they belong; the virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag; According to each of the virtual watchdog data structures, the core of each of the processors performs the dog flushing operation on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each of the processors.

2. The method according to claim 1, characterized in that The watchdog brushing operation includes the cores of each processor enabling the corresponding virtual watchdog respectively, and outputting a kicking signal to the corresponding virtual watchdog according to a preset interval time.

3. The method according to claim 1, characterized in that: The step of obtaining the virtual watchdog data of the core of each processor in the target device system includes: In a shared memory of a processor, first virtual watchdog data of a core in the processor is obtained, and second virtual watchdog data of a core in another processor transmitted by a core in another processor other than the processor is received; the other processors include at least one processor; The virtual watchdog data of the cores in each processor in the target device system is obtained according to the first virtual watchdog data and the second virtual watchdog data.

4. The method according to claim 1, characterized in that: The method further comprises: If the cores in each of the processors have executed the refresh operation, a refresh signal is sent to the hardware watchdog, and the refresh signal is used to perform a refresh operation on the hardware watchdog.

5. A device system monitoring system, characterized in that: The system comprises: a plurality of processors and a hardware watchdog of a target device system, each of the processors comprises at least one core, and a virtual watchdog is pre-established on the core; the virtual watchdog is a virtual watchdog simulating a real object and realizing the function of a watchdog circuit through a program; a target processor among the plurality of processors is connected to the hardware watchdog; The target core in the target processor is used to obtain virtual watchdog data of the cores in each of the processors, and when there is a core in each of the processors that does not perform a preset watchdog refresh operation, send a control signal to the hardware watchdog, wherein the control signal is used to instruct the hardware watchdog to perform a reset operation on each of the processors at the same time; The process of generating the virtual watchdog data of the core of each processor includes: The cores of each processor respectively create a corresponding virtual watchdog data structure in the shared memory of the processor to which they belong; the virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag; According to each of the virtual watchdog data structures, the core of each of the processors performs the dog flushing operation on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each of the processors.

6. The system according to claim 5, characterized in that A shared memory is pre-built in each of the processors, and the shared memory is used to store virtual watchdog data of the core in the corresponding processor.

7. A device system monitoring device, characterized in that: The device comprises: An acquisition module is used to acquire virtual watchdog data of the core of each processor in the target device system, wherein the virtual watchdog data represents the refresh status of the virtual watchdog of the core of each processor; the virtual watchdog is a virtual watchdog that simulates a real object and implements the function of the watchdog circuit through a program; An analysis module, configured to analyze the virtual watchdog data of the cores in each of the processors based on a pre-trained neural network model and / or data information in the virtual watchdog data; A reset module, used for sending a control signal to the hardware watchdog if there is a core in each of the processors that does not perform the preset watchdog operation, wherein the control signal is used to instruct the hardware watchdog to perform a reset operation on each of the processors at the same time; The process of generating the virtual watchdog data of the core of each processor includes: The cores of each processor respectively create a corresponding virtual watchdog data structure in the shared memory of the processor to which they belong; the virtual watchdog data structure includes a virtual watchdog enable flag, a virtual watchdog timeout time and a kick dog flag; According to each of the virtual watchdog data structures, the core of each of the processors performs the dog flushing operation on the corresponding virtual watchdog to obtain the virtual watchdog data of the core of each of the processors.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

Images