Nonvolatile memory with multi-level storage cell array and control method thereof

Abstract

A non-volatile memory includes a memory cell array, a current supply circuit, a path selection circuit and a judgment circuit. The memory cell array includes m×n multi-level memory cells connected to m word lines and n bit lines. The current supply circuit can provide one of a plurality of reference currents according to a current control value. The path selection circuit is connected to the current supply circuit and the n bit lines. The judgment circuit is connected to the path selection circuit and generates n output data. The first path selector in the path selection circuit is connected to the current supply circuit and the first bit line. The first judgment element in the judgment circuit is connected to the first path selector and generates the first output data.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory and a related control method thereof, and in particular to a non-volatile memory with a multi-level memory cell array and a related reading control method thereof. Background Art

[0002] As we all know, non-volatile memory can continue to store data even after power is removed. Therefore, non-volatile memory has been widely used in various electronic devices. Generally speaking, non-volatile memory can be divided into one-time programmable non-volatile memory (OTP) and multi-time programmable non-volatile memory (MTP). Furthermore, the storage cell of OTP non-volatile memory is called OTP storage cell, and the storage cell of MTP non-volatile memory is called MTP storage cell.

[0003] Furthermore, memory cells can be categorized as single-level cells and multi-level cells based on the amount of data they store. Basically, a single-level cell can store one bit of data, meaning that the data can be in either a first storage state or a second storage state. Furthermore, a multi-level cell can store more than two bits of data.

[0004] Taking a multi-level memory cell storing 2 bits as an example, the data in each memory cell can be in a first storage state, a second storage state, a third storage state, or a fourth storage state. A multi-level memory cell storing 3 bits has eight (23) storage states, and a multi-level memory cell storing 4 bits has sixteen (24) storage states. The following introduces several types of non-volatile memory cells.

[0005] Please refer to Figure 1A , which illustrates a schematic diagram of an OTP memory cell. The OTP memory cell c1 includes a floating gate transistor F and a switch transistor M. The first terminal of the OTP memory cell c1 is connected to a source line (SL), the second terminal of the OTP memory cell c1 is connected to a bit line (BL), and the control terminal of the OTP memory cell c1 is connected to a word line (WL). The OTP memory cell c1 is a multi-level memory cell.

[0006] like Figure 1AAs shown, a first source / drain terminal of the switch gate transistor M is connected to the source line SL, and a gate terminal of the switch gate transistor M is connected to the word line WL. A first source / drain terminal of the floating gate transistor F is connected to a second source / drain terminal of the switch transistor M, and a second source / drain terminal of the floating gate transistor F is connected to the bit line BL.

[0007] During a write operation, an appropriate bias voltage is provided to the OTP memory cell c1 to program the OTP memory cell c1 and control the amount of hot carriers injected into the floating gate, so that the OTP memory cell c1 can exhibit different storage states. Hot carriers are electrons.

[0008] For example, during a write operation, a program voltage is applied to the source line SL, an on voltage is applied to the word line WL, and a ground voltage is applied to the bit line BL. Consequently, hot carriers are injected into the floating gate through the channel region of the floating gate transistor F. Furthermore, during a write operation, adjusting the bias duration can control the amount of hot carriers injected into the floating gate, allowing the OTP memory cell c1 to exhibit various storage states. The longer the bias duration is applied to the memory cell c1, the greater the amount of hot carriers injected into the floating gate. The shorter the bias duration is applied to the memory cell c1, the smaller the amount of hot carriers injected into the floating gate.

[0009] For example, depending on the number of hot carriers injected into the floating gate, from small to large, memory cell c1 can be in a first storage state to an Xth storage state, where X is greater than or equal to 4. When the multi-level memory cell c1 can store two bits of data, then X=4, meaning that the memory cell c1 is in one of the first to fourth storage states. Similarly, when the multi-level memory cell c1 can store three bits of data, X=8, meaning that the memory cell c1 can be in one of the first to eighth storage states. When the multi-level memory cell c1 can store four bits of data, X=16, meaning that the memory cell c1 can be in one of the first to sixteenth storage states.

[0010] In addition to controlling the bias duration of memory cell c1, controlling the programming voltage can also cause the OTP memory cell c1 to assume different storage states. Generally speaking, a higher programming voltage increases the number of hot carriers injected into the floating gate. A lower programming voltage decreases the number of hot carriers injected into the floating gate.

[0011] In addition, during a read operation, an appropriate bias voltage is provided to the OTP memory cell c1 so that the OTP memory cell c1 generates a cell current. The various storage states of the OTP memory cell c1 can be determined according to the magnitude of the cell current.

[0012] During a read operation, a read voltage is provided to the source line SL, a turn-on voltage is provided to the word line WL, and a ground voltage is provided to the bit line BL. Therefore, OTP memory cells c1 in different storage states generate memory cell currents of different magnitudes.

[0013] For example, assume a multi-level memory cell storing two bits of data. During a read operation, the memory cell current in the first storage state is 0.1 μA, the memory cell current in the second storage state is 0.6 μA, the memory cell current in the third storage state is 1.1 μA, and the memory cell current in the fourth storage state is 1.6 μA. Similarly, a multi-level memory cell storing three bits of data has eight storage states and can generate eight different memory cell currents during a read operation. A multi-level memory cell storing four bits of data has sixteen storage states and can generate sixteen different memory cell currents during a read operation.

[0014] Since the programming voltage is very high, in order to prevent the switch transistor M from being damaged during the writing operation, a following transistor can be added to the OTP memory cell. Figure 1B FIG2 is a schematic diagram of another OTP memory cell. The OTP memory cell c2 includes a floating gate transistor F, a follower transistor Mg, and a switch transistor M. The first terminal of the OTP memory cell c2 is connected to the source line SL, the second terminal of the OTP memory cell c2 is connected to the bit line BL, the first control terminal of the OTP memory cell c2 is connected to the word line WL, and the second control terminal of the OTP memory cell c2 is connected to the following line (FL).

[0015] like Figure 1B As shown, the first source / drain terminal of the switching transistor M is connected to the source line SL, and the gate terminal of the switching transistor M is connected to the word line WL. The first source / drain terminal of the follower transistor Mg is connected to the second source / drain terminal of the switching transistor M, and the gate terminal of the follower transistor Mg is connected to the follower line FL. The first source / drain terminal of the floating gate transistor F is connected to the second source / drain terminal of the follower transistor Mg, and the second source / drain terminal of the floating gate transistor F is connected to the bit line BL. Similarly, the OTP memory cell c2 is a multi-level memory cell.

[0016] Fundamentally, the switch transistor M and the follower transistor Mg have the same operational relationship: when the switch transistor M is on, the follower transistor Mg is also on; when the switch transistor M is off, the follower transistor Mg is also off. Furthermore, the bias voltages and operational principles for writing and reading OTP memory cells c1 and c2 are similar and will not be further elaborated here.

[0017] Please refer to Figure 1C , which is a schematic diagram of an MTP memory cell. Among them, the MTP memory cell c3 is a multi-level memory cell. Compared with Figure 1A The OTP memory cell c1 and the MTP memory cell c3 also include an erase capacitor C connected between the floating gate of the floating-gate transistor F and an erase line (EL). During write and read operations, a ground voltage is supplied to the erase line EL. The bias voltages of the other terminals of the MTP memory cell c3 are similar to those of the OTP memory cell c1. The detailed operation of the MTP memory cell c3 is not further described.

[0018] During an erase operation, an erase voltage is applied to the erase line EL, causing hot carriers to move to the erase line EL via the erase capacitor C and eject from the floating gate.

[0019] Please refer to Figure 1D , which is another schematic diagram of an MTP memory cell. Among them, the MTP memory cell c4 is a multi-level memory cell. Compared with Figure 1B The OTP memory cell c2 and the MTP memory cell c4 also include an erase capacitor C connected between the floating gate of the floating-gate transistor F and an erase line (EL). During write and read operations, a ground voltage is supplied to the erase line EL. The bias voltages of the other terminals of the MTP memory cell c4 are similar to those of the OTP memory cell c2. The detailed operation of the MTP memory cell c4 is not further described.

[0020] Similarly, during an erase operation, an erase voltage is provided to the erase line EL, so that hot carriers move to the erase line EL through the erase capacitor C and exit the floating gate.

[0021] above Figures 1A to 1D The memory cells in the present invention are described using P-type transistors as an example. In fact, OTP memory cells and MTP memory cells can also be implemented using N-type transistors.

[0022] Please refer to Figure 1E, which illustrates another MTP memory cell schematic. MTP memory cell c5 is a multi-level memory cell. MTP memory cell c5 includes a switch transistor M and a resistor R. A first terminal of MTP memory cell c5 is connected to source line SL, a second terminal of MTP memory cell c5 is connected to bit line BL, and a control terminal of MTP memory cell c5 is connected to word line WL.

[0023] Furthermore, a first source / drain terminal of the switch transistor M is connected to the source line SL, a gate terminal of the switch transistor M is connected to the word line WL, a second source / drain terminal of the switch transistor M is connected to a first end of a resistor R, and a second end of the resistor R is connected to the bit line BL. Resistor R may be formed of a transition metal oxide (TMO).

[0024] Basically, controlling the voltage difference across resistor R determines the resistance value of resistor R and its corresponding storage state. In other words, during a write operation, providing an appropriate bias voltage to MTP memory cell c5 can control MTP memory cell c5 to exhibit various storage states.

[0025] In addition, the above-mentioned memory cells c1 to c5 can form a memory cell array. The following description uses the OTP memory cell c1 as an example. Of course, the memory cell array can also be formed by other memory cells.

[0026] like Figure 2 As shown, the memory cell array 200 includes m×n memory cells c11-cmn, each of which includes a switch transistor M1,1-Mm,n and a floating gate transistor F1,1-Fm,n. Furthermore, the structure of each memory cell c11-cmn is the same as Figure 1A The OTP memory cell c1 is not described in detail. In addition, the first end of each memory cell c11-cmn is connected to the source line SL, and m and n are positive integers.

[0027] In memory cell array 200, the control terminals of the n memory cells c11-c1n in the first row are all connected to word line WL1, and the second terminals of the n memory cells c11-c1n in the first row are connected to corresponding bit lines BL1-BLn. The control terminals of the n memory cells c21-c2n in the second row are all connected to word line WL2, and the second terminals of the n memory cells c21-c2n in the second row are connected to corresponding bit lines BL1-BLn. Similarly, the memory cells in other rows have similar connection relationships, which will not be further described here.

[0028] Basically, during a write operation or a read operation of the nonvolatile memory, only one word line among the m word lines WL1 -WLm in the memory cell array 200 is activated, and the other word lines are not activated.

[0029] For example, during a write operation, word line WL1 is activated, making the first row the selected row. By controlling the time when memory cells c11-c1n in the selected row receive bias voltages, memory cells c11-c1n can be controlled to exhibit various storage states. Summary of the Invention

[0030] The present invention provides a nonvolatile memory device with a multi-level memory cell array and a related read control method. During a read operation, the sensing circuit in the nonvolatile memory sequentially provides different reference currents to determine the storage state of the memory cells. Once all reference currents are provided, the sensing circuit can determine the storage state of all memory cells in a selected row.

[0031] The present invention provides a non-volatile memory, comprising: a memory cell array, comprising m×n multi-level memory cells, connected to m word lines and n bit lines, wherein each of the multi-level memory cells can be in one of X storage states, and X is greater than or equal to 4; a current supply circuit, providing one of X reference currents according to Mc, wherein Mc is a current control value; a path selection circuit, connected to the current supply circuit and the n bit lines, wherein the path selection circuit includes n path selectors, and a first path selector is connected to the current supply circuit and a first bit line; a judgment circuit, connected to the path selection circuit, and generating n output data, wherein the judgment circuit generates n output data. The shutdown circuit includes n judgment elements, wherein the first judgment element is connected to the first path selector and generates first output data. During the Mcth storage state judgment phase of a read operation, the current supply circuit first provides a Mcth reference current, which is transmitted to the first judgment element via the first path selector and converted into a first reference voltage. Thereafter, the first multi-level memory cell generates a first memory cell current, which is transmitted to the first judgment element via the first bit line and the first path selector and converted into a first sensing voltage. Furthermore, the judgment element selectively uses Mc as the first output data based on a comparison result between the first reference voltage and the first sensing voltage. m, n, Mc, and X are positive integers, Mc is greater than or equal to 1, and Mc is less than or equal to X.

[0032] The present invention proposes a read control method for the above-mentioned non-volatile memory, comprising the following steps: determining a selected n memory cells in the memory cell array; setting Mc equal to X; (a) the current supply circuit provides the Mcth reference current; (b) n judgment circuits sequentially receive the Mcth reference current and generate a corresponding reference voltage; (c) n judgment circuits receive the n memory cell currents generated by the n memory cells on the selected row and generate n sensing voltages; (d) each judgment circuit selectively stores Mc based on a comparison result between the sensing voltage and the reference voltage; determining whether Mc is equal to 1; when Mc is not equal to 1, decrementing M by 1 and returning to step (a); and, when M is equal to 1, using the n current control values ​​stored by the n judgment circuits as the n output data to determine the storage state of the n memory cells.

[0033] In order to better understand the above and other aspects of the present invention, preferred embodiments are described in detail below with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figures 1A to 1E Schematic diagram of various storage units.

[0035] Figure 2 Schematic diagram of a memory cell array.

[0036] Figure 3 The non-volatile memory of the present invention.

[0037] Figure 4A and Figure 4B This is a schematic diagram of the detailed structure of the current supply circuit, path selection circuit, and judgment circuit, as well as their related signals.

[0038] 5A to 5D FIG. 4 is a schematic diagram of the operation of the path selector and the determination element in the fourth storage state determination phase.

[0039] Figures 6A to 6C The present invention provides a read control method and an example thereof applied to a multi-level memory cell array.

[0040] Figure 7A and Figure 7B Other embodiments of the voltage clamping circuit and the path selection circuit. DETAILED DESCRIPTION

[0041] The present invention provides a nonvolatile memory device with a multi-level memory cell array and a related read control method. During a read operation, the sensing circuit in the nonvolatile memory device sequentially provides different reference currents to determine the storage state of the memory cells. Once all reference currents are provided, the sensing circuit determines the storage state of all memory cells in the selected row.

[0042] by Figure 1A Taking the memory cell c1 shown as an example, according to the number of hot carriers injected into the floating gate, from small to large, the memory cell c1 can be in the first storage state to the Xth storage state, and X is greater than or equal to 4. For example, when the multi-level memory cell c1 can store two bits of data, then X=4, which means that the memory cell c1 is in one of the first storage state to the fourth storage state. Similarly, when the multi-level memory cell c1 can store three bits of data, X=8, which means that the memory cell c1 can be in one of the first storage state to the eighth storage state. When the multi-level memory cell c1 can store four bits of data, X=16, which means that the memory cell c1 can be in one of the first storage state to the sixteenth storage state.

[0043] Furthermore, assuming a multi-level memory cell storing two bits of data, the memory cell current in the first storage state is 0.1 μA, the memory cell current in the second storage state is 0.6 μA, the memory cell current in the third storage state is 1.1 μA, and the memory cell current in the fourth storage state is 1.6 μA. If the memory cell array is composed of multi-level memory cells storing two bits of data, the sensing circuit will sequentially provide reference currents of 1.6 μA, 1.1 μA, 0.6 μA, and 0.1 μA during a read operation to determine the storage states of all memory cells in the selected row.

[0044] The following description uses a multi-level memory cell storing two bits of data as an example. Of course, the present invention is not limited thereto, and those skilled in the art can also apply the present invention to memory cells storing more bits.

[0045] Please refer to Figure 3 , which illustrates the non-volatile memory of the present invention. The non-volatile memory includes a memory cell array 300 and a sensing circuit 350. The sensing circuit 350 includes a current supplying circuit 310, a path selecting circuit 320, and a judging circuit 330. The structure of the m×n memory cell array 300 is the same as that of Figure 2 Furthermore, the memory cells in the memory cell array 300 are multi-level memory cells, and the memory cells can be either OTP memory cells or MTP memory cells.

[0046] The current supplying circuit 310 in the sensing circuit 350 includes a plurality of current sources. The current supplying circuit 310 receives a current control value Mc and outputs one of a plurality of reference currents. For example, when used in a multi-level memory cell storing two bits of data, the current supplying circuit 310 can output one of four reference currents based on the current control value Mc. When used in a multi-level memory cell storing three bits of data, the current supplying circuit 310 can output one of eight reference currents based on the current control value Mc. When used in a multi-level memory cell storing four bits of data, the current supplying circuit 310 can output one of sixteen reference currents based on the current control value Mc.

[0047] The path selecting circuit 320 in the sensing circuit 350 includes n path selectors 321-32n. Furthermore, the judgment circuit 330 includes n judging devices 331-33n, which can generate n output data Do1-Don. Each of the path selectors 321-32n has the same structure, and each of the judging devices 331-33n has the same structure.

[0048] Taking the path selector 321 and the determination element 331 as an example, the path selector 321 includes a reference current path and a memory cell current path. The reference current path is connected to the current supply circuit 310, while the memory cell current path is connected to the bit line BL1. Furthermore, the reference current path is controlled by a reference current enable signal ENsa1, while the memory cell current path is controlled by a cell current enable signal ENcell. Specifically, when the reference current enable signal ENsa1 is active, the reference current path of the path selector 321 is connected between the current supply circuit 310 and the determination element 331. When the cell current enable signal ENcell is active, the memory cell current path of the path selector 321 is connected between the bit line BL1 and the determination element 331.

[0049] During a read operation, the current supply circuit 310 generates a corresponding reference current based on the current control value Mc. Furthermore, the determination element 331 first receives the reference current provided by the current supply circuit 310 and converts it into a reference voltage. Thereafter, the determination element 331 receives the memory cell current on the bit line BL1 and converts it into a sensed voltage. Finally, the determination element 331 generates a latching signal based on the comparison result between the reference voltage and the sensed voltage. When the latching signal is activated, the latching circuit within the determination element 331 is enabled and stores the current control value Mc as output data Do1, which represents the storage state of the memory cell.

[0050] Please refer to Figure 4A and Figure 4B , which shows the detailed structure of the current supply circuit, path selection circuit and judgment circuit and their related signal schematics. Figure 4A In FIG. 3 , the memory cell array 300 only shows a row of memory cells cj1 ˜cjn connected to a word line WLj, and the rest are not shown.

[0051] The current supply circuit 310 includes four current sources and a multiplexer 312. The first current source generates a first reference current Ir1, the second current source generates a second reference current Ir2, the third current source generates a third reference current Ir3, and the fourth current source generates a fourth reference current Ir4. The four input terminals of the multiplexer 312 are connected to the four current sources. The control terminal of the multiplexer 312 receives a current control value Mc and outputs one of the four reference currents Ir1-Ir4.

[0052] For example, in a multi-level memory cell storing two bits of data, current supply circuit 310 can generate four (X=4) reference currents corresponding to different storage states. When the current control value Mc is "1," current supply circuit 310 outputs a first reference current of 0.1 μA; when the current control value Mc is "2," current supply circuit 310 outputs a second reference current of 0.6 μA; when the current control value Mc is "3," current supply circuit 310 outputs a third reference current of 1.1 μA; and when the current control value Mc is "4," current supply circuit 310 outputs a fourth reference current of 1.6 μA.

[0053] The path selection circuit 320 includes n path selectors 321 to 32n, and the determination circuit 330 includes n determination elements 331 to 33n. Only the path selector 321 and the determination element 331 are described below.

[0054] The reference current path in the path selector 321 includes a switch transistor s11. A first source / drain terminal of the switch transistor s11 is connected to the current supply circuit 310, a second source / drain terminal of the switch transistor s11 is connected to the node a1, and a gate terminal of the switch transistor s11 receives a reference current enable signal ENsa1. Furthermore, the memory cell current path in the path selector 321 includes a switch transistor s12. A first source / drain terminal of the switch transistor s12 is connected to the bit line BL1, a second source / drain terminal of the switch transistor s12 is connected to the node a1, and a gate terminal of the switch transistor s12 receives a memory cell current enable signal ENcell.

[0055] The determination element 331 includes an operational amplifier 341, switches s13 and s14, capacitors C11 and C12, and a latch circuit 361. The first terminal of switch s13 is connected to node a1, the second terminal of switch s13 is connected to ground GND, and the control terminal of switch s13 receives a discharge enable signal ENdisc. The first terminal of capacitor C11 is connected to node a1, and the second terminal of capacitor C11 is connected to ground GND. The first terminal of capacitor C12 is connected to the negative input terminal of the operational amplifier, and the second terminal of capacitor C12 is connected to ground GND. The positive input terminal of operational amplifier 341 is connected to node a1, and the output terminal of operational amplifier 341 generates a latch signal La1. The first terminal of switch s14 is connected to the output terminal of operational amplifier 341, the second terminal of switch s14 is connected to the negative input terminal of operational amplifier 341, and the control terminal of switch s14 receives a closed-loop enable signal ENcls1. The latch circuit 361 receives the current control value Mc and the latch signal La1. When the latch signal La1 is activated, the latch circuit 361 is enabled and stores the current control value Mc as output data Do1 to represent the storage state of the memory cell. The switches s13 and s14 can be implemented using transistors.

[0056] like Figure 4A As shown in FIG. 1 , when word line WLj is activated, the memory cells cj1 to cjn in the selected row can be read. During the reading operation, the current supply circuit 310, the path selection circuit 320, and the determination circuit 330 begin to operate and determine the storage states of the memory cells cj1 to cjn in the selected row.

[0057] Furthermore, the read operation includes four storage state judging phases. The following only describes the current supply circuit 310, the path selection circuit 320, and the judging circuit 330 during the fourth storage state judging phase.

[0058] like Figure 4B As shown, during the fourth storage state determination phase, the current control value Mc is "4," and the current supply circuit 310 outputs the fourth reference current Ir4. Furthermore, the fourth storage state determination phase also includes n reference current sampling phases and one cell current sampling phase. During each of the n reference current sampling phases, the corresponding reference current enable signals ENsa1-ENsan and closed-loop enable signals ENcls1-ENclsn are activated.

[0059] exist Figure 4B In the example, time t0 to time t1 is the first reference current sampling phase, during which path selector 321 and decision element 331 are active. Time t1 to time t2 is the second reference current sampling phase, during which path selector 322 and decision element 332 are active. Similarly, time tn-1 to time tn is the nth reference current sampling phase, during which path selector 32n and decision element 33n are active. Furthermore, time tn to time tn+1 is the memory cell current sampling phase, during which all path selectors 321-32n and decision elements 331-33n are active.

[0060] Furthermore, each reference current sampling phase includes a discharge period and a sample period. Taking the first reference current sampling phase as an example, time point t0 to time point t0a is the discharge period (Discharge), and time point t0a to time point t1 is the sample period (Sample_1).

[0061] According to an embodiment of the present invention, the duration of the sampling intervals Samle_1 to Sample_n in the reference current sampling phase is the same as the duration of the judgment interval Judge in the memory cell current sampling phase. Of course, the present invention is not limited to this, and those skilled in the art may modify the durations of the sampling intervals Samle_1 to Sample_n and the judgment interval Judge based on actual conditions.

[0062] like 5A to 5D , which is a schematic diagram of the operation of the path selector 321 and the determination element 331 in the fourth storage state determination phase. Figure 4B and Figure 5ADuring the discharge interval (Discharge) from time points t0 to t0a, only the discharge enable signal ENdisc is active. Therefore, the switch s13 in the determination element 331 is in a closed state, causing the capacitor C11 to be discharged to the ground voltage (0V).

[0063] Please refer to Figure 4B and Figure 5B During the sampling interval (Sample_1) from time points t0a to t1, the reference current enable signal ENsa1 and the closed-loop enable signal ENcls1 are active. Therefore, the reference current path in the path selector 321 is connected between the current supply circuit 310 and the determination element 331, and the switch s14 in the determination element 331 is closed, causing the operational amplifier 341 to function as a unit gain buffer. At this time, the fourth reference current Ir4 provided by the current supply circuit 310 charges the capacitor C11. Simultaneously, the unit gain buffer duplicates the voltage of capacitor C11 to capacitor C12. In other words, at time point t1, capacitor C11 is charged to the reference voltage Vr4, and the voltage of capacitor C12 is also the reference voltage Vr4.

[0064] Between time point t1 and time point t2, it is the second reference current sampling phase, and the path selector 322 and the determination element 332 operate similarly to Figure 5A and Figure 5B , I will not go into details here. Figure 4B and Figure 5C After the time point t1, the switch s13 in the determination element 331 discharges the capacitor C11 to the ground voltage (0V) according to the discharge enable signal ENdisc, leaving only the capacitor C12 to store the reference voltage Vr4.

[0065] From the above description, it can be seen that after n reference current sampling phases, at time point tn, the capacitors C12 - Cn2 in all the determination elements 331 - 33n store the corresponding reference voltage Vr4.

[0066] like Figure 4BAs shown, time point tn to time point tn+1 is the memory cell current sampling phase of the fourth storage state judgment phase. During the discharge interval (Discharge) of the memory cell current sampling phase, the discharge enable signal ENdisc is activated to ensure that the capacitors C11-Cn1 in all judgment elements 331-33n are discharged to the ground voltage (0V). Then, during the judgment interval (Judge) of the memory cell current sampling phase, the memory cell current enable signal ENcell is activated. Therefore, the memory cell current paths in all path selectors 321-32n connect the corresponding bit lines BL1-BLn to the corresponding judgment elements 331-33n. At this time, all memory cells cj1-cjn on the selected row generate memory cell currents to the corresponding judgment elements 331-33n.

[0067] Take the judgment element 331 as an example for explanation. Figure 5D As shown, the memory cell current path of the path selector 321 is connected between the bit line BL1 and the determination element 331. Therefore, the memory cell cj1 on the selected row generates a memory cell current Icell1 to the determination element 331 and charges the capacitor C11.

[0068] At the end of the memory cell current sampling phase, i.e., time tn+1, operational amplifier 341 functions as a comparator, comparing the sensed voltage Vcell1 on capacitor C11 with the reference voltage Vr4 on capacitor C12. When the sensed voltage Vcell1 is less than the reference voltage Vr4, indicating that the memory cell current Icell1 is less than the reference current Ir4, latch signal La1 is at a low level, and latch circuit 361 is disabled, indicating that memory cell cj1 is not in the fourth storage state. Conversely, when the sensed voltage Vcell1 is greater than the reference voltage Vr4, indicating that the memory cell current Icell1 is greater than the reference current Ir4, latch signal La1 is at a high level, enabling latch circuit 361 to latch the current control value Mc (Mc = "4"), which becomes output data Do1, indicating that memory cell cj1 is in the fourth storage state.

[0069] Similarly, other decision elements 332-33n enable or disable corresponding latch circuits based on the activation of latch signals La2-Lan. Based on the output data Do2-Don from decision elements 332-33n, whether memory cells cj2-cjn are in the fourth storage state is determined. Furthermore, once a latch circuit is enabled and generates output data, its output data remains unchanged during subsequent storage state determination phases.

[0070] The fourth storage state determination phase is followed by the third storage state determination phase. In the third storage state determination phase, the current control value Mc is 3, and the current supply circuit 310 outputs the third reference current Ir3. The determination elements 331-33n can determine the memory cells in the selected row in the third storage state.

[0071] Similarly, in the second storage state determination phase, the current control value Mc is 2, the current supply circuit 310 outputs the second reference current Ir2, and the determination elements 331-33n can determine whether the memory cells in the selected row are in the second storage state. In the first storage state determination phase, the current control value Mc is 1, the current supply circuit 310 outputs the first reference current Ir1, and the determination elements 331-33n can determine whether the memory cells in the selected row are in the first storage state.

[0072] From the above description, it can be seen that during the reading operation of the present invention, after multiple storage state determination phases, the storage states of all memory cells cj1-cjn on the selected row can be confirmed according to the output data Do1-Don of the n latch circuits 361-36n.

[0073] Please refer to Figures 6A to 6C , which illustrates a read control method and an example thereof for a multi-level memory cell array according to the present invention. According to an embodiment of the present invention, during a read operation, the storage states of n memory cells in a selected row of the memory cell array 300 are determined.

[0074] like Figure 6A As shown, when the read operation starts, the current control value Mc is set to X (step S604), and the current supply circuit 310 provides the Mcth reference current (step S606). That is, when the current control value Mc is set to X, it is the Xth storage state determination phase.

[0075] At this time, the n decision elements sequentially receive the Mc-th reference current and generate corresponding reference voltages (step S608). That is, after n reference current sampling phases, all decision elements 331-33n store corresponding reference voltages.

[0076] Next, n decision elements receive the n memory cell currents on the selected row and generate n sensing voltages (step S610). That is, during the memory cell current sampling phase, all decision elements 331-33n generate corresponding sensing voltages according to the received memory cell currents.

[0077] Next, each determination circuit determines whether to disable or enable the latch circuit to store Mc based on the comparison result between the sensing voltage and the reference voltage (step S612). In other words, after step S612 is completed, the memory cell with the Mcth storage state in the selected row can be determined.

[0078] Next, a determination is made as to whether Mc is equal to 1 (step S614). If Mc is not equal to 1, Mc is decremented by 1 (step S616) and the process returns to step S606 to proceed to the next storage state determination phase. Conversely, if M is equal to 1, this indicates that X storage state determination phases have been completed, and all n memory cells in the selected row have been determined. At this point, the storage states of the n memory cells in the selected row are determined based on the n output signals of the n latch circuits (step S618). Here, both X and Mc are positive integers.

[0079] The following Figure 6B and Figure 6C Similarly, the following description is made by taking a multi-level memory cell storing two bits of data as an example, ie, X=4.

[0080] like Figure 6B As shown, a selected row in the memory cell array includes six memory cells ci1 to ci6. The storage states of the six memory cells ci1 to ci6 are respectively the fourth storage state (4th), the second storage state (2nd), the first storage state (1st), the third storage state (3rd), the second storage state (2nd), and the third storage state (3rd).

[0081] like Figure 6C As shown, after the read operation begins, when the current control value Mc is 4, the current supply circuit 310 provides a fourth reference current, representing the fourth storage state determination phase. Therefore, in the fourth storage state determination phase, the latch circuit 361 is enabled and stores the current control value Mc, indicating that the memory cell ci1 is determined to be in the fourth storage state, while the other memory cells ci2-ci6 are disabled and their storage states cannot yet be determined.

[0082] When the current control value Mc is 3, the current supply circuit 310 provides a third reference current, indicating the third storage state determination phase. Therefore, in the third storage state determination phase, the latch circuits 364 and 366 are enabled and store the current control value Mc, indicating that the memory cells ci4 and ci6 are determined to be in the third storage state.

[0083] When the current control value Mc is 2, the current supply circuit 310 provides a second reference current, indicating the second storage state determination phase. Therefore, in the second storage state determination phase, the latch circuits 362 and 365 are enabled and store the current control value Mc, indicating that the memory cells ci2 and ci5 are determined to be in the second storage state.

[0084] When the current control value Mc is 1, the current supply circuit 310 provides the first reference current, indicating the first storage state determination phase. Therefore, in the first storage state determination phase, the latch circuit 363 is enabled and stores the current control value Mc, indicating that the memory cell ci3 is determined to be in the first storage state.

[0085] After the four storage state determination phases are completed, the read operation ends. The values ​​stored in all latch circuits 361-366 are output data, indicating the storage states of the memory cells ci1-ci6 in the selected row. Afterwards, a new read operation can be performed on the next selected row of the memory cell array.

[0086] As can be seen from the above description, a multi-level memory cell array storing two bits of data requires four (X=4) storage state determination phases to confirm the storage state of all memory cells in the selected row during a read operation. Similarly, a multi-level memory cell array storing three bits of data requires eight (X=8) storage state determination phases to confirm the storage state of all memory cells in the selected row during a read operation. A multi-level memory cell array storing four bits of data requires sixteen (X=16) storage state determination phases to confirm the storage state of all memory cells in the selected row during a read operation.

[0087] In addition, in order to allow the memory cell to generate a more accurate memory cell current, a voltage clamping circuit can be added to fix the reference current path and the memory cell current path at a specific bias voltage. Figure 7A and Figure 7B , which shows other embodiments of the path selection circuit.

[0088] like Figure 7A As shown, the path selection circuit 320a includes n path selectors 321a-32na and a voltage clamp circuit 313. Each path selector 321a-32na has the same structure, and only the path selector 321a is described below.

[0089] The reference current path in the path selector 321a includes a switch transistor s11 and a control transistor s15. A first source / drain terminal of the control transistor s15 is connected to the current supply circuit 310. A gate terminal of the control transistor s15 receives the clamping voltage Vclamp. A first source / drain terminal of the switch transistor s11 is connected to a second source / drain terminal of the control transistor s15. A second source / drain terminal of the switch transistor s11 is connected to a node a1. A gate terminal of the switch transistor s11 receives a reference current enable signal ENsa1.

[0090] The memory cell current path in the path selector 321a includes a switch transistor s12 and a control transistor s16. A first source / drain terminal of the control transistor s16 is connected to the bit line BL1, a gate terminal of the control transistor s16 receives a clamping voltage Vclamp, a first source / drain terminal of the switch transistor s12 is connected to a second source / drain terminal of the control transistor s16, a second source / drain terminal of the switch transistor s12 is connected to a node a1, and a gate terminal of the switch transistor s12 receives a memory cell current enable signal ENcell.

[0091] Furthermore, the voltage clamp circuit 313 includes an operational amplifier 315, a switching transistor sc2, and a control transistor sc1. The positive input of the operational amplifier 315 receives a bias voltage Vb, and the negative input of the operational amplifier 315 is connected to the first source / drain of the control transistor sc1. The output of the operational amplifier 315 generates a clamping voltage Vclamp. The first source / drain of the control transistor sc1 is connected to the current supply circuit 310, and the gate of the control transistor sc1 is connected to the output of the operational amplifier 315. The first source / drain of the switching transistor sc2 is connected to the second source / drain of the control transistor sc1, and the second source / drain of the switching transistor sc2 is connected to the power supply voltage Vss. The gate of the switching transistor sc2 receives a clamp enable signal (ENclamp).

[0092] When path selection circuit 320a operates, clamp enable signal ENclamp is activated, and the negative input terminal of operational amplifier 315 in voltage clamp circuit 313 is clamped at bias voltage Vb. The difference between bias voltage Vb and clamp voltage Vclamp is a threshold voltage Vt. Threshold voltage Vt is the threshold voltage of control transistor sc1, i.e., Vb = Vclamp + Vt. Similarly, since the gate terminals of other control transistors s15-sn5 and s16-sn6 in path selection circuit 320a also receive clamp voltage Vclamp, the first source / drain terminals of control transistors s15-sn5 and s16-sn6 can also be clamped at approximately bias voltage Vb.

[0093] like Figure 7B As shown, the path selection circuit 320b includes n path selectors 321b-32nb and a voltage clamp circuit 314. Each path selector 321b-32nb has the same structure, and only the path selector 321b is described below.

[0094] The reference current path in the path selector 321b includes a switch transistor s11 and a control transistor s15. A first source / drain terminal of the switch transistor s11 is connected to the current supply circuit 310, a gate terminal of the switch transistor s11 receives the reference current enable signal ENsa1, a first source / drain terminal of the control transistor s15 is connected to a second source / drain terminal of the switch transistor s11, a second source / drain terminal of the control transistor s15 is connected to a node a1, and a gate terminal of the control transistor s15 receives a clamping voltage Vclamp.

[0095] The memory cell current path in the path selector 321b includes a switch transistor s12 and a control transistor s15. A first source / drain terminal of the switch transistor s12 is connected to the bit line BL1, a second source / drain terminal of the switch transistor s12 is connected to a first source / drain terminal of the control transistor s15, and a gate terminal of the switch transistor s12 receives a memory cell current enable signal ENcell.

[0096] Furthermore, the voltage clamp circuit 314 includes an operational amplifier 316, a switching transistor sc3, and a control transistor sc4. The positive input of the operational amplifier 316 receives a bias voltage Vb, and the negative input of the operational amplifier 316 is connected to the first source / drain of the control transistor sc4. The output of the operational amplifier 316 generates a clamp voltage Vclamp. The first source / drain of the switching transistor sc3 is connected to the current supply circuit 310, the gate of the switching transistor sc3 receives a clamp enable signal ENclamp, the first source / drain of the control transistor sc4 is connected to the second source / drain of the switching transistor sc3, the second source / drain of the control transistor sc4 is connected to the power supply voltage Vss, and the gate of the control transistor sc4 is connected to the output of the operational amplifier 316.

[0097] When path selection circuit 320b is operating, clamp enable signal ENclamp is activated, and the negative input terminal of operational amplifier 316 in voltage clamp circuit 314 is clamped at bias voltage Vb. The difference between bias voltage Vb and clamp voltage Vclamp is a threshold voltage Vt. Threshold voltage Vt is the threshold voltage of control transistor sc4, i.e., Vb = Vclamp + Vt. Similarly, since the gate terminals of other control transistors s15-sn5 also receive clamp voltage Vclamp, the first source / drain terminals of control transistors s15-sn5 can also be clamped at approximately bias voltage Vb.

[0098] As can be seen from the above description, the present invention provides a nonvolatile memory device with a multi-level memory cell array and a related read control method. During a read operation, the sensing circuit in the nonvolatile memory device sequentially provides different reference currents to determine the storage state of the memory cells. Once all reference currents are provided, the sensing circuit can determine the storage state of all memory cells in the selected row.

[0099] In summary, although the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0100]

Explanation of symbols

[0101] 200,300: storage cell array

[0102] 310: Current supply circuit

[0103] 312: Multiplexer

[0104] 313,314: Voltage clamp circuit

[0105] 315,316,341,34n: Operational amplifier

[0106] 320, 320a, 320b: Path selection circuit

[0107] 321~32n, 321a~32na, 321b~32nb: Path selector

[0108] 330: Judgment circuit

[0109] 331~33n: Judgment element

[0110] 350:Induction circuit

[0111] 361~36n: Latch circuit

Claims

1. A non-volatile memory, comprising: A memory cell array, comprising m×n multi-level memory cells connected to m word lines and n bit lines, wherein each of the multi-level memory cells can be in one of X storage states, and X is greater than or equal to 4; A current supply circuit provides one of X reference currents according to Mc, wherein Mc is a current control value; A path selection circuit connected to the current supply circuit and the n bit lines, wherein the path selection circuit includes n path selectors, and a first path selector is connected to the current supply circuit and the first bit line; wherein the first path selector includes a reference current path and a memory cell current path; the reference current path is controlled by a reference current enable signal; and the memory cell current path is controlled by a memory cell current enable signal; A judgment circuit connected to the path selection circuit and generating n output data, wherein the judgment circuit includes n judgment elements, and a first judgment element is connected to the first path selector and generates first output data; Wherein, in the Mcth storage state judgment phase of the read operation, during the sampling interval of the reference current sampling phase, the reference current enable signal is activated, and the storage unit current enable signal is inactivated, the reference current path is connected between the current supply circuit and the first judgment element, the current supply circuit first provides the Mcth reference current, which is transmitted to the first judgment element via the first path selector, and converted and stored as a first reference voltage; wherein, after the reference current sampling phase, in the judgment interval of the memory cell current sampling phase, the memory cell current enable signal is activated, the reference current enable signal is inactivated, the memory cell current path is connected between the first bit line and the first judgment element, the first multi-level memory cell generates a first memory cell current, which is transmitted to the first judgment element via the first bit line and the first path selector and converted into a first sensing voltage; and the first judgment element selectively uses Mc as the first output data according to the comparison result between the first reference voltage and the first sensing voltage; Wherein, m, n, Mc and X are positive integers, Mc is greater than or equal to 1 and Mc is less than or equal to X.

2. The nonvolatile memory according to claim 1, wherein the reference current path includes a first switch transistor; the storage unit current path includes a second switch transistor; the first source / drain terminal of the first switch transistor is connected to the current supply circuit, the second source / drain terminal of the first switch transistor is connected to the first judgment element, and the gate terminal of the first switch transistor receives the reference current enable signal; and the first source / drain terminal of the second switch transistor is connected to the first bit line, the second source / drain terminal of the second switch transistor is connected to the first judgment element, and the gate terminal of the second switch transistor receives the storage unit current enable signal.

3. The nonvolatile memory according to claim 1 further comprises a voltage clamping circuit connected to the current supply circuit and the path selection circuit, the voltage clamping circuit providing a clamping voltage to the path selection circuit for fixing the reference current path of the first path selector and the memory cell current path at a bias voltage.

4. The nonvolatile memory according to claim 3, wherein the reference current path comprises a first switch transistor and a first control transistor; the memory cell current path comprises a second switch transistor and a second control transistor; the voltage clamping circuit comprises an operational amplifier, a third switch transistor and a third control transistor; the first input terminal of the operational amplifier receives the bias voltage, the second input terminal of the operational amplifier is connected to the first source / drain terminal of the third control transistor, and the output terminal of the operational amplifier generates the clamping voltage; the first source / drain terminal of the third control transistor is connected to the current supply circuit, the gate terminal of the third control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the third switch transistor is connected to the second source / drain terminal of the third control transistor, the second source / drain terminal of the third switch transistor is connected to the power supply voltage, and the third switch transistor The gate terminal of the first control transistor receives the clamp enable signal; the first source / drain terminal of the first control transistor is connected to the current supply circuit, and the gate terminal of the first control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the first switch transistor is connected to the second source / drain terminal of the first control transistor, the second source / drain terminal of the first switch transistor is connected to the first judgment element, and the gate terminal of the first switch transistor receives the reference current enable signal; and, the first source / drain terminal of the second control transistor is connected to the first bit line, and the gate terminal of the second control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the second switch transistor is connected to the second source / drain terminal of the second switch transistor, the second source / drain terminal of the second switch transistor is connected to the first judgment element, and the gate terminal of the second switch transistor receives the storage unit current enable signal.

5. The nonvolatile memory according to claim 3, wherein the reference current path comprises a first switch transistor and a first control transistor; the memory cell current path comprises a second switch transistor and the first control transistor; the voltage clamping circuit comprises an operational amplifier, a third switch transistor and a second control transistor; the first input terminal of the operational amplifier receives the bias voltage, the second input terminal of the operational amplifier is connected to the first source / drain terminal of the second control transistor, and the output terminal of the operational amplifier generates the clamping voltage; the first source / drain terminal of the third switch transistor is connected to the current supply circuit, and the gate terminal of the third switch transistor receives the clamping enable signal; the first source / drain terminal of the second control transistor is connected to the second source / drain terminal of the third switch transistor, and the second The source / drain terminal is connected to a power supply voltage, and the gate terminal of the second control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the first switch transistor is connected to the current supply circuit, the gate terminal of the first switch transistor receives the reference current enable signal, the first source / drain terminal of the first control transistor is connected to the second source / drain terminal of the first switch transistor, the second source / drain terminal of the first control transistor is connected to the first judgment element, and the gate terminal of the first control transistor is connected to the output terminal of the operational amplifier; and the first source / drain terminal of the second switch transistor is connected to the first bit line, the gate terminal of the second switch transistor receives the storage unit current enable signal, and the second source / drain terminal of the second switch transistor is connected to the first source / drain terminal of the first control transistor.

6. The non-volatile memory according to claim 1, wherein the first determination element comprises: an operational amplifier having a first input terminal connected to the first path selector and an output terminal generating a first latch signal; A first switch having a first terminal connected to the first input terminal of the operational amplifier, a second terminal connected to a ground terminal, and a control terminal receiving a discharge enabling signal; A second switch having a first end connected to the output end of the operational amplifier, a second end connected to the second input end of the operational amplifier, and a control end receiving a closed-loop enabling signal; A first capacitor having a first end connected to the first input terminal of the operational amplifier and a second end connected to the ground terminal; A second capacitor having a first end connected to the second input terminal of the operational amplifier and a second end connected to the ground terminal; and The first latch circuit receives the first latch signal and the current control value, wherein when the first latch signal is activated, the first latch circuit is enabled to store the current control value and uses the current control value as the first output data.

7. The nonvolatile memory according to claim 6, wherein during the reference current sampling phase of the Mc storage state determination phase, the Mc reference current charges the first capacitor to the first reference voltage, the closed-loop enable signal is activated, so that the operational amplifier copies the first reference voltage to the second capacitor; during the storage cell current sampling phase of the Mc storage state determination phase, the first storage cell current charges the first capacitor to the first sensing voltage; and the operational amplifier activates or does not activate the first latch signal according to the comparison result between the first reference voltage and the first sensing voltage. 8 . The nonvolatile memory according to claim 7 , wherein during the discharge interval of the reference current sampling phase and the discharge interval of the memory cell current sampling phase, the discharge enable signal is activated so that the first capacitor is discharged to a ground voltage.

9. A read control method for a non-volatile memory according to claim 1, comprising the following steps: Determining n memory cells in a selected row in the memory cell array; Set Mc equal to X; (a) the current supply circuit provides the Mcth reference current; (b) n determination elements sequentially receive the Mcth reference current and generate corresponding reference voltages; (c) n determination elements receive n memory cell currents generated by the n memory cells on the selected row and generate n sensing voltages; (d) each determination element selectively stores Mc according to a comparison result between the sensing voltage and the reference voltage; Determine whether Mc is equal to 1; When Mc is not equal to 1, reduce M by 1 and return to step (a); and When M is equal to 1, the n current control values ​​stored in the n judging elements are used as n output data to determine the storage states of the n storage units.

10. The reading control method according to claim 9, wherein the step (c) further comprises the following steps: generating a latch signal according to a comparison result between the sensing voltage and the reference voltage; When the latch signal is activated, the latch circuit is enabled to store Mc; and When the latch signal is inactive, the latch circuit is disabled.

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