Lock detection circuit and phase-locked loop circuit system

Abstract

The present invention provides a locking detection circuit for locking detection of a phase-locked loop circuit, comprising a first sampling unit, a second sampling unit, an AND gate and a counting unit, wherein the AND gate is connected to the first sampling unit, the second sampling unit and the counting unit, the first sampling unit is used to receive a pre-frequency division signal and a feedback frequency division signal, and to sample the pre-frequency division signal through the feedback frequency division signal to output a first sampling signal, the second sampling unit is used to receive an inverse signal of the pre-frequency division signal and the feedback frequency division signal, and to sample the feedback frequency division signal through the inverse signal of the pre-frequency division signal to output an inverse signal of the second sampling signal, and a dual-edge loop locking detection is adopted to reduce the false locking probability of the phase-locked loop circuit. The present invention provides a phase-locked loop circuit system.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a lock detection circuit and a phase-locked loop circuit system. Background Art

[0002] Phase-locked loop circuits are widely used in today's integrated circuits, wireless communications, wired transmission, and sample-and-hold circuits.

[0003] Currently, the locking of the dual-loop phase-locked loop circuit is detected by a loop lock detection circuit (Lock detector). Figure 1 As shown, it includes a D flip-flop (data flip-flop, DFF) and a counter (Counter), the D input end of the D flip-flop is used to receive the pre-frequency division signal ref, the clock end CK of the D flip-flop is used to receive the feedback frequency division signal fbk, the Q output end of the D flip-flop is connected to the enable signal receiving end of the counter, the D input end of the counter is connected to the high level signal, the clock end CK of the counter is used to receive the feedback frequency division signal fbk, the loop lock detection circuit samples the pre-frequency division signal through the feedback frequency division signal, if two consecutive N If both samples are sampled to a high level, the loop lock detection circuit determines that the dual-loop phase-locked loop circuit is locked.

[0004] However, the time span of the detection signal of the existing dual-loop lock detection circuit is heavily dependent on the number of bits of the counter. The longer the duration of the signal to be detected, the larger the number of bits of the counter required. After the dual-loop phase-locked loop is locked, the waiting time required to detect the lock of the dual-loop phase-locked loop also increases accordingly. If the detection signal duration is short, the following may occur: Figure 2 In the situation shown, the correct locking time of the dual-loop phase-locked loop circuit is 32μs, but the integral path voltage and the proportional path voltage in the dual-loop phase-locked loop circuit have not yet established stability, that is, the dual-loop phase-locked loop circuit has not yet locked, and the dual-loop lock detection circuit has output a high level representing that the dual-loop phase-locked loop circuit is locked.

[0005] Therefore, it is necessary to provide a novel lock detection circuit and phase-locked loop circuit system to solve the above problems existing in the prior art. Summary of the invention

[0006] The object of the present invention is to provide a lock detection circuit and a phase-locked loop circuit system to reduce the false lock probability of the phase-locked loop circuit.

[0007] To achieve the above object, the lock detection circuit of the present invention is used for lock detection of a phase-locked loop circuit, comprising:

[0008] A first sampling unit, configured to receive a pre-frequency division signal and a feedback frequency division signal, and sample the pre-frequency division signal through the feedback frequency division signal to output a first sampling signal;

[0009] a second sampling unit, configured to receive the reverse signal of the pre-frequency division signal and the feedback frequency division signal, and to sample the feedback frequency division signal through the reverse signal of the pre-frequency division signal to output a reverse signal of a second sampling signal;

[0010] An AND gate connected to the first sampling unit and the second sampling unit to receive inverse signals of the first sampling signal and the second sampling signal and output a control signal;

[0011] A counting unit is connected to the AND gate, and is used to use the received control signal as an enable signal, and simultaneously receive the feedback frequency division signal and the preset sampling signal, sample the preset sampling signal through the feedback frequency division signal, and output a locking signal when the number of samples of the preset sampling signal reaches a preset value.

[0012] The beneficial effect of the locking detection circuit is that: the first sampling unit is used to receive the pre-frequency division signal and the feedback frequency division signal, and samples the pre-frequency division signal through the feedback frequency division signal to output a first sampling signal, and the second sampling unit is used to receive the reverse signal of the pre-frequency division signal and the feedback frequency division signal, and samples the feedback frequency division signal through the reverse signal of the pre-frequency division signal to output the reverse signal of the second sampling signal, and adopts dual-edge loop locking detection to reduce the false locking probability of the phase-locked loop circuit.

[0013] Preferably, the first sampling unit is a D flip-flop, the D input terminal of the first sampling unit is used to receive the pre-frequency division signal, and the clock terminal of the first sampling unit is used to receive the feedback frequency division signal. The beneficial effect is that it is convenient to sample the pre-frequency division signal through the rising edge of the feedback frequency division signal.

[0014] Further preferably, the second sampling unit is a D flip-flop, the D input terminal of the second sampling unit is used to receive the feedback frequency division signal, and the clock terminal of the second sampling unit is used to receive the reverse signal of the pre-frequency division signal. The beneficial effect is that it is convenient to sample the feedback frequency division signal through the falling edge of the pre-frequency division signal.

[0015] Further preferably, the lock detection circuit further comprises an inverter unit, the output end of the inverter unit is connected to the second sampling unit, and the input end of the inverter unit is used to receive the pre-frequency division signal. The beneficial effect is that it is easy to obtain the reverse signal of the pre-frequency division signal.

[0016] Further preferably, the first input terminal of the AND gate is connected to the Q output terminal of the first sampling unit, and the second input terminal of the AND gate is connected to the QN output terminal of the second sampling unit.

[0017] The present invention also provides a phase-locked loop circuit system, comprising:

[0018] Phase-locked loop circuit;

[0019] The locking detection circuit is connected to the phase-locked loop circuit and is used for locking detection of the phase-locked loop circuit.

[0020] The beneficial effect of the phase-locked loop circuit system is that a lock detection circuit is connected to the phase-locked loop circuit to detect whether the phase-locked loop circuit is locked, and a double-edge loop lock detection is adopted to reduce the false lock probability of the phase-locked loop circuit.

[0021] Preferably, the phase-locked loop circuit includes an oscillator unit, a pre-frequency divider unit, a phase frequency detector unit, a charge pump unit, a voltage-controlled oscillator unit and a feedback frequency divider unit, the oscillator unit is connected to the pre-frequency divider unit, the pre-frequency divider unit is connected to the phase frequency detector unit and the lock detection circuit for outputting a pre-frequency divided signal, the phase frequency detector unit is connected to the charge pump unit, the charge pump unit is connected to the voltage-controlled oscillator unit, the voltage-controlled oscillator unit is connected to the feedback frequency divider unit, the feedback frequency divider unit is connected to the phase frequency detector unit and the lock detection circuit for outputting a feedback frequency divided signal.

[0022] Further preferably, the pre-divider unit and the feedback divider unit are both falling edge counting dividers or rising and falling edge counting dividers.

[0023] Further preferably, the duty cycle of the feedback frequency-divided signal output by the feedback frequency divider unit is less than 50%. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a loop lock detection circuit in the prior art;

[0025] Figure 2 It is a curve diagram of the integral path voltage, the proportional path voltage and the counter output signal in the prior art;

[0026] Figure 3 is a schematic diagram of a phase-locked loop circuit system of the present invention;

[0027] Figure 4 is a schematic diagram of a phase-locked loop circuit of the present invention;

[0028] Figure 5A schematic diagram of waveforms of an input signal and a feedback frequency-divided signal of a feedback frequency divider unit of the present invention;

[0029] Figure 6 Schematic diagram of waveforms of the pre-frequency division signal and the feedback frequency division signal of the present invention;

[0030] Figure 7 is a schematic diagram of a lock detection circuit of the present invention;

[0031] Figure 8 It is a curve diagram of the integral path voltage, the proportional path voltage and the output signal of the counting unit of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0033] In view of the problems existing in the prior art, an embodiment of the present invention provides a phase-locked loop circuit system, referring to Figure 3 The phase-locked loop circuit system 100 includes a phase-locked loop circuit 101 and a lock detection circuit 102 . The lock detection circuit 102 is connected to the phase-locked loop circuit 101 and is used for lock detection of the phase-locked loop circuit 101 .

[0034] Figure 4 Schematic diagram of the phase-locked loop circuit of the present invention. Figure 4The phase-locked loop circuit 101 includes an oscillator unit 1011, a pre-frequency divider unit 1012, a frequency detector unit 1013, a charge pump unit 1014, a voltage-controlled oscillator unit 1015 and a feedback frequency divider unit 1016. The oscillator unit 1011 is connected to the pre-frequency divider unit 1012, the pre-frequency divider unit 1012 is connected to the frequency detector unit 1013 and the lock detection circuit (not shown in the figure), and is used to output a pre-frequency divided signal ref, the frequency detector unit 1013 is connected to the charge pump unit 1014, the charge pump unit 1014 is connected to the voltage-controlled oscillator unit 1015, the voltage-controlled oscillator unit 1015 is connected to the feedback frequency divider unit 1016, and the feedback frequency divider unit 1016 is connected to the frequency detector unit 1013 and the lock detection circuit, and is used to output a feedback frequency divided signal fbk.

[0035] Reference Figure 4 The charge pump unit 1014 includes an integral path circuit 10141 and a proportional path circuit 10142. The integral path circuit 10141 and the proportional path circuit 10142 are well-known technologies in the art and will not be described in detail here.

[0036] In some embodiments, when the phase-locked loop circuit is applied to the port of the MIPI D-PHY protocol, the reference frequency input to the phase-locked loop circuit is 266 MHz, and the output frequency of the phase-locked loop circuit is 600 MHz to 1.5 GHz. It can be seen that the output frequency of the phase-locked loop circuit is higher than the reference frequency input to the phase-locked loop circuit.

[0037] In some embodiments, the output frequencies of the pre-divider unit and the feedback divider unit are equal. For example, the reference frequency input to the phase-locked loop circuit is 266 MHz, the output frequency is 1.07 GHz, the output frequency after division by the pre-divider unit is 133 MHz, and the output frequency after division by the feedback divider unit is also 133 MHz.

[0038] In some embodiments, the pre-divider unit and the feedback divider unit are both falling edge counting dividers or rising and falling edge counting dividers, and the duty cycle of the feedback divided signal output by the feedback divider unit is less than 50%.

[0039] In some embodiments, taking the falling edge counting divider as an example, it can be known from the working principle of the falling edge counting divider that the width of a high level of the output signal of the falling edge counting divider is related to the frequency of the input signal. The higher the frequency of the input signal, the narrower the width of a high level of the output signal.

[0040] Figure 5Schematic diagram of the waveform of the input signal and the feedback frequency division signal of the feedback frequency divider unit of the present invention. Figure 5 , the figure includes an input signal and a feedback divided signal, the feedback divided signal is formed by dividing the input signal by 10, the width of a high level signal of the feedback divided signal is equal to the width of one cycle of the input signal, and the width of a low level signal of the feedback divided signal is equal to the width of 9 cycles of the input signal.

[0041] In some embodiments, the output frequency of the phase-locked loop circuit is higher than the reference frequency input to the phase-locked loop circuit, and therefore, the width of a high level of the pre-division signal is greater than the width of a high level of the feedback signal.

[0042] Figure 6 Schematic diagram of the waveform of the pre-frequency division signal and the feedback frequency division signal of the present invention. Figure 6 , the figure includes a pre-frequency division signal and a feedback frequency division signal, the pre-frequency division signal and the feedback frequency division signal have the same frequency, and the width of a high level of the feedback frequency division signal is smaller than the width of a high level of the pre-frequency division signal. If the phase-locked loop circuit is locked, the rising edge of the feedback frequency division signal corresponds to the high level of the pre-frequency division signal, and the falling edge of the pre-frequency division signal corresponds to the low level of the feedback frequency division signal.

[0043] In some embodiments, the lock detection circuit includes a first sampling unit, a second sampling unit, an AND gate, and a counting unit. The first sampling unit is used to receive a pre-frequency division signal and a feedback frequency division signal, and to sample the pre-frequency division signal through the feedback frequency division signal to output a first sampling signal; the second sampling unit is used to receive an inverse signal of the pre-frequency division signal and the feedback frequency division signal, and to sample the feedback frequency division signal through the inverse signal of the pre-frequency division signal to output an inverse signal of the second sampling signal; the AND gate is connected to the first sampling unit and the second sampling unit to receive the inverse signals of the first sampling signal and the second sampling signal, and to output a control signal; the counting unit is connected to the AND gate, and is used to use the received control signal as an enable signal, and to simultaneously receive the feedback frequency division signal and a preset sampling signal, sample the preset sampling signal through the feedback frequency division signal, and output a lock signal when the number of samples of the preset sampling signal reaches a preset value.

[0044] In some embodiments, the preset sampling signal is a high level signal or a low level signal, and the counting unit is a well-known technology in the art and will not be described in detail here, such as a counter in a loop lock detection circuit.

[0045] In some embodiments, the lock detection circuit further includes an inverter unit, an output end of the inverter unit is connected to the second sampling unit, and an input end of the inverter unit is used to receive the pre-frequency division signal.

[0046] Figure 7 FIG. 4 is a schematic diagram of a lock detection circuit of the present invention. Figure 7 The lock detection circuit 102 includes a first sampling unit 1021, an inverter unit 1022, a second sampling unit 1023, an AND gate 1024 and a counting unit 1025. The first sampling unit 1021 and the second sampling unit 1023 are both D flip-flops. The D input terminal of the first sampling unit 1021 is used to receive the pre-frequency division signal ref. The clock terminal ck of the first sampling unit 1021 is used to receive the feedback frequency division signal fbk. The input terminal of the inverter unit 1022 is used to receive the pre-frequency division signal ref. The output terminal of the inverter unit 1022 is connected to the clock terminal ck of the second sampling unit 1023 to send the reverse signal of the pre-frequency division signal ref to the clock terminal ck of the second sampling unit 1023. The D input terminal of the sampling unit 1023 is used to receive the feedback frequency division signal fbk, the first input terminal of the AND gate 1024 is connected to the Q output terminal of the first sampling unit 1021, the second input terminal of the AND gate 1024 is connected to the QN output terminal of the second sampling unit 1023, the output terminal of the AND gate 1024 is connected to the enable terminal of the counting unit 1025, so that the control signal output by the AND gate 1024 is used as the enable signal, the D input terminal of the counting unit 1025 is connected to a high-level signal, the clock terminal ck of the counting unit 1025 is used to receive the feedback frequency division signal fbk, sample the high-level signal through the feedback frequency division signal fbk, and output a locking signal lock_signal when the number of samples of the high-level signal reaches a preset value.

[0047] Reference Figure 4 and Figure 7The D input terminal of the first sampling unit 1021 is connected to the output terminal of the pre-frequency divider unit 1012 to receive the pre-frequency divided signal ref output by the pre-frequency divider unit 1012, the clock terminal ck of the second sampling unit 1023 is connected to the output terminal of the feedback frequency divider unit 1016 to receive the feedback frequency divided signal fbk output by the feedback frequency divider unit 1016, the D input terminal of the second sampling unit 1023 is connected to the output terminal of the feedback frequency divider unit 1016 to receive the feedback frequency divided signal fbk output by the feedback frequency divider unit 1016, and the input terminal of the inverter unit 1022 is connected to the output terminal of the pre-frequency divider unit ref to receive the pre-frequency divided signal ref output by the pre-frequency divider unit 1012.

[0048] Reference Figure 7 The first sampling unit 1021 samples the pre-frequency division signal ref through the rising edge of the feedback frequency division signal fbk. If a high level is sampled, the Q output end of the first sampling unit 1021 outputs a high level. If a low level is sampled, the Q output end of the first sampling unit 1021 outputs a low level.

[0049] Reference Figure 7 The second sampling unit 1023 samples the feedback frequency-divided signal fbk through the rising edge of the reverse signal of the pre-frequency-divided signal ref, which is equivalent to the second sampling unit 1023 sampling the feedback frequency-divided signal fbk through the falling edge of the pre-frequency-divided signal ref. If a high level is sampled, the QN output terminal of the second sampling unit 1023 outputs a low level. If a low level is sampled, the QN output terminal of the second sampling unit 1023 outputs a high level.

[0050] Reference Figure 7 If the Q output terminal of the first sampling unit 1021 outputs a high level and the QN terminal of the second sampling unit 1023 outputs a high level, the control signal output by the AND gate 1024 is a high level, and the high level serves as an enable signal of the counting unit 1025. The counting unit 1025 works by sampling the high level at the rising edge of the feedback frequency division signal fbk. Each time a high level is sampled, the number of samples of the high level signal increases by 1.

[0051] Reference Figure 7If the Q output terminal of the first sampling unit 1021 outputs a low level, it means that the low level of the pre-frequency division signal ref is sampled through the rising edge of the feedback frequency division signal fbk, which further means that the phase-locked loop circuit 101 is not locked. Then the control signal output by the AND gate 1024 must be a low level, and the low level serves as the enable signal of the counting unit 1025. The counting unit 1025 is reset and the counting unit 1025 counts again.

[0052] Reference Figure 7 If the QN output terminal of the second sampling unit 1023 outputs a low level, it means that the high level of the feedback frequency-divided signal fbk is sampled through the rising edge of the reverse signal of the pre-frequency-divided signal ref, which is also equivalent to sampling the high level of the feedback frequency-divided signal fbk through the falling edge of the pre-frequency-divided signal ref, which further means that the phase-locked loop circuit 101 is not locked. Then the control signal output by the AND gate 1024 must be a low level, and the low level serves as the enable signal of the counting unit 1025, the counting unit 1025 is reset, and the counting unit 1025 counts again.

[0053] Figure 8 Schematic diagram of the curve of the integral path voltage, the proportional path voltage and the output signal of the counting unit of the present invention. Figure 8 It can be seen that after the integral path voltage and the proportional path voltage are stabilized, that is, at 32μs, the counting unit sends a high-level locking signal, indicating that the phase-locked loop circuit is locked, and does not send a false-locked high-level locking signal before the integral path voltage and the proportional path voltage are stabilized.

[0054] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A lock detection circuit for lock detection of a phase-locked loop circuit, characterized in that: include: A first sampling unit, wherein the first sampling unit is a D flip-flop, a D input terminal of the first sampling unit is used to receive a pre-frequency division signal, a clock terminal of the first sampling unit is used to receive a feedback frequency division signal, and the pre-frequency division signal is sampled through a rising edge of the feedback frequency division signal to output a first sampling signal; A second sampling unit, wherein the second sampling unit is a D flip-flop, a D input terminal of the second sampling unit is used to receive the feedback frequency-divided signal, a clock terminal of the second sampling unit is used to receive the reverse signal of the pre-frequency-divided signal, and the feedback frequency-divided signal is sampled by the reverse signal of the pre-frequency-divided signal to output the reverse signal of the second sampling signal; An AND gate connected to the first sampling unit and the second sampling unit to receive inverse signals of the first sampling signal and the second sampling signal and output a control signal; A counting unit is connected to the AND gate, and is used to use the received control signal as an enable signal, and simultaneously receive the feedback frequency division signal and the preset sampling signal, sample the preset sampling signal through the feedback frequency division signal, and output a locking signal when the number of samples of the preset sampling signal reaches a preset value.

2. The lock detection circuit according to claim 1, characterized in that: It also includes an inverter unit, the output end of the inverter unit is connected to the second sampling unit, and the input end of the inverter unit is used to receive the pre-frequency division signal.

3. The lock detection circuit according to claim 1, characterized in that: The first input terminal of the AND gate is connected to the Q output terminal of the first sampling unit, and the second input terminal of the AND gate is connected to the QN output terminal of the second sampling unit.

4. A phase-locked loop circuit system, characterized in that: include: Phase-locked loop circuit; The lock detection circuit according to any one of claims 1 to 3, connected to the phase-locked loop circuit, and used for lock detection of the phase-locked loop circuit.

5. The phase-locked loop circuit system according to claim 4, characterized in that: The phase-locked loop circuit includes an oscillator unit, a pre-frequency divider unit, a frequency detector unit, a charge pump unit, a voltage-controlled oscillator unit and a feedback frequency divider unit. The oscillator unit is connected to the pre-frequency divider unit, the pre-frequency divider unit is connected to the frequency detector unit and the lock detection circuit, and is used to output a pre-frequency division signal. The frequency detector unit is connected to the charge pump unit, the charge pump unit is connected to the voltage-controlled oscillator unit, the voltage-controlled oscillator unit is connected to the feedback frequency divider unit, and the feedback frequency divider unit is connected to the frequency detector unit and the lock detection circuit, and is used to output a feedback frequency division signal.

6. The phase-locked loop circuit system according to claim 5, characterized in that: The pre-frequency divider unit and the feedback frequency divider unit are both falling edge counting frequency dividers or rising and falling edge counting frequency dividers.

7. The phase-locked loop circuit system according to claim 6, characterized in that: The duty cycle of the feedback frequency-divided signal output by the feedback frequency divider unit is less than 50%.

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