Phase-locked loop circuit and image sensor

Abstract

The utility model provides a phase-locked loop circuit and an image sensor wherein the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a filter circuit, a first voltage-controlled oscillator and a second voltage-controlled oscillator, the filter circuit filters a first voltage signal output by the charge pump circuit and outputs a second voltage signal; the first voltage signal and the second voltage signal are superposed and output to the second voltage-controlled oscillator according to the proportion, the loop bandwidth is reduced, the input noise introduced into the loop is reduced, the first voltage signal is subjected to frequency discrimination phase locking and filtering through a phase-locked loop composed of the phase frequency detector, the charge pump circuit, the filter circuit and the second voltage-controlled oscillator, and then the first voltage signal is output to the second voltage-controlled oscillator. And a stable and small-jitter second voltage signal is output to the first voltage-controlled oscillator, and the first voltage-controlled oscillator adjusts the frequency of the output signal of the phase-locked loop circuit according to the second voltage signal and outputs a clock signal with small frequency jitter, so that the output stability is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of image sensors, and in particular relates to a phase-locked loop circuit and an image sensor. Background Art

[0002] Phase-locked loop (PLL) circuits are found in a variety of high-frequency applications, from simple clock purification circuits to local oscillators (LOs) for high-performance radio communication links, and ultrafast switching frequency synthesizers in vector network analyzers (VNAs), image sensors, etc.

[0003] The phase-locked loop circuit usually includes a feedback loop composed of a phase frequency detector, a charge pump circuit and a voltage-controlled oscillator. Due to problems such as signal crosstalk and clock feedthrough in the loop, the control voltage of the voltage-controlled oscillator is unstable and has ripples. Under the influence of the unstable control voltage, the phase-locked loop circuit outputs an unstable signal frequency, with large frequency jitter and loop noise. Utility Model Content

[0004] The utility model aims to provide a phase-locked loop circuit, aiming to solve the problems of frequency jitter and loop noise in traditional phase-locked loop circuits.

[0005] A first aspect of an embodiment of the utility model provides a phase-locked loop circuit, comprising:

[0006] A frequency detector and a phase detector configured to detect a frequency and a phase difference between a reference signal and a feedback signal, and generate a first control signal and a second control signal;

[0007] a charge pump circuit connected to the phase and frequency detector, configured to charge and discharge according to the received first control signal and second control signal, and output a first voltage signal of corresponding magnitude;

[0008] a filter circuit, connected to the charge pump circuit, configured to perform low-pass filtering on the first voltage signal and output a filtered second voltage signal;

[0009] a first voltage-controlled oscillator connected to the output end of the filter circuit and configured to adjust the frequency and phase of the output signal of the phase-locked loop circuit according to the second voltage signal to output a clock signal;

[0010] A second voltage-controlled oscillator is connected to the input and output ends of the filter circuit and is configured to adjust the frequency and phase of the feedback signal according to the proportional superposition of the first voltage signal and the second voltage signal so that the feedback signal has the same frequency and phase as the reference signal.

[0011] Optionally, the filtering circuit includes a first capacitor, a second capacitor, a third capacitor, a first resistor and a second resistor;

[0012] The first end of the first capacitor, the first end of the first resistor and the first end of the second resistor are connected to form the input end of the filter circuit, the second end of the first resistor is connected to the first end of the second capacitor, the second end of the second resistor is connected to the first end of the third capacitor to form the output end of the filter circuit, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are grounded.

[0013] Optionally, the resistance value of the first resistor ranges from 50 kΩ to 200 kΩ;

[0014] The resistance of the second resistor is greater than 1MΩ;

[0015] The capacitance value of the first capacitor ranges from 0.2pF to 2pF;

[0016] The capacitance value of the second capacitor ranges from 10pF to 20pF;

[0017] The capacitance value of the third capacitor ranges from 15 pF to 30 pF.

[0018] Optionally, the phase-locked loop circuit further includes:

[0019] The first frequency divider is connected to the output end of the first voltage-controlled oscillator, and is configured to divide the frequency of the output signal of the first voltage-controlled oscillator and output the divided output signal of the phase-locked loop circuit.

[0020] Optionally, the phase-locked loop circuit further includes:

[0021] A second frequency divider, wherein the input end of the second frequency divider is connected to the output end of the second voltage-controlled oscillator, the output end of the second frequency divider is connected to the input end of the frequency detector and phase detector, and the second frequency divider is configured to divide the feedback signal output by the second voltage-controlled oscillator and output the divided feedback signal to the frequency detector and phase detector.

[0022] Optionally, the first voltage-controlled oscillator includes:

[0023] a first bias circuit, connected to the positive voltage terminal and the output terminal of the filter circuit respectively, and configured to output a first current signal according to the second voltage signal;

[0024] The first oscillation circuit is connected to the first bias circuit and is configured to oscillate at a corresponding frequency according to the first current signal and output the clock signal.

[0025] Optionally, the first bias circuit comprises a first bias transistor;

[0026] The first end of the first bias transistor is connected to the positive voltage end, the control end of the first bias transistor is used to input the second voltage signal, and the second end of the first bias transistor is used to output the first current signal.

[0027] Optionally, the second voltage-controlled oscillator includes:

[0028] A second bias circuit is connected to the positive voltage terminal and the input terminal of the filter circuit respectively, and is configured to output a second current signal with a first proportional coefficient according to the first voltage signal;

[0029] a third bias circuit, connected to the positive voltage terminal and the output terminal of the filter circuit respectively, and configured to output a third current signal of a second proportional coefficient according to the second voltage signal;

[0030] The second oscillation circuit is connected to the second bias circuit and the third bias circuit respectively, and is configured to oscillate at a corresponding frequency according to the superimposed second current signal and the third current signal, and output the feedback signal.

[0031] Optionally, the second bias circuit includes a second bias transistor, a first terminal of the second bias transistor is connected to the positive voltage terminal, a control terminal of the second bias transistor is used to input the first voltage signal, and a second terminal of the second bias transistor is used to output the second current signal;

[0032] The third bias circuit comprises a third bias transistor, a first terminal of the third bias transistor is connected to the positive voltage terminal, a control terminal of the third bias transistor is used to input the second voltage signal, and a second terminal of the third bias transistor is used to output the third current signal;

[0033] A size ratio of the second bias transistor to the third bias transistor is positively correlated with a ratio of the first proportionality coefficient to the second proportionality coefficient, and a sum of the first proportionality coefficient and the second proportionality coefficient is equal to 1.

[0034] A second aspect of the embodiments of the present invention provides an image sensor, comprising the phase-locked loop circuit as described above.

[0035] Compared with the prior art, the embodiments of the utility model have the following beneficial effects: the above-mentioned phase-locked loop circuit includes a frequency detector, a charge pump circuit, a filter circuit, a first voltage-controlled oscillator and a second voltage-controlled oscillator; the filter circuit filters the first voltage signal output by the charge pump circuit and outputs a second voltage signal; the first voltage signal and the second voltage signal are proportionally superimposed and output to the second voltage-controlled oscillator, thereby reducing the loop bandwidth and the input noise introduced into the loop; and after the first voltage signal is frequency-locked and filtered by the phase-locked loop composed of the frequency detector, the charge pump circuit, the filter circuit and the second voltage-controlled oscillator, a stable second voltage signal with small jitter is output to the first voltage-controlled oscillator; the first voltage-controlled oscillator adjusts the frequency of the output signal of the phase-locked loop circuit according to the second voltage signal, and outputs a clock signal with small frequency jitter, thereby improving the output stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0037] Figure 1 A schematic diagram of the first structure of a phase-locked loop circuit provided in an embodiment of the utility model;

[0038] Figure 2 A second structural schematic diagram of a phase-locked loop circuit provided in an embodiment of the utility model;

[0039] Figure 3 A circuit diagram of a filter circuit provided by an embodiment of the utility model;

[0040] Figure 4 A schematic diagram of the structure of a first voltage-controlled oscillator provided in an embodiment of the utility model;

[0041] Figure 5 A circuit diagram of a first voltage-controlled oscillator provided in an embodiment of the utility model;

[0042] Figure 6 A schematic diagram of the structure of a second voltage-controlled oscillator provided in an embodiment of the utility model;

[0043] Figure 7 A circuit diagram of a second voltage-controlled oscillator provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] A first aspect of an embodiment of the utility model provides a phase-locked loop circuit, comprising:

[0047] The phase frequency detector 10 is configured to detect the frequency and phase difference between the reference signal Vref and the feedback signal Vfb, and generate a first control signal up and a second control signal down;

[0048] The charge pump circuit 20 is connected to the phase frequency detector 10 and is configured to charge and discharge according to the received first control signal up and the second control signal down, and output a first voltage signal Vctrl of corresponding magnitude;

[0049] The filter circuit 30 is connected to the charge pump circuit 20 and is configured to perform low-pass filtering on the first voltage signal Vctrl and output a filtered second voltage signal Vctrh;

[0050] A first voltage-controlled oscillator 40 is connected to the output end of the filter circuit 30 and is configured to adjust the frequency and phase of the output signal of the phase-locked loop circuit according to the second voltage signal Vctrh to output a clock signal;

[0051] The second voltage-controlled oscillator 50 is connected to the input and output ends of the filter circuit 30, and is configured to adjust the frequency and phase of the feedback signal Vfb according to the proportional superposition of the first voltage signal Vctrl and the second voltage signal Vctrh, so that the feedback signal Vfb has the same frequency and phase as the reference signal Vref.

[0052] In this embodiment, the phase frequency detector 10, the charge pump circuit 20, the filter circuit 30, and the second voltage controlled oscillator 50 form a feedback loop. The phase frequency detector 10 compares the reference signal Vref and the feedback signal Vfb output by the second voltage controlled oscillator 50, for example, compares the rising edges of the two, and obtains the first control signal up and the second control signal down according to the frequency and phase difference comparison between the two. Specifically, in the phase locked loop circuit, if the reference signal Vref has a rising edge, but the output signal does not have a rising edge, the first control signal up is a high level, and the second control signal down is a low level. If the reference signal Vref has a rising edge and the output signal has a rising edge, the phase frequency detector 10 simultaneously outputs the first control signal up and the second control signal down of low level. If the reference signal Vref does not have a rising edge, but the output signal has a rising edge, the first control signal up is a low level, and the second control signal down is a high level.

[0053] The charge pump circuit 20 charges and discharges according to the high and low levels of the first control signal up and the second control signal down. When the first control signal up is a high level signal and the second control signal down is a low level signal, the charge pump circuit 20 charges and the output first voltage signal Vctrl increases; and when the first control signal up is a low level signal and the second control signal down is a high level signal, the charge pump circuit 20 discharges and the output first voltage signal Vctrl decreases; and, when the first control signal up and the second control signal down are both high level signals or low level signals, the charge pump circuit 20 charges and discharges simultaneously, or cuts off charging and discharging at the same time. At this time, the charge pump circuit 20 outputs a constant first voltage signal Vctrl, and the constant voltage signal can be zero voltage or a preset voltage.

[0054] The first voltage signal Vctrl is filtered by the filter circuit 30, and the second voltage signal Vctrh is output, so as to reduce the input noise of the loop. The input end of the second voltage-controlled oscillator 50 is connected to the input end and the output end of the filter circuit 30 at the same time, and receives the proportionally superimposed first voltage signal Vctrl and the second voltage signal Vctrh. The second voltage-controlled oscillator 50 adjusts the frequency and phase of the feedback signal Vfb according to the proportionally superimposed first voltage signal Vctrl and the second voltage signal Vctrh. When the received first voltage signal Vctrl and the second voltage signal Vctrh increase, the voltage-controlled oscillator increases the frequency of the feedback signal Vfb to catch up with the frequency and phase of the reference signal Vref, until the frequencies and phases of the two are the same, the first control signal up and the second control signal down are at the same level, the frequency detector 10 is reset, and the frequency detection and phase locking operation is completed.

[0055] And when the received voltage signal decreases, the second voltage-controlled oscillator 50 reduces the frequency of the feedback signal Vfb, making it gradually approach the frequency and phase of the reference signal Vref, until the frequencies and phases of the two are the same, the first control signal up and the second control signal down are at the same level, the frequency detector 10 is reset, and the frequency detection and phase locking operation is completed.

[0056] The input end of the first voltage-controlled oscillator 40 is connected to the output end of the filter circuit 30, and the output end of the first voltage-controlled oscillator 40 constitutes the output end of the phase-locked loop circuit, and adjusts the frequency and phase of the output signal of the phase-locked loop circuit according to the received second voltage signal Vctrh, and outputs a clock signal.

[0057] On the one hand, the second voltage signal Vctrh is filtered and outputted through the filter circuit 30, thereby reducing the input noise of the loop. On the other hand, the feedback loop composed of the frequency detector 10, the filter circuit 30 and the second voltage-controlled oscillator 50 performs frequency detection and phase locking on the second voltage signal Vctrh. When the loop is stable, a stable second voltage signal Vctrh is generated. The stable and low-noise second voltage signal Vctrh is outputted to the first voltage-controlled oscillator 40. The first voltage-controlled oscillator 40 adjusts the frequency of the output signal of the phase-locked loop circuit according to the second voltage signal Vctrh, and outputs a clock signal with small frequency jitter, thereby improving output stability.

[0058] The phase and frequency detector 10 may be composed of structures such as a D flip-flop, a logic gate, etc., and the charge pump circuit 20 may be composed of a current source, a controllable switch, and an energy storage element.

[0059] The filter circuit 30 can select a corresponding filter structure according to the filtering requirements. In an optional embodiment, for example Figure 3 As shown, the filter circuit 30 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1 and a second resistor R2;

[0060] The first end of the first capacitor C1, the first end of the first resistor R1 and the first end of the second resistor R2 are connected to form the input end of the filter circuit 30, the second end of the first resistor R1 is connected to the first end of the second capacitor C2, the second end of the second resistor R2 is connected to the first end of the third capacitor C3 to form the output end of the filter circuit 30, and the second end of the first capacitor C1, the second end of the second capacitor C2 and the second end of the third capacitor C3 are grounded.

[0061] In this embodiment, the filter circuit 30 is a third-order filter structure, which filters out more high-frequency noise compared to a common second-order low-pass filter. After the first voltage signal Vctrl passes through the filter circuit 30, a second voltage signal Vctrh with smaller jitter is output.

[0062] Among them, in order to further improve the filtering capability and reduce signal jitter, in an optional embodiment, the resistance value range of the first resistor R1 is 50kΩ~200kΩ, the resistance value of the second resistor R2 is greater than 1MΩ, the capacitance value range of the first capacitor C1 is 0.2pF~2pF, the capacitance value range of the second capacitor C2 is 10pF~20pF, and the capacitance value range of the third capacitor C3 is 15pF~30pF.

[0063] The second resistor R2 is in megohm level, the capacitance value of the third capacitor C3 is in the range of 15pF to 30pF, and the size of the second capacitor C2 and the third resistor is adjusted to introduce zero poles at lower frequency positions, so that the cutoff frequency of the filter circuit 30 becomes lower, and the performance of filtering high-frequency signals is more significant.

[0064] Furthermore, in order to achieve different frequency outputs, such as Figure 2 As shown, in an optional embodiment, the phase-locked loop circuit further includes:

[0065] The first frequency divider 60 is connected to the output end of the first voltage-controlled oscillator 40 , and is configured to divide the frequency of the output signal of the first voltage-controlled oscillator 40 , and output the divided output signal of the phase-locked loop circuit.

[0066] In this embodiment, the input end of the first frequency divider 60 is connected to the output end of the first voltage-controlled oscillator 40, and the output end of the first frequency divider 60 constitutes the output end of the phase-locked loop circuit. The first voltage-controlled oscillator 40 adjusts the frequency and phase of its own output signal according to the second voltage signal Vctrh, and outputs a clock signal. The first frequency divider 60 divides the clock signal and outputs the required target frequency. The division ratio of the first frequency divider 60 can be set according to the requirements of the back-end module, and can be divided into two or three parts.

[0067] In another alternative embodiment, if Figure 2 As shown, in order to increase the output frequency of the loop, the phase-locked loop circuit also includes:

[0068] The second frequency divider 70, the input end of the second frequency divider 70 is connected to the output end of the second voltage-controlled oscillator 50, the output end of the second frequency divider 70 is connected to the input end of the frequency detector 10, the second frequency divider 70 is configured to divide the feedback signal Vfb output by the second voltage-controlled oscillator 50, and output the divided feedback signal Vfb to the frequency detector 10.

[0069] In this embodiment, the frequency detector 10 compares the reference signal Vref and the divided feedback signal Vfb, and outputs a first control signal up and a second control signal down. The first control signal up and the second control signal down control the charging and discharging of the charge pump circuit 20, and outputs a first voltage signal Vctrl to the filter circuit 30. The filter circuit 30 outputs a second voltage signal Vctrh after filtering. The second voltage signal Vctrh adjusts the frequency of the output signal of the second voltage-controlled oscillator 50 so that the frequency and phase of the loop are locked. When the loop is locked, the frequency of the output signal of the second voltage-controlled oscillator 50 is equal to the frequency of the reference signal Vref after being divided by the second frequency divider 70. Therefore, the phase-locked loop circuit realizes the function of N-fold frequency multiplication. The final frequency of the phase-locked loop circuit is determined according to the product of the frequency division ratios of the first frequency divider 60 and the second frequency divider 70.

[0070] The first voltage-controlled oscillator 40 and the second voltage-controlled oscillator 50 may adopt corresponding current source circuits, oscillation circuits and other structures. In an optional embodiment, as shown in FIG. Figure 4 As shown, the first voltage controlled oscillator 40 includes:

[0071] The first bias circuit 41 is connected to the positive voltage terminal AVDD and the output terminal of the filter circuit 30 respectively, and is configured to output a first current signal according to the second voltage signal Vctrh;

[0072] The first oscillator circuit 42 is connected to the first bias circuit 41 , and is configured to oscillate at a corresponding frequency according to the first current signal and output a clock signal.

[0073] In this embodiment, the first bias circuit 41 performs voltage-current conversion after receiving the second voltage signal Vctrh. The first current signal generated by the conversion and the second voltage signal Vctrh can change linearly or nonlinearly. The first current signal generated by the conversion is output to the first oscillation circuit 42. The first oscillation circuit 42 oscillates at different frequencies according to different current sizes and outputs a clock signal. The oscillation frequency of the clock signal changes positively correlated with the size of the current signal and changes linearly.

[0074] The first bias circuit 41 may be a bias tube, a current source, or the like. In an optional embodiment, Figure 5 As shown, the first bias circuit 41 includes a first bias transistor M1;

[0075] A first terminal of the first bias transistor M1 is connected to the positive voltage terminal AVDD, a control terminal of the first bias transistor M1 is used to input a second voltage signal Vctrh, and a second terminal of the first bias transistor M1 is used to output a first current signal.

[0076] In this embodiment, when the voltage at the control end of the first bias transistor M1 changes, the bias generates first current signals of different sizes, and the first current signals are output to the first oscillation circuit 42. The first oscillation circuit 42 oscillates at different frequencies according to different current sizes and outputs a clock signal. The oscillation frequency of the clock signal changes in a positive correlation with the size of the current signal and changes linearly.

[0077] The first oscillator circuit 42 may be a transistor, an inverter, or the like. In an optional embodiment, Figure 5 As shown, the first oscillator circuit 42 includes an odd number of first inverter circuits 421;

[0078] The input and output ends of an odd number of first inverter circuits 421 are connected in sequence to form a ring oscillator, and the output end or input end of a corresponding first inverter circuit 421 constitutes the output end of the first oscillation circuit 42, and the control ends of the odd number of first inverter circuits 421 are connected together to form the input end of the first oscillation circuit 42.

[0079] In this embodiment, an odd number of first inverter circuits 421 form an inverter chain, which oscillates at different frequencies according to first current signals of different magnitudes, and the clock signal generated by the oscillation is output from the input end or output end of a corresponding first inverter circuit 421 .

[0080] The first inverter circuit 421 may be composed of corresponding switch tubes and inverters.

[0081] like Figure 6 As shown, in an optional embodiment, the second voltage-controlled oscillator 50 includes:

[0082] The second bias circuit 51 is connected to the positive voltage terminal AVDD and the input terminal of the filter circuit 30 respectively, and is configured to output a second current signal with a first proportional coefficient according to the first voltage signal Vctrl;

[0083] The third bias circuit 52 is connected to the positive voltage terminal AVDD and the output terminal of the filter circuit 30 respectively, and is configured to output a third current signal of a second proportional coefficient according to the second voltage signal Vctrh;

[0084] The second oscillation circuit 53 is connected to the second bias circuit 51 and the third bias circuit 52 respectively, and is configured to oscillate at a corresponding frequency according to the superimposed second current signal and the third current signal, and output a feedback signal Vfb.

[0085] In this embodiment, the second bias circuit 51 performs voltage-current conversion after receiving the first voltage signal Vctrl, and the second current signal generated by the conversion changes linearly with the first voltage signal Vctrl, and the ratio is a first proportional coefficient. The second current signal generated by the conversion is output to the second oscillation circuit 53. The third bias circuit 52 performs voltage-current conversion after receiving the filtered second voltage signal Vctrh, and the third current signal generated by the conversion changes linearly with the second voltage signal Vctrh, and the ratio is a second proportional coefficient. The third current signal generated by the conversion is output to the second oscillation circuit 53. The second current signal and the third current signal are superimposed and output to the second oscillation circuit 53. The second oscillation circuit 53 oscillates at different frequencies according to the magnitude of the superimposed current, and outputs a feedback signal Vfb. The oscillation frequency of the feedback signal Vfb changes positively correlated with the magnitude of the superimposed current signal, and changes linearly.

[0086] The second bias circuit 51 and the third bias circuit 52 may adopt structures such as bias tubes and current sources. In an optional embodiment, the second bias circuit 51 includes a second bias transistor M2, a first end of the second bias transistor M2 is connected to the positive voltage end AVDD, a control end of the second bias transistor M2 is used to input the first voltage signal Vctrl, and a second end of the second bias transistor M2 is used to output a second current signal;

[0087] The third bias circuit 52 includes a third bias transistor M3, a first terminal of the third bias transistor M3 is connected to the positive voltage terminal AVDD, a control terminal of the third bias transistor M3 is used to input the second voltage signal Vctrh, and a second terminal of the third bias transistor M3 is used to output a third current signal;

[0088] The size ratio of the second bias transistor M2 to the third bias transistor M3 is positively correlated with the ratio of the first proportional coefficient to the second proportional coefficient, and the sum of the first proportional coefficient and the second proportional coefficient is equal to 1.

[0089] In this embodiment, when the voltage of the first voltage signal Vctrl at the control end changes, the second bias transistor M2 generates second current signals of different sizes according to the first proportional coefficient ratio, and the ratio of the second current signal to the first voltage signal Vctrl is the first proportional coefficient. When the voltage of the second voltage signal Vctrh at the control end changes, the third bias transistor M3 generates third current signals of different sizes according to the second proportional coefficient ratio, and the ratio of the third current signal to the second voltage signal Vctrh is the second proportional coefficient. The second current signal and the third current signal are output to the second oscillation circuit 53. The second oscillation circuit 53 oscillates at different frequencies according to the magnitude of the superimposed current, and outputs a feedback signal Vfb. The oscillation frequency of the feedback signal Vfb changes in a positive correlation with the magnitude of the current signal and changes linearly.

[0090] At the same time, in order to achieve proportional superposition, the sizes of the first bias transistor M1 and the second bias transistor M2 are controlled so that their size ratio is positively correlated with the ratio of the first proportional coefficient to the second proportional coefficient, so that the first voltage signal Vctrl and the second voltage signal Vctrh are weightedly added to the feedback signal Vfb signal finally output, thereby achieving signal superposition after interpolation.

[0091] The first oscillator circuit 42 may be a transistor, an inverter, or the like. In an optional embodiment, Figure 7 As shown, the second oscillator circuit 53 includes an odd number of second inverter circuits 531;

[0092] The input and output ends of an odd number of second inverter circuits 531 are connected in sequence to form a ring oscillator, and the output end or input end of a corresponding second inverter circuit 531 constitutes the output end of the second oscillation circuit 53, and the control ends of the odd number of second inverter circuits 531 are connected together to form the input end of the second oscillation circuit 53.

[0093] In this embodiment, an odd number of second inverter circuits 531 form an inverter chain, which oscillates at different frequencies according to the superimposed first current signals of different magnitudes, and the feedback signal Vfb generated by the oscillation is output from the input end or output end of a corresponding second inverter circuit 531.

[0094] The first inverter circuit 421 may be composed of corresponding switch tubes and inverters.

[0095] Compared with the prior art, the embodiment of the utility model has the following beneficial effects: the above-mentioned phase-locked loop circuit includes a phase frequency detector 10, a charge pump circuit 20, a filter circuit 30, a first voltage-controlled oscillator 40 and a second voltage-controlled oscillator 50; the filter circuit 30 filters the first voltage signal Vctrl output by the charge pump circuit 20 and outputs a second voltage signal Vctrh; the first voltage signal Vctrl and the second voltage signal Vctrh are proportionally superimposed and output to the second voltage-controlled oscillator 50, thereby reducing the loop bandwidth and the input noise introduced into the loop; and after the first voltage signal Vctrl is frequency-locked and filtered by the phase-locked loop composed of the phase frequency detector 10, the charge pump circuit 20, the filter circuit 30 and the second voltage-controlled oscillator 50, a stable second voltage signal Vctrh with small jitter is output to the first voltage-controlled oscillator 40; the first voltage-controlled oscillator 40 adjusts the frequency of the output signal of the phase-locked loop circuit according to the second voltage signal Vctrh, and outputs a clock signal with small frequency jitter, thereby improving the output stability.

[0096] The utility model also provides an image sensor, which includes a phase-locked loop circuit. The specific structure of the phase-locked loop circuit refers to the above embodiment. Since the image sensor adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the phase-locked loop circuit acts as a high-speed clock generator to provide the image sensor with a clock signal that meets the working requirements of each module.

[0097] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A phase-locked loop circuit, characterized in that: include: A frequency detector and a phase detector configured to detect a frequency and a phase difference between a reference signal and a feedback signal, and generate a first control signal and a second control signal; a charge pump circuit connected to the phase and frequency detector, configured to charge and discharge according to the received first control signal and second control signal, and output a first voltage signal of corresponding magnitude; a filter circuit, connected to the charge pump circuit, configured to perform low-pass filtering on the first voltage signal and output a filtered second voltage signal; a first voltage-controlled oscillator connected to the output end of the filter circuit and configured to adjust the frequency and phase of the output signal of the phase-locked loop circuit according to the second voltage signal to output a clock signal; A second voltage-controlled oscillator is connected to the input and output ends of the filter circuit and is configured to adjust the frequency and phase of the feedback signal according to the proportional superposition of the first voltage signal and the second voltage signal so that the feedback signal has the same frequency and phase as the reference signal.

2. The phase-locked loop circuit according to claim 1, characterized in that: The filter circuit includes a first capacitor, a second capacitor, a third capacitor, a first resistor and a second resistor; The first end of the first capacitor, the first end of the first resistor and the first end of the second resistor are connected to form the input end of the filter circuit, the second end of the first resistor is connected to the first end of the second capacitor, the second end of the second resistor is connected to the first end of the third capacitor to form the output end of the filter circuit, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are grounded.

3. The phase-locked loop circuit according to claim 2, characterized in that: The resistance value of the first resistor ranges from 50 kΩ to 200 kΩ; The resistance of the second resistor is greater than 1MΩ; The capacitance value of the first capacitor ranges from 0.2pF to 2pF; The capacitance value of the second capacitor ranges from 10pF to 20pF; The capacitance value of the third capacitor ranges from 15 pF to 30 pF.

4. The phase-locked loop circuit according to claim 1, characterized in that: The phase-locked loop circuit also includes: The first frequency divider is connected to the output end of the first voltage-controlled oscillator, and is configured to divide the frequency of the output signal of the first voltage-controlled oscillator and output the divided output signal of the phase-locked loop circuit.

5. The phase-locked loop circuit according to claim 4, characterized in that: The phase-locked loop circuit also includes: A second frequency divider, wherein the input end of the second frequency divider is connected to the output end of the second voltage-controlled oscillator, the output end of the second frequency divider is connected to the input end of the frequency detector and phase detector, and the second frequency divider is configured to divide the feedback signal output by the second voltage-controlled oscillator and output the divided feedback signal to the frequency detector and phase detector.

6. The phase-locked loop circuit according to claim 1, characterized in that: The first voltage controlled oscillator comprises: a first bias circuit, connected to the positive voltage terminal and the output terminal of the filter circuit respectively, and configured to output a first current signal according to the second voltage signal; The first oscillation circuit is connected to the first bias circuit and is configured to oscillate at a corresponding frequency according to the first current signal and output the clock signal.

7. The phase-locked loop circuit according to claim 6, characterized in that: The first bias circuit includes a first bias transistor; The first end of the first bias transistor is connected to the positive voltage end, the control end of the first bias transistor is used to input the second voltage signal, and the second end of the first bias transistor is used to output the first current signal.

8. The phase-locked loop circuit according to claim 1, characterized in that: The second voltage-controlled oscillator comprises: A second bias circuit is connected to the positive voltage terminal and the input terminal of the filter circuit respectively, and is configured to output a second current signal with a first proportional coefficient according to the first voltage signal; a third bias circuit, connected to the positive voltage terminal and the output terminal of the filter circuit respectively, and configured to output a third current signal of a second proportional coefficient according to the second voltage signal; The second oscillation circuit is connected to the second bias circuit and the third bias circuit respectively, and is configured to oscillate at a corresponding frequency according to the superimposed second current signal and the third current signal, and output the feedback signal.

9. The phase-locked loop circuit according to claim 8, characterized in that: The second bias circuit comprises a second bias transistor, a first terminal of the second bias transistor is connected to the positive voltage terminal, a control terminal of the second bias transistor is used to input the first voltage signal, and a second terminal of the second bias transistor is used to output the second current signal; The third bias circuit comprises a third bias transistor, a first terminal of the third bias transistor is connected to the positive voltage terminal, a control terminal of the third bias transistor is used to input the second voltage signal, and a second terminal of the third bias transistor is used to output the third current signal; A size ratio of the second bias transistor to the third bias transistor is positively correlated with a ratio of the first proportionality coefficient to the second proportionality coefficient, and a sum of the first proportionality coefficient and the second proportionality coefficient is equal to 1.

10. An image sensor, characterized in that: It comprises a phase-locked loop circuit as claimed in any one of claims 1 to 9.

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