Internal wire delay measurement device and method

Abstract

The present disclosure relates to the measurement of internal wire delays. A semiconductor device includes a test circuit system for measuring an internal signal wire propagation delay during a memory access operation; and a circuit system configured to store delay information for configuring an internal delay based on the measured internal signal propagation circuit delay. The semiconductor device includes a test circuit configured to measure a signal propagation delay between a command decoder and a memory bank logic circuit based on a time between receiving a test command signal directly from a command decoder and receiving the test command signal routed through a memory bank logic circuit.

Description

Technical Field

[0001] The present application relates to a semiconductor device, and more particularly to a semiconductor device including a circuit system for measuring internal wire delay. Background Art

[0002] High data reliability, high memory access speed, low power consumption and reduced chip size are the characteristics required of semiconductor memories. Within the memory, relative timing is important to ensure that data is reliably transmitted from and received at the semiconductor device. Due to the conductive properties of the wire traces and the transition speed of the components on the device, process, voltage and / or temperature (PVT) differences on the semiconductor device may cause timing variations between semiconductor devices. For devices with slower operating speeds, the transmitted data may be unstable due to the reduced timing margin, which may affect the reliability of the device. Summary of the invention

[0003] One aspect of the present disclosure relates to a device comprising: a memory cell array; a storage body logic circuit arranged adjacent to the memory cell array; and a peripheral circuit arranged away from each of the memory cell array and the storage body logic circuit, wherein the peripheral circuit includes a command decoder connected to the storage body logic circuit via a first bus and a test circuit connected to the storage body logic circuit via a second bus and connected to the command decoder via the first bus; wherein in a test operation mode, the command decoder is configured to transmit a test command signal to the test circuit via the first bus and via the second bus.

[0004] Another aspect of the present disclosure relates to a device comprising: a test circuit configured to measure a signal propagation delay between a command decoder and a memory logic circuit based on a time between receiving a test command signal directly from a command decoder and receiving the test command signal routed through a memory logic circuit.

[0005] Another aspect of the present disclosure relates to a method, comprising: in a test mode: providing a test command signal to a memory logic circuit and a test circuit of the semiconductor device; providing the test command signal from the memory logic circuit to the test circuit; determining a delay value based on a time between receiving the test command signal from the command decoder and receiving the test command signal from the memory logic circuit; and providing the delay value at an output of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic block diagram of a semiconductor device according to an embodiment of the present disclosure is shown.

[0007] Figure 2 A schematic block diagram of a portion of a memory array according to one embodiment of the present disclosure is shown.

[0008] Figure 3 A schematic block diagram of a portion of a memory array according to one embodiment of the present disclosure is shown.

[0009] 4a depicts an exemplary timing diagram showing a first test mode signal timing for measuring a wait time between receiving a RASACT signal from a command decoder at a test circuit and receiving a BankActive signal from a memory bank logic at the test circuit, according to an embodiment of the present disclosure.

[0010] 4 b depicts an exemplary timing diagram 401 showing a second test mode signal timing for measuring a signal propagation delay between receipt of a RASACT signal from a command decoder at a test circuit and receipt of a RASACTWire signal from memory bank logic at the test circuit, according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Certain details are set forth below to provide a full understanding of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In addition, the specific embodiments of the present disclosure described herein are provided by way of example, and should not be used to limit the scope of the present disclosure to these specific embodiments.

[0012] The present disclosure describes a semiconductor device that includes a circuit system for detecting internal signal conductor propagation delays (e.g., based on signal transfer or propagation timing and component transition timing) during an access operation; and a circuit system configured to store delay information, the delay information being used to control internal delays based on the detected internal circuit delays. Typically, during a memory access operation, a series of operations occur within the semiconductor device, and the subsequent operations depend on information from previous operations in the series. For example, in response to receiving an activation command (ACT), a command decoder may provide a row address strobe (RAS) activation signal RASACT (e.g., an internal command signal) to a memory body logic circuit system (or row decoder). After a predetermined wait time, the memory body logic circuit system may provide a BankActive signal (e.g., read word line activation (RWLACT)). After generating the BankActive signal, a logic circuit (e.g., AND logic) evaluates the memory body address signal and the BankActive signal to activate the selected memory body. Thus, when the selected memory body is activated, other control signals may activate a row of memory cells to be accessed. The data read from the row memory cells may be sensed via a sense amplifier and may be provided to an input / output (I / O) circuit system (e.g., including a buffer and a driver) coupled to each data terminal DQ. The I / O circuit system may be configured to provide the read data to a data bus via a data terminal in response to a control signal generated based on an ACT command.

[0013] In this example, the logic circuit depends on the BankActive signal generated before the BankActive signal and the bank address signal are evaluated. If the logic circuit is activated too early (e.g., before the BankActive signal is generated), the memory access operation may fail. Conversely, if a delay is added before activating the logic circuit, the downstream timing margin may be reduced.

[0014] The timing of generating the BankActive signal is based on a combination of predetermined internal wait times and signal propagation delays (e.g., based on the relative physical location of the associated circuits of the semiconductor device, and based on the physical timing characteristics of the semiconductor device that are affected by PVT variations). The predetermined internal wait times can be set based on an operating mode for compatible operation of the semiconductor device within an installed system. However, signal propagation delays can be measured and compensated within the semiconductor device. For example, a memory array and a memory bank logic circuit system (e.g., including logic circuits) can be physically located in one part of a silicon wafer, while a command decoder can be physically located in another part of the silicon wafer. The physical distance between the command decoder and the memory bank logic circuit system can be such that variations in the signal propagation delay between the command decoder and the memory bank logic circuit system caused by PVT differences between different devices can result in significant delay differences in high-speed memory applications.

[0015] The semiconductor device may include a test circuit configured to determine the signal propagation delay and to configure the semiconductor device to adjust the delay before activating the logic circuit based on the determined signal propagation delay. The test circuit may include a process monitor configured to measure the signal delay. In one example, the semiconductor device may be placed in a first test mode to measure the time between receiving the activation command ACT and activating the BankActive signal, or placed in a second test mode to measure the signal propagation delay. For example, in the first test mode or the second test mode, an ACT command may be provided to the semiconductor device, and in response, the command decoder is configured to provide a RASACT signal (e.g., in the test mode, a test command signal) to the memory body logic circuit system (e.g., via a first bus) and the test circuit (e.g., via a second bus) in response to the ACT command. In response to the RASACT signal, the counter of the test circuit is configured to start counting the oscillations of a clock signal (e.g., such as a clock signal provided by a ring oscillator of the test circuit).

[0016] The bank logic circuit system includes a multiplexer (e.g., or a switch) configured to provide one of a BankActive signal (e.g., a first test mode) or a RASACT signal (e.g., a second test mode) to the test circuit (e.g., via a third bus). Thus, in the first test mode, the bank logic circuit system can be configured to provide the BankActive signal to the test circuit. In response to receiving the BankActive signal, the test circuit is configured to stop the counter and provide a delay value based on the time between receiving the RASACT signal and the BankActive signal (e.g., BankActive delay).

[0017] In the second test mode, the memory logic circuit system can be configured to provide the RASACT signal (RASACTWire) received from the command decoder to the test circuit. In response to receiving the RASACTWire signal, the test circuit is configured to stop the counter and provide a delay value based on the time (e.g., signal propagation delay) between the received RASACT signal and the RASACTWire signal. In some instances, the test circuit can provide the delay value to the tester via the data terminal (DQ). In some instances, the original count value can be adjusted to determine the delay value. For example, the original count value can be adjusted based on the difference between the distance between the command decoder and the memory logic circuit system and the distance between the memory logic circuit system and the test circuit. In one example, the distance between the command decoder and the memory logic can be approximately equal to the distance between the memory logic and the test circuit. In this way, the original count value in the second mode can indicate a propagation delay, which is approximately twice the propagation delay between the command decoder and the memory logic. Therefore, in some instances, for the second mode, the test circuit can divide the original signal propagation delay count value by two to provide a delay value. In other examples, the test circuit may provide the raw count value to the tester, and the tester may derive the delay value from the raw count value. Based on the determined signal propagation delay, the tester (or test circuit) may cause the semiconductor device to store a delay parameter indicating the signal propagation delay, which may be used to adjust the timing of the internal circuit system of the memory logic. In some examples, the delay parameter may be permanently stored in a programmable circuit, such as a fuse memory or an anti-fuse memory. By individually configuring delay values ​​specific to the physical characteristics of the semiconductor device, the problem of prematurely activating the logic circuit and / or applying a longer delay than necessary may be avoided.

[0018] Figure 1 A schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure is shown. The semiconductor device 100 includes a memory die. The memory die may include a command / address input circuit 115, an address decoder 120, a command decoder 125, a clock input circuit 105, an internal clock generator 107, a row decoder 130, a column decoder 140, a memory cell array 145, a read / write amplifier 165, an I / O circuit 170, a test circuit, and a power supply circuit 190.

[0019] In some embodiments, the semiconductor device 100 may include, but is not limited to, for example, a dynamic random access memory (DRAM) device integrated into a single semiconductor chip, such as double data rate (DDR) DDR4, DDR5, low power (LP) DDR. The die may be mounted on an external substrate, such as a memory module substrate, a motherboard, etc. The semiconductor device 100 may further include a memory cell array 145. The memory cell array 145 includes a plurality of memory banks, each memory bank including a plurality of word lines WL, a plurality of bit lines BL (e.g., digital lines, access lines, data I / O lines, etc.), and a plurality of memory cells MC arranged at the intersection of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by the row decoder 130, and the selection of the bit line BL (together with the column select signal CS) is performed by the column decoder 140. The sense amplifier (SA) 150 is located near its corresponding bit line BL and is connected to at least one corresponding local I / O line based on the CS signal, and the at least one corresponding local I / O line is coupled to a corresponding one of the at least two main I / O line pairs via a transmission gate (TG) 195 used as a switch.

[0020] In some embodiments, the memory cell array 145 may include memory array pads with respective digit lines and memory cells. The memory array pads may be separated by regions for control circuitry including sense amplifiers 150 connected to corresponding subsets (e.g., even or odd) of bit lines of adjacent memory array pads to perform sensing operations on corresponding memory cells.

[0021] The semiconductor device 100 may employ a plurality of external terminals including address and command terminals coupled to a command / address bus (C / A), clock terminals CK and / CK, data terminals DQ, DQS and DM, and power supply terminals VDD, VSS.

[0022] The command / address terminal may be provided with an address signal and a memory address signal from the outside via the command / address bus 110. The address signal and the memory address signal provided to the address terminal are transmitted to the address decoder 120 via the command / address input circuit 115. The address decoder 120 receives the address signal and decodes the address signal to provide a decoded address signal ADD. The ADD signal includes a decoded row address signal and a decoded column address signal. The decoded row address signal is provided to the row decoder 130, and the decoded column address signal is provided to the column decoder 140. The address decoder 120 also receives the memory address signal and provides the memory address signal to the row decoder 130 and the column decoder 140.

[0023] The command / address terminal may be further provided with a command signal from, for example, an external device such as a memory controller. The command signal may be provided to a command decoder 125 via a C / A bus via the command / address input circuit 115. The command decoder 125 decodes the command signal to generate various internal commands / signals and test mode signals, including a RASACT signal for selecting a word line and a column command signal for selecting a bit line to read / write, such as a read command or a write command.

[0024] Therefore, when a read command is issued and the row address and column address are provided in time with the read command, read data is read from the memory cell array 145 specified by these row addresses and column addresses. The read data DQ is output to the outside from the data terminals DQ (data), DQS (data strobe), and DM (data mask) via the read / write amplifier 165 and the input / output circuit 170. Similarly, when a write command is issued and the row address and column address are provided in time with such a command, and then the write data is provided to the data terminals DQ, DQS, and DM, the write data is received by the data receiver in the input / output circuit 170, and is provided to the memory cell array 145 via the input / output circuit 170 and the read / write amplifier 165 and written into the memory cell specified by the row address and column address.

[0025] Typically, during a memory access operation, a series of operations occur within the semiconductor device 100, and the subsequent operations sometimes depend on information from previous operations in the series. For example, in response to receiving an activation command (ACT), the command decoder 115 may provide a RASACT signal (e.g., an internal command signal) to the memory bank logic circuit system 131 of the row decoder 130 (e.g., via a first bus). After a predetermined wait time, the memory bank logic circuit system 131 may provide a BankActive signal (e.g., read word line activation (RWLACT)). After generating the BankActive signal, the logic circuit (e.g., AND logic) of the memory bank logic circuit system 131 evaluates the memory bank address signal and the BankActive signal to activate the selected memory bank BANK0-N. Therefore, when the selected memory bank is activated, other control signals may activate a row of memory cells to be accessed. The data read from the row memory cell may be sensed via a sense amplifier 150 and may be provided to an IO circuit 170 (e.g., including a buffer and a driver) via a read / write amplifier 165. The IO circuit 170 may be configured to provide read data to the data bus via the data terminal DQ in response to a control signal (eg, such as an LCLK signal) generated based on the ACT command.

[0026] In this example, the logic circuit depends on the BankActive signal generated before the BankActive signal and the bank address signal are evaluated. If the logic circuit is activated too early (e.g., before the BankActive signal is generated), the memory access operation may fail. Conversely, if a delay is added before activating the logic circuit, the downstream timing margin may be reduced.

[0027] The timing of generating the BankActive signal is based on a combination of a predetermined internal latency and a signal propagation delay (e.g., based on the relative physical location of the associated circuits of the semiconductor device 100, and based on the physical timing characteristics of the semiconductor device 100 that are affected by PVT variations). The predetermined internal latency may be set based on an operating mode for compatible operation of the semiconductor device 100 within an installed system. However, the signal propagation delay may be measured and compensated within the semiconductor device 100. For example, the memory cell array 145 and the memory logic circuit system 131 (e.g., including logic circuits) may be physically located in one portion of the silicon wafer, while the command decoder 125 may be physically located in another portion of the silicon wafer (e.g., a peripheral circuit area). The physical distance between the command decoder 125 and the memory logic circuit system 131 may be such that variations in the signal propagation delay between the command decoder 125 and the memory logic circuit system 131 caused by PVT differences between devices may result in significant delay differences in high-speed memory applications.

[0028] The semiconductor device 100 may include a test circuit 180 configured to determine the signal propagation delay and configure the semiconductor device 100 to adjust the delay before activating the logic circuit of the memory bank logic circuit system 131 based on the determined signal propagation delay. In one example, the semiconductor device 100 may be placed in a first test mode to measure the time between receiving the activation command ACT and activating the BankActive signal, or in a second test mode to measure the signal propagation delay. For example, the semiconductor device 100 may be placed in the first or second test mode via a command from a tester or a host. The command decoder 125 may provide a test mode signal indicating the test mode to the row decoder 130. In the first test mode or the second test mode, the ACT command may be provided to the semiconductor device 100. The command decoder 125 may be configured to provide a RASACT signal (e.g., in the test mode, a test command signal) to the memory bank logic circuit system 131 (e.g., via a first bus) and the test circuit 180 (e.g., via a second bus) in response to the ACT command. In response to the RASACT signal, test circuit 180 may begin counting oscillations of a count clock (eg, such as a count clock provided by a ring oscillator of test circuit 180 ).

[0029] The bank logic circuit system 131 includes a multiplexer (e.g., or a switch) configured to provide one of the BankActive signal (e.g., the first test mode) or the RASACTWire signal (e.g., the second test mode) to the test circuit 180 (e.g., via the third bus as a test command signal). Therefore, in the first test mode, the bank logic circuit system 131 can be configured to provide the BankActive signal to the test circuit 180. In response to receiving the BankActive signal, the test circuit 180 is configured to stop counting the count clock and provide a delay value based on the count value to indicate the waiting time between providing the RASACT signal and generating the BankActive signal. In the second test mode, the bank logic circuit system 131 can be configured to provide the RASACT signal (RASACTWire) received from the command decoder to the test circuit 180. In response to receiving the RASACTWire signal, the test circuit 180 can be configured to stop counting the oscillations of the count clock and provide a delay value based on the count value to indicate the time between receiving the RASACT signal and receiving the RASACTWire signal (e.g., signal propagation delay). In some examples, test circuit 180 may provide the delay value to a tester (not shown) via a data terminal (DQ).

[0030] The raw count value may be based on a signal propagation path from the command decoder 125 to the memory logic circuit system 131 and a signal propagation path from the memory logic circuit system 131 to the test circuit 180. In some examples, the test circuit 180 may adjust the raw count value to determine the delay value. For example, the test circuit 180 may reduce the raw count value from the second mode to compensate for the additional delay path. The test circuit 180 may adjust the raw count value based on the difference between the distance between the command decoder 125 and the memory logic circuit system 131 and the distance between the memory logic circuit system 131 and the test circuit 180. In one example, the distance between the command decoder 125 and the memory logic circuit 131 may be approximately equal to the distance between the memory logic circuit 131 and the test circuit 180. In this example, the test circuit 180 may divide the raw count value by two to provide a delay value.

[0031] In other examples, the test circuit 180 may provide the raw count value as a delay value to the tester via the data terminal DQ, and the tester may compensate and process the raw count value to determine the signal propagation delay. Based on the determined signal propagation delay, the tester (or the test circuit 180) may cause the semiconductor device 200 to store a delay parameter for selecting a delay value to be applied before activating the logic circuit of the memory logic circuit system 131. The delay parameter may be permanently stored in a programmable circuit, such as a fuse memory 181 (or an anti-fuse memory). By individually configuring delay values ​​specific to the physical characteristics of the semiconductor device 100, the problem of prematurely activating the logic circuit of the memory logic circuit system 131 and / or applying a longer delay than necessary may be avoided.

[0032] Turning to the description of the external terminals included in the semiconductor device 100, the clock terminals CK and / CK are provided with an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be provided to the clock input circuit 105. The clock input circuit 105 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK is provided to the internal clock generator 107, so that a phase-controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. Although not limited to this, a delay locked loop (DLL) circuit, a duty cycle correction (DCC) circuit, or a combination thereof can be used as the internal clock generator 107. The phase-controlled internal clock signal LCLK can be used as a timing signal for determining the output timing of read data.

[0033] The power supply terminal is provided with power supply potentials VDD and VSS. These power supply potentials VDD2 and VSS are provided to the power supply circuit 190. The power supply circuit 190 generates various internal potentials VKK, VARY, VPERI, etc. based on the power supply potentials VDD2 and VSS. The internal potential VKK is mainly used in the row decoder 130, the internal potential VARY is mainly used in the sense amplifier included in the memory cell array 145, and the internal potential VPERI is used in many other circuit blocks.

[0034] The power supply terminal is also provided with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are provided to the input / output circuit 170. The power supply potentials VDDQ and VSSQ are usually the same as the power supply potentials VDD2 and VSS, respectively. However, dedicated power supply potentials VDDQ and VSSQ are used for the input / output circuit 170 so that the power supply noise generated by the input / output circuit 170 will not propagate to other circuit blocks.

[0035] Figure 2A block diagram of a portion of a semiconductor device 200 according to an embodiment of the present disclosure is shown. The semiconductor device 200 includes a peripheral circuit region 210 having a command decoder 212 , a test circuit 214 and a data terminal DQ 218 , a memory array 220 ( 1 )-( 2 ) and a bank logic 230 . Figure 1 The semiconductor device 200 may be implemented based on the semiconductor device 100 .

[0036] The peripheral circuit area 210 may include circuitry of the semiconductor device 200 configured to interface with an external bus coupled to the semiconductor device, and may be physically located on a portion of the semiconductor device 200 different from the memory array 220(1)-(2) and the memory logic 230. The command decoder 212 may be configured to receive an ACT command from the command and address bus, and provide a RASACT signal (e.g., a test command signal) to the test circuit 214 (via the first bus) and the memory logic 230 (e.g., via the second bus). The command decoder 212 may also be configured to provide a test mode signal to the memory logic 230. The test mode may be stored in a mode register of the command decoder 212, and may be set by a host or tester coupled to the semiconductor device 200. The test circuit 214 may include a process monitor controller 215 coupled to a process monitor 216.

[0037] The process monitor controller 215 may be configured to receive a RASACT signal (e.g., a pulse) and may provide a start control signal to the process monitor 216. In response to the start control signal, the process monitor 216 may start counting the oscillations of the counter clock. In some instances, the counter clock may be generated by a ring oscillator of the process monitor 216. The process monitor controller 215 may receive one of the BankActive signal or the RASACTWire signal from the bank logic 230 (e.g., via a third bus as a test command signal) and may provide a stop control signal to the process monitor 216 in response to the BankActive signal or the RASACTWire signal. In response to the stop control signal, the process monitor 216 may stop counting the oscillations of the counter clock and may process the count value to provide a delay value to the data terminal DQ 218 to provide to a tester or host.

[0038] The bank logic 230 may include a BankActive circuit 232 coupled to a multiplexer 234 and a logic circuit 236. The BankActive circuit 232 and the multiplexer 234 (second input) may receive a RASACT signal from the command decoder 212. In addition, the multiplexer 234 may receive a test mode signal from the command decoder 212 to control the operation of the multiplexer 234. The BankActive circuit 232 may generate a BankActive signal based on the RASACT signal and may provide the BankActive signal to the multiplexer 234 (first input) and the logic circuit 236. The logic circuit 236 may initiate activation of a bank in one of the memory arrays 220 (1)-(2) based on a received bank address signal (not shown) and the BankActive signal. Based on the value of the test mode signal, the multiplexer 234 may selectively provide one of the BankActive signal or the RASACT signal (RASACTWire) received from the command decoder 212 to the test circuit 214. For example, in response to a test mode signal having a first value, multiplexer 234 may provide a BankActive signal to test circuit 214. In response to a test mode signal having a second value, multiplexer 234 may provide a RASACTWire signal to test circuit 214.

[0039] In operation, during a memory access operation, a series of operations occurs within the semiconductor device 200, where a later operation sometimes depends on information from a previous operation in the series. For example, in response to receiving an ACT command, the command decoder 212 may provide a RASACT signal to the bank logic 230. After a predetermined wait time, the BankActive circuit 232 of the bank logic 230 may generate a BankActive signal (e.g., read word line activation (RWLACT)). Based on the BankActive signal and the bank address signal, the logic circuit 236 (e.g., AND logic) may activate the memory banks of the memory array 220 (1)-(2).

[0040] However, in this example, although logic circuit 236 depends on the BankActive signal generated before evaluating the BankActive signal and the bank address signal, the operation of the logic circuit of logic circuit 236 may be triggered by another signal. Therefore, if logic circuit 236 is activated too early (e.g., before the BankActive signal is generated), the memory access operation may fail. Conversely, if a delay is added before activating logic circuit 236, the downstream timing margin for the memory access operation may be reduced.

[0041] The timing of generating the BankActive signal is based on a combination of predetermined internal latencies and signal propagation delays (e.g., based on the relative physical locations of the associated circuits of the semiconductor device 200, and based on physical timing characteristics of the semiconductor device 200 that are affected by PVT variations). The predetermined internal latencies may be set based on an operating mode for compatible operation of the semiconductor device 200 within an installed system. In some examples, signal propagation delays may be measured and compensated within the semiconductor device 200. For example, the memory array 220(1)-(2) and the memory logic 230 may be physically located in one portion of a silicon wafer, while the peripheral circuit region 210 may be physically located in another portion of the semiconductor device 200. The physical distance between the peripheral circuit region 210 and the memory logic 230 may be such that variations in signal propagation delays between the command decoder 212 and the memory logic 230 caused by PVT differences between different devices may result in significant propagation delay differences in high-speed memory applications.

[0042] The test circuit 214 may be configured to determine a signal propagation delay, which may be used to configure the semiconductor device 200 to adjust a delay before activating the logic circuit 236 based on the determined signal propagation delay. The semiconductor device 200 may be placed in a first test mode to measure the time between receiving an activation command ACT and activating the BankActive signal, or in a second test mode to measure the signal propagation delay. For example, in the first test mode or the second test mode, an ACT command is provided to the command decoder 212. The command decoder 212 is configured to provide a RASACT signal to the memory logic 230 and the test circuit 214 in response to the ACT command. In response to the RASACT signal, the process monitor controller 215 is configured to provide a start control signal to the process monitor 216. In response to the start control signal, the process monitor 216 is configured to start counting the oscillations of a counter clock (e.g., a counter clock provided by a ring oscillator of the test circuit 214).

[0043] The multiplexer 234 may be configured to selectively provide one of a BankActive signal (e.g., a first test mode) or a RASACTWire signal (e.g., a second test mode) from the BankActive circuit 232 to the test circuit 214. Thus, in the first test mode, the multiplexer 234 may be configured to provide the BankActive signal to the test circuit 214. In response to receiving the BankActive signal, the process monitor controller 215 is configured to provide a stop control signal to the process monitor 216. In response to the stop control signal, the process monitor 216 is configured to stop counting and process the count value to provide a delay value (e.g., BankActive delay) indicating the time between receiving the RASACT signal and receiving the BankActive signal. In the second test mode, the multiplexer 234 may be configured to provide the RASACT signal (RASACTWire) received from the command decoder 212 to the test circuit 214. In response to receiving the RASACTWire signal, the process monitor controller 215 is configured to provide the stop control signal to the process monitor 216. In response to the stop control signal, the process monitor 216 is configured to stop counting and process the count value to provide a delay value (e.g., signal propagation delay) indicating the time between receiving the RASACT signal and receiving the RASACTWire signal. In some examples, the process monitor 216 can provide the delay value to a tester (not shown) via the data terminal DQ 218.

[0044] In some examples, the raw count value may be based on a signal propagation path from the command decoder 212 to the memory logic 230 and a signal propagation path from the memory logic 230 to the test circuit 214. In some examples, the process monitor 216 may adjust the raw count value to determine the delay value. For example, the process monitor 216 may reduce the raw count value from the second mode to compensate for the additional delay path. The process monitor 216 may adjust the raw count value based on the difference between the distance between the command decoder 212 and the memory logic circuit 230 and the distance between the memory logic circuit 230 and the test circuit 214. In one example, the distance between the command decoder 212 and the memory logic circuit 230 may be approximately equal to the distance between the memory logic circuit 230 and the test circuit 214. In this example, the process monitor 216 may divide the raw count value by two to provide a delay value.

[0045] In other examples, the process monitor 216 can provide the raw count value as a delay value to the tester via the data terminal DQ 218, and the tester can compensate and process the raw count value to determine the signal propagation delay. Based on the determined signal propagation delay, the tester (or command decoder 212) can cause the semiconductor device 200 to store a delay parameter for selecting a delay value to be applied before activating the logic circuit 236 of the memory logic 230. The delay parameter can be permanently stored in a programmable circuit (not shown), such as a fuse memory or an anti-fuse memory. By individually configuring delay values ​​specific to the physical characteristics of the semiconductor device 200, the problem of prematurely activating the logic circuit 236 of the memory logic 230 and / or applying a longer delay than necessary can be avoided.

[0046] Figure 3 A block diagram of a portion of a semiconductor device 300 according to an embodiment of the present disclosure is shown. The semiconductor device 300 includes a command decoder 304, a bank logic 310, and a test circuit 320. Figure 1 The semiconductor device 100 and / or Figure 2 The semiconductor device 200 may be used to implement the semiconductor device 300 .

[0047] The command decoder 304 may be configured to receive an ACT command from the command and address bus, and provide a RASACT signal (e.g., an internal command signal in a normal operation mode and a test command signal in a test operation mode) to the memory logic 310 (e.g., via a first bus) and the test circuit 320 (e.g., via a second bus) in response to the ACT command. The command decoder 304 may also be configured to provide a test mode signal to the memory logic 310 to indicate a test mode of the semiconductor device 300. The test mode may be stored in a mode register of the command decoder 304 and may be set by a host or a tester coupled to the semiconductor device 300.

[0048] The bank logic 310 may include a BankActive circuit 312 coupled to a multiplexer 314. The BankActive circuit 312 and the multiplexer 314 (first input) may receive a RASACT signal from the command decoder 304. In addition, the multiplexer 314 may receive a test mode signal from the command decoder 304 to control the operation of the multiplexer 314. The BankActive circuit 312 may generate a BankActive signal based on the RASACT signal, and may provide the BankActive signal to the multiplexer 314 (second input) and a logic circuit (not shown) that may initiate activation of a bank of the memory array based on a received bank address signal (not shown) and the BankActive signal. Based on the value of the test mode signal, the multiplexer 314 may selectively provide one of the BankActive signal or the RASACTWire signal to the test circuit 320. For example, in response to a test mode signal having a first value, the multiplexer 314 may provide the BankActive signal to the test circuit 320 (e.g., via a third bus). In response to the test mode signal having the second value, multiplexer 314 may provide the RASACTWire signal to test circuit 320 (eg, via a third bus).

[0049] The test circuit 320 may include a process monitor controller 322 coupled to a process monitor 324. The process monitor controller 322 may be configured to receive a RASACT signal (e.g., a pulse) and may provide a start control signal to the process monitor 324. In response to the start control signal, the process monitor 324 may start counting counter clock oscillations in response to the RASACT signal. In some instances, the counter clock may be generated by a ring oscillator of the process monitor 324. The process monitor controller 322 may receive one of the BankActive signal or the RASACTWire signal from the multiplexer 314 and may provide a stop control signal to the process monitor 324. In response to the stop control signal, the process monitor 324 may stop counting the oscillations of the counter clock. The process monitor 324 may process the count value and provide a delay value to provide to the tester or host.

[0050] In operation, during a memory access operation, a series of operations occur within semiconductor device 300, wherein a later operation sometimes depends on completing the processing of information from a previous operation in the series. For example, in response to receiving an ACT command, command decoder 304 may provide a RASACT signal to bank logic 310. After a predetermined wait time, BankActive circuit 312 may generate a BankActive signal (e.g., read word line activation (RWLACT)) for activating a memory bank of the memory array.

[0051] Therefore, if the BankActive signal is not generated before it is used, the memory access operation may fail. If a delay is added to ensure that the BankActive circuit 312 has enough time to generate the BankActive signal, the downstream timing margin for the memory access operation may be reduced.

[0052] The timing of the generation of the BankActive signal is based on a combination of a predetermined internal latency and a signal propagation delay (e.g., based on the relative physical location of the associated circuits of the semiconductor device 300, and based on the physical timing characteristics of the semiconductor device 300 that are affected by PVT variations). The predetermined internal latency may be set according to an operating mode of compatible operation of the semiconductor device 300 within an installed system. However, the signal propagation delay is device-specific and may be measured and compensated within the semiconductor device 300.

[0053] As an example, FIG. 4a depicts an exemplary timing diagram 400 according to an embodiment of the present disclosure, which shows a first test mode signal timing for measuring the wait time between receiving a RASACT signal from a command decoder 304 at the test circuit 320 and receiving a BankActive signal from the memory logic 310 at the test circuit 320. The semiconductor device 300 can be set to a first test mode or a second test mode based on the value of the test mode signal. At time T1, the test circuit 320 can receive a RASACT signal from the command decoder 304 at time T1. In response to receiving the RASACT signal, the process monitor controller 322 can provide a start control signal to the process monitor 324. In response to the start control signal, the process monitor 324 can start counting counter clock oscillations. In the first test mode (e.g., a test mode signal having a first value), the multiplexer 314 can provide a BankActive signal to the test circuit 320. Thus, at time T2, the test circuit 320 may receive the BankActive signal from the multiplexer 314, and in response, the process monitor controller 322 may provide a stop control signal to the process monitor 324. In response to the stop control signal, the process monitor 324 may stop counting clock oscillations, and may process the count value to provide a delay value indicating the BankActive signal wait time. The time indicating the BankActive signal wait time between T1 and T2 includes the predetermined wait time plus the signal propagation delay. PVT variations may cause differences in signal propagation delays between semiconductor devices, which may cause significant delay differences in high-speed memory applications.

[0054] FIG. 4 b depicts an exemplary timing diagram 401 according to one embodiment of the present disclosure, which shows a second test mode signal timing for measuring a signal propagation delay between receiving a RASACT signal from the command decoder 304 at the test circuit 320 and receiving a RASACTWire signal from the memory bank logic 310 at the test circuit 320. At time T1, the test circuit 320 may receive the RASACT signal from the command decoder 304. In response to receiving the RASACT signal, the process monitor controller 322 may provide a start control signal to the process monitor 324. In response to the start control signal, the process monitor 324 may start counting counter clock oscillations. In the second test mode (e.g., a test mode signal having a second value), the RASACTWire signal may be routed through the memory bank logic 310 and may be provided to the test circuit 320 via the multiplexer 314. Therefore, at time T2, the test circuit 320 may receive the RASACTWire signal from the multiplexer 314, and in response, the process monitor controller 322 may provide a stop control signal to the process monitor 324. In response to the stop control signal, the process monitor 324 may stop counting clock oscillations and may process the count value to provide a delay value indicative of a signal propagation delay. The time between T1 and T2 indicates the signal propagation delay.

[0055] In some instances, the process monitor 324 can set the delay value to the raw count value. In other instances, the process monitor 324 can derive the delay value from the raw count value. The signal propagation path from the command decoder 304 to the memory logic 310 and from the memory logic 310 to the test circuit 320 may cause the propagation delay indicated by the raw count value to be greater than (e.g., approximately twice) the signal propagation delay from the command decoder 304 to the test circuit 320. In some instances, the process monitor 324 can adjust the raw count value to determine the delay value. For example, the process monitor 324 can reduce the raw count value from the second mode to compensate for the additional delay path. The process monitor 324 can adjust the raw count value based on the difference between the distance between the command decoder 304 and the memory logic circuit 310 and the distance between the memory logic circuit 310 and the test circuit 320. In one instance, the distance between the command decoder 304 and the memory logic circuit 310 can be approximately equal to the distance between the memory logic circuit 310 and the test circuit 320. In this example, the process monitor 324 can divide the raw count value by two to provide the delay value. In other examples, the tester can convert the raw count value to a delay value.

[0056] Based on the determined signal propagation delay, the tester (or test circuit 320) can configure the semiconductor device 300 to store delay parameters, which are used to select delay values ​​to be used during memory access operations. The delay parameters can be permanently stored in a programmable circuit (not shown), such as a fuse memory bank or an anti-fuse memory bank. By individually configuring delay values ​​specific to the physical characteristics of the semiconductor device 300, memory access operation failures can be reduced.

[0057] From the foregoing it will be appreciated that although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not to be restricted, except as in the appended claims.

Claims

1. A device comprising: a memory cell array; A memory bank logic circuit is arranged adjacent to the memory cell array; and a peripheral circuit disposed remote from each of the memory cell array and the bank logic circuit, wherein the peripheral circuit includes a command decoder connected to the bank logic circuit via a first bus and a test circuit connected to the command decoder via a second bus; wherein, in a test operation mode, the command decoder is configured to transmit a test command signal to the test circuit via the second bus; and Wherein, in the test operation mode, the test circuit is configured to determine a delay value based on a time difference between receiving the test command signal received from the command decoder via the third bus and receiving the test command signal via the second bus. 2 . The device of claim 1 , wherein in a normal operation mode, the command decoder is further configured to transmit an internal command signal to the memory bank logic circuit through the first bus.

3. The apparatus of claim 2, wherein the bank logic circuit comprises logic circuitry configured to cause activation of a bank of a memory array in response to the internal command signal in the normal operating mode.

4. The apparatus of claim 1 , wherein in the test operation mode, the test circuit includes a process monitor configured to start counting oscillations of a counting clock in response to receiving the test command signal received via the second bus and to stop counting oscillations of the counting clock in response to receiving the test command signal received via the third bus to provide a count value, wherein the delay value is based on the count value. 5 . The apparatus of claim 4 , wherein the test circuit comprises a ring oscillator configured to provide the count clock.

6. The apparatus of claim 4, wherein in the test mode of operation, the process monitor is configured to provide the delay value as half of the count value. 7 . The apparatus of claim 1 , wherein the test circuit is configured to provide the delay value to indicate an internal signal propagation delay between the command decoder and the bank logic circuit when the output signal is a RASACTWire signal.

8. The apparatus of claim 2, wherein the bank logic circuit comprises a multiplexer configured to selectively provide one of the internal command signal or the test command signal as an output signal based on whether a mode of operation is a normal operation mode or a test operation mode.

9. The apparatus of claim 1, further comprising a fuse memory bank or an anti-fuse memory bank configured to store a delay parameter based on the delay value in response to a program command.

10. The apparatus of claim 1, further comprising a data terminal configured to provide the delay value to a data bus.

11. A device comprising: A test circuit is configured to measure a signal propagation delay between the command decoder and the bank logic circuit based on a time between receiving a test command signal directly from the command decoder and receiving the test command signal routed through the bank logic circuit.

12. The apparatus of claim 11 , wherein the test circuit is configured to measure the signal propagation delay to provide a count value by counting oscillations of a count clock from a time when the test command signal is received to a time when the test command signal routed through the memory body logic circuit is received, wherein the signal propagation delay is based on the count value.

13. The apparatus of claim 12 , wherein the test circuit is configured to adjust the count value based on a difference between a first distance between the command decoder and the memory logic circuit and a second distance between the memory logic circuit and the test circuit to measure the signal propagation delay.

14. The apparatus of claim 12, wherein the test circuit is configured to divide the count value by two to measure the signal propagation delay.

15. A method comprising: In test mode: providing a test command signal to a memory bank logic circuit and a test circuit of a semiconductor device; providing the test command signal from the bank logic circuit to the test circuit; determining a delay value based on a time between receiving the test command signal from a command decoder and receiving the test command signal from the bank logic circuit; and The delay value is provided at an output of the semiconductor device.

16. The method of claim 15 , further comprising counting oscillations of a count clock from a time when the test command signal is received from the command decoder to a time when the test command signal is received from the memory body logic circuit to provide a count value, wherein the delay value is based on the count value.

17. The method of claim 16, further comprising adjusting the count value to determine the delay value based on a difference between a first distance between the command decoder and the bank logic circuit and a second distance between the bank logic circuit and the test circuit.

18. The method of claim 16, further comprising dividing the count value by two to determine the delay value.

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