Photoelectric conversion device, photoelectric conversion system, and movable body

Abstract

The present application provides a photoelectric conversion device, a photoelectric conversion system, and a movable body. The photoelectric conversion device includes a pad, a first protection circuit provided on a first semiconductor substrate, and a second protection circuit provided on a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are laminated, the first semiconductor substrate includes a plurality of photoelectric conversion units each of which receives incident light and generates signal charge, and the second semiconductor substrate includes at least one signal processing circuit which processes an input signal based on the generated signal charge. The pad receives a power supply voltage as an input from outside the photoelectric conversion device. In a plan view, at least one of the first protection circuit and the second protection circuit is provided outside a region in which the pad is provided. At least one of the first protection circuit and the second protection circuit is connected to the pad.

Description

Technical Field

[0001] This invention relates to photoelectric conversion devices, photoelectric conversion systems, and movable bodies. Background Technology

[0002] In the field of photoelectric conversion devices, miniaturization is a key trend. With miniaturization, for example, the gate oxide film in metal-oxide-semiconductor (MOS) transistors is becoming thinner. This reduces the voltage at which dielectric breakdown occurs in MOS transistors. As a means to reduce this dielectric breakdown, structures including protection circuits are known.

[0003] By increasing the area of ​​the protection circuit, the load on the photoelectric conversion device due to electrostatic discharge can be reduced. However, increasing the area occupied by the protection circuit reduces the area of ​​other circuits (internal circuits installed in the photoelectric conversion device). Alternatively, if the area of ​​the internal circuits is ensured, the chip area increases. According to the technology discussed in Japanese Patent Application Publication No. 2012-033878, the protection circuit is arranged in an area overlapping with the pads from which voltage is supplied from the outside in a plan view. This allows for an increase in the area of ​​the protection circuit while suppressing an increase in the chip area.

[0004] When the protection circuit is positioned in an area overlapping with the pads in a plan view, it experiences stress during wire bonding on the pads. In this situation, the characteristics of the protection circuit (including electrostatic resistance) change. As a result, electrostatic noise can interfere with the signal generated by the photoelectric converter or damage internal circuitry, thus reducing the operational reliability of the photoelectric converter. Summary of the Invention

[0005] According to one aspect of the present invention, a photoelectric conversion device is provided, wherein a first semiconductor substrate and a second semiconductor substrate are stacked in the photoelectric conversion device, the first semiconductor substrate including a plurality of photoelectric conversion units each configured to receive incident light and generate signal charge, and the second semiconductor substrate including at least one signal processing circuit configured to process an input signal based on the generated signal charge, the photoelectric conversion device including: a pad configured to receive a power supply voltage as an input from outside the photoelectric conversion device; a first protection circuit disposed on the first semiconductor substrate; and a second protection circuit disposed on the second semiconductor substrate, wherein, in a plan view, at least one of the first protection circuit and the second protection circuit is disposed outside the area where the pad is disposed, and wherein at least one of the first protection circuit and the second protection circuit is connected to the pad.

[0006] Other features of the invention will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0007] Figure 1 It is an equivalent circuit diagram according to the first exemplary embodiment.

[0008] Figure 2A and Figure 2B It is a plan layout diagram according to the first exemplary embodiment.

[0009] Figure 3A and Figure 3B It is a plan layout diagram according to the first exemplary embodiment.

[0010] Figure 4 This is a cross-sectional schematic diagram according to the first exemplary embodiment.

[0011] Figure 5 This is a cross-sectional schematic diagram according to the first exemplary embodiment.

[0012] Figure 6A and Figure 6B It is a plan layout diagram according to the second exemplary embodiment.

[0013] Figure 7A and Figure 7B It is a plan layout diagram according to the second exemplary embodiment.

[0014] Figure 8 This is a cross-sectional schematic diagram according to the second exemplary embodiment.

[0015] Figure 9 This is a cross-sectional schematic diagram according to the second exemplary embodiment.

[0016] Figure 10A and Figure 10B It is a plan layout diagram according to the third exemplary embodiment.

[0017] Figure 11 This is a cross-sectional schematic diagram according to a third exemplary embodiment.

[0018] Figure 12A and Figure 12B It is a plan layout diagram according to the fourth exemplary embodiment.

[0019] Figure 13 This is a cross-sectional schematic diagram according to the fourth exemplary embodiment.

[0020] Figure 14 This is an equivalent circuit diagram according to the fifth exemplary embodiment.

[0021] Figure 15A and Figure 15B It is a plan layout diagram according to the fifth exemplary embodiment.

[0022] Figure 16This is a cross-sectional schematic diagram according to the fifth exemplary embodiment.

[0023] Figure 17 This is a cross-sectional schematic diagram according to the fifth exemplary embodiment.

[0024] Figure 18 This is an equivalent circuit diagram according to the sixth exemplary embodiment.

[0025] Figure 19A and Figure 19B This is a plan view according to the sixth exemplary embodiment.

[0026] Figure 20 This is a cross-sectional schematic diagram according to the sixth exemplary embodiment.

[0027] Figure 21 This is an equivalent circuit diagram according to the seventh exemplary embodiment.

[0028] Figure 22A and Figure 22B This is a plan layout diagram according to the seventh exemplary embodiment.

[0029] Figure 23A and Figure 23B This is a plan layout diagram according to the seventh exemplary embodiment.

[0030] Figure 24 This is a cross-sectional schematic diagram according to the seventh exemplary embodiment.

[0031] Figure 25 This is a schematic diagram according to the eighth exemplary embodiment.

[0032] Figure 26A and Figure 26B This is a plan layout diagram according to the eighth exemplary embodiment.

[0033] Figure 27A and Figure 27B This is a plan layout diagram according to the eighth exemplary embodiment.

[0034] Figure 28 This is a cross-sectional schematic diagram according to the eighth exemplary embodiment.

[0035] Figure 29 This is a diagram illustrating the construction of a photoelectric conversion system according to a ninth exemplary embodiment.

[0036] Figure 30A and Figure 30B This is a diagram illustrating the construction and operation of a photoelectric conversion system in a movable body according to a tenth exemplary embodiment. Detailed Implementation

[0037] If electrostatic noise gets mixed into the signal generated by the photoelectric conversion device or the internal circuitry is damaged, the operational reliability of the photoelectric conversion device will decrease. The following disclosure relates to techniques for enhancing the operational reliability of photoelectric conversion devices.

[0038] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0039] In the following exemplary embodiments, the imaging device will be primarily described as an example of a photoelectric conversion device. However, the photoelectric conversion device according to the exemplary embodiments is not limited to an imaging device, and the exemplary embodiments can also be applied to other types of photoelectric conversion devices. For example, the exemplary embodiments can be applied to a ranging device (a ranging device using focus detection or time-of-flight (TOF)) or a photometer (a device for measuring the amount of incident light).

[0040] Furthermore, the conductivity types of the semiconductor regions and wells, as well as the dopants to be implanted, described in the following exemplary embodiments are merely examples. The conductivity types and dopants are not limited to those described in the exemplary embodiments. The conductivity types and dopants can be appropriately varied according to those described in the exemplary embodiments, and with such variations, the potentials of the semiconductor regions and wells will also be appropriately varied.

[0041] The conductivity type of the transistor to be described in the following exemplary embodiments is merely an example, and the conductivity type is not limited to the conductivity type described in the exemplary embodiments. The conductivity type can be appropriately changed from the conductivity type described in the exemplary embodiments, and with such change, the potentials of the gate, source, and drain of the transistor are also appropriately changed.

[0042] For example, when a transistor is used as a switch, the low-level and high-level potentials supplied to the gate, as described in the exemplary embodiments, are reversed as the conductivity type changes. Furthermore, the conductivity type of the semiconductor region to be described in the following exemplary embodiments is merely an example, and the conductivity type is not limited to that described in the exemplary embodiments. The conductivity type can be appropriately changed according to the conductivity type described in the exemplary embodiments, and with this change, the potential of the semiconductor region also changes appropriately.

[0043] In the following text, reference will be made to Figures 1 to 5 The structure of a photoelectric conversion device according to a first exemplary embodiment of the present disclosure is described.

[0044] Figure 1 This is an equivalent circuit diagram of the electrostatic discharge protection circuit according to this exemplary embodiment. Diodes 101 and 102 are connected to internal circuit 103. Diodes 101 and 102 are also connected to pad 100.

[0045] The cathode of diode 101 is connected to the power supply voltage node VDD. The anode of diode 101 and the cathode of diode 102 are connected to pad 100 and internal circuit 103. The anode of diode 102 is connected to the power supply voltage node GND. Typically, the potential of power supply voltage node GND is ground. Typically, the potential of power supply voltage node VDD is positive.

[0046] The internal circuitry 103 includes, for example, a driver circuit for amplifying signals input from an external source. The internal circuitry 103 may also include circuitry other than the driver circuitry. Additionally, besides... Figure 1 In addition to the circuit elements shown, circuit elements such as resistors or capacitors may also be included.

[0047] exist Figure 1 In the illustrated configuration, if a voltage of the power supply voltage node VDD is applied to pad 100, current will not flow to diode 101 or diode 102. On the other hand, if a positive voltage greater than the potential of the power supply voltage node VDD is applied to pad 100 due to electrostatic discharge, current flows to the power supply voltage node VDD via diode 101. If a negative voltage is applied to pad 100, current flows from the power supply voltage node GND to pad 100 via diode 102. Through this operation, even if electrostatic discharge is applied to pad 100, breakdown of the internal circuit 103 can be suppressed.

[0048] Figure 2A and Figure 2B as well as Figure 3A and Figure 3B This is a plan view of an electrostatic discharge (ESD) protection circuit according to this exemplary embodiment. Figure 2A , Figure 2B , Figure 3A and Figure 3B In, it has the same Figure 1 Components with the same function as those shown are assigned the same reference numerals. In the photoelectric conversion device according to this exemplary embodiment, Figure 2A The first component 202 shown and Figure 2B The second component 203 shown is joined together. The first component 202 and the second component 203 are each typically a chip including a semiconductor substrate and at least one wiring layer. Figure 2A and Figure 2B middle, Figure 1 A portion of the circuit elements shown are arranged in a distributed manner in both the first component 202 and the second component 203. For example, by respectively in Figure 2A and Figure 2B The combination of diodes 101A and 101B shown in the figure forms a... Figure 1 The diode 101 is shown in the diagram. Similarly, by respectively in Figure 2A and Figure 2B The combination of diodes 102A and 102B shown in the figure forms a... Figure 1 Diode 102 is shown in the image. Regarding... Figure 2A and Figure 2B The pad 100 shown may be an opening in one of the first component 202 and the second component 203, and the pad 100 may be located only in the other component. Alternatively, the pad 100 may be located in both the first component 202 and the second component 203. In this case, the pad 100 in one of the first component 202 and the second component 203 is connected to the outside, and the pad 100 in the other component is connected via a through-hole connector to the pad 100 in the mating component to be engaged.

[0049] The first component 202 and the second component 203 are joined such that the corresponding pads 100 of the first component 202 and the second component 203 overlap in a plan view. A plurality of pads 100 are arranged in the photoelectric conversion device. The plurality of pads 100 include: pads for outputting signals generated by the internal circuitry 103 (output pads); and pads for inputting voltages for driving the internal circuitry 103 (input pads).

[0050] exist Figure 2A and Figure 2B In the layout shown, a portion of the internal circuit 103A, diodes 101A and 102A, and pad 100 are arranged in a straight line. From another perspective, it can be said that diodes 101A, 102A, and pad 100 are arranged along a direction intersecting the direction connecting diode 101A and internal circuit 103A. A portion of the internal circuit 103B, diodes 101B and 102B, and pad 100 are arranged in a straight line. From another perspective, it can be said that diodes 101B and 102B, and pad 100 are arranged along a direction intersecting the direction connecting diode 101B and internal circuit 103B.

[0051] exist Figure 3A and Figure 3B In the layout shown, diodes 101A, 102A, and pad 100 are arranged along a direction that intersects the direction connecting diode 101A and internal circuit 103A.

[0052] exist Figure 2A and Figure 2B The layout shown and Figure 3A and Figure 3BIn the illustrated layouts, pads 100, diodes 101A and 102A, internal circuitry 103A, VDD power routing 104, and GND routing 105 are formed in the first component 202. Pads 100, diodes 101B and 102B, and internal circuitry 103B are formed in the second component 203. In this exemplary embodiment, VDD power routing 104 and GND routing 105 are arranged in the first component 202. As another example, VDD power routing 104 and GND routing 105 may be arranged in the second component 203. Alternatively, both VDD power routing 104 and GND routing 105 may be arranged in each of the first component 202 and the second component 203.

[0053] exist Figure 2A and Figure 2B In the layout shown, diode 101A is positioned closer to pad 100 than diode 102A. Diode 101B is positioned closer to pad 100 than diode 102B. The arrangement order is not limited to this. Diode 102A can be positioned closer to pad 100 than diode 101A. Diode 102B can be positioned closer to pad 100 than diode 101B.

[0054] In addition, Figure 3A and Figure 3B In the layout shown, diodes 101A, 101B, 102A and 102B are arranged between multiple pads 100. Figure 3A and Figure 3B The arrangement order of diodes 101A and 101B and the arrangement order of diodes 102A and 102B in the shown configuration can be reversed.

[0055] Figure 4 It is along Figure 2A , Figure 2B , Figure 3A and Figure 3B The cross-sectional view of the photoelectric conversion device is shown by the dashed line A-A'.

[0056] exist Figure 4 In, it has the same Figures 1 to 3BComponents with the same function are assigned the same reference numerals. The first component 202 includes a first substrate 200 and a wiring layer. The second component 203 includes a second substrate 201 and a wiring layer. The first substrate 200 and the second substrate 201 are, for example, silicon semiconductor substrates. Circuit elements constituting the internal circuit 103, such as MOS transistors, resistive elements, capacitive elements, and photodiodes, are formed in each of the first substrate 200 and the second substrate 201. The first component 202 and the second component 203 are electrically connected to each other at a bonding portion 204. Additionally, the first component 202 includes wiring layers 205 and 206, and contact layers 208, 209, 210, 213, and 214 including multiple contacts or through-holes. Similarly, the second component 203 includes a wiring layer 207, and contact layers 211, 212, and 215 including multiple contacts or through-holes.

[0057] The bonding portion 204, wiring layers 205 to 207, and contact layers 208 to 215 are formed of a metallic material such as copper, aluminum, tungsten, or titanium. An interlayer insulating film is formed between the wiring layers and is formed, for example, of any combination of one or more types of films selected from silicon oxide, silicon nitride, and silicon carbide films. The number of wiring layers included in each of the first component 202 and the second component 203 can be arbitrarily set. In this exemplary embodiment, the first component 202 includes two wiring layers, and the second component 203 includes one wiring layer.

[0058] Furthermore, in this exemplary embodiment, diodes 101A and 102A are formed in the first substrate 200, and diodes 101B and 102B are formed in the second substrate 201. Diode 101A is a component constituting part of diode 101, and the anode region of diode 101A is as follows: Figure 4 As shown. Diode 102A is a component constituting part of diode 102, and the cathode region of diode 102A is as follows. Figure 4 As shown. Diode 101B is a component constituting part of diode 101, and the anode region of diode 101B is as follows. Figure 4 As shown. Diode 102B is a component constituting part of diode 102, and the cathode region of diode 102B is as follows. Figure 4 As shown.

[0059] The anode region of diode 101A is formed by providing a p-type semiconductor region 218 on an n-type semiconductor region 217 formed on the first substrate 200. The anode region of diode 101B is formed by providing a p-type semiconductor region 223 on an n-type semiconductor region 222 formed on the second substrate 201. The cathode region of diode 102A is formed by providing an n-type semiconductor region 220 on a p-type semiconductor region 219 formed on the first substrate 200. The cathode region of diode 102B is formed by providing an n-type semiconductor region 225 on a p-type semiconductor region 224 formed on the second substrate 201. A device isolation region 216 is formed between diodes 101A and 102A. A device isolation region 221 is formed between diodes 101B and 102B.

[0060] Diode 101A is connected to pad 100 via wiring layers 205 and 206 and contact layers 209 and 213. Diode 102A is connected to pad 100 via wiring layers 205 and 206 and contact layers 208 and 213. Diode 101B is connected to pad 100 via wiring layers 206 and 207, bonding portion 204, and contact layers 212, 215, and 214. Diode 102B is connected to pad 100 via wiring layers 206 and 207, bonding portion 204, and contact layers 212, 215, and 214. Furthermore, internal circuitry 103A is connected to pad 100 via wiring layers 205 and 206 and contact layers 210 and 213. In this exemplary embodiment, the gate 226 of the MOS transistor is connected to contact layer 210. As another example, contact layer 210 may be connected to the source or drain region of the MOS transistor, or to circuit elements outside the MOS transistor. In addition, the contact layer 210 can be connected to the internal circuit 103B.

[0061] Figure 5 It is along Figure 2A , Figure 2B , Figure 3A and Figure 3B A schematic diagram of the cross-section of the photoelectric conversion device, intercepted by the dashed line B-B'. (See diagram below.) Figure 4 As shown, the anode region of diode 101A is connected to pad 100 via wiring layers 205 and 206 and contact layers 209 and 213. The cathode region of diode 101A is formed by providing an n-type semiconductor region 308 on an n-type semiconductor region 217. The cathode region of diode 101A is connected to VDD power wiring 104 via contact layer 303. The anode region of diode 101B is connected to pad 100 via wiring layers 206 and 207, bonding portion 204, and contact layers 212, 215, and 214. Diodes 101 and 102 overlap with the wiring of wiring layer 205 in the plan view.

[0062] In the cathode region of diode 101B, an n-type semiconductor region 311 is formed on an n-type semiconductor region 222. The cathode region of diode 101B is connected to VDD power wiring 104 via wiring layers 301 and 302, contact layers 304 to 307, and a bonding portion 30. In this exemplary embodiment, n-type semiconductor regions 308 and 311 are formed in the cathode regions of diodes 101A and 101B, respectively. As another example, the contact layers may be connected to n-type semiconductor regions 217 and 222 instead of p-type semiconductor regions 218 and 223. Additionally, in this exemplary embodiment, element isolation regions 309 and 319 are formed to separate the n-type semiconductor region and the p-type semiconductor region. The separation method is not limited to this. Instead of forming element isolation regions 309 and 319, a pn-bonded isolation region may be formed to bond the n-type semiconductor region and the p-type semiconductor region. Alternatively, the element isolation regions 309 and 319 may be provided on the first substrate 200 or the second substrate 201. Figure 5 Structures such as silicide structures are not shown.

[0063] In the photoelectric conversion device according to this exemplary embodiment, the electrostatic discharge (ESD) protection circuit is arranged on each of the two stacked semiconductor substrates. With this configuration, compared to arranging the ESD protection circuit only on one of the two substrates, the photoelectric conversion device according to this exemplary embodiment has the following advantages: it increases the area of ​​the ESD protection circuit while suppressing the increase in chip area. Furthermore, in this exemplary embodiment, the ESD protection circuit is arranged in an area that does not overlap with the pad 100 in a plan view. Therefore, it is less likely that the ESD protection circuit will receive stress generated through wiring connections with the pad 100, and the occurrence of ESD protection circuit failures is suppressed.

[0064] Although a stacked structure having two semiconductor substrates has been described in this exemplary embodiment, a larger number of semiconductor substrates can be stacked.

[0065] In the following text, reference will be made to Figures 6A to 9 A photoelectric conversion device according to a second exemplary embodiment of the present disclosure is described. In the following description, the differences from the first exemplary embodiment will be mainly described, and parts similar to the first exemplary embodiment may be omitted.

[0066] The equivalent circuit of the electrostatic protection circuit according to this exemplary embodiment can be compared with the reference circuit. Figure 1 The equivalent circuit described in the first exemplary embodiment is the same. Figure 6A and Figure 6B as well as Figure 7A and Figure 7B This is a plan view of an electrostatic discharge (ESD) protection circuit according to this exemplary embodiment. Figure 6A , Figure 6B , Figure 7A and Figure 7B In, it has a reference Figures 1 to 5 Components with the same function as the described components are assigned to... Figures 1 to 5 The figure labels assigned in the figure are the same as those in the figure labels.

[0067] In this exemplary embodiment, by joining Figure 6A The first component 402 shown and Figure 6B The second component 403 shown forms a photoelectric conversion device. Similar to the first exemplary embodiment, Figure 6A The first component 402 shown and Figure 6B The second component 403 shown is joined in a manner in which the corresponding pads 100 overlap in the plan view.

[0068] Also in Figure 6A and Figure 6B as well as Figure 7A and Figure 7B In the first component 402, pads 100, diodes 101, internal circuitry 103A, VDD power supply wiring 104, and GND wiring 105 are formed. In the second component 403, pads 100, diodes 102, and internal circuitry 103B are formed. In this exemplary embodiment, the VDD power supply wiring 104 and GND wiring 105 are arranged in the first component 402. Alternatively, the VDD power supply wiring 104 and GND wiring 105 may be arranged in the second component 403. Furthermore, both the VDD power supply wiring 104 and GND wiring 105 may be arranged in each of the first component 402 and the second component 403.

[0069] exist Figure 6A and Figure 6B In the planar layout diagram shown, diodes 101 and 102 are positioned between pad 100 and internal circuits 103A and 103B, respectively. Figure 7A and Figure 7B In the planar layout shown, diodes 101 and 102 are arranged between pads 100.

[0070] Figure 8 It is along Figure 6A , Figure 6B , Figure 7A and Figure 7B A schematic diagram of the cross-section of the photoelectric conversion device, intercepted by the dashed line C-C'. Figure 8 In, it has a reference Figures 1 to 7B Components with the same function as the described components are assigned to... Figures 1 to 7BThe same reference numerals are assigned to the figures in the figures. In the photoelectric conversion device according to this exemplary embodiment, a first component 402 including a first substrate 400 and a second component 403 including a second substrate 401 are joined together. The first component 402 and the second component 403 are electrically connected to each other at a joining portion 404. The first component 402 includes wiring layers 405 and 406 and contact layers 408, 409, 411 and 412. The second component 403 includes wiring layer 407 and contact layers 410 and 413.

[0071] In this exemplary embodiment, diode 101 is formed on the first substrate 400 and diode 102 is formed on the second substrate 401, but the arrangement positions can be reversed. Figure 8 The anode region of diode 101 and the cathode region of diode 102 are shown. In the anode region of diode 101, a p-type semiconductor region 415 is formed on an n-type semiconductor region 414 formed on the first substrate 400. In the cathode region of diode 102, an n-type semiconductor region 417 is formed on a p-type semiconductor region 416 formed on the second substrate 401. A device isolation region 418 is disposed adjacent to the n-type semiconductor region 414. In one embodiment, the device isolation region 418 is formed as shallow trench isolation (STI). The device isolation region 418 can be formed by a local oxidation of silicon (LOCOS) process or a deep trench isolation process.

[0072] Diode 101 is connected to pad 100 via wiring layers 405 and 406 and contact layers 408 and 411. Diode 102 is connected to pad 100 via wiring layers 407 and 406, junction portion 404, and contact layers 410, 412, and 413. Internal circuit 103A is connected to pad 100 via wiring layers 405 and 406 and contact layers 409 and 411. Contact layer 409 is connected to the gate electrode 419 of the transistor.

[0073] Figure 9 It is along Figure 6A , Figure 6B , Figure 7A and Figure 7BThe diagram shows a cross-sectional view of the photoelectric conversion device, captured by the dashed line D-D'. The cathode region of diode 101 is formed by providing an n-type semiconductor region 506 on an n-type semiconductor region 414. This cathode region is connected to the VDD power supply wiring 104 via a contact layer 502. The anode region of diode 102 is formed by providing a p-type semiconductor region 508 on a p-type semiconductor region 416. This anode region is connected to the GND wiring 105 via wiring layers 501, contact layers 503, 504, and 505, and a bonding portion 500. Component isolation region 507 is disposed adjacent to n-type semiconductor region 414. Component isolation region 509 is disposed adjacent to n-type semiconductor region 417. Component isolation regions 507 and 509 are formed as shallow trench isolation (STI). Component isolation regions 507 and 509 can be formed using a LOCOS process or a deep trench isolation process.

[0074] In the photoelectric conversion device according to this exemplary embodiment, diode 101 is disposed on one of two stacked substrates, while diode 102 is disposed on the other stacked substrate. Using this configuration, for example, in this exemplary embodiment, for example, [the following can be omitted]. Figure 4 The component isolation regions 216 and 221 are shown. Therefore, the circuit area allocated to component isolation regions 216 and 221 in the first exemplary embodiment can be allocated to the electrostatic discharge (ESD) protection circuit. Therefore, the photoelectric conversion device according to this exemplary embodiment has the effect of further increasing the circuit area of ​​the ESD protection circuit.

[0075] In the following text, reference will be made to Figures 10A to 11 The structure of the photoelectric conversion device according to the third exemplary embodiment is described. The equivalent circuit diagram of the electrostatic protection circuit according to the third exemplary embodiment is shown. Figure 1 Similar to the Chinese.

[0076] Figure 10A and Figure 10B This is a plan view of an electrostatic discharge protection circuit according to a third exemplary embodiment. Figures 1 to 9 The same components shown are assigned the same reference numerals, and their descriptions will be omitted. Figure 10A and Figure 10B In the diagram, the arrangement of pad 100, diodes 101A, 101B, 102A and 102B, internal circuits 103A and 103B, VDD power supply wiring 104, and GND wiring 105 is... Figure 2A and Figure 2B The arrangement shown is similar. As another example, a similar arrangement could be adopted. Figure 3A and Figure 3B The arrangement shown is similar to the one depicted. Additionally, as... Figure 6A and Figure 6B as well as Figure 7A and Figure 7BAs shown, diodes 101 and 102 can be arranged in the first component 602 and the second component 603, respectively. Diodes 101C and 102C are portions of diodes 101 and 102, respectively. In this exemplary embodiment, diodes 101C and 102C are arranged in the first component 602 and formed in the area overlapping with pad 100 in a plan view. Figure 10A and Figure 10B In the plan view, diodes 101C and 102C are arranged at positions overlapping with pad 100, but the arrangement is not limited to this. For example, diodes 101C and 102C may each partially overlap with pad 100 in the plan view, and other portions of diodes 101C and 102C may be located at positions not overlapping with pad 100.

[0077] Figure 11 It is along Figure 10A and Figure 10B A schematic diagram of the cross-section of the photoelectric conversion device, intercepted by the dashed line E-E'. Figure 11 In, with Figures 1 to 10B The same parts shown are assigned the same reference numerals, and their descriptions will be omitted.

[0078] In the photoelectric conversion device according to the third exemplary embodiment, a first component 602 including a first substrate 600 and a second component 603 including a second substrate 601 are bonded together. The first component 602 and the second component 603 are electrically connected to each other at a bonding portion 604. The first component 602 includes wiring layers 605 and 606 and contact layers 607 to 609. Diodes 101A, 102A, 101C, and 102C are formed in the first substrate 600, and diodes 101B and 102B are formed in the second substrate 601. The structure and connection relationship of diodes 101A, 102A, 101B, and 102B are consistent with reference to [reference]. Figure 4 The diodes described are similar. In the anode region of diode 101C, a p-type semiconductor region 611 is formed on the n-type semiconductor region 610 formed on the first substrate 600. In the cathode region of diode 102C, an n-type semiconductor region 613 is formed on the p-type semiconductor region 612 formed on the first substrate 600. Diode 101C is connected to pad 100 via wiring layers 605 and 606 and contact layers 607 and 609. Diode 102C is connected to pad 100 via wiring layers 605 and 606 and contact layers 608 and 609. In this example, diodes 101C and 102C are arranged in the region overlapping with pad 100 in a plan view. Furthermore, the cathode region of diode 101C is connected to VDD power wiring 104, and the anode region of diode 102C is connected to GND wiring 105. Figure 11 Not shown in the image.

[0079] In the structure according to this exemplary embodiment, in addition to the structure according to the first exemplary embodiment, diodes 101C and 102C are also arranged in the region overlapping with pad 100. This configuration allows for a further increase in the area of ​​the electrostatic discharge (ESD) protection circuit. Diodes 101C and 102C may change their characteristics or ESD resistance due to the stress received when forming wire bonds on pad 100. However, in this exemplary embodiment, diodes 101A, 101B, 102A, and 102B, located in positions not overlapping with pad 100 in the plan view, are less likely to be affected by the formation of wire bonds. Therefore, diodes 101A, 101B, 102A, and 102B can be stably used as the ESD protection circuit. Therefore, in the photoelectric conversion device according to this exemplary embodiment, the entire ESD protection circuit can operate stably.

[0080] In the following text, reference will be made to Figure 12A , Figure 12B and Figure 13 The structure of a photoelectric conversion device according to a fourth exemplary embodiment of the present disclosure is described.

[0081] The equivalent circuit diagram of the electrostatic protection circuit according to the fourth exemplary embodiment and Figure 1 Similar to that in [the text].

[0082] Figure 12A and Figure 12B This is a plan view of an electrostatic discharge protection circuit according to a fourth exemplary embodiment. Figures 1 to 11 Components shown are assigned the same reference numerals, and their descriptions will be omitted. In this exemplary embodiment, pads 100 are formed in the second component 703. No openings for pads 100 are formed in the first component 702.

[0083] The arrangement of diodes 101A, 101B, 102A and 102B, internal circuits 103A and 103B, VDD power supply wiring 104 and GND wiring 105 and Figure 2A and Figure 2B The arrangement shown is similar, but it can be made to resemble... Figure 3A and Figure 3B The arrangement shown. Additionally, as... Figure 6A and Figure 6B and Figure 7A and Figure 7B As shown, diodes 101 and 102 can be arranged in the first component 702 and the second component 703, respectively.

[0084] Figure 13 It is along Figure 12A and Figure 12B The cross-sectional diagram of the photoelectric conversion device is shown by the dashed line F-F'.

[0085] exist Figure 13 In, with Figures 1 to 12B Components shown are assigned the same reference numerals, and their descriptions will be omitted. In the photoelectric conversion device according to the fourth exemplary embodiment, a first component 702 including a first substrate 700 and a second component 703 including a second substrate 701 are bonded together. The first component 702 and the second component 703 are electrically connected to each other at bonding portions 704 and 705. The first component 702 includes wiring layers 706 and 707 and contact layers 709 to 712, and the second component 703 includes wiring layer 708 and contact layers 713 to 715. The structures of diodes 101A, 102A, 101B, and 102B are similar. Figure 4 The structure shown.

[0086] Diode 101A is connected to pad 100 via wiring layers 706 to 708, junction 704, and contact layers 710 to 713. Diode 102A is connected to pad 100 via wiring layers 706 to 708, junction 704, and contact layers 709 and 711 to 713. Diode 101B is connected to pad 100 via wiring layer 708 and contact layer 715. Diode 102B is connected to pad 100 via wiring layer 708 and contact layer 714. Additionally, similar to... Figure 5 In the configuration shown, diodes 101A and 101B are connected to the VDD power supply line 104. Similarly, diodes 102A and 102B are connected to the GND line 105.

[0087] In the structure according to this exemplary embodiment, a pad 100 is formed in the second member 703, and a bonding portion 705 can be arranged in the area overlapping the pad 100 in a plan view. This structure enhances the bonding strength between the first member 702 and the second member 703.

[0088] In the following text, reference will be made to Figures 14 to 17 The structure of a photoelectric conversion device according to a fifth exemplary embodiment of the present disclosure is described.

[0089] Figure 14 This is an equivalent circuit diagram of a photoelectric conversion device according to a fifth exemplary embodiment. The photoelectric conversion device according to this exemplary embodiment includes pads 800 and 801, diodes 802 to 805, and internal circuits 806 and 807. A first electrostatic discharge (ESD) protection circuit including pad 800, diodes 802 and 803, and internal circuit 806, and a second ESD protection circuit including pad 801, diodes 804 and 805, and internal circuit 807, each have... Figure 1 The circuit shown has the same construction.

[0090] Figure 15A and Figure 15B This is a plan view of an electrostatic discharge protection circuit according to a fifth exemplary embodiment of the present disclosure. Figures 1 to 14 Components shown are assigned the same reference numerals, and their descriptions will be omitted. In the photoelectric conversion device according to this exemplary embodiment, respectively in Figure 15A and Figure 15B The two components (chips) shown are bonded together. In the first component 902, pads 800, diodes 802 and 803, internal circuitry 806, VDD power supply wiring 808, and GND wiring 809 are formed. In the second component 903, pads 801, diodes 804 and 805, internal circuitry 807, VDD power supply wiring 810, and GND wiring 811 are formed.

[0091] Figure 16 It is along Figure 15A and 15B The cross-sectional diagram of the photoelectric conversion device is shown by the dashed line G-G'.

[0092] exist Figure 16 In, with Figures 1 to 15B Components shown are assigned the same reference numerals and their descriptions will be omitted. In the photoelectric conversion device according to the fifth exemplary embodiment, a first component 902 including a first substrate 900 and a second component 903 including a second substrate 901 are joined together. The first component 902 and the second component 903 are joined at a joining portion 904. The first component 902 includes wiring layers 905 and 906 and contact layers 908 to 910. The second component 903 includes wiring layer 907 and contact layers 911 and 912. In addition, diodes 802 and 803 are formed on the first substrate 900, and diodes 804 and 805 are formed on the second substrate 901. In this example, the structures of diodes 802 and 803 are similar to Figure 4 The structures of diodes 101A and 102A are shown. The structures of diodes 804 and 805 are similar. Figure 4 The structures of diodes 101B and 102B are shown. In this example, diode 802 is connected to pad 800 via wiring layers 905 and 906 and contact layers 909 and 910. Diode 803 is connected to pad 800 via wiring layers 905 and 906 and contact layers 908 and 910. Additionally, diode 804 is connected to pad 801 via wiring layer 907 and contact layer 912. Diode 805 is connected to pad 801 via wiring layer 907 and contact layer 911.

[0093] Figure 17 It is along Figure 15A and 15B A schematic diagram of the cross-section of the photoelectric conversion device, intercepted by the dashed line H-H'. Figures 1 to 16Components shown are assigned the same reference numerals, and their descriptions will be omitted. The structure of diode 802 is similar to... Figure 4 The structure of diode 101A is shown, and diode 802 is connected to VDD power supply wiring 808 via contact layer 991. The structure of diode 804 is similar. Figure 4 The structure of diode 101B is shown, and diode 804 is connected to VDD power supply wiring 810 via contact layer 992.

[0094] In the structure according to this exemplary embodiment, the pad 800 formed in the first component 902 and diodes 802 and 803 are connected to the internal circuit 806 formed in the first component 902. The pad 801 formed in the second component 903 and diodes 804 and 805 are connected to the internal circuit 807 formed in the second component 903. Furthermore, diodes 802 and 803 overlap with diodes 804 and 805 in a plan view, respectively. With this configuration, even when the first component 902 includes pad 800 and the second component 903 includes pad 801, the increase in the area of ​​the electrostatic discharge protection circuit in a plan view can be suppressed. Additionally, because the wiring length between the internal circuit and the pad can be reduced, the parasitic resistance between the internal circuit and the pad can be reduced. Therefore, electrical signals input or output via pads 800 or 801 can be transmitted to the internal circuit at high speed.

[0095] In the following text, reference will be made to Figures 18 to 20 The structure of a photoelectric conversion device according to a sixth exemplary embodiment of the present disclosure is described.

[0096] Figure 18This is an equivalent circuit diagram of a photoelectric conversion device according to a sixth exemplary embodiment. The photoelectric conversion device according to this exemplary embodiment includes a pad 1100, a diode 1101, an N-channel metal-oxide-semiconductor (NMOS) gate-grounded MOS (GGMOS) 1102, and internal circuitry 1103. The cathode 1101 of the diode is connected to the VDD power supply line, and the anode of the diode 1101 is connected to the pad 1100, the drain of the GGMOS 1102, and the internal circuitry 1103. Except that the GGMOS 1102 is connected to a node supplied with a GND potential while its gate and source are short-circuited, the GGMOS 1102 has the same structure as a typical MOS transistor. Furthermore, the drain of the GGMOS 1102 is connected to the pad 1100, the anode of the diode 1101, and the internal circuitry 1103. If a voltage is applied to the drain of the GGMOS 1102, the GGMOS 1102 remains in an operation-suppressed state (where the current flowing between the source and drain is very small and negligible) until the voltage reaches a specific voltage. If the voltage exceeds the specific voltage, current will flow between the source and drain (this is called snap-back operation).

[0097] exist Figure 1 In the equivalent circuit shown, if a negative voltage is applied to pad 100 during normal operation of the photoelectric conversion device, current flows to the power supply voltage node GND via diode 102. This can cause increased current consumption or operational failure. In the electrostatic discharge protection circuit according to this exemplary embodiment, even if a negative voltage is applied to pad 1100, GGMOS 1102 remains in an operation suppression state, and the impact on the normal operation of the photoelectric conversion device can be minimized. A GGMOS can be used instead of a diode as diode 1101. Additionally, besides... Figure 18 In addition to the circuit elements shown, circuit elements such as resistors or capacitors may also be included.

[0098] Figure 19A and Figure 19B This is a plan view of an electrostatic discharge protection circuit according to a sixth exemplary embodiment. Figures 1 to 18Components shown are assigned the same reference numerals, and their descriptions will be omitted. In this example, diode 1101A included in the first component 1202 and diode 1101B included in the second component 1203 each constitute a part of diode 1101. Furthermore, GGMOS 1102A included in the first component 1202 and GGMOS 1102B included in the second component 1203 each constitute a part of GGMOS 1102. Additionally, the photoelectric conversion device according to this exemplary embodiment includes internal circuits 1103A and 1103B, a VDD power supply wiring 1104, and a GND wiring 1105.

[0099] Figure 19A and Figure 19B The plan layout shown has the following structure, wherein, Figure 2A and Figure 2B In the planar layout shown, diodes 102A and 102B are replaced with GGMOS 1102A and 1102B, respectively. However, the construction is not limited to this. A construction can be adopted where, Figure 3A and Figure 3B , Figure 10A and Figure 10B , Figure 12A and Figure 12B or Figure 15A and Figure 15B The diodes 102A (or 803) and 102B (or 805) shown are replaced with GGMOS 1102A and 1102B, respectively.

[0100] Figure 20 It is along Figure 19A and Figure 19B The cross-sectional diagram of the photoelectric conversion device is shown by the dashed line I-I'.

[0101] exist Figure 20 In, with Figures 1 to 19BComponents shown are assigned the same reference numerals and their descriptions will be omitted. In the photoelectric conversion device according to the sixth exemplary embodiment, a first component 1202 including a first substrate 1200 and a second component 1203 including a second substrate 1201 are joined together. The first component 1202 and the second component 1203 are electrically connected to each other at joining portions 1204 and 1205. The first component 1202 includes wiring layers 1206 to 1208 and contact layers 1211 to 1218. The second component 1203 includes wiring layers 1209 and 1210 and contact layers 1219 to 1224. Diodes 1101A and GGMOS 1102A are formed on the first substrate 1200, and diodes 1101B and GGMOS 1102B are formed on the second substrate 1201. In this example, the structure and connection relationship of diodes 1101A and 1101B are as follows: Figure 4 The diodes 101A and 101B shown have similar structures and connections. GGMOS 1102A includes a gate electrode 1231, a drain region 1226, and a source region 1227 disposed on a p-type semiconductor region 1225. The drain region 1226 is connected to the pad 1100 via wiring layers 1207 and 1208 and contact layers 1213 and 1217. The gate electrode 1231 and the source region 1227 are connected to the GND wiring 1105 via contact layers 1212 and 1211, respectively. GGMOS 1102B includes a gate electrode 1232, a drain region 1229, and a source region 1230 formed on an n-type semiconductor region 1228. The drain region 1229 is connected to the pad 1100 via wiring layers 1208 and 1209, a bonding portion 1204, and contact layers 1218, 1220, and 1222. The gate electrode 1232 and the source region 1230 are connected to the GND wiring 1105 via wiring layers 1210 and 1206, bonding portion 1205 and contact layers 1215, 1216, 1219, 1223 and 1224.

[0102] In this exemplary embodiment, because the electrostatic discharge (ESD) protection circuit includes a GGMOS, ESD protection can be achieved without affecting normal operation even when a negative voltage is applied to the pad 1100. Furthermore, similar to the first to fifth exemplary embodiments described above, ESD protection circuits including GGMOS can be arranged on each of the two laminated substrates. Because the ESD protection circuit is positioned at a location that does not overlap with the pad 1100 in the plan view, the photoelectric conversion device according to this exemplary embodiment has the effect that the ESD protection circuit is less likely to be affected by wire bonding formed on the pad 1100. Additionally, similar to the first exemplary embodiment, the photoelectric conversion device also has the effect of increasing the area of ​​the ESD protection circuit.

[0103] In the following text, reference will be made to Figures 21 to 24The structure of a photoelectric conversion device according to a seventh exemplary embodiment of the present disclosure is described.

[0104] Figure 21 This is an equivalent circuit diagram of a photoelectric conversion device according to a seventh exemplary embodiment. The photoelectric conversion device according to this exemplary embodiment includes a power-clamping MOS transistor 1300. The power-clamping MOS transistor 1300 is an RC-triggered power-clamping MOS transistor. The power-clamping MOS transistor 1300 includes a series circuit (hereinafter referred to as an RC series circuit) including a resistive element 1301 and a capacitor element 1302 disposed between a VDD power line and a GND line, and a complementary metal-oxide-semiconductor (CMOS) inverter 1303 having an input terminal connected to the connection point of the resistive element 1301 and the capacitor element 1302. Additionally, the output terminal of the CMOS inverter 1303 is connected to the gate electrode of a MOS transistor 1304. In this exemplary embodiment, a single-stage CMOS inverter is shown as the CMOS inverter 1303, but multiple stages of CMOS inverters can be connected. Furthermore, an N-type MOS transistor is shown as the MOS transistor 1304, but a P-type MOS transistor can be used.

[0105] The operation of the power clamping MOS transistor 1300 will be described below. If an excessive positive voltage is applied to the VDD power supply line due to electrostatic discharge, the potential at the input terminal of the CMOS inverter 1303 will be lower than the potential of the VDD power supply line within the time constant R×C of the RC series circuit. As a result, the potential at the output terminal of the CMOS inverter 1303 becomes high, and the MOS transistor 1304 enters the on state (turn-on state). On the other hand, during normal operation, the input terminal of the CMOS inverter 1303 becomes high, while the output terminal becomes low. The MOS transistor 1304 therefore enters the off state (turn-off state). In this way, the power clamping MOS transistor 1300 is unlikely to affect normal operation. Furthermore, when static electricity is released, the MOS transistor 1304 enters the on state, and the charge caused by static electricity can be appropriately released.

[0106] Figure 22A and Figure 22B as well as Figure 23A and Figure 23B This is a plan view of an electrostatic discharge (ESD) protection circuit according to this exemplary embodiment. Figures 1 to 21 Components shown are assigned the same reference numerals, and their descriptions will be omitted. In the photoelectric conversion device according to this exemplary embodiment, respectively in Figure 22A and Figure 22B The two components (chips) shown are joined together, and respectively in Figure 23A and Figure 23B The two components (chips) shown are bonded together. The electrostatic discharge (ESD) protection circuit includes power clamping MOS transistors 1300A and 1300B, a VDD power supply line 1305, and a GND power supply line 1306. In this example, power clamping MOS transistor 1300A, VDD power supply line 1305, and GND power supply line 1306 are formed in the first component 1402. Power clamping MOS transistor 1300B is formed in the second component 1403.

[0107] exist Figure 22A and Figure 22B In the planar layout shown, power clamping MOS transistors 1300A and 1300B are arranged in an area that overlaps with at least one of the VDD power supply line 1305 and the GND line 1306 in the plan view. Figure 23A and Figure 23B In the planar layout shown, power clamping MOS transistors 1300A and 1300B are arranged so that they do not overlap with VDD power line 1305 or GND line 1306 in the plan view.

[0108] Figure 24 It is along Figure 22A , Figure 22B , Figure 23A and Figure 23B The cross-sectional diagram of the photoelectric conversion device is shown by the dashed line J-J'.

[0109] exist Figure 24 In, with Figures 1 to 23B Components shown are assigned the same reference numerals and their descriptions will be omitted. In the photoelectric conversion device according to the seventh exemplary embodiment, a first component 1402 including a first substrate 1400 and a second component 1403 including a second substrate 1401 are joined together. The first component 1402 and the second component 1403 are electrically connected to each other at joining portions 1404 and 1405. The first component 1402 includes wiring layers 1406 and 1407 and contact layers 1410 to 1415. The second component 1403 includes wiring layers 1408 and 1409 and contact layers 1416 to 1419. Furthermore, a power clamping MOS transistor 1300A is formed on the first substrate 1400, and a power clamping MOS transistor 1300B is formed on the second substrate 1401. For simplicity, Figure 24 The main examples shown are MOS transistors 1304A and 1304B. MOS transistor 1304A includes a gate electrode 1426, a drain region 1421, and a source region 1422 disposed on a p-type semiconductor region 1420. In this example, the drain region 1421 is connected to the VDD power supply line 1305 via a contact layer 1411. The source region 1422 is connected to the GND line 1306 via a contact layer 1410.

[0110] The MOS transistor 1304B includes a gate electrode 1427, a drain region 1424, and a source region 1425 disposed on a p-type semiconductor region 1423. The drain region 1424 is connected to the VDD power supply line 1305 via wiring layers 1409 and 1407, a junction portion 1404, and contact layers 1413, 1415, 1417, and 1419. The source region 1425 is connected to the GND line 1306 via wiring layers 1406 and 1408, a junction portion 1405, and contact layers 1412, 1414, 1416, and 1418.

[0111] In this exemplary embodiment, by arranging power clamping MOS transistors on each of the two stacked components, the circuit area of ​​the power clamping element can be increased. This configuration enhances the protection capability of the electrostatic discharge (ESD) protection circuit.

[0112] In the following description, an electrostatic discharge (ESD) protection circuit included in a solid-state imaging apparatus having a stacked structure will be used as an ESD protection circuit according to an eighth exemplary embodiment of the present disclosure. An image sensor (CMOS image sensor) will be described as an ESD protection circuit according to the present exemplary embodiment. The configuration of the image sensor to be described in this exemplary embodiment is merely an example, and the configuration is not limited thereto. For example, the ESD protection circuit may also be applied to a ranging device for measuring the distance to a target object, a photometer for measuring the intensity of light from a subject, or a line sensor used in the document reading unit of a copier.

[0113] Furthermore, the stacked structure according to this exemplary embodiment is not limited to a stacked structure having two components (chips). As another variation, a stacked structure having three or more components (chips) can be employed. In this exemplary embodiment, one or more electrostatic discharge (ESD) protection circuits are arranged in two or more stacked components (chips). The number of components (chips) used to form the stacked structure and the number of semiconductor substrates on which ESD protection circuits are formed need not always be the same.

[0114] First, refer to Figure 25 The construction of an image sensor according to this exemplary embodiment is described. Figure 25 This is a block diagram illustrating a concept of an image sensor according to this exemplary embodiment, and the arrangement of the components differs from the actual arrangement. The image sensor according to this exemplary embodiment has a stacked structure as described below, and will be referred to below. Figure 26A and Figure 26B Describe the circuit layout. First, refer to... Figure 25 Describe the function of the circuitry included in the image sensor.

[0115] Image sensor 1500 includes a sensor array 1502 comprising sensors 1501 arranged in multiple rows and columns. Each sensor 1501 includes a photoelectric conversion element (photoelectric conversion unit) for converting incident light into signal charge and outputting the signal charge as an analog electrical signal. Image sensor 1500 also includes: a control unit 1503 that controls the entire image sensor 1500; a vertical scanning unit 1504 that selects the sensor rows from the sensor array 1502 from which to output analog electrical signals; and an analog-to-digital (AD) unit 1505 that converts the analog electrical signals into digital signals. Image sensor 1500 also includes: a horizontal scanning unit 1506 that selects and outputs digital signals stored in the column memory of the AD unit 1505; and at least one signal processing unit (here, signal processing unit 1507) that processes the output digital signals. The peripheral circuit unit 1508 includes a control unit 1503, a vertical scanning unit 1504, an AD unit 1505, a horizontal scanning unit 1506, and a signal processing unit 1507. The image sensor 1500 also includes an electrostatic discharge protection unit 1509 that dissipates electrostatic discharge entering from the input-output terminals to the VDD power supply wiring or the GND wiring. The image sensor 1500 also includes an input-output (I / O) unit 1510, which includes an input-output terminal portion with pads. The pads serve as electrical connection portions, where metal wiring is partially opened to allow connection to the outside.

[0116] Each sensor 1501 included in sensor array 1502 includes a photodiode (PD) 1511, a transfer transistor (TX Tr) 1512, a reset transistor (RST Tr) 1513, and an amplification transistor 1514. Each sensor 1501 also includes a row selection transistor (SEL Tr) 1515. Pixel signals acquired by sensors 1501 in the sensor row selected by vertical scan unit 1504 are sent via vertical output line 1516 to AD unit 1505, which is part of peripheral circuit unit 1508. The configuration is not limited to the vertical output line 1516 and AD unit 1505 being arranged to correspond to the columns of sensor array 1502. For example, a memory included in the AD unit, consisting of circuitry such as trigger circuitry, can be provided for each column, block, or entire sensor array 1502.

[0117] The analog electrical signal output from the sensor array 1502 is converted into a digital signal by the AD unit 1505 and temporarily stored in the column memory. The column memory is included in a part of the AD unit 1505, and... Figure 25The diagram is omitted. The digital signal obtained through AD conversion undergoes parallel-to-serial conversion in conjunction with the drive of the horizontal scanning unit 1506, and then sequentially undergoes signal processing by the signal processing unit 1507 via the horizontal output line 1517. More specifically, the signal processing performed by the signal processing unit 1507 includes noise removal processing using correlated double sampling (CDS) and signal correction processing. The processed signal is output to the outside of the image sensor 1500 via the I / O unit 1510.

[0118] Figure 26A and Figure 26B This is a diagram illustrating an example of the construction of various semiconductor substrates in an image sensor 1500 having a stacked structure according to this exemplary embodiment. The image sensor 1500 has a stacked structure utilizing a first component 1702 and a second component 1703. In this stacked structure, the first component 1702 includes components arranged with... Figure 25 The sensor array 1502 and PAD unit 1600A of the sensor 1501 shown are illustrated. The first component 702 also includes: a substrate connection portion 1601A electrically connecting the semiconductor substrate (a) and the semiconductor substrate (b); and an I / O unit 1510 including an electrostatic discharge protection unit 1509A. The semiconductor substrate (a) and the semiconductor substrate (b) can be bonded, for example, by a known method discussed in Japanese Patent Application Publication No. 2012-033878. In addition, the substrate connection portion 1601A, which serves as a connection portion in the stacked structure, can have, for example, a through-silicon via (TSV) structure. Alternatively, the substrate connection portion 1601A can have a copper-copper bonding (CCB) structure, wherein copper electrodes with exposed surfaces are formed in the respective insulating layers of the plurality of chips, and the plurality of chips are bonded in such a way that the copper electrodes are bonded to each other. CCB is sometimes referred to as hybrid bonding. Alternatively, the substrate connection portion 1601A can have a microbump structure.

[0119] In this exemplary embodiment, the main surfaces of semiconductor substrate (a) and semiconductor substrate (b) are considered the front surfaces of the substrates. In each substrate, the surface opposite to the main surface is considered the back surface. The image sensor 1500 has a configuration in which the main surfaces of semiconductor substrate (a) and semiconductor substrate (b) are bonded together. As another example, the image sensor 1500 may have a configuration where the main surfaces and back surfaces of the substrates are bonded, or a configuration where the back surfaces of the substrates are bonded. Regarding the connection of the above-described stacked structure, the substrate connection portions 1601A can be arranged to suit various purposes, such as control signals, power supplies, or sensor signals. The substrate connection portions 1601A do not necessarily have to be arranged on each of the left and right sides of the substrate. In addition to electrical connection portions, virtual substrate connection portions (not shown on the left and right sides of the substrate) can also be arranged. Figure 26A and Figure 26B(As shown in the diagram) to enhance the reliability of the bonding between substrates. Semiconductor substrate (b) includes a peripheral circuit unit 1508, which includes a control unit 1503, an AD unit 1505, a signal processing unit 1507, a vertical scanning unit 1504, and a horizontal scanning unit 1506. Semiconductor substrate (b) also includes a PAD unit 1600B, a substrate connection portion 1601B electrically connecting semiconductor substrate (a) and semiconductor substrate (b), and an I / O unit 1510 including an electrostatic protection unit 1509B.

[0120] Multiple I / O units 1510 are arranged in the image sensor 1500, and include pads for outputting pixel signals based on signals photoelectrically converted by the image sensor 1500, and pads for receiving voltages from the outside to drive peripheral circuit units 1508. After stacking semiconductor substrates (a) and (b), external terminals are connected to PAD unit 1600B via PAD unit 1600A (opening). Examples of external terminals include bonding wires connected to PAD unit 1600B via wire bonding. PAD units 1600A and 1600B, as openings, do not always need to be arranged on semiconductor substrates (a) and (b) respectively. For example, PAD units 1600B and 1600A, as openings, can be arranged on semiconductor substrates (a) and (b) respectively. Additionally, in Figure 26B In the semiconductor substrate (b), the peripheral circuit unit 1508 is arranged on the semiconductor substrate (b). The circuits of each of the control unit 1503, AD unit 1505, signal processing unit 1507, vertical scanning unit 1504 and horizontal scanning unit 1506 included in the peripheral circuit unit 1508 can be arranged entirely or partially on the semiconductor substrate (a).

[0121] Figure 27A and Figure 27B This is a plan view showing the periphery of the I / O unit 1510 according to the eighth exemplary embodiment. Figure 27A and Figure 27B In, with Figures 1 to 26A and Figure 26B Components shown are assigned the same reference numerals, and their descriptions will be omitted. In this example, the electrostatic protection circuit is constructed similarly to that shown in Figure 2, but can be used with... Figure 3A and Figure 3B , Figure 6A and Figure 6B , Figure 7A and Figure 7B , Figure 10A and Figure 10B , Figure 12A and Figure 12B , Figure 15A and Figure 15B as well as Figure 19A and Figure 19B Any construction similar to the one shown, or a combination of these constructions, can be used.

[0122] Figure 28 It is along Figure 27A and Figure 27B A schematic diagram of the cross-section of the photoelectric conversion device, intercepted by the dashed line K-K'. Figure 28 In, with Figures 1 to 27B Components shown are assigned the same reference numerals, and their descriptions will be omitted. In the photoelectric conversion device according to the eighth exemplary embodiment, a first member 1702 including a first substrate 1700 and a second member 1703 including a second substrate 1701 are joined together. Figure 28 In the image sensor 1500 shown, the electrostatic protection unit 1509 is related to the image sensor 1500 in terms of structure and connection. Figure 4 The electrostatic discharge protection circuit shown is similar. In this exemplary embodiment, a peripheral circuit unit 1508 is used instead. Figure 4 The internal circuit 103A shown is used to form a sensor array 1502 instead. Figure 4 The internal circuit 103B is shown.

[0123] The sensor array 1502 includes an n-type semiconductor region 1707 constituting a photoelectric conversion element, an n-type semiconductor region 1705 serving as the drain of a transfer transistor 1512, and an element isolation structure 1706. The transfer transistor 1512 includes the n-type semiconductor region 1705, the n-type semiconductor region 1707, and a gate electrode 1708. In this example, the signal charge accumulated in the n-type semiconductor region 1705 is transferred to the n-type semiconductor region 1707 via the gate electrode 1708. On the back side of the sensor array 1502, a color filter layer 1709 including multiple color filters, a planarization layer 1710, and a microlens layer 1711 including multiple microlenses are arranged. Figure 28 In this configuration, each of the multiple color filters and each of the multiple microlenses is arranged for a corresponding one of the photoelectric conversion elements. In other words, each of the multiple color filters and each of the multiple microlenses is arranged for a corresponding one of the pixels. Alternatively, a color filter and a microlens may be arranged for multiple pixels. See reference. Figure 28 A back-illuminated image sensor is described, wherein light is incident from the microlens layer 1711 side and received by the n-type semiconductor region 1705 of the photoelectric conversion element. However, the configuration of the image sensor 1500 described in this exemplary embodiment is merely an example, and the configuration is not limited thereto. At least a portion of the peripheral circuitry, such as the control unit 1503, the AD unit 1505, the vertical scanning unit 1504, and the horizontal scanning unit 1506, is arranged in the peripheral circuitry unit 1508. Figure 28 The diagram shows n-type and p-type transistors in any circuit included in the peripheral circuit unit 1508.

[0124] In this exemplary embodiment, in the image sensor 1500 with two stacked semiconductor substrates, electrostatic discharge (ESD) protection circuits are arranged on each of the stacked semiconductor substrates. This configuration allows for an increase in the area occupied by the ESD protection circuits without subjecting them to stress caused by wire bonding. This enhances the characteristics of the ESD protection circuits while reducing the impact of wire bonding and ensuring operational stability. Alternatively, by increasing the area occupied by the image sensor itself, rather than by increasing the area occupied by the ESD protection circuits, higher pixel counts and higher sensitivity can be achieved. Alternatively, by increasing the area occupied by peripheral circuitry in the image sensor (such as circuitry for reading out pixel signals and circuitry for processing the readout pixel signals), rather than by increasing the area occupied by the ESD protection circuits, higher speeds and greater functionality can be achieved.

[0125] Reference Figure 29 A photoelectric conversion system according to a ninth exemplary embodiment of the present disclosure is described. Figure 29 This is a block diagram illustrating a schematic construction of a photoelectric conversion system according to this exemplary embodiment.

[0126] The imaging apparatus described in the first to eighth exemplary embodiments above can be applied to various photoelectric conversion systems. Examples of photoelectric conversion systems include digital still cameras, digital portable video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Additionally, photoelectric conversion systems also include camera modules (including optical systems such as lenses and imaging devices). As an example of a photoelectric conversion system, Figure 29 A block diagram of a digital still camera is shown.

[0127] Figure 29 The photoelectric conversion system shown includes an imaging device 1004, a lens 1002 that forms an optical image of a subject on the imaging device 1004, an aperture 1003 for changing the amount of light passing through the lens 1002, and a baffle 1001 for protecting the lens 1002. The lens 1002 and the aperture 1003 serve as an optical system for converging light onto the imaging device 1004. The imaging device 1004 is a photoelectric conversion device (imaging device) according to any of the above exemplary embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0128] The photoelectric conversion system also includes a signal processing unit 1007, which serves as an image generation unit. This image generation unit generates an image by processing the signal output from the imaging device 1004. The signal processing unit 1007 performs various types of corrections and compressions as needed before outputting image data. The signal processing unit 1007 can be formed on a semiconductor substrate on which the imaging device 1004 is mounted, or it can be formed on other semiconductor substrates.

[0129] The photoelectric conversion system also includes a storage unit 1010 for temporarily storing image data and an external interface unit (external I / F unit) 1013 for communicating with an external computer. The photoelectric conversion system also includes a recording medium 1012, such as a semiconductor memory, for recording or reading captured image data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording (or reading) image data to (or from) the recording medium 1012. The recording medium 1012 can be built into the photoelectric conversion system or detachably attached to it.

[0130] The photoelectric conversion system also includes a general control / computing unit 1009 for controlling various types of calculations and the entire digital still camera, and a timing signal generation unit 1008 for outputting various timing signals to the imaging device 1004 and the signal processing unit 1007. The timing signals can be input from an external source. The photoelectric conversion system includes at least the imaging device 1004 and a signal processing unit 1007 for processing signals output from the imaging device 1004.

[0131] Imaging device 1004 outputs an imaging signal to signal processing unit 1007. Signal processing unit 1007 performs predetermined signal processing on the imaging signal output from imaging device 1004 and outputs image data. Signal processing unit 1007 uses the imaging signal to generate an image.

[0132] In this way, according to this exemplary embodiment, a photoelectric conversion system applicable to the photoelectric conversion device (imaging device) according to any of the above exemplary embodiments can be realized.

[0133] Reference Figure 30A and Figure 30B A photoelectric conversion system and a movable body according to a tenth exemplary embodiment of the present disclosure are described. Figure 30A and Figure 30B The diagrams show the construction of the photoelectric conversion system and the movable body according to this exemplary embodiment.

[0134] Figure 30AAn example of a photoelectric conversion system 300 related to an in-vehicle camera is shown. The photoelectric conversion system 300 includes an imaging device 310. The imaging device 310 is a photoelectric conversion device (imaging device) according to any of the exemplary embodiments described above. The photoelectric conversion system 300 also includes: an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310; and a disparity acquisition unit 314 that calculates disparity (phase difference between disparity images) based on the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also includes: a distance acquisition unit 316 that calculates the distance to a target object based on the calculated disparity; and a collision determination unit 318 that determines whether a collision may occur based on the calculated distance. In this example, the disparity acquisition unit 314 and the distance acquisition unit 316 serve as examples of distance information acquisition units that acquire distance information about the distance to a target object. More specifically, the distance information is information about disparity, defocus, distance to the target object, etc. The collision determination unit 318 can use any information from this distance information to determine the likelihood of a collision. The distance information acquisition unit can be implemented by specially designed hardware or by a software module. Alternatively, the distance information acquisition unit can be implemented by a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), or a combination thereof.

[0135] The photoelectric conversion system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, or steering angle. Additionally, a control electronic control unit (ECU) 330 is connected to the photoelectric conversion system 300. The control ECU 330 functions as a control device that outputs control signals to the vehicle to generate braking force based on the determination results made by the collision determination unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340, which issues an alarm to the driver based on the determination results made by the collision determination unit 318. For example, if the determination results indicate a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or reduce damage, for example, by braking, reducing throttle, or suppressing engine output. The alarm device 340 warns the user, for example, by issuing an alarm, displaying a warning message on the screen of the car navigation system, or vibrating the seatbelt or steering wheel.

[0136] In this exemplary embodiment, the photoelectric conversion system 300 captures images of the vehicle's periphery (such as the front or rear side). Figure 30B A photoelectric conversion system 300 is shown that captures an image of the front side of a vehicle (imaging range 350). A vehicle information acquisition device 320 sends commands to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve ranging accuracy.

[0137] The above describes examples of control measures to avoid collisions with other vehicles. Photoelectric conversion systems can also be applied to control automatic operation while following other vehicles, or to automatic operation to avoid deviating from the lane. Furthermore, in addition to private vehicles, photoelectric conversion systems can be applied to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. Moreover, besides mobile bodies, photoelectric conversion systems can also be applied to devices that widely use object recognition, such as Intelligent Transportation Systems (ITS).

[0138] [Exemplary embodiments of the variant]

[0139] This disclosure is not limited to the exemplary embodiments described above, and various modifications are possible.

[0140] For example, exemplary embodiments of this disclosure also include: examples of adding a portion of the construction according to any exemplary embodiment to any other exemplary embodiment, and examples of replacing a portion of the construction according to any exemplary embodiment with a portion of the construction according to any other exemplary embodiment.

[0141] Furthermore, the photoelectric conversion system according to the ninth and tenth exemplary embodiments described above is an example of a photoelectric conversion system to which a photoelectric conversion device according to any exemplary embodiment can be applied. The photoelectric conversion system to which a photoelectric conversion device according to any exemplary embodiment can be applied is not limited to... Figure 29 , Figure 30A and Figure 30B The structure shown.

[0142] The exemplary embodiments described above are merely examples of implementations for carrying out this disclosure, and should not be construed as limiting the scope of the disclosure. This disclosure may be implemented in various forms without departing from its technical concept or key features.

[0143] According to exemplary embodiments of the present disclosure, the changes in the characteristics of the protection circuit caused by wire bonding can be reduced, thereby suppressing the reduction in signal accuracy and operational reliability of the photoelectric conversion device.

[0144] Embodiments of the invention can also be implemented by a computer that reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (also more fully referred to as a "non-transitory computer-readable storage medium") to perform one or more functions in the above embodiments, and / or includes one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing one or more functions in the above embodiments. Furthermore, embodiments of the invention can be implemented using a method by which the computer of the system or device, for example, reads and executes the computer-executable instructions from the storage medium to perform one or more functions in the above embodiments, and / or controls the one or more circuits to perform one or more functions in the above embodiments. The computer may include one or more processors (e.g., central processing unit (CPU), microprocessor unit (MPU)) and may include separate computers or a network of separate processors to read and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, a hard disk, random access memory (RAM), read-only memory (ROM), the memory of a distributed computing system, or an optical disc (such as a compact disc (CD), a digital versatile optical disc (DVD), or a Blu-ray disc (BD)). TM One or more of the following: flash memory devices and memory cards.

[0145] The embodiments of the present invention can also be implemented by providing software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads out and executes the program.

[0146] Although the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The appended claims should be interpreted in the broadest possible sense to encompass all such variations and equivalent structures and functions.

Claims

1. A photoelectric conversion device, wherein a first semiconductor substrate and a second semiconductor substrate are stacked in the photoelectric conversion device, the first semiconductor substrate including a plurality of photoelectric conversion units each configured to receive incident light and generate signal charges, and the second semiconductor substrate including at least one signal processing circuit configured to process an input signal based on the generated signal charges, the photoelectric conversion device comprising: The pads are configured to receive power supply voltage as an input from outside the photoelectric conversion device; A first protection circuit is disposed on the first semiconductor substrate and includes a first diode and a second diode; as well as The second protection circuit is disposed on the second semiconductor substrate and includes a third diode and a fourth diode. In the plan view, at least one of the first protection circuit and the second protection circuit is disposed outside the area where the pads are located. Wherein, at least one of the first protection circuit and the second protection circuit is connected to the pad, and The first protection circuit and the second protection circuit are disposed at the position where at least a portion of the first diode and at least a portion of the third diode overlap in a plan view, or at the position where at least a portion of the second diode and at least a portion of the fourth diode overlap in a plan view.

2. The photoelectric conversion device according to claim 1, wherein In a plan view, the first diode, the second diode, the third diode, and the fourth diode are positioned outside the area where the pads are located.

3. The photoelectric conversion device according to claim 1, wherein The pads, in a plan view, are positioned between the edge of the second semiconductor substrate closest to the pads and the third and fourth diodes. In a plan view, the third diode and the fourth diode are disposed between the pad and the at least one signal processing circuit.

4. The photoelectric conversion device according to claim 1, wherein The second protection circuit is located at the position where it overlaps with the pad in the plan view.

5. The photoelectric conversion device according to claim 4, wherein Both the first protection circuit and the second protection circuit are connected to the pad.

6. The photoelectric conversion device according to claim 1, wherein Both the first protection circuit and the second protection circuit are connected to the pad.

7. The photoelectric conversion device according to claim 1, further comprising: A power supply wiring is configured to supply power voltage to the at least one signal processing circuit, wherein the second protection circuit is connected to the power supply wiring.

8. The photoelectric conversion device according to claim 1, wherein The pads are connected to wiring in the wiring layer at a depth different from the depth at which the pads are disposed, and at least one of the first protection circuit and the second protection circuit overlaps with the wiring in a plan view.

9. The photoelectric conversion device according to claim 1, wherein The wiring is arranged in a wiring layer disposed on the second semiconductor substrate, wherein the wiring is arranged at a depth different from the depth at which the pads are disposed. Wherein, the pads are connected to the wiring, and The wiring is connected to a plurality of protection circuits, including the second protection circuit, disposed on the second semiconductor substrate.

10. A photoelectric conversion system, comprising: The photoelectric conversion device according to any one of claims 1 to 9; as well as A signal processing unit is configured to generate an image using the signal output from the photoelectric conversion device.

11. A movable body comprising the photoelectric conversion device according to any one of claims 1 to 9, said movable body comprising: The control unit is configured to control the movement of the movable body using signals output from the photoelectric conversion device.

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