Arc fault detection circuit

Abstract

The present disclosure provides an arc fault detection circuit, comprising: a signal acquisition circuit configured to acquire a current on a power supply line and output a first signal; a window gating circuit configured to output a window gating signal corresponding to the first signal; and a signal processing circuit electrically connected to the signal acquisition circuit and the window gating circuit, and configured to generate an arc fault signal based on the window gating signal and the first signal. The present disclosure adds a window gating circuit to the arc fault detection circuit, and only determines whether there is a fault arc feature during a period when a harmful arc will definitely occur, thereby greatly improving the accuracy of harmful arc determination and reducing the probability of false operation of the arc fault protection device.

Description

Technical Field

[0001] This disclosure relates to the field of electrical safety protection, and more specifically, to a more accurate arc fault detection circuit. Background Technology

[0002] Electrical wiring and equipment in residences can experience arcing due to prolonged overload operation or poor electrical connections, causing the insulation layer of wires to age, lose its effectiveness, or become damaged. This arcing spark can ignite the wiring, causing a fire. According to a survey by NEC in the United States, approximately 40% of home fires are caused by arcing faults.

[0003] As people become more safety-conscious, more and more families are choosing to install arc fault protection devices in their homes. However, most arc fault protection devices currently on the market have the problem of inaccurate detection of harmful arcs, which often leads to malfunctions and causes great inconvenience to users. Summary of the Invention

[0004] To address the aforementioned problems, this disclosure provides an arc fault detection circuit capable of accurately detecting arc fault signals in power supply lines and implementing corresponding protection.

[0005] Based on this, according to one embodiment of the present disclosure, an arc fault detection circuit is provided, comprising: a signal acquisition circuit for acquiring current on a power supply line and outputting a first signal; a window gating circuit for outputting a window gating signal corresponding to the first signal, the window gating signal including a first level signal and a second level signal, the first level signal being used to shield signals corresponding to a preset time period in the first signal, and the second level signal being used to retain signals in the first signal that do not correspond to the preset time period; and a signal processing circuit electrically connected to the signal acquisition circuit and the window gating circuit for generating an arc fault signal based on the window gating signal and the first signal.

[0006] This disclosure improves the accuracy of harmful arc detection by adding a window selection circuit to the arc fault detection circuit. It determines the presence of fault arc characteristics only during the time period when harmful arcs that are likely to cause fires will definitely occur, and does not make a judgment during other time periods. This greatly improves the accuracy of harmful arc detection and significantly reduces the probability of arc fault protection devices malfunctioning. It solves the power supply problems of users while realizing arc fault protection.

[0007] In one embodiment of this implementation, the signal processing circuit includes a feature extraction sub-circuit for extracting arc features from the first signal to generate an arc feature signal.

[0008] In one embodiment of this implementation, the signal processing circuit includes: a signal amplification sub-circuit for amplifying the first signal to obtain a second signal; and a feature extraction sub-circuit electrically connected to the signal amplification sub-circuit for extracting arc features from the second signal to generate an arc feature signal.

[0009] In one embodiment of this implementation, the signal processing circuit includes: a driving pulse sub-circuit electrically connected to the feature extraction sub-circuit, used to generate an arc pulse signal based on the arc feature signal.

[0010] In one embodiment of this implementation, the signal processing circuit includes a pulse counting sub-circuit electrically connected to the driving pulse sub-circuit, used to record the number of pulses in the arc pulse signal and generate the arc fault signal based on the number of pulses in the arc pulse signal over a preset time period.

[0011] In one embodiment of this implementation, the window gating circuit includes: a first voltage divider circuit for dividing the voltage from the power supply line and outputting a first voltage signal; a second voltage divider circuit for dividing the voltage from the power supply line and outputting a second voltage signal; and a gating sub-circuit, the input terminal of which is connected to the output terminal of the first voltage divider circuit, and the output terminal of which is connected to the output terminal of the second voltage divider circuit. The gating sub-circuit is turned on when the input voltage at its input terminal is within a preset range, and turned off otherwise, thereby outputting the window gating signal.

[0012] In one embodiment of this implementation, the gating sub-circuit includes a first Zener diode, a first transistor, a second transistor, a first protection resistor, and a second protection resistor. The first terminal of the first Zener diode is the input terminal of the gating sub-circuit. The second terminal of the first Zener diode is connected to the first terminal of the first transistor, and the second terminal of the first transistor is grounded. The third terminal of the first transistor is connected to the first terminal of the second transistor through the first protection resistor. The first terminal of the second transistor is connected to the first terminal of the second protection resistor. The second terminal of the second protection resistor is connected to the second terminal of the second transistor and the power supply voltage. The third terminal of the second transistor is the output terminal of the gating sub-circuit.

[0013] In one embodiment of this implementation, the gating sub-circuit includes a three-terminal adjustable voltage regulator, a second transistor, a first protection resistor, and a second protection resistor. The first terminal of the three-terminal adjustable voltage regulator is the input terminal of the gating sub-circuit, the second terminal of the three-terminal adjustable voltage regulator is grounded, the third terminal of the three-terminal adjustable voltage regulator is connected to the first terminal of the second transistor through the first protection resistor, the first terminal of the second transistor is connected to the first terminal of the second protection resistor, the second terminal of the second protection resistor is connected to the second terminal of the second transistor and the power supply voltage, and the third terminal of the second transistor is the output terminal of the gating sub-circuit.

[0014] In one embodiment of this implementation, the gating sub-circuit includes a first comparator, a first voltage divider resistor, a second voltage divider resistor, and a diode. The non-inverting input of the first comparator is the input of the gating sub-circuit, the inverting input of the first comparator is connected to the first and second voltage divider resistors, the other end of the first voltage divider resistor is connected to the power supply voltage, the other end of the second voltage divider resistor is grounded, the output of the first comparator is connected to the anode of the diode, and the cathode of the diode is the output of the gating sub-circuit.

[0015] In one embodiment of this implementation, the arc fault detection circuit includes: an arc fault driving circuit electrically connected to the signal processing circuit, used to generate a switch control signal based on the arc fault signal; and a switch circuit electrically connected to the arc fault driving circuit, used to open or close the input / output switch of the power supply line according to the switch control signal.

[0016] In one embodiment of this implementation, the arc fault detection circuit includes: a simulated arc test circuit, the output of which is connected to the signal acquisition circuit or signal processing circuit, for generating a simulated arc signal, thereby causing the switching circuit to disconnect the input / output switch of the power supply line according to the simulated arc signal.

[0017] In one embodiment of this implementation, the arc fault detection circuit includes a power supply circuit, which includes a rectifier and a second voltage regulator, for rectifying and regulating the voltage of the power supply line to supply power to the window selection circuit and the signal processing circuit.

[0018] In one embodiment of this implementation, the signal processing circuit includes a filter sub-circuit electrically connected to the signal acquisition circuit, used to filter and process the first signal before outputting it.

[0019] In one embodiment of this implementation, the signal processing circuit includes a filtering sub-circuit, a feature extraction sub-circuit, and a driving pulse sub-circuit. The window gating circuit is electrically connected to at least one of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and the driving pulse sub-circuit, and is used to shield the signal of the preset time period in the output signal of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and / or the driving pulse sub-circuit. Attached Figure Description

[0020] This disclosure will be better understood after the following description of specific embodiments of the disclosure given with reference to the accompanying drawings, and other objects, details, features, and advantages of the disclosure will become more apparent. In the drawings:

[0021] Figure 1 A system architecture diagram of an arc fault detection circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 2 A detailed circuit diagram of an arc fault detection circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A detailed circuit diagram of an arc fault detection circuit according to another embodiment of this disclosure is shown.

[0024] Figure 4 A circuit diagram of a window gating circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 5 A circuit diagram of a window gating circuit according to another embodiment of this disclosure is shown.

[0026] Figure 6 A circuit diagram of a window gating circuit according to yet another embodiment of this disclosure is shown.

[0027] Figure 7 The diagram shows the signal waveforms corresponding to the resistive load in one embodiment of this disclosure.

[0028] Figure 8 The diagram shows the waveforms of various signals corresponding to the load of an induction cooker in one embodiment of this disclosure.

[0029] Figure 9 The following diagram shows the signal waveforms corresponding to the induction cooker load in another embodiment of this disclosure. Detailed Implementation

[0030] The present disclosure will now be described in further detail with reference to specific embodiments and accompanying drawings. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0031] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0032] like Figure 1 As shown in the figure, an embodiment of this disclosure proposes a system architecture diagram of an arc fault detection circuit, which includes: a signal acquisition circuit 11, a window gating circuit 13, and a signal processing circuit 15. The signal acquisition circuit 11 is used to acquire data from the power supply line (e.g., ...). Figure 1 The current on the L-line and N-line (as shown) is collected, and a first signal is output. A window gating circuit 13 outputs a window gating signal corresponding to the first signal. This window gating signal is used to shield the current signal during a preset time period in each current cycle, while retaining the current characteristic signal during the arc period. The window gating signal is at a higher level for a portion of each cycle of the current signal on the power supply line, and at a lower level for the remainder. A signal processing circuit 15 is electrically connected to the signal acquisition circuit 11 and the window gating circuit 13, and is used to generate an arc fault signal based on the window gating signal and the first signal.

[0033] In some examples, the signal processing circuit 15 includes a filtering sub-circuit 150, a signal amplification sub-circuit 151, a feature extraction sub-circuit 153, a driving pulse sub-circuit 155, and a pulse counting sub-circuit 157. The filtering sub-circuit 150 is electrically connected to the signal acquisition circuit 11 and is used to filter the first signal and output it (i.e., output the current characteristic signal of the frequency band where the arc is located). The signal amplification sub-circuit 151 is used to amplify the filtered first signal to obtain a second signal. The feature extraction sub-circuit 153 is electrically connected to the signal amplification sub-circuit 151 and is used to extract arc features from the second signal to generate an arc characteristic signal. The driving pulse sub-circuit 155 is electrically connected to the feature extraction sub-circuit 153 and is used to generate an arc pulse signal based on the arc characteristic signal (i.e., standardize the arc characteristic signal into an arc pulse signal with a certain duty cycle). The pulse counting sub-circuit 157 is electrically connected to the driving pulse sub-circuit 155 and is used to record the number of pulses in the arc pulse signal and generate the arc fault signal based on the number of pulses in the arc pulse signal over a preset time period. By amplifying the first signal using the signal amplification sub-circuit 151, the accuracy of arc fault detection can be improved. In other examples, the signal processing circuit 15 may not include the signal amplification sub-circuit, which simplifies the circuit and reduces costs.

[0034] In some examples, the arc fault detection circuit further includes an arc fault driving circuit 17 and a switching circuit 19. The arc fault driving circuit 17 is electrically connected to the signal processing circuit 15 and is used to generate a switching control signal based on the arc fault signal. The switching circuit 19 is electrically connected to the arc fault driving circuit 17 and is used to open or close the input / output switch of the power supply line according to the switching control signal.

[0035] In some examples, the arc fault detection circuit further includes a simulated arc test circuit 21, the output of which is connected to the signal acquisition circuit 11 or the signal processing circuit 15 to generate a simulated arc signal, thereby causing the switching circuit 19 to disconnect the input / output switch of the power supply line according to the simulated arc signal. The simulated arc test circuit 21 detects whether the arc fault protection function of the product is normal by generating a simulated fault arc.

[0036] In some examples, the arc fault detection circuit also includes a power supply circuit 23, which rectifies and regulates the voltage of the power supply line to supply power to the window gating circuit 13 and the signal processing circuit 15. The power supply circuit 23 is electrically connected to the power supply line, rectifies and regulates the AC power from the power supply line through a rectifier, and then regulates it through a voltage regulator, thereby providing a stable DC power to the signal processing circuit, the window gating circuit, etc.

[0037] In some examples, the window gating circuit is electrically connected to at least one of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and the driving pulse sub-circuit, for shielding the signal during the preset time period in the output signal of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and / or the driving pulse sub-circuit. That is, the window gating circuit can process signals containing arc characteristics at any one or more stages of the signal processing process, shielding the current signal during a preset time period in each current cycle, while retaining the current characteristic waveform during the arc period, thereby improving the accuracy of fault arc detection. Figure 2 As shown, a detailed circuit diagram of an arc fault detection circuit is provided in one embodiment of this disclosure. (Refer to...) Figure 2 The arc fault detection circuit can be described in detail below.

[0038] In some examples, the signal acquisition circuit 11 includes a current transformer CT1, which acquires the current on the power supply line and outputs a first signal, namely the current signal of the power supply line.

[0039] In some examples, the filter sub-circuit includes resistors R1, R2, R3, R4, and R24, capacitors C2, C3, and C4, and a Zener diode ZD1. Resistor R1 is connected in parallel with the secondary winding of CT1, converting the secondary current signal output by CT1 into a secondary voltage waveform. This waveform is then filtered by R2, R3, R4, C2, C3, and C4, retaining the voltage waveform in the arc frequency band. Zener diode ZD1 limits the output voltage waveform. Specifically, the first terminal of R1 is connected to the first terminal of R2, and the second terminal of R1 is connected to the negative terminal of Zener diode ZD1. The positive terminal of Zener diode is connected to the second terminal of R2 and the first terminal of C2. The second terminal of C2 is connected to the first terminal of R3 and the first terminal of C3. The second terminal of C3 is connected to the first terminals of R4 and C4. The second terminal of C4 is grounded through R24. The second terminals of R3 and R4 are connected to the negative terminal of ZD1 and grounded. The second terminal of C4 is the output terminal of the filter sub-circuit.

[0040] In some examples, the window gating circuit 13 includes a first voltage divider circuit, a second voltage divider circuit, and a gating sub-circuit. The first voltage divider circuit consists of resistors R17 and R27 connected in series, and the second voltage divider circuit consists of resistors R10 and R22 connected in series. The connection point of R17 and R27 is the output terminal of the first voltage divider circuit, which outputs a first voltage signal. The connection point of R10 and R22 is the output terminal of the second voltage divider circuit, which outputs a second voltage signal.

[0041] In some examples, the gating sub-circuit includes a Zener diode ZD3, a first transistor Q3, a second transistor Q1, a first protection resistor R16, and a second protection resistor R13. The first terminal of the Zener diode ZD3 is the input terminal of the gating sub-circuit. The second terminal of the Zener diode ZD3 is connected to the first terminal of the first transistor Q3, which is grounded. The third terminal of the first transistor Q3 is connected to the first terminal of the second transistor Q1 through the first protection resistor R16. The first terminal of the second transistor Q1 is connected to the first terminal of the second protection resistor R13. The second terminal of the second protection resistor R13 is connected to the second terminal of the second transistor Q1 and the power supply voltage VCC. The third terminal of the second transistor Q1 is the output terminal of the gating sub-circuit.

[0042] In some examples, the first transistor Q3 is an NPN bipolar transistor (with its first terminal being the base, second terminal being the emitter, and third terminal being the collector), and the second transistor Q1 is a PNP bipolar transistor (with its first terminal being the base, second terminal being the emitter, and third terminal being the collector). In other examples, the first transistor Q3 and the second transistor Q1 can be field-effect transistors.

[0043] In some examples, the window gating circuit 13 also includes filter capacitors C8 and C10. C8 is connected in parallel with voltage divider resistor R27, and C10 is connected in parallel with voltage divider resistor R22. Filtering improves the gating effect of the window gating signal. Preferably, capacitor C8 is a phase-shifting capacitor, which improves the gating accuracy of the window gating circuit by adjusting the phase of the voltage input to the rectifier DB1 into the window gating circuit 13.

[0044] like Figure 3 As shown, one embodiment of this disclosure presents a detailed circuit diagram of another arc fault detection circuit. Wherein, Figure 3 The switching circuit 19 is located at the power supply terminal (the input terminal of the power supply line). Figure 2 The switching circuit 19 is located at the load end (output end of the power supply line). Figure 2 and Figure 3 The example illustrates that the position where the arc fault detection circuit performs the protection action can be flexibly adjusted as needed, but is not limited to this. Figure 3 The connection method between the window gating circuit 13 and the signal processing circuit 15 is also the same as Figure 2 different, Figure 3 and Figure 2 This example illustrates that the window gating circuit can shield signals for a preset time period at various stages of the signal processing process. The connection between the window gating circuit 13 and the signal processing circuit and signal acquisition circuit can be flexibly adjusted as needed, but is not limited to this. Figure 2 and Figure 3 As shown in the diagram.

[0045] refer to Figure 3 In some examples, the third terminal of the second transistor Q1, i.e. the output terminal of the gating sub-circuit, is connected in parallel with the secondary winding of CT1 in the signal acquisition circuit 11 through the fourth transistor Q4. That is, the first terminal of the fourth transistor Q4 (such as the base of a bipolar transistor) is connected to the third terminal of Q1, the second terminal of Q4 (such as the emitter of a bipolar transistor) is grounded, and the third terminal of Q4 (such as the collector of a bipolar transistor) is connected to the output terminal of CT1.

[0046] Figure 4 , Figure 5 and Figure 6 The figures below show circuit diagrams for different implementations of the window gating circuit 13. It should be noted that... Figure 4-6 Taking the window gating circuit 13 as an example of gating the signal from the signal amplification sub-circuit 151 and outputting it to the driving pulse sub-circuit, the window gating circuit 13 in this disclosure is not limited to gating the output of the signal amplification sub-circuit 151. It can also gating the outputs of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and the driving pulse sub-circuit.

[0047] like Figure 4 As shown, the window selection signal output from the window selection circuit 13 is input to the inverting input (-) of the comparator IC1A in the feature extraction sub-circuit 153, and the second signal output from the signal amplification sub-circuit 151 is input to the non-inverting input (+) of the comparator IC1A. The first voltage divider circuits R17 and R27 receive the AC voltage from the power supply line, which is then rectified by the rectifier DB1 and output as the voltage. The working principle of this circuit can be explained as follows:

[0048] When the inverting input of IC1A is at a high level, the second signal output from the signal amplification subcircuit is prevented from being output to the next stage; when the inverting input of IC1A is at a low level, the second signal (stronger signal) from the signal amplification subcircuit is allowed to be transmitted to the next stage. Specifically, the AC power from the power supply line is rectified by DB1 and then divided by R17 and R27. The voltage at the upper end of R27 changes linearly with the voltage of the power supply line. When the voltage at the upper end of R27 exceeds the set value, the current triggers Q3 to conduct through ZD3, which in turn triggers Q1 to conduct. At this time, the voltage at the inverting input of comparator IC1A rises to the operating voltage of IC1, and the voltage signal from the signal amplification subcircuit 151 cannot pass through IC1A. When the voltage at the upper end of R27 does not exceed the set value, Q3 and Q1 are cut off, and the voltage at the inverting input of IC1A is the lower voltage after the IC1 power supply voltage is divided by R10 and R22. At this time, if a stronger signal from the signal amplification subcircuit exceeds the set value, the output of IC1A is at a high level.

[0049] In some examples, the model parameters of ZD3 and / or the setting values ​​of R17 and R27 are adjusted. Adjusting these setting values ​​allows the window gating signal output by the window gating circuit to extract the third signal within the corresponding time period of the second signal. If an arc fault occurs on the power supply line, this arc fault signal will inevitably appear in the third signal. Therefore, extracting arc features from the third signal significantly improves the accuracy of harmful arc detection.

[0050] like Figure 5 As shown, in some examples, the gating sub-circuit includes a three-terminal adjustable voltage regulator U1, a second transistor Q1, a first protection resistor R16, and a second protection resistor R13. The first terminal of the three-terminal adjustable voltage regulator U1 is the input terminal of the gating sub-circuit, the second terminal is grounded, and the third terminal is connected to the first terminal of the second transistor Q1 through the first protection resistor R16. The first terminal of the second transistor Q1 is connected to the first terminal of the second protection resistor R13, the second terminal of the second protection resistor R13 is connected to the second terminal of the second transistor Q1 and the power supply voltage VCC, and the third terminal of the second transistor Q1 is the output terminal of the gating sub-circuit. In some examples, the second transistor Q1 is a PNP bipolar transistor (its first terminal is the base, the second terminal is the emitter, and the third terminal is the collector). In other examples, the second transistor Q1 can be a field-effect transistor. Figure 5 The working principle of the circuit diagram shown is... Figure 4 Similarly, so I won't go into details. Figure 5 and Figure 4 The difference is that a three-terminal adjustable voltage regulator U1 is used instead. Figure 4 The ZD3 and Q3 in the design reduce the number of surface mount components, which helps to reduce the product size.

[0051] like Figure 6 As shown, in some examples, the gating sub-circuit includes a first comparator IC1B, a first voltage divider resistor R13, a second voltage divider resistor R16, and a diode D5. The non-inverting input of the first comparator IC1B is the input of the gating sub-circuit, and the inverting input of the first comparator IC1B is connected to the first voltage divider resistor R13 and the second voltage divider resistor R16. The other end of the first voltage divider resistor R13 is connected to the power supply voltage VCC, and the other end of the second voltage divider resistor R16 is grounded. The output of the first comparator IC1B is connected to the anode of the diode D5, and the cathode of the diode D5 is the output of the gating sub-circuit. Figure 6The working principle of the circuit diagram shown can be described as follows: The reference voltage of the inverting input of comparator IC1B is set by the voltage divider between R13 and R16. When the voltage at the upper end of R27 exceeds the reference voltage at the inverting input of comparator IC1B, IC1B outputs a high level, and the voltage at the inverting input of comparator IC1A rises to the operating voltage. At this time, the voltage signal from the signal amplification sub-circuit 151 cannot pass through IC1A. When the voltage at the upper end of R27 is lower than the set value, IC1B outputs a low level, and the voltage at the inverting input of IC1A is the lower voltage after the power supply voltage is divided by R10 and R22. At this time, if there is a strong signal from the voltage amplification sub-circuit 151 that exceeds the set value, the output of IC1A will be high.

[0052] In some examples, the arc fault drive circuit 17 includes a solenoid SOL and a silicon controlled rectifier (SCR) Q2. The output of the signal processing circuit 15 is connected to the control terminal of the SCR Q2 via a resistor R14, thereby controlling the arc fault drive circuit 17 through the generated arc fault signal, i.e., controlling whether the SCR Q2 is turned on. When the SCR Q2 is turned on, the input / output switch circuit 19 disconnects the power connection, i.e., a large current flows through the solenoid SOL, which generates magnetic force, and its internal iron core moves, causing the switch circuit 19 to disconnect.

[0053] In some examples, the power supply circuit 23 includes a rectifier DB1, a resistor R11, a Zener diode ZD4, and a filter capacitor C7. The first terminal (1) and the third terminal (3) of the rectifier DB1 are electrically connected to the L (HOT) line and N (WHITE) line of the power supply, respectively. The second terminal of the rectifier DB1 is connected to the input terminal of the window gating circuit and the first terminal of the resistor R11. The second terminal of R11 is connected to the negative terminal of the Zener diode ZD4. The Zener diode ZD4 and the capacitor C7 are connected in parallel to ground.

[0054] In some examples, the simulated arc test circuit 21 includes a test button (TEST) and a protective resistor R6. When the user presses the test button, a simulated arc signal is generated and output to the signal acquisition circuit 11 or the signal processing circuit 15 to detect whether the arc fault protection function can be implemented normally.

[0055] Figure 7 and Figure 8 respectively application Figure 2 The output waveforms of each circuit module of the resistive load and induction cooker load of this disclosure are shown in the diagram, which more intuitively demonstrate the technical effects of this disclosure.

[0056] Figure 7 The signals displayed are the window selection signal A1, the load current signal A2, the arc characteristic signal A3, and the arc pulse signal A4 corresponding to the resistive load. Figure 7It is known that when the load current signal A2 crosses zero, an arc feature ("flat shoulder") appears in the lower level portion of the corresponding window selection signal A1, a corresponding feature waveform appears in the arc feature signal A3, and a corresponding arc pulse appears in the arc pulse signal A4. Therefore, the arc fault detection circuit of this disclosure extracts the arc feature in A3 through A1, and then determines whether an arc fault has occurred through the generated arc pulse, thus narrowing the judgment range and improving the judgment accuracy.

[0057] Figure 8 The signals displayed are the window selection signal B1, load current signal B2, arc characteristic signal B3, and arc pulse signal B4 corresponding to the induction cooker load. Figure 8 It can be seen that a significant high-frequency signal appeared in the peak part of the load current signal B2, which overlapped with the arc frequency band. A corresponding significant characteristic signal appeared on the arc characteristic signal B3. However, since this characteristic signal corresponds to the high-level part of the window gating signal B1, it was completely shielded and therefore did not appear on the arc pulse signal B4, thus avoiding malfunction.

[0058] Figure 9 For application Figure 2 The output waveform diagrams of the various circuit modules of the induction cooker load shown in this disclosure include a window selection signal C1, a load current signal C2, an arc characteristic signal C3, and an arc pulse signal C4. Figure 9 It can be seen that a significant high-frequency signal appears in the peak part of the load current signal C2, which overlaps with the arc frequency band. However, since this characteristic signal corresponds to the high-level part of the window gating signal C1, it is completely shielded and therefore does not appear in the arc characteristic signal C3 and the arc pulse signal C4, thus avoiding malfunction.

[0059] This document has been described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. While the principles of this document have been shown in various embodiments, many modifications to structures, arrangements, proportions, elements, materials, and components particularly suited to specific environments and operational requirements can be used without departing from the principles and scope of this disclosure. These modifications and other changes or alterations will be included within the scope of this document. The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, considerations for this disclosure are to be illustrative rather than restrictive, and all such modifications will be included within its scope. Similarly, advantages, other advantages, and solutions to problems with respect to various embodiments have been described above. However, benefits, advantages, solutions to problems, and any elements that produce these, or make them more explicit, should not be construed as critical, essential, or necessary. The term "comprising" and any other variations thereof, as used herein, are non-exclusive inclusions, meaning that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or not part of that process, method, system, article, or apparatus. Furthermore, the term "coupling" and any other variations thereof, as used herein, refers to a physical connection, electrical connection, magnetic connection, optical connection, communication connection, functional connection, and / or any other connection.

[0060] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of this disclosure. Therefore, the scope of this disclosure should be determined only by the claims.

Claims

1. An arc fault detection circuit, characterized in that, include: The signal acquisition circuit is used to acquire the current on the power supply line and output the first signal; A window gating circuit is used to output a window gating signal corresponding to the first signal. The window gating signal includes a first level signal and a second level signal. The first level signal is used to shield signals in the first signal that correspond to a preset time period. The second level signal is used to retain signals in the first signal that are not corresponding to the preset time period and are greater than the second level. The signal processing circuit is electrically connected to the signal acquisition circuit and the window gating circuit, and is used to generate an arc fault signal based on the window gating signal and the first signal.

2. The arc fault detection circuit according to claim 1, characterized in that, The signal processing circuit includes: The feature extraction sub-circuit is used to extract arc features from the first signal to generate an arc feature signal.

3. The arc fault detection circuit according to claim 1, characterized in that, The signal processing circuit includes: A signal amplification sub-circuit is used to amplify the first signal to obtain a second signal; The feature extraction sub-circuit, electrically connected to the signal amplification sub-circuit, is used to extract arc features from the second signal to generate an arc feature signal.

4. The arc fault detection circuit according to claim 2 or 3, characterized in that, The signal processing circuit includes: A driving pulse sub-circuit, electrically connected to the feature extraction sub-circuit, is used to generate an arc pulse signal based on the arc feature signal.

5. The arc fault detection circuit according to claim 4, characterized in that, The signal processing circuit includes: The pulse counting sub-circuit, electrically connected to the driving pulse sub-circuit, is used to record the number of pulses in the arc pulse signal and generate the arc fault signal based on the number of pulses in the arc pulse signal over a preset time period.

6. The arc fault detection circuit according to claim 1, characterized in that, The window gating circuit includes: The first voltage divider circuit is used to divide the voltage from the power supply line and output a first voltage signal; The second voltage divider circuit is used to divide the voltage from the power supply line and output a second voltage signal; The gating sub-circuit has its input terminal connected to the output terminal of the first voltage divider sub-circuit and its output terminal connected to the output terminal of the second voltage divider sub-circuit. The gating sub-circuit is turned on when the input voltage at its input terminal is within a preset range, and turned off otherwise, thereby outputting the window gating signal.

7. The arc fault detection circuit according to claim 6, characterized in that, The gating sub-circuit includes a first Zener diode, a first transistor, a second transistor, a first protection resistor, and a second protection resistor. The first terminal of the first Zener diode is the input terminal of the gating sub-circuit. The second terminal of the first Zener diode is connected to the first terminal of the first transistor. The second terminal of the first transistor is grounded. The third terminal of the first transistor is connected to the first terminal of the second transistor through the first protection resistor. The first terminal of the second transistor is connected to the first terminal of the second protection resistor. The second terminal of the second protection resistor is connected to the second terminal of the second transistor and the power supply voltage. The third terminal of the second transistor is the output terminal of the gating sub-circuit.

8. The arc fault detection circuit according to claim 6, characterized in that, The gating sub-circuit includes a three-terminal adjustable voltage regulator, a second transistor, a first protection resistor, and a second protection resistor. The first terminal of the three-terminal adjustable voltage regulator is the input terminal of the gating sub-circuit. The second terminal of the three-terminal adjustable voltage regulator is grounded. The third terminal of the three-terminal adjustable voltage regulator is connected to the first terminal of the second transistor through the first protection resistor. The first terminal of the second transistor is connected to the first terminal of the second protection resistor. The second terminal of the second protection resistor is connected to the second terminal of the second transistor and the power supply voltage. The third terminal of the second transistor is the output terminal of the gating sub-circuit.

9. The arc fault detection circuit according to claim 6, characterized in that, The gating sub-circuit includes a first comparator, a first voltage divider resistor, a second voltage divider resistor, and a diode. The non-inverting input of the first comparator is the input of the gating sub-circuit. The inverting input of the first comparator is connected to the first and second voltage divider resistors. The other end of the first voltage divider resistor is connected to the power supply voltage, and the other end of the second voltage divider resistor is grounded. The output of the first comparator is connected to the anode of the diode, and the cathode of the diode is the output of the gating sub-circuit.

10. The arc fault detection circuit according to claim 1, characterized in that, include: An arc fault driving circuit, electrically connected to the signal processing circuit, is used to generate a switch control signal based on the arc fault signal. A switching circuit, electrically connected to the arc fault drive circuit, is used to open or close the input / output switch of the power supply line according to the switch control signal.

11. The arc fault detection circuit according to claim 10, characterized in that, include: The simulated electric arc test circuit has its output terminal connected to the signal acquisition circuit or signal processing circuit to generate a simulated electric arc signal, thereby causing the switching circuit to disconnect the input / output switch of the power supply line according to the simulated electric arc signal.

12. The arc fault detection circuit according to claim 1, characterized in that, include: The power supply circuit includes a rectifier and a second voltage regulator, which are used to rectify, transform and regulate the voltage of the power supply line to supply power to the window gating circuit and the signal processing circuit.

13. The arc fault detection circuit according to claim 1, characterized in that, The signal processing circuit includes: The filter sub-circuit is electrically connected to the signal acquisition circuit and is used to filter and process the first signal before outputting it.

14. The arc fault detection circuit according to claim 1, characterized in that, The signal processing circuit includes a filtering sub-circuit, a feature extraction sub-circuit, and a driving pulse sub-circuit. The window gating circuit is electrically connected to at least one of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and the driving pulse sub-circuit, and is used to shield the signal of the preset time period in the output signal of the signal acquisition circuit, the filtering sub-circuit, the feature extraction sub-circuit, and / or the driving pulse sub-circuit.

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