Display device

Abstract

A display device includes a substrate having a display area and a peripheral area surrounding the display area; a first initialization voltage line on the substrate; an organic film layer on the first initialization voltage line and having a first contact hole exposing at least a portion of the first initialization voltage line; and a bridge wiring on the organic film layer corresponding to the peripheral area and contacting the first initialization voltage line through the first contact hole, wherein the organic film layer corresponding to the peripheral area has a recess or a dummy hole, each of the recess and the dummy hole being adjacent to the first contact hole.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0057189, filed May 13, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] One or more embodiments relate to a display device. BACKGROUND

[0004] Generally, a display device has a configuration in which various layers are stacked. For example, an organic light emitting display device includes an organic light emitting element including a pixel electrode, an intermediate layer including an organic emission layer, and a counter electrode. In addition, a circuit unit for driving the organic light emitting element also has a configuration in which a plurality of wiring layers are stacked and an insulating layer for preventing short circuit between the plurality of wiring layers can be disposed between the plurality of wiring layers. The insulating layer can include an inorganic material or an organic material. On the other hand, because a gas generated from the organic material can not be all discharged and can be partially remaining in the insulating layer including the organic material during a manufacturing process of the display device, outgassing can occur in the insulating layer including the organic material while the display device is being used. In addition, when the display device is used for a long time outdoors, sunlight can decompose the insulating layer including the organic material, and a gas can be generated in the process of decomposition. As described above, when the insulating layer including the organic material generates a gas, the generated gas deteriorates the organic emission layer, and defects such as pixel contraction can occur, thereby reducing the reliability of the display device. Therefore, research has been actively conducted to prevent defects such as pixel contraction due to a gas generated from the insulating layer including the organic material.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the present disclosure, and therefore it can contain information that does not constitute prior art. SUMMARY

[0006] Aspects of embodiments of the present disclosure relate to a display device capable of significantly reducing outgassing from an insulating layer including an organic material, etc. However, these problems are exemplary, and the scope of the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following description, or can be learned by practice of the presented embodiments of the disclosure.

[0008] According to some embodiments of the disclosure, a display device is provided, including: a substrate having a display area and a peripheral area surrounding the display area; a first initialization voltage line on the substrate; an organic film layer on the first initialization voltage line and having a first contact hole exposing at least a portion of the first initialization voltage line; and a bridge wiring on the organic film layer corresponding to the peripheral area and contacting the first initialization voltage line through the first contact hole, wherein the organic film layer corresponding to the peripheral area has a recess or a dummy hole adjacent to the first contact hole.

[0009] In some embodiments, the display device further includes: a second initialization voltage line on the same layer as the first initialization voltage line, wherein the organic film layer further has a second contact hole at least partially exposing the second initialization voltage line, and wherein the bridge wiring contacts the second initialization voltage line through the second contact hole.

[0010] In some embodiments, the bridge wiring includes a first portion extending in the first direction and contacting the first initialization voltage line, and a second portion extending in the first direction and contacting the second initialization voltage line.

[0011] In some embodiments, the recess or the dummy hole is located between the first portion and the second portion.

[0012] In some embodiments, the bridge wiring at least partially overlaps the recess, and includes a stepped portion corresponding to the recess.

[0013] In some embodiments, a vertical distance from the substrate to a portion of an upper surface of the bridge wiring overlapping the recess is less than a vertical distance from the substrate to another portion of the upper surface of the bridge wiring other than the portion overlapping the recess.

[0014] In some embodiments, the display device further includes a connection wiring on the same layer as the bridge wiring.

[0015] In some embodiments, the bridge wiring is integrated with the connection wiring.

[0016] In some embodiments, the connection wiring is bent at least twice in a plan view.

[0017] According to some embodiments of the disclosure, a display device is provided, including: a substrate having a display area and a peripheral area surrounding the display area; a first initialization voltage line on the substrate; a first organic film layer on the first initialization voltage line and having a first contact hole exposing at least a portion of the first initialization voltage line; a second organic film layer on the first organic film layer and including a third contact hole corresponding to the first contact hole; and a bridge wiring on the second organic film layer corresponding to the peripheral area and in contact with the first initialization voltage line, wherein the second organic film layer corresponding to the peripheral area has a first dummy hole adjacent to the first contact hole and the third contact hole.

[0018] In some embodiments, the first organic film layer has a second dummy hole corresponding to the first dummy hole.

[0019] In some embodiments, the display device further includes: a second initialization voltage line on the same layer as the first initialization voltage line, wherein the first organic film layer further has a second contact hole at least partially exposing the second initialization voltage line, wherein the second organic film layer further includes a fourth contact hole corresponding to the second contact hole, and wherein the bridge wiring contacts the second initialization voltage line through the second contact hole and the fourth contact hole.

[0020] In some embodiments, the bridge wiring includes a first portion extending in the first direction and in contact with the first initialization voltage line, and a second portion extending in the first direction and in contact with the second initialization voltage line, and the first dummy hole is located between the first portion and the second portion.

[0021] In some embodiments, the second organic film layer further has a third dummy hole spaced apart from the first dummy hole and located between the first portion and the second portion.

[0022] In some embodiments, the display device further includes a connection wiring on the same layer as the bridge wiring.

[0023] In some embodiments, the display device further includes a light emitting device spaced apart from the bridge wiring in a plan view, the connection wiring is located between the light emitting device and the bridge wiring, and the light emitting device is arranged to correspond to the display area.

[0024] In some embodiments, the light emitting device includes: a pixel electrode on the same layer as the bridge wiring; an intermediate layer on the pixel electrode; and a counter electrode on the intermediate layer.

[0025] According to some embodiments of the disclosure, a display device is provided, including: a substrate having a display area and a peripheral area surrounding the display area; a voltage wiring on the substrate; a first organic film layer on the voltage wiring and having a first contact hole exposing at least a portion of the voltage wiring; a second organic film layer on the first organic film layer and having a third contact hole corresponding to the first contact hole; and a bridge wiring on the second organic film layer corresponding to the peripheral area and in contact with the voltage wiring, wherein the second organic film layer corresponding to the peripheral area has a dummy hole adjacent to the first contact hole and the third contact hole.

[0026] In some embodiments, the display device further includes: a plurality of pixels in the display area, each pixel receiving a first scan signal, a second scan signal, a third scan signal, a data voltage, and an initialization voltage, wherein each of the plurality of pixels includes: a light emitting device; a driving thin film transistor configured to control a size of a current flowing through the light emitting device based on a gate-source voltage; a storage capacitor between a power supply line and a gate of the driving thin film transistor; a scan thin film transistor configured to transfer the data voltage to a source of the driving thin film transistor in response to the second scan signal; a compensation thin film transistor configured to connect a drain of the driving thin film transistor to the gate of the driving thin film transistor in response to the second scan signal; a gate initialization thin film transistor configured to apply the initialization voltage to the gate of the driving thin film transistor in response to the first scan signal; and an anode initialization thin film transistor configured to apply the initialization voltage to an anode of the light emitting device in response to the third scan signal.

[0027] In some embodiments, the voltage wiring is an initialization voltage line configured to transfer the initialization voltage to each of the plurality of pixels.

[0028] Other aspects and features will become apparent from the following detailed description considered in conjunction with the accompanying drawings and the claims, which are not to be limited to those aspects and features expressly set forth in the above summary. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects and features of certain embodiments will become more apparent from the following description considered in connection with the accompanying drawings, in which:

[0030] Figure 1 is a plan view schematically showing a display device according to an embodiment;

[0031] Figure 2 is an equivalent circuit diagram schematically showing one pixel of a display device according to an embodiment;

[0032] Figure 3 is an enlarged plan view schematically showing a portion of a display device according to an embodiment of Figure 1 ;

[0033] Figure 4 is an enlarged plan view schematically showing a portion of a display device according to an embodiment of the present disclosure; Figure 3

[0034] Figure 5A and Figure 5B is an exemplary cross-sectional view of the bridge wiring of Figure 4

[0035] Figure 6 is an exemplary cross-sectional view of the bridge wiring and light emitting device of Figure 4

[0036] Figure 7A , Figure 7B and Figure 7C is an exemplary cross-sectional view of the bridge wiring of Figure 4 DETAILED DESCRIPTION

[0037] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are described below, by referring to the drawings, only, to explain aspects of the present description.

[0038] Various modifications can be made to the present disclosure and various embodiments are possible, and specific embodiments will be illustrated in the accompanying drawings and described in detail in the detailed description. The effects and features of the present disclosure will be clarified by the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, and can be implemented in various forms.

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When described with reference to the drawings, the same or corresponding components will be designated by the same reference numerals, and redundant descriptions thereof will be omitted.

[0040] It will be understood that, although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the inventive concept.

[0041] ​​​​For ease of description, spatially relative terms, such as "beneath", "below", "lower", "bottom", "on", "above", and "upper", can be used herein for describing an element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will be understood that, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0042] For purposes of this disclosure, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ.

[0043] Furthermore, use of "may" throughout this disclosure translates to "one or more embodiments of the inventive concept." Moreover, the term "exemplary" means example or illustrative.

[0044] As used herein, the terms "use", "using", and "used" can be considered synonymous with the terms "utilize", "utilizing", and "utilized", respectively.

[0045] As used herein, the terms "substantially", "approximately", and like terms are used as terms of approximation and not as terms of degree, unless expressly specified otherwise, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0046] In the following embodiments, singular expressions include plural expressions unless the context clearly dictates otherwise.

[0047] In the following embodiments, terms such as "include" or "has" indicate the presence of the described features or components, but do not preclude the presence of one or more other features or components.

[0048] In the following embodiments, when a part of a film, a region, a component, etc. is referred to as being on or above another part, it includes not only when the part is directly above the other part, but also when another film, region, component, etc. is disposed between the part and the other part.

[0049] In the drawings, the size of a component can be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present disclosure is not necessarily limited to what is shown.

[0050] When an embodiment can be variously implemented, a specific process sequence can be performed in an order different from that described. For example, two processes described in succession can be performed substantially simultaneously, or can be performed in an order opposite to that described.

[0051] In the following embodiments, when a film, a region, a component, etc. is connected, it includes a case where the film, the region, the component is directly connected, and / or a case where another film, region, component, etc. is disposed between them and is indirectly connected. For example, throughout the present specification, when a film, a region, a component, etc. is electrically connected, the film, the region, the component, etc. is directly electrically connected, or the film, the region, the component, etc. has another film, region, component, etc. disposed therebetween and is indirectly electrically connected.

[0052] The X-axis, the Y-axis, and the Z-axis are not limited to three axes on a Cartesian coordinate system, and can be interpreted in a broad sense including them. For example, the X-axis, the Y-axis, and the Z-axis can be orthogonal to each other, but can refer to different directions that are not orthogonal to each other.

[0053] Figure 1 is a plan view schematically showing a display device according to an embodiment.

[0054] Reference Figure 1 The display device 1 includes a display region DA for displaying an image and a peripheral region PA arranged around the display region DA. The display device 1 can provide (e.g., display) an image to the outside using light emitted from the display region DA. Of course, since the display device 1 includes the substrate 100, the substrate 100 can include such a display region DA and a peripheral region PA.

[0055] The substrate 100 can include various materials, such as glass, metal, and / or plastic, etc. According to an embodiment, the substrate 100 can include a flexible material. Here, the flexible material can refer to a material that is well curved, foldable, or rollable. The substrate 100 of the flexible material can include ultra-thin glass, metal, and / or plastic, etc.

[0056] A plurality of pixels PX including various display elements such as organic light emitting diodes (OLEDs) can be arranged in the display area DA of the substrate 100. The plurality of pixels PX can be provided and arranged in various forms such as a stripe arrangement, a pentile arrangement, and a mosaic arrangement to implement an image.

[0057] When the display area DA is viewed in a planar shape, the display area DA can be provided in a rectangular shape as shown in FIG. 1A. Figure 1 In another embodiment, the display area DA can be provided in a polygonal shape such as a triangular shape, a pentagonal shape, and a hexagonal shape, a circular shape, an elliptical shape, or an irregular shape.

[0058] The peripheral area PA of the substrate 100 is arranged around (e.g., surrounding) the display area DA and can be an area in which an image is not displayed. In the peripheral area PA, various wirings configured to transmit electrical signals to be applied to the display area DA and pads attached to a printed circuit board or a driver IC chip can be disposed.

[0059] Figure 2 FIG. 1B is a circuit diagram schematically illustrating one pixel of a display apparatus according to an embodiment.

[0060] Referring to FIG. 1B, one pixel PX can include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. Figure 2 As an example, as shown in FIG. 1B, the pixel circuit PC includes first through seventh thin film transistors T1 through T7 and a storage capacitor Cst. The first through seventh thin film transistors T1 through T7 and the storage capacitor Cst are connected to first through third scan lines SL, SL-1, and SL+1 configured to transmit first through third scan signals Sn, Sn-1, and Sn+1, respectively, a data line DL configured to transmit a data voltage Dm, an emission control line EL configured to transmit an emission control signal En, a driving voltage line PL configured to transmit a driving voltage ELVDD, an initialization voltage line VL configured to transmit an initialization voltage Vint, and a common electrode to which a common voltage ELVSS is applied, respectively.

[0061] Figure 2 The first thin film transistor T1 can be a driving transistor in which the magnitude of a drain current is determined according to a gate-source voltage, and the second through seventh thin film transistors T2 through T7 can be switching transistors that are turned on / off according to a gate-source voltage (essentially a gate voltage).

[0062] The first thin film transistor T1 can be a driving transistor in which the magnitude of a drain current is determined according to a gate-source voltage, and the second through seventh thin film transistors T2 through T7 can be switching transistors that are turned on / off according to a gate-source voltage (essentially a gate voltage).

[0063] ​The first thin-film transistor T1 can be referred to as a driving thin-film transistor, the second thin-film transistor T2 can be referred to as a scanning thin-film transistor, the third thin-film transistor T3 can be referred to as a compensation thin-film transistor, the fourth thin-film transistor T4 can be referred to as a gate initialization thin-film transistor, the fifth thin-film transistor T5 can be referred to as a first emission control thin-film transistor, the sixth thin-film transistor T6 can be referred to as a second emission control thin-film transistor, and the seventh thin-film transistor T7 can be referred to as an anode initialization thin-film transistor.

[0064] The storage capacitor Cst is connected between the driving voltage line PL and the driving gate G1 of the driving thin-film transistor T1. The storage capacitor Cst can have an upper electrode CE2 connected to the driving voltage line PL and a lower electrode CE1 connected to the driving gate G1 of the driving thin-film transistor T1.

[0065] The driving thin-film transistor T1 can control the size of the driving current I OLED flowing from the driving voltage line PL to the organic light emitting diode OLED according to a gate-source voltage. The driving thin-film transistor T1 can include the driving gate G1 connected to the lower electrode CE1 of the storage capacitor Cst, the driving source S1 connected to the driving voltage line PL through the first emission control thin-film transistor T5, and the driving drain D1 connected to the organic light emitting diode OLED through the second emission control thin-film transistor T6.

[0066] The driving thin-film transistor T1 can output the driving current I OLED to the organic light emitting diode OLED according to the gate-source voltage. The size of the driving current I OLED is determined based on a difference between the gate-source voltage and a threshold voltage of the driving thin-film transistor T1. The organic light emitting diode OLED can receive the driving current I OLED from the driving thin-film transistor T1 and can emit light with a luminance corresponding to the size of the driving current I OLED .

[0067] The scanning thin-film transistor T2 can transmit the data voltage Dm to the driving source S1 of the driving thin-film transistor T1 in response to the first scan signal Sn. The scanning thin-film transistor T2 can include the scanning gate G2 connected to the first scan line SL, the scanning source S2 connected to the data line DL, and the scanning drain D2 connected to the driving source S1 of the driving thin-film transistor T1.

[0068] A compensation thin film transistor T3 is connected in series between the driving drain D1 of the driving thin film transistor T1 and the driving gate G1, and connects the driving drain D1 of the driving thin film transistor T1 to the driving gate G1 in response to a first scan signal Sn. The compensation thin film transistor T3 can include a compensation gate G3 connected to the first scan line SL, a compensation source S3 connected to the driving drain D1 of the driving thin film transistor T1, and a compensation drain D3 connected to the driving gate G1 of the driving thin film transistor T1. Although Figure 2 It is shown that the compensation thin film transistor T3 includes two thin film transistors connected in series to each other, but the compensation thin film transistor T3 can consist of one thin film transistor.

[0069] The gate initialization thin film transistor T4 applies an initialization voltage Vint to the driving gate G1 of the driving thin film transistor T1 in response to a second scan signal Sn-1. The gate initialization thin film transistor T4 can include a first initialization gate G4 connected to the second scan line SL-1, a first initialization source S4 connected to the driving gate G1 of the driving thin film transistor T1, and a first initialization drain D4 connected to an initialization voltage line VL. Figure 2 In the embodiment of the disclosure, the gate initialization thin film transistor T4 is shown to include two thin film transistors connected in series to each other; however, the embodiment of the disclosure is not limited thereto, and the gate initialization thin film transistor T4 can consist of one thin film transistor.

[0070] The anode initialization thin film transistor T7 applies an initialization voltage Vint to the anode of the organic light emitting diode OLED in response to a third scan signal Sn+1. The anode initialization thin film transistor T7 can include a second initialization gate G7 connected to the third scan line SL+1, a second initialization source S7 connected to the anode of the organic light emitting diode OLED, and a second initialization drain D7 connected to the initialization voltage line VL.

[0071] The first emission control thin film transistor T5 can connect the driving voltage line PL to the driving source S1 of the driving thin film transistor T1 in response to an emission control signal En. The first emission control thin film transistor T5 can include a first emission control gate G5 connected to an emission control line EL, a first emission control source S5 connected to the driving voltage line PL, and a first emission control drain D5 connected to the driving source S1.

[0072] The second emission control thin-film transistor T6 can, in response to the emission control signal En, connect the driving drain D1 of the driving thin-film transistor T1 to the anode of the organic light-emitting diode (OLED). The second emission control thin-film transistor T6 may include a second emission control gate G6 connected to the emission control line EL, a second emission control source S6 connected to the driving drain D1 of the driving thin-film transistor T1, and a second emission control drain D6 connected to the anode of the organic light-emitting diode (OLED).

[0073] The second scan signal Sn-1 can be substantially synchronized with the first scan signal Sn of the previous row of pixels. The third scan signal Sn+1 can be substantially synchronized with the first scan signal Sn. According to another example, the third scan signal Sn+1 can be substantially synchronized with the first scan signal Sn in the next row of pixels.

[0074] In the current embodiment, the first thin-film transistor T1 to the seventh thin-film transistor T7 may include a semiconductor layer comprising silicon. For example, the first thin-film transistor T1 to the seventh thin-film transistor T7 may include a semiconductor layer comprising low-temperature polycrystalline silicon (LTPS). Polycrystalline silicon material has a high electron mobility (over 100 cm⁻¹). 2 Low power consumption and excellent reliability. As another example, the semiconductor layers of the first thin-film transistor T1 to the seventh thin-film transistor T7 may include oxides of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer may be an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer, etc. As another example, some semiconductor layers of the first thin-film transistor T1 to the seventh thin-film transistor T7 may include low-temperature polycrystalline silicon (LTPS), and some other semiconductor layers may include oxide semiconductors (e.g., IGZO).

[0075] The detailed operation of a pixel PX of the display device 1 according to an embodiment will be described in detail below. Figure 2 As shown, it is assumed that the first thin-film transistor T1 to the seventh thin-film transistor T7 are p-type MOSFETs; however, the embodiments of this disclosure are not limited thereto, and any one of the first thin-film transistor T1 to the seventh thin-film transistor T7 may also be an n-type MOSFET if the corresponding drive signal is changed accordingly.

[0076] First, when a high-level transmit control signal En is received, the first transmit control thin-film transistor T5 and the second transmit control thin-film transistor T6 are turned off, and the driving thin-film transistor T1 stops driving current I. OLEDthe output of the first scan signal Sn and the organic light emitting diode OLED stops emitting light.

[0077] Thereafter, during a gate initialization period in which the low-level second scan signal Sn-1 is received, the gate initialization thin film transistor T4 is turned on, and an initialization voltage Vint is applied to the driving gate G1 of the driving thin film transistor T1, i.e., the lower electrode CE1 of the storage capacitor Cst. A difference between the driving voltage ELVDD and the initialization voltage Vint, i.e., ELVDD-Vint, is stored in the storage capacitor Cst.

[0078] Thereafter, during a data write period in which the low-level first scan signal Sn is received, the scan thin film transistor T2 and the compensation thin film transistor T3 are turned on, and the driving source S1 of the driving thin film transistor T1 receives a data voltage Dm. The driving thin film transistor T1 is diode-connected by the compensation thin film transistor T3, and is forwardly compensated. The gate voltage of the driving thin film transistor T1 rises on the initialization voltage Vint. When the gate voltage of the driving thin film transistor T1 becomes equal to a data compensation voltage (Dm-|Vth|) obtained by subtracting a threshold voltage Vth of the driving thin film transistor T1 from the data voltage Dm, the driving thin film transistor T1 is turned off, and the rising of the gate voltage of the driving thin film transistor T1 is stopped. Accordingly, the storage capacitor Cst stores a difference (ELVDD-Dm+|Vth|) between the driving voltage ELVDD and the data compensation voltage (Dm-|Vth|).

[0079] In addition, during an anode initialization period when the low-level third scan signal Sn+1 is received, the anode initialization thin film transistor T7 is turned on, and the initialization voltage Vint is applied to the anode of the organic light emitting diode OLED. By applying the initialization voltage Vint to the anode of the organic light emitting diode OLED, the organic light emitting diode OLED is completely not emitting light (e.g., completely turned off or dimmed), and thus a phenomenon that the organic light emitting diode OLED is weakly emitting light can be eliminated even if the pixel PX receives the data voltage Dm corresponding to a black gray scale in the next frame.

[0080] The first scan signal Sn and the third scan signal Sn+1 can be substantially synchronized, and in this case, the data write period and the anode initialization period can be the same period.

[0081] Then, when receiving the low-level emission control signal En, the first emission control thin-film transistor T5 and the second emission control thin-film transistor T6 are turned on, and the drive thin-film transistor T1 can output a drive current I corresponding to a voltage (i.e., a voltage (ELVDD-Dm) obtained by subtracting a threshold voltage (|Vth|) of the drive thin-film transistor T1 from a source-gate voltage (ELVDD-Dm+|Vth|) of the drive thin-film transistor T1) stored in the storage capacitor Cst OLED , and the organic light-emitting diode OLED can emit light having a luminance corresponding to the size of the drive current I OLED .

[0082] The operation of one pixel PX of the display device 1 is described assuming that the first thin-film transistor T1 to the seventh thin-film transistor T7 are p-type MOSFETs, but as another example, some of the first thin-film transistor T1 to the seventh thin-film transistor T7 can include p-type MOSFETs, and some can include n-type MOSFETs.

[0083] Figure 3 is an enlarged plan view schematically showing a portion of the display device of Figure 1 according to an embodiment.

[0084] Figure 3 is an enlarged first area AR1 of the display device 1 of Figure 1 , and the first area AR1 corresponds to a boundary between the display area DA and the peripheral area PA.

[0085] Referring to Figure 3 , the display device 1 can include a plurality of light-emitting devices 200 arranged in the display area DA, and can include an initialization bridge wiring VB and a drive bridge wiring EB as bridge wirings, a first pad connection wiring PCL1 and a second pad connection wiring PCL2, and the like arranged in the peripheral area PA.

[0086] Each of the plurality of light-emitting devices 200 can be an organic light-emitting diode OLED including an anode and a cathode. As shown in Figure 3 , the plurality of light-emitting devices 200 can be arranged in a row direction X and / or a column direction Y. For example, the plurality of light-emitting devices 200 can be arranged in a matrix form. As another example, the plurality of light-emitting devices 200 can be arranged to have various suitable structures, such as a stripe structure, a mosaic array structure, a delta array structure, and a pentile matrix structure. Because the plurality of pixels PX (see Figure 1Each of the initialization bridge wirings VB includes a plurality of light emitting devices 200, so a plurality of pixels PX can also be arranged in various suitable structures such as a stripe structure, a mosaic array structure, a triangular array structure, and a pentile matrix structure.

[0087] The initialization bridge wiring VB can include a plurality of portions each extending in the +Y direction, and each of the plurality of portions can transmit an initialization voltage Vint (see Figure 2 ) to the plurality of pixels PX through each of a plurality of contact holes VCNT (hereinafter referred to as initialization contact holes).

[0088] The initialization bridge wiring VB can be a light-transmitting electrode (e.g., a semi-light-transmitting electrode) or a reflective electrode. In some embodiments, the initialization bridge wiring VB can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and / or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The initialization bridge wiring VB can have a plurality of holes H, and for example, the plurality of holes H can be degassing holes.

[0089] The initialization bridge wiring VB can be connected to the first pad connection wiring PCL1 through a first pad contact hole PCNT1. The first pad connection wiring PCL1 can extend in a first direction (e.g., the Y direction), and can be connected to a pad unit arranged at one side of the display device 1. The pad unit can be exposed without being covered by an insulating layer, and electrically connected to a printed circuit board. The printed circuit board can transmit a signal or power of a controller to the display device 1.

[0090] For example, the initialization voltage Vint can be supplied by a signal of a controller transmitted from the printed circuit board. The initialization voltage Vint can be transmitted to the initialization bridge wiring VB through the first pad connection wiring PCL1 connected to the pad unit. The initialization bridge wiring VB can transmit the initialization voltage Vint to each of the plurality of pixels PX through each of the plurality of initialization contact holes VCNT. That is, the initialization bridge wiring VB can transmit the initialization voltage Vint received from the printed circuit board and the pad unit to each of the plurality of pixels PX through the first pad connection wiring PCL1. A portion in which the initialization bridge wiring VB is arranged can be understood as a portion in which the initialization voltage Vint is input.

[0091] The drive bridge wiring EB can be arranged at the left and / or right of the initialization bridge wiring VB. Figure 3 It is illustrated that the drive bridge wiring EB is arranged at opposite sides of the initialization bridge wiring VB; however, embodiments of the present disclosure are not limited thereto, and the drive bridge wiring EB can be arranged at only one side (e.g., the left side) of the initialization bridge wiring VB.

[0092] The drive bridge wiring EB can transmit a drive voltage ELVDD (see Figure 2 ) to the drive voltage supply wiring arranged below the drive bridge wiring EB through a drive contact hole ECNT extending in the X direction. The drive bridge wiring EB can include the same or substantially the same material as the initialization bridge wiring VB. For example, the drive bridge wiring EB can be a light-transmissive electrode (e.g., a semi-light-transmissive electrode) or a reflective electrode. In addition, the drive bridge wiring EB can be provided with a plurality of holes H, which can be, for example, outgassing holes.

[0093] The drive bridge wiring EB can be connected to the second pad connection wiring PCL2 through the second pad contact hole PCNT2. The second pad connection wiring PCL2 can extend in the first direction and can be connected to a pad unit arranged at one side of the display device 1. The pad unit can be exposed without being covered by the insulating layer and electrically connected to a printed circuit board. The drive voltage ELVDD can be supplied by a signal of a controller received from the printed circuit board. The drive voltage ELVDD can be transmitted to the drive bridge wiring EB through the second pad connection wiring PCL2 connected to the pad unit. The drive bridge wiring EB can transmit the drive voltage ELVDD received from the printed circuit board and the pad unit to the drive voltage supply wiring through the drive contact hole ECNT. That is, the drive bridge wiring EB can transmit the drive voltage ELVDD received from the printed circuit board and the pad unit to the drive voltage supply wiring through the second pad connection wiring PCL2, and the drive voltage ELVDD can be transmitted from the drive voltage supply wiring to each of the plurality of pixels PX. The portion in which the drive bridge wiring EB is arranged can be understood as a portion in which the drive voltage ELVDD is input.

[0094] A gate driving circuit, a multiplexer (mux), a demultiplexer (demux), and various wirings can be arranged below the initialization bridge wiring VB and the drive bridge wiring EB.

[0095] The gate driving circuit can provide a first scan signal Sn (see Figure 2 ) to each of the pixels PX through a first scan line SL (see Figure 2 ). In addition, the gate driving circuit can provide an emission control signal En (see Figure 2 ) to each of the pixels PX through an emission control line EL (see Figure 2 ). The multiplexer corresponds to a device for selecting one of several analog or digital input signals and transferring the selected input signal to one line, and the demultiplexer corresponds to a device for receiving one input signal and selecting one of a plurality of data output lines. The various wirings can correspond to a common voltage supply wiring, a data connection wiring, and a drive voltage connection wiring, etc.

[0096] It is appreciated that the initialization bridge line VB and the drive bridge line EB function as a bridge to avoid the gate driver circuit, the multiplexer, and the demultiplexer arranged below the initialization bridge line VB and the drive bridge line EB, and to transmit the initialization voltage Vint and the drive voltage ELVDD to the display area DA, respectively.

[0097] Although Figure 3 While the initialization bridge line VB and the drive bridge line EB are shown to be arranged at the lower end of the display device 1, as another example, the initialization bridge line VB and the drive bridge line EB can also be arranged at the other side of the display device 1. In addition, a plurality of initialization bridge lines VB and a plurality of drive bridge lines EB can be formed. That is, a plurality of portions can receive input of the initialization voltage Vint and the drive voltage ELVDD. For example, four initialization bridge lines VB and four drive bridge lines EB can be arranged at the lower end of the display device 1.

[0098] Figure 4 is an enlarged plan view schematically showing Figure 3 a portion of the display device of Figure 5A and Figure 5B is an exemplary cross-sectional view of the bridge line of Figure 4 taken along the line I-I'. Figure 6 is an exemplary cross-sectional view of the bridge line and the light emitting device of Figure 4 taken along the line II-II'.

[0099] Referring to Figure 4 , the display device 1 (see Figure 1 ) can include a plurality of light emitting devices 200 arranged in a display area DA, an initialization connection line VCL as a connection line, and an initialization bridge line VB arranged in a peripheral area PA.

[0100] As shown in Figure 4 , the plurality of light emitting devices 200 can be arranged to be spaced apart from the initialization bridge line VB, and the initialization connection line VCL is between the plurality of light emitting devices 200 and the initialization bridge line VB. The plurality of light emitting devices 200 can be arranged in various suitable structures such as a stripe structure, a mosaic array structure, a triangular array structure, and a pentile matrix structure.

[0101] The initialization connection line VCL can be arranged adjacent to the plurality of light emitting devices 200, and can include the same or substantially the same material as the initialization bridge line VB. For example, the initialization connection line VCL can be a light-transmissive electrode (e.g., a semi-light-transmissive electrode) or a reflective electrode.

[0102] The initialization connection wiring VCL can be connected to each portion of the initialization bridging wiring VB extending in the +Y direction. For example, each of the first portion P1 and the second portion P2 of the initialization bridging wiring VB can extend in the +Y direction and can be connected to the initialization connection wiring VCL. The initialization connection wiring VCL can be integrated with the initialization bridging wiring VB. Therefore, like the initialization bridging wiring VB, the initialization connection wiring VCL can initialize the voltage Vint (see [link to initialization connection wiring]). Figure 2 Transmitted to multiple pixel PX (see Figure 1 Each of them.

[0103] like Figure 4 As shown in the plan view, the initialization connection wiring VCL can have a shape with at least two bends and can be arranged to avoid multiple light-emitting devices 200. For example, in the plan view, the initialization connection wiring VCL can not overlap with the multiple light-emitting devices 200 and can be wired around the multiple light-emitting devices 200. In addition, the initialization connection wiring VCL can have a mesh structure. The initialization connection wiring VCL and the initialization bridging wiring VB can each be connected to the initialization voltage line VL, which is a voltage wiring arranged below the initialization connection wiring VCL and the initialization bridging wiring VB, through each of the multiple initialization contact holes VCNT. In addition, since the initialization bridging wiring VB has multiple parts, the initialization connection wiring VCL and the initialization bridging wiring VB can be connected to different initialization voltage lines VL. For example, the first part P1 of the initialization bridging wiring VB can be connected to the first initialization voltage line VL1 through the first initialization contact hole VCNT1, and the second part P2 of the initialization bridging wiring VB can be connected to the second initialization voltage line VL2 through the second initialization contact hole VCNT2. Additionally, the initialization voltage line VL can extend in the X or Y direction, and the initialization voltage Vint can be transmitted to each of the multiple pixels PX via the initialization voltage line VL.

[0104] In an embodiment, the display device 1 may include an organic film layer 117 disposed on a substrate 100. Initialization connection wiring VCL and initialization bridging wiring VB may both be disposed on the organic film layer 117, and the organic film layer 117 may have multiple initialization contact holes VCNT. The organic film layer 117 corresponding to the peripheral region PA may have a groove GR or a dummy hole DH adjacent to the multiple initialization contact holes VCNT. In other words, the organic film layer 117 may have a groove GR or a dummy hole DH corresponding to the portion of the peripheral region PA surrounding the multiple initialization contact holes VCNT.

[0105] The groove GR or the dummy hole DH formed in the organic film layer 117 can be arranged between portions of the initialization bridge wiring VB, each of the portions of the initialization bridge wiring VB extending in the +Y direction. For example, the groove GR or the dummy hole DH can be arranged between a first portion P1 of the initialization bridge wiring VB and a second portion P2 of the initialization bridge wiring VB.

[0106] Hereinafter, the configuration included in the display device 1 will be described in more detail with reference to Figure 5A , Figure 5B and Figure 6 The arrangement relationship between the initialization bridge wiring VB, the initialization voltage line VL, the groove GR, and the dummy hole DH will be described in more detail according to the stacked structure.

[0107] The substrate 100 can include glass or a polymer resin. The polymer resin includes polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate, etc. The substrate 100 including the polymer resin can have a flexible, rollable, or bendable characteristic. The substrate 100 can be a multi-layer structure including a layer including the above-described polymer resin and an inorganic layer.

[0108] The buffer layer 111 can reduce or prevent penetration of foreign matter, moisture, or external air from the bottom of the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 can include an inorganic material such as an oxide or a nitride, or an organic material, or an organic-inorganic composite, and can be a single layer or a multi-layer structure of inorganic materials and organic materials.

[0109] A barrier layer can be further included between the substrate 100 and the buffer layer 111. The barrier layer can be used to prevent or reduce penetration of impurities from the substrate 100, etc., into the semiconductor layer A. The barrier layer can include an inorganic material such as an oxide or a nitride, or an organic material, or an organic-inorganic composite, and can be a single layer or a multi-layer structure of inorganic materials and organic materials.

[0110] The semiconductor layer A can be arranged on the buffer layer 111 corresponding to the display area DA. The semiconductor layer A can include amorphous silicon and / or polycrystalline silicon, etc. In another embodiment, the semiconductor layer A can include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0111] The semiconductor layer A can include a channel region C and a source region S and a drain region D arranged on opposite sides of the channel region C. The semiconductor layer A can include a single layer or multiple layers.

[0112] The gate insulating layer 113 can be stacked and arranged on the substrate 100 to cover the semiconductor layer A. The gate insulating layer 113 can include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2), etc.

[0113] The gate electrode G can be arranged on the gate insulating layer 113 corresponding to the display area DA to at least partially overlap with the semiconductor layer A, and a gate layer GAT corresponding to the peripheral area PA can be arranged on the gate insulating layer 113. The gate electrode G and the gate layer GAT can each be formed of a single layer or multiple layers of one or more metals selected from the group consisting of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In an embodiment, the gate layer GAT can correspond to various wirings such as a common voltage supply wiring, a data connection wiring, and a driving voltage connection wiring, etc. In Figure 5A In the embodiment, the gate layer GAT covers the entire surface of the gate insulating layer 113; however, embodiments of the present disclosure are not limited thereto. For example, as shown in Figure 6 In the embodiment, the gate layer GAT is patterned together with the gate electrode G.

[0114] The interlayer insulating layer 115 can be arranged on the gate insulating layer 113 to cover the gate electrode G and the gate layer GAT. The interlayer insulating layer 115 can include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2), etc.

[0115] A source electrode, a drain electrode, a data line, or an initialization voltage line VL, etc. can be arranged on the interlayer insulating layer 115. The source electrode, the drain electrode, the data line, and the initialization voltage line VL can include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), etc. and can be configured to include multiple layers or a single layer of the above-described materials. For example, the source electrode, the drain electrode, the data line, and the initialization voltage line VL can have a multi-layer structure of Ti / Al / Ti. The source electrode and the drain electrode can be connected to the source region S and the drain region D of the semiconductor layer A, respectively, through contact holes.Figure 6 The cross-sectional view shown in FIG. 3 is taken along the line II-II' of FIG. 2, and thus, the initialization voltage line VL is shown in a broken manner. However, the initialization voltage line VL can continuously extend in the Y direction, and the initialization voltage Vint can be transmitted to each of the plurality of pixels PX arranged in the same column through the initialization voltage line VL. Figure 4

[0116] The source electrode, the drain electrode, the data line, and the initialization voltage line VL can be covered by an inorganic protective layer. The inorganic protective layer can be a single layer or multiple layers of silicon nitride (SiNX) and / or silicon oxide (SiOX). The inorganic protective layer can be introduced to cover and protect some of the wiring lines arranged on the interlayer insulating layer 115.

[0117] The organic film layer 117 is arranged to cover the source electrode, the drain electrode, the data line, and the initialization voltage line VL, and can have anode contact holes ACNT for connecting the thin film transistor TFT to the pixel electrode 210. The thin film transistor TFT and the pixel electrode 210 can be arranged in the display area DA. In addition, the organic film layer 117 has a plurality of initialization contact holes VCNT for connecting portions of the initialization bridge wiring VB and the initialization voltage line VL, each of which is arranged in the peripheral area PA. The organic film layer 117 has a plurality of initialization contact holes VCNT for connecting portions (each of which extends in the +Y direction) of the initialization bridge wiring VB and a plurality of initialization voltage lines VL. For example, the organic film layer 117 has a first initialization contact hole VCNT1 connecting a first portion P1 of the initialization bridge wiring VB to a first initialization voltage line VL1 and a second initialization contact hole VCNT2 connecting a second portion P2 of the initialization bridge wiring VB to a second initialization voltage line VL2.

[0118] In an embodiment, as shown in FIG. 3, the organic film layer 117 corresponding to the peripheral area PA can have a groove GR adjacent to each of the plurality of initialization contact holes VCNT, or as shown in FIG. 4, the organic film layer 117 corresponding to the peripheral area PA can have a dummy hole DH adjacent to each of the plurality of initialization contact holes VCNT. In other words, the organic film layer 117 can have a groove GR or a dummy hole DH corresponding to a portion of the peripheral area PA surrounding the plurality of initialization contact holes VCNT. Figure 5A Figure 5B In an embodiment, as shown in FIG. 3, the organic film layer 117 corresponding to the peripheral area PA can have a groove GR adjacent to each of the plurality of initialization contact holes VCNT, or as shown in FIG. 4, the organic film layer 117 corresponding to the peripheral area PA can have a dummy hole DH adjacent to each of the plurality of initialization contact holes VCNT. In other words, the organic film layer 117 can have a groove GR or a dummy hole DH corresponding to a portion of the peripheral area PA surrounding the plurality of initialization contact holes VCNT.

[0119] ​​The groove GR or the dummy hole DH formed in the organic film layer 117 can be arranged between portions of the initialization bridge wiring VB, each of the portions of the initialization bridge wiring VB extending in the +Y direction. For example, the groove GR or the dummy hole DH can be arranged between a first portion P1 of the initialization bridge wiring VB and a second portion P2 of the initialization bridge wiring VB.

[0120] When the organic film layer 117 corresponding to the peripheral area PA includes the groove GR, the organic film layer 117 can be formed by a hardening drying process by using a half-tone mask or a slit mask.

[0121] The organic film layer 117 can be formed of a single layer or multiple layers of organic material and provide a flat top surface. The organic film layer 117 is a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), poly(methyl methacrylate) (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, and a mixture thereof.

[0122] The light emitting device 200, the initialization bridge wiring VB, and the initialization connection wiring VCL are arranged on the organic film layer 117. The light emitting device 200 includes a pixel electrode 210, an intermediate layer 220 including an organic emission layer, and a counter electrode 230.

[0123] In an embodiment, as shown in Figure 6 The initialization bridge wiring VB can at least partially overlap the groove GR formed in the organic film layer 117 and can have a stepped portion (e.g., a step having a height st) due to the groove GR, as shown in

[0124] In Figure 6 , the organic film layer 117 is shown to include the groove GR disposed in the -Y direction from the first portion P1 of the initialization bridge wiring VB; however, embodiments of the present disclosure are not limited thereto. For example, as shown in Figure 5A and Figure 5BAs shown in FIG. 1, the organic film layer 117 can also have a groove GR or dummy hole DH located only between the first portion P1 and the second portion P2 of the initialization bridge wiring VB. The groove GR or dummy hole DH formed in a portion extending in the -Y direction from the first portion P1 of the initialization bridge wiring VB can be omitted.

[0125] The pixel electrode 210, the initialization bridge wiring VB, and the initialization connection wiring VCL can be a light-transmissive electrode (e.g., a semi-light-transmissive electrode) or a reflective electrode. In some embodiments, the pixel electrode 210, the initialization bridge wiring VB, and the initialization connection wiring VCL can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and / or a compound thereof, etc., and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210, the initialization bridge wiring VB, and the initialization connection wiring VCL can be provided with ITO / Ag / ITO.

[0126] The pixel-defining layer 119 can be arranged on the organic film layer 117. In addition, the pixel-defining layer 119 can function to prevent or greatly reduce the occurrence of an arc at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 located on top of the pixel electrode 210.

[0127] The pixel-defining layer 119 is at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and can be formed by a method such as spin coating.

[0128] The intermediate layer 220 can be arranged in the opening OP formed by the pixel-defining layer 119, and can include an organic emission layer. The organic emission layer can include an organic material including a fluorescent or phosphorescent material that emits red light, green light, blue light, or white light. The organic emission layer can be a low molecular organic material or a high molecular organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) can be selectively further arranged above and below the organic emission layer.

[0129] The counter electrode 230 can be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 can be a transparent or semi-transparent electrode, and can include a metal thin film having a small work function, including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. In addition, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be further disposed on the metal thin film. The counter electrode 230 can be disposed over the display area DA, and can be disposed over the intermediate layer 220 and the pixel definition layer 119. The counter electrode 230 can be integrally formed with respect to a plurality of organic light emitting diodes (OLEDs), and can correspond to the plurality of pixel electrodes 210.

[0130] Because the organic light emitting device can be easily damaged by moisture or oxygen from the outside, an encapsulation layer can cover the organic light emitting device to protect the organic light emitting device. The encapsulation layer can extend to at least a portion of the peripheral area PA while covering the display area DA. The encapsulation layer can include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0131] As described above, in embodiments, the organic film layer 117 corresponding to the peripheral area PA can have a groove GR or a dummy hole DH adjacent to each of the plurality of initialization contact holes VCNT. In other words, the organic film layer 117 can have a groove GR or a dummy hole DH corresponding to a portion of the peripheral area PA surrounding the plurality of initialization contact holes VCNT.

[0132] As a comparative example, the organic film layer corresponding to the peripheral area can not have a groove or a dummy hole. In this case, outgassing can occur from the organic film layer made of an organic material, and defects such as pixel contraction can occur due to deterioration of the organic emission layer by the generated gas, thereby reducing the reliability of the display device. In particular, in pixels disposed adjacent to a portion to which an initialization voltage is input, pixel contraction due to outgassing of the organic film layer can frequently occur. The reason is as follows. As shown in FIG. 1, the initialization voltage and the driving voltage can be transmitted to the pixels through the bridge wiring. The bridge wiring can transmit the initialization voltage and the driving voltage to the pixels through the contact holes. The contact hole formed to transmit the initialization voltage can have a smaller area and volume than the contact hole formed to transmit the driving voltage. In addition, the contact hole formed to transmit the initialization voltage can be disposed closer to the display area than the contact hole formed to transmit the driving voltage. Because the contact hole formed to transmit the initialization voltage has a smaller area and volume than the contact hole formed to transmit the driving voltage, many organic film layers are distributed around the contact hole formed to transmit the initialization voltage, and thus defects such as pixel contraction due to outgassing of the organic film layer can occur more frequently. Figure 3 As a comparative example, the organic film layer corresponding to the peripheral area can not have a groove or a dummy hole. In this case, outgassing can occur from the organic film layer made of an organic material, and defects such as pixel contraction can occur due to deterioration of the organic emission layer by the generated gas, thereby reducing the reliability of the display device. In particular, in pixels disposed adjacent to a portion to which an initialization voltage is input, pixel contraction due to outgassing of the organic film layer can frequently occur. The reason is as follows. As shown in FIG. 1, the initialization voltage and the driving voltage can be transmitted to the pixels through the bridge wiring. The bridge wiring can transmit the initialization voltage and the driving voltage to the pixels through the contact holes. The contact hole formed to transmit the initialization voltage can have a smaller area and volume than the contact hole formed to transmit the driving voltage. In addition, the contact hole formed to transmit the initialization voltage can be disposed closer to the display area than the contact hole formed to transmit the driving voltage. Because the contact hole formed to transmit the initialization voltage has a smaller area and volume than the contact hole formed to transmit the driving voltage, many organic film layers are distributed around the contact hole formed to transmit the initialization voltage, and thus defects such as pixel contraction due to outgassing of the organic film layer can occur more frequently.

[0133] However, as shown in the embodiments, the organic film layer 117 corresponding to the peripheral area PA can have the groove GR or the dummy hole DH arranged adjacent to the initialization contact hole VCNT which connects the initialization bridge wiring VB for transmitting the initialization voltage Vint to the initialization voltage line VL. In other words, the organic film layer 117 can have the groove GR or the dummy hole DH corresponding to a portion of the peripheral area PA surrounding the initialization contact hole VCNT. In this case, because the organic film layer 117 adjacent to the light emitting device 200 arranged in the display area DA is partially removed due to the groove GR or the dummy hole DH, the volume of the organic matter in the display device 1 is reduced, and thus, the outgassing of the organic matter can be significantly reduced. Therefore, even if the display device 1 is exposed to sunlight for a long time, the decomposition of the organic matter caused by the sunlight can be prevented or significantly reduced, so that the defects such as pixel shrinkage due to the outgassing can be prevented or greatly reduced. The reliability of the display device 1 can be improved.

[0134] Figure 7A 、 Figure 7B and Figure 7C is an exemplary cross-sectional view of the bridge wiring of Figure 4 In Figure 7A 、 Figure 7B and Figure 7C , the same reference numerals as in Figure 5A and Figure 5B denote the same members, and a repeated description thereof will be omitted.

[0135] Referring to Figure 7A 、 Figure 7B and Figure 7C , the organic film layer 117 can include a first organic film layer 117a and a second organic film layer 117b arranged sequentially. It can be understood that the first organic film layer 117a can correspond to the organic film layer 117 shown in Figure 5A 、 Figure 5B and Figure 6 , and the second organic film layer 117b is arranged on the first organic film layer 117a separately from the first organic film layer 117a.

[0136] In this way, when the first organic film layer 117a and the second organic film layer 117b are sequentially arranged so that the organic film layer 117 forms a double layer, the flatness of the organic film layer 117 can increase. Therefore, due to the organic film layer 117, the pixel electrode 210 arranged on the organic film layer 117 does not form a step or the like. When external light is reflected from the surface of the pixel electrode 210, it can be shifted in one direction due to a step difference or the like. In this case, depending on the position where the emission region is formed, a color separation phenomenon in which a specific color is emphasized (for example, relatively enhanced or highlighted) can occur. However, when the organic film layer 117 forms a double layer, the flatness of the organic film layer 117 increases, and due to the organic film layer 117, the pixel electrode 210 does not form a step or the like. Therefore, the color separation phenomenon due to external light can be reduced.

[0137] The first organic film layer 117a and the second organic film layer 117b can be formed of a single layer or a plurality of layers of an organic material, and provide a flat top surface. The organic film layer 117 can be a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), poly(methyl methacrylate) (PMMA), or polystyrene (PS), or can be a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, and a mixture thereof.

[0138] The first organic film layer 117a can have a first initialization contact hole VCNT1 that connects a first portion P1 of the first initialization bridge wiring VB arranged in the peripheral area PA to the first initialization voltage line VL1, and can have a second initialization contact hole VCNT2 that connects a second portion P2 of the initialization bridge wiring VB arranged in the peripheral area PA to the second initialization voltage line VL2. The second organic film layer 117b can have a third initialization contact hole VCNT3 corresponding to the first initialization contact hole VCNT1 and a fourth initialization contact hole VCNT4 corresponding to the second initialization contact hole VCNT2.

[0139] In an embodiment, as shown in Figure 7A In an embodiment, as shown in

[0140] The first dummy hole DH1 formed in the second organic film layer 117b can be arranged between portions of the initialization bridge wiring VB, each of the portions of the initialization bridge wiring VB extending in the +Y direction. For example, the first dummy hole DH1 can be arranged between a first portion P1 of the initialization bridge wiring VB and a second portion P2 of the initialization bridge wiring VB. In this way, the volume of organic matter in the display device 1 is reduced, and thus, outgassing of the organic matter can be significantly reduced.

[0141] In an embodiment, as shown in Figure 7B the first organic film layer 117a can have a second dummy hole DH2 corresponding to the first dummy hole DH1 formed in the second organic film layer 117b. In this case, the volume of organic matter in the display device 1 is reduced compared to when only the second organic film layer 117b has the first dummy hole DH1, and thus, outgassing of the organic matter can be significantly reduced.

[0142] In an embodiment, as shown in Figure 7C the second organic film layer 117b corresponding to the peripheral area PA can have a third dummy hole DH3 and a fourth dummy hole DH4 adjacent to the third initialization contact hole VCNT3 and the fourth initialization contact hole VCNT4, respectively. In other words, the second organic film layer 117b can have the third dummy hole DH3 and the fourth dummy hole DH4 corresponding to portions of the peripheral area PA surrounding the third initialization contact hole VCNT3 and the fourth initialization contact hole VCNT4, respectively.

[0143] The third dummy hole DH3 and the fourth dummy hole DH4 formed in the second organic film layer 117b can be arranged between portions of the initialization bridge wiring VB, each of the portions of the initialization bridge wiring VB extending in the +Y direction. For example, the third dummy hole DH3 and the fourth dummy hole DH4 can be arranged between a first portion P1 of the initialization bridge wiring VB and a second portion P2 of the initialization bridge wiring VB. Figure 7C A total of two dummy holes are shown to be formed between the first portion P1 and the second portion P2 of the initialization bridge wiring VB; however, the number of dummy holes can be different from two. For example, a total of four dummy holes can be formed in the second organic film layer 117b. In addition, as described above with reference to Figure 7B the first organic film layer 117a can include a dummy hole corresponding to a dummy hole formed in the second organic film layer 117b.

[0144] By various embodiments of the present disclosure, the volume of organic material in the display device 1 can be reduced, and outgassing of the organic material can be significantly reduced, so that defects such as pixel shrinkage due to outgassing can be prevented or greatly reduced. The reliability of the display device 1 can be improved.

[0145] According to one or more embodiments of the present disclosure, the volume of organic matter in the display device is reduced, and thus, outgassing of the organic matter can be significantly reduced. Accordingly, even if the display device is exposed to sunlight for a long time, decomposition of the organic matter due to sunlight can be prevented or significantly reduced, such that the reliability of the display device can be improved. The scope of the present disclosure is not limited by these effects.

[0146] Hitherto, the display device has been mainly described, but the present disclosure is not limited thereto. For example, a method of manufacturing the display device also falls within the scope of the present disclosure for manufacturing such a display device.

[0147] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.

Claims

1. A display device comprising: a substrate having a display region and a peripheral region surrounding the display region; a first initialization voltage line on the substrate; an organic film layer on the first initialization voltage line and having a first contact hole exposing at least a portion of the first initialization voltage line; a bridge wiring on the organic film layer corresponding to the peripheral region and contacting the first initialization voltage line through the first contact hole; and a plurality of pixels on the display region, each of the plurality of pixels including a plurality of transistors, wherein the organic film layer corresponding to the peripheral region has a recess or a dummy hole adjacent to the first contact hole, and wherein the first initialization voltage line is configured to transmit an initialization voltage to at least one of the plurality of transistors.

2. The display device according to claim 1, further comprising: a second initialization voltage line on the same layer as the first initialization voltage line, wherein the organic film layer further has a second contact hole at least partially exposing the second initialization voltage line, wherein the bridge wiring contacts the second initialization voltage line through the second contact hole, wherein the bridge wiring includes a first portion extending in a first direction and contacting the first initialization voltage line and a second portion extending in the first direction and contacting the second initialization voltage line, and wherein the recess or the dummy hole is between the first portion and the second portion. The bridge wiring at least partially overlaps the recess, and includes a stepped portion corresponding to the recess.

3. The display device according to claim 1, wherein 4. The display device according to claim 1, further comprising a connection wiring on the same layer as the bridge wiring, The bridge wiring is integrated with the connection wiring. wherein The connection wiring is bent at least twice in plan view.

5. The display device of claim 4, wherein, 6. A display device comprising: a substrate having a display region and a peripheral region surrounding the display region; a first initialization voltage line on the substrate; a first organic film layer on the first initialization voltage line and having a first contact hole exposing at least a portion of the first initialization voltage line; a second organic film layer on the first organic film layer and including a third contact hole corresponding to the first contact hole; a bridge wiring on the second organic film layer corresponding to the peripheral region and contacting the first initialization voltage line; and a plurality of pixels on the display region, each of the plurality of pixels including a plurality of transistors, wherein the second organic film layer corresponding to the peripheral region has a first dummy hole adjacent to the first contact hole and the third contact hole, and wherein the first initialization voltage line is configured to transmit an initialization voltage to at least one of the plurality of transistors. The first organic film layer has a second dummy hole corresponding to the first dummy hole.

7. The display device of claim 6, wherein, 8. The display device according to claim 6, further comprising: a second initialization voltage line on the same layer as the first initialization voltage line, wherein the second organic film layer further has a fourth contact hole at least partially exposing the second initialization voltage line, wherein the bridge wiring contacts the second initialization voltage line through the fourth contact hole, wherein the bridge wiring includes a first portion extending in a first direction and contacting the first initialization voltage line and a second portion extending in the first direction and contacting the second initialization voltage line, and wherein the first dummy hole is between the first portion and the second portion. wherein the first organic film layer further has a second contact hole at least partially exposing the second initialization voltage line, wherein the second organic film layer further includes a fourth contact hole corresponding to the second contact hole, wherein the bridge wiring contacts the second initialization voltage line through the second contact hole and the fourth contact hole, and wherein the bridge wiring includes a first portion extending in a first direction and contacting the first initialization voltage line and a second portion extending in the first direction and contacting the second initialization voltage line, and the first dummy hole is located between the first portion and the second portion.

9. The display device of claim 8, wherein, The second organic film layer further has a third dummy hole spaced apart from the first dummy hole and located between the first portion and the second portion.

10. A display device comprising: a substrate having a display region and a peripheral region surrounding the display region; a voltage wiring on the substrate; a first organic film layer on the voltage wiring and having a first contact hole exposing at least a portion of the voltage wiring; a second organic film layer on the first organic film layer and having a third contact hole corresponding to the first contact hole; a bridge wiring on the second organic film layer corresponding to the peripheral region and contacting the voltage wiring; and a plurality of pixels on the display region, each of the plurality of pixels including a plurality of transistors, wherein the second organic film layer corresponding to the peripheral region has a dummy hole adjacent to the first contact hole and the third contact hole, and wherein the voltage wiring is configured to transmit an initialization voltage to at least one of the plurality of transistors. ​

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