A full-duplex data communication device

Abstract

The present invention proposes a full-duplex data communication device, comprising a filtering circuit, an interference elimination circuit, a receiving antenna, a transmitting antenna, a combiner, a power splitter, a receiving mixer, a central processing unit, a transmitting mixer and a power supply. The output end of the receiving antenna is connected to the input end of the interference elimination circuit, the output end of the interference elimination circuit is connected to the input end of the filtering circuit, the output end of the filtering circuit is connected to the input end of the combiner, the output end of the combiner is connected to the input end of the receiving mixer, the output end of the receiving mixer is connected to the input end of the central processing unit, the output end of the central processing unit is connected to the input end of the transmitting mixer, the output end of the transmitting mixer is connected to the input end of the power splitter, the output end of the power splitter is connected to the input end of the transmitting antenna, and the power supply is connected to the central processing unit. The present invention can effectively reduce the interference of a signal transmitted by the transmitting antenna on a signal received by the receiving antenna, thereby making the signal received by the receiving antenna more accurate.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a full-duplex data communication device. Background Art

[0002] With the development of science and technology, the demand for communication networks is constantly increasing. From smart cities and the Internet of Things to various wearable devices, the demand for data transmission rate and transmission quantity is also constantly increasing. Full-duplex means that at any time of communication, there is bidirectional signal transmission from A to B and from B to A on the line, which can effectively improve the data transmission efficiency; in full-duplex mode, a transmitter and a receiver are set at each end of the communication system, so that data can be controlled to be transmitted in two directions at the same time; this method requires that both parties in communication have a transmitter and a receiver, and at the same time, two data lines are required to transmit data signals; for smaller miniature wearable devices, full-duplex communication often has the problem of high power consumption and high power consumption, which cannot meet people's demand for low power consumption in the Internet of Things, and there is also the problem that the receiver is easily interfered with by the transmitter. Summary of the Invention

[0003] The object of the present invention is to solve at least one of the technical drawbacks.

[0004] To this end, one object of the present invention is to provide a full-duplex data communication device, including a filtering circuit, an interference cancellation circuit, a receiving antenna, a transmitting antenna, a combiner, a power splitter, a receiving mixer, a central processing unit, a transmitting mixer and a power supply, wherein the output end of the receiving antenna is connected to the input end of the interference cancellation circuit so that the interference cancellation circuit eliminates the interference signal received by the receiving antenna, the output end of the interference cancellation circuit is connected to the input end of the filtering circuit so that the filtering circuit further filters the signal after interference elimination, the output end of the filtering circuit is connected to the input end of the combiner, the output end of the combiner is connected to the input end of the receiving mixer, the output end of the receiving mixer is connected to the input end of the central processing unit, the output end of the central processing unit is connected to the input end of the transmitting mixer, the output end of the transmitting mixer is connected to the input end of the power splitter, the output end of the power splitter is connected to the input end of the transmitting antenna, and the power supply is connected to the central processing unit.

[0005] The interference elimination circuit includes first to fourteenth resistors, first to eighth capacitors, first to sixth diodes, a first transistor, a first operational amplifier and a second operational amplifier, one end of the first capacitor is connected to the anode of the first diode, one end of the first resistor and the anode of the second diode, the second resistor is connected in parallel with the second capacitor, one end thereof in parallel is connected to the other end of the first resistor, and the other end thereof in parallel is connected to one end of the fourth resistor and one end of the eighth resistor, the third capacitor is connected in parallel with the sixth resistor, one end thereof in parallel is connected to the cathode of the first diode, and the other end thereof in parallel is grounded, the cathode of the second diode is connected to one end of the fourth capacitor and one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the fifth capacitor and the base of the first transistor, the collector of the first transistor is connected to the other end of the fourth resistor, the emitter of the first transistor is connected to one end of the seventh resistor, the other end of the eighth resistor and one end of the seventh capacitor, and the The other end is connected to the non-inverting input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is connected to one end of the eighth capacitor through the fifteenth resistor, the third resistor is connected to the sixth capacitor in parallel, one end of the parallel connection is connected to one end of the eighth resistor, and the other end of the parallel connection is connected to the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is connected to one end of the eighth capacitor and the output terminal of the first operational amplifier through one end of the ninth resistor, the output terminal of the second operational amplifier is connected to the positive electrode of the third diode, one end of the twelfth resistor and one end of the thirteenth resistor, the negative electrode of the third diode is connected to the other end of the eighth capacitor, the negative electrode of the fourth diode and one end of the tenth resistor, the other end of the twelfth resistor is connected to the other end of the tenth resistor, the negative electrode of the fifth diode and one end of the eleventh resistor, and the other end of the thirteenth resistor is connected to the positive electrode of the sixth diode, the other end of the eleventh resistor and one end of the fourteenth resistor.

[0006] Preferably, the filtering circuit includes a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first polarity capacitor, a second polarity capacitor, sixteenth to twenty-eighth resistors, a second transistor, a third transistor, a seventh diode, an eighth diode, a third operational amplifier and a fourth operational amplifier, one end of the ninth capacitor is connected to one end of the sixteenth resistor, the other end of the ninth capacitor is connected to the output end of the third operational amplifier through the tenth capacitor, the other end of the sixteenth resistor is connected to the non-inverting input end of the third operational amplifier, the inverting input end of the third operational amplifier is connected to one end of the seventeenth resistor and one end of the eighteenth resistor, the output end of the third operational amplifier is connected to one end of the twentieth resistor, one end of the twenty-first resistor and the other end of the eighteenth resistor, the other end of the twentieth resistor is connected to one end of the twenty-second resistor and the collector of the second transistor through the nineteenth resistor, The base of the second transistor is connected to the other end of the twenty-first resistor, the emitter of the second transistor is grounded, the other end of the twenty-second resistor is connected to one end of the twenty-third resistor and the positive electrode of the first polarity capacitor, the other end of the twenty-third resistor is connected to the positive electrode of the second capacitor and one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is connected to one end of the twenty-fifth resistor, one end of the eleventh capacitor, one end of the twelfth capacitor and the emitter of the third transistor, the other end of the twenty-fifth resistor is connected to the cathode of the seventh diode, the collector of the third transistor is grounded, the base of the third transistor is connected to the inverting input terminal of the fourth operational amplifier through the twenty-seventh resistor, the other end of the twelfth capacitor is connected to the output terminal of the fourth operational amplifier through the twenty-sixth resistor, and the output terminal of the fourth operational amplifier is connected to the cathode of the eighth diode, one end of the twenty-eighth resistor and the other end of the eleventh capacitor.

[0007] In any of the above schemes, preferably, the power supply includes twenty-ninth to thirty-ninth resistors, ninth to twelfth diodes, third to fifth polarity capacitors and fourth to seventh transistors, the thirty-eighth resistor is connected in parallel with the twenty-ninth resistor, one end of the parallel connection is connected to the positive electrode of the third polarity capacitor, the negative electrode of the ninth diode and one end of the thirty-first resistor, the other end of the parallel connection is connected to one end of the thirtieth resistor, the positive electrode of the ninth diode is connected to the negative electrode of the tenth diode, the other end of the thirtieth resistor is connected to the negative electrode of the eleventh diode, the collector of the fourth transistor and one end of the thirty-third resistor, the base of the fourth transistor is connected to the positive electrode of the eleventh diode, the other end of the thirty-first resistor and the other end of the thirty-second resistor, The emitter of the fourth transistor is connected to one end of the thirty-ninth resistor and the emitter of the seventh transistor, the base of the seventh transistor is connected to one end of the thirty-fourth resistor, the cathode of the twelfth diode and the positive electrode of the fourth polarity capacitor through the thirty-fifth resistor, the base of the fifth transistor is connected to the other end of the thirty-ninth resistor, the collector of the fifth transistor is connected to the other end of the thirty-third resistor, the emitter of the fifth transistor is connected to the base of the sixth transistor, the emitter of the sixth transistor is connected to the other end of the thirty-fourth resistor and one end of the thirty-sixth resistor, the other end of the thirty-sixth resistor is connected to one end of the thirty-seventh resistor and the positive electrode of the fifth polarity capacitor, and the other end of the thirty-seventh resistor is connected to the cathode of the thirteenth diode.

[0008] In any of the above schemes, it is preferred that it also includes a phase shifter, an attenuator and a delayer, the output end of the power divider is connected to the input end of the delayer, the output end of the delayer is connected to the input end of the phase shifter through the attenuator, so that the attenuator adjusts the size of the signal after passing through the delayer, and the output end of the phase shifter is connected to the input end of the combiner, so that the phase shifter adjusts the phase of the signal processed by the attenuator.

[0009] In any of the above schemes, it is preferred that a circulator is further included, wherein the input end of the circulator is connected to the output end of the transmitting antenna, and the output end of the circulator is connected to the input end of the receiving antenna, so that the circulator can isolate the signal emitted by the transmitting antenna to avoid interference with the signal received by the receiving antenna.

[0010] In any of the above solutions, preferably, the central processing unit adopts a chip of the SIT488E model.

[0011] The advantages and beneficial effects of the present invention over the prior art are:

[0012] 1. A full-duplex data communication device of the present invention can effectively eliminate the interference of the signal emitted by the transmitting antenna on the signal received by the receiving antenna through the interference cancellation circuit, and eliminate the noise interference of the received signal to the maximum extent, so that the signal received by the receiving antenna is better, the interference cancellation effect is good, the accuracy is higher, and the cost is lower.

[0013] 2. The present invention further filters and removes noise from the signal received by the receiving antenna through the filtering circuit, and filters the signal processed by the interference elimination circuit, thereby achieving multi-stage filtering of the signal to eliminate interference and provide a more accurate signal.

[0014] 3. The power supply circuit of the present invention can ensure stable power supply, prevent current surge from damaging the central processing unit, and can also reduce power consumption, save more electricity, and meet the low power consumption requirements of network transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 is a structural block diagram of a full-duplex data communication device according to the present invention;

[0017] Figure 2 A full-duplex data communication device according to the present invention Figure 1 The circuit schematic diagram of the interference elimination circuit shown;

[0018] Figure 3 A full-duplex data communication device according to the present invention Figure 1 The circuit schematic diagram of the filter circuit shown;

[0019] Figure 4 A full-duplex data communication device according to the present invention Figure 1 The circuit diagram of the power supply is shown.

[0020] Wherein the accompanying drawings are:

[0021] 1-Filter circuit; 2-Interference cancellation circuit; 3-Receive antenna; 4-Transmit antenna; 5-Combiner; 6-Phase shifter; 7-Attenuator; 8-Delay; 9-Power divider; 10-Receive mixer; 11-Central processing unit; 12-Transmit mixer; 13-Power supply. DETAILED DESCRIPTION

[0022] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0023] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0024] As shown in Figure 1, Figure 2 As shown, a full-duplex data communication device includes a filtering circuit 1, an interference elimination circuit 2, a receiving antenna 3, a transmitting antenna 4, a combiner 5, a power splitter 9, a receiving mixer 10, a central processing unit 11, a transmitting mixer 12 and a power supply 13. The output end of the receiving antenna 3 is connected to the input end of the interference elimination circuit 2. The receiving antenna 13 receives a signal. The interference elimination circuit 2 denoises the interference signal received by the receiving antenna 3. The output end of the interference elimination circuit 2 is connected to the input end of the filtering circuit 1 so that the filtering circuit 1 further filters the signal after the interference is eliminated. The output end of the circuit 1 is connected to the input end of the combiner 5, the output end of the combiner 5 is connected to the input end of the receiving mixer 10, the output end of the receiving mixer 10 is connected to the input end of the central processing unit 11, the receiving mixer 10 adjusts the signal processed by the combiner 5, and then sends the adjusted signal to the central processing unit 11, the output end of the central processing unit 11 is connected to the input end of the transmitting mixer 12, the output end of the transmitting mixer 12 is connected to the input end of the power divider 9, the output end of the power divider 9 is connected to the input end of the transmitting antenna 4, and the power supply 13 is connected to the central processing unit 11.

[0025] The interference elimination circuit 2 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a fourteenth resistor R14, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor D6, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor D6, a first transistor Q1, a first transistor Q2 ... first transistor Q2, a first transistor Q2, a first transistor Q2 An operational amplifier U1 and a second operational amplifier U2, one end of the first capacitor C1 is connected to the anode of the first diode D1, one end of the first resistor R1 and the anode of the second diode D2, the second resistor R2 is connected in parallel with the second capacitor C2, one end of the parallel connection is connected to the other end of the first resistor R1, and the other end of the parallel connection is connected to one end of the fourth resistor R4 and one end of the eighth resistor R8, the third capacitor C3 is connected in parallel with the sixth resistor R6, one end of the parallel connection is connected to the cathode of the first diode D1, and the other end of the parallel connection is grounded, the cathode of the second diode D2 is connected to one end of the fourth capacitor C4 and one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the fifth capacitor C5 and the first The base of the transistor Q1 is connected, the collector of the first transistor Q1 is connected to the other end of the fourth resistor R4, the emitter of the first transistor Q1 is connected to one end of the seventh resistor R7, the other end of the eighth resistor R8 and one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is connected to the non-inverting input terminal of the first operational amplifier U1, the inverting input terminal of the first operational amplifier U1 is connected to one end of the eighth capacitor C8 through the fifteenth resistor R15, the third resistor R3 and the sixth capacitor C6 are connected in parallel, one end of the parallel connection is connected to one end of the eighth resistor R8, and the other end of the parallel connection is connected to the non-inverting input terminal of the second operational amplifier U2, and the inverting input terminal of the second operational amplifier U2 is connected through the ninth resistor One end of R9 is connected to one end of the eighth capacitor C8 and the output end of the first operational amplifier U1. The output end of the second operational amplifier U2 is connected to the anode of the third diode D3, one end of the twelfth resistor R12, and one end of the thirteenth resistor R13. The cathode of the third diode D3 is connected to the other end of the eighth capacitor C8, the cathode of the fourth diode D4, and one end of the tenth resistor R10. The other end of the twelfth resistor R12 is connected to the other end of the tenth resistor R10, the cathode of the fifth diode D5, and one end of the eleventh resistor R11. The other end of the thirteenth resistor R13 is connected to the anode of the sixth diode D6, the other end of the eleventh resistor R11, and one end of the fourteenth resistor R14.

[0026] A full-duplex data communication device of the present invention can effectively eliminate the noise interference of the signal sent by the transmitting antenna 4 on the signal received by the receiving antenna 3 through the interference elimination circuit 2, thereby making the signal received by the receiving antenna 3 more accurate, having a good interference elimination effect, and lowering the cost.

[0027] Further, such as Figure 3 As shown, the filter circuit 1 includes a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C13, a twelfth capacitor C14, a first polarity capacitor C11, a second polarity capacitor C12, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a second transistor Q2, a third transistor Q3, and a seventh diode D7, the eighth diode D8, the third operational amplifier U3 and the fourth operational amplifier U4, one end of the ninth capacitor C9 is connected to one end of the sixteenth resistor R16, the other end of the ninth capacitor C9 is connected to the output end of the third operational amplifier U3 through the tenth capacitor C10, the other end of the sixteenth resistor R16 is connected to the non-inverting input end of the third operational amplifier U3, the inverting input end of the third operational amplifier U3 is connected to one end of the seventeenth resistor R17 and one end of the eighteenth resistor R18, the output end of the third operational amplifier U3 is connected to one end of the twentieth resistor R20, one end of the twenty-first resistor R21 and the eighteenth resistor R1 8, the other end of the twentieth resistor R20 is connected to one end of the twenty-second resistor R22 and the collector of the second transistor Q2 through the nineteenth resistor R19, the base of the second transistor Q2 is connected to the other end of the twenty-first resistor R21, the emitter of the second transistor Q2 is grounded, the other end of the twenty-second resistor R22 is connected to one end of the twenty-third resistor R23 and the positive electrode of the first polarity capacitor C11, the other end of the twenty-third resistor R23 is connected to the positive electrode of the second capacitor C2, one end of the twenty-fourth resistor R24, the other end of the twenty-fourth resistor R24 ​​is connected to one end of the twenty-fifth resistor R25, the positive electrode of the tenth resistor R26, and the positive electrode of the second capacitor C2. One end of the first capacitor C13, one end of the twelfth capacitor C14, and the emitter of the third transistor Q3 are connected, the other end of the twenty-fifth resistor R25 is connected to the cathode of the seventh diode D7, the collector of the third transistor Q3 is grounded, the base of the third transistor Q3 is connected to the inverting input terminal of the fourth operational amplifier U4 via the twenty-seventh resistor R27, the other end of the twelfth capacitor C14 is connected to the output terminal of the fourth operational amplifier U4 via the twenty-sixth resistor R26, and the output terminal of the fourth operational amplifier U4 is connected to the cathode of the eighth diode D8, one end of the twenty-eighth resistor R28, and the other end of the eleventh capacitor C13.

[0028] The present invention realizes multi-stage filtering and denoising through a filtering circuit, and filters the signal processed by the interference elimination circuit 2, with good filtering effect, lower power consumption, and providing a more accurate signal.

[0029] Specifically, such as Figure 4 As shown, the power supply 13 includes a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, a thirty-ninth resistor R39, a ninth diode D9, a tenth diode D10, an eleventh diode D11, a twelfth diode D12, a third polarity capacitor C15, a fourth polarity capacitor C16, and a fifth polarity capacitor C 17. The fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the thirty-eighth resistor R38 and the twenty-ninth resistor R29 are connected in parallel. One end of the parallel connection is connected to the positive electrode of the third polarity capacitor C15, the negative electrode of the ninth diode D9, and one end of the thirty-first resistor R31. The other end of the parallel connection is connected to one end of the thirtieth resistor R30. The positive electrode of the ninth diode D9 is connected to the negative electrode of the tenth diode D10. The other end of the thirtieth resistor R30 is connected to the negative electrode of the eleventh diode D11 and the fourth transistor Q4. The collector of the fourth transistor Q4 is connected to one end of the thirty-third resistor R33, the base of the fourth transistor Q4 is connected to the anode of the eleventh diode D11, the other end of the thirty-first resistor R31 and the other end of the thirty-second resistor R32, the emitter of the fourth transistor Q4 is connected to one end of the thirty-ninth resistor R39 and the emitter of the seventh transistor Q7, the base of the seventh transistor Q7 is connected to one end of the thirty-fourth resistor R34, the cathode of the twelfth diode D12 and the anode of the fourth polarity capacitor C16 through the thirty-fifth resistor R35, and the fifth transistor Q The base of the fifth transistor Q5 is connected to the other end of the thirty-ninth resistor R39, the collector of the fifth transistor Q5 is connected to the other end of the thirty-third resistor R33, the emitter of the fifth transistor Q5 is connected to the base of the sixth transistor Q6, the emitter of the sixth transistor Q6 is connected to the other end of the thirty-fourth resistor R34 and one end of the thirty-sixth resistor R36, the other end of the thirty-sixth resistor R36 is connected to one end of the thirty-seventh resistor R37 and the positive electrode of the fifth polarity capacitor C17, and the other end of the thirty-seventh resistor R37 is connected to the cathode of the thirteenth diode.

[0030] The power supply 13 circuit of the present invention can ensure the stable power supply of the power supply 13, prevent the sudden increase of current from damaging the central processing unit 11, and can also reduce power consumption, save more electricity, and meet the low power consumption requirements of network transmission.

[0031] Specifically, it also includes a phase shifter 6, an attenuator 7 and a delayer 8. The output end of the power divider 9 is connected to the input end of the delayer 8, and the output end of the delayer 8 is connected to the input end of the phase shifter 6 through the attenuator 7 so that the attenuator 7 adjusts the signal size after passing through the delayer 8. The output end of the phase shifter 6 is connected to the input end of the combiner 5 so that the phase shifter 6 adjusts the phase of the signal processed by the attenuator 7.

[0032] Optionally, a circulator is further included, with the input end of the circulator connected to the output end of the transmitting antenna 4, and the output end of the circulator connected to the input end of the receiving antenna 3, so that the circulator isolates the signal emitted by the transmitting antenna 4 to avoid interference with the signal received by the receiving antenna 3. The circulator can further reduce the interference of the transmitting antenna 4 on the receiving antenna 3.

[0033] Optionally, the central processing unit 11 uses a chip of the SIT488E model.

[0034] The working principle of the present invention is as follows: after the receiving antenna 3 receives the signal, the signal passes through the interference elimination circuit 2, which adjusts and restores it according to the signal situation, eliminates the impurity interference factors in the signal, and then further adjusts and filters it through the filter circuit 1. The filtered signal is then transmitted to the central processing unit 11 through the combiner 5 and the receiving mixer 10 for signal processing.

[0035] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0036] Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments without departing from the principles and intent of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A full-duplex data communication device, characterized in that: The invention comprises a filtering circuit, an interference elimination circuit, a receiving antenna, a transmitting antenna, a combiner, a power splitter, a receiving mixer, a central processing unit, a transmitting mixer and a power supply. The output end of the receiving antenna is connected to the input end of the interference elimination circuit so that the interference elimination circuit eliminates the interference signal received by the receiving antenna. The output end of the interference elimination circuit is connected to the input end of the filtering circuit so that the filtering circuit further filters the signal after interference elimination. The output end of the filtering circuit is connected to the input end of the combiner, the output end of the combiner is connected to the input end of the receiving mixer, the output end of the receiving mixer is connected to the input end of the central processing unit, the output end of the central processing unit is connected to the input end of the transmitting mixer, the output end of the transmitting mixer is connected to the input end of the power splitter, the output end of the power splitter is connected to the input end of the transmitting antenna, and the power supply is connected to the central processing unit, wherein: The interference elimination circuit includes first to fifteenth resistors, first to eighth capacitors, first to sixth diodes, a first transistor, a first operational amplifier and a second operational amplifier, one end of the first capacitor is connected to the anode of the first diode, one end of the first resistor and the anode of the second diode, the second resistor is connected in parallel with the second capacitor, one end thereof in parallel is connected to the other end of the first resistor, and the other end thereof in parallel is connected to one end of the fourth resistor and one end of the eighth resistor, the third capacitor is connected in parallel with the sixth resistor, one end thereof in parallel is connected to the cathode of the first diode, and the other end thereof in parallel is grounded, the cathode of the second diode is connected to one end of the fourth capacitor and one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the fifth capacitor and the base of the first transistor, the collector of the first transistor is connected to the other end of the fourth resistor, the emitter of the first transistor is connected to one end of the seventh resistor, the other end of the eighth resistor and one end of the seventh capacitor, and the other end of the seventh capacitor is connected to the cathode of the first diode. the first operational amplifier is connected to the non-inverting input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is connected to one end of the eighth capacitor through the fifteenth resistor, the third resistor is connected in parallel with the sixth capacitor, one end of the third resistor is connected in parallel to one end of the eighth resistor, and the other end of the third resistor is connected to the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is connected to one end of the eighth capacitor and the output terminal of the first operational amplifier through one end of the ninth resistor, the output terminal of the second operational amplifier is connected to the anode of the third diode, one end of the twelfth resistor, and one end of the thirteenth resistor, the cathode of the third diode is connected to the other end of the eighth capacitor, the cathode of the fourth diode, and one end of the tenth resistor, the other end of the twelfth resistor is connected to the other end of the tenth resistor, the cathode of the fifth diode, and one end of the eleventh resistor, and the other end of the thirteenth resistor is connected to the anode of the sixth diode, the other end of the eleventh resistor, and one end of the fourteenth resistor; The power divider further includes a phase shifter, an attenuator, and a delayer, wherein the output end of the power divider is connected to the input end of the delayer, the output end of the delayer is connected to the input end of the phase shifter through the attenuator, so that the attenuator adjusts the magnitude of the signal after passing through the delayer, and the output end of the phase shifter is connected to the input end of the combiner, so that the phase shifter adjusts the phase of the signal processed by the attenuator; A circulator is also included, wherein the input end of the circulator is connected to the output end of the transmitting antenna, and the output end of the circulator is connected to the input end of the receiving antenna, so that the circulator can isolate the signal emitted by the transmitting antenna to avoid interference with the signal received by the receiving antenna.

2. A full-duplex data communication device according to claim 1, characterized in that: The filtering circuit includes a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first polarity capacitor, a second polarity capacitor, sixteenth to twenty-eighth resistors, a second transistor, a third transistor, a seventh diode, an eighth diode, a third operational amplifier and a fourth operational amplifier, one end of the ninth capacitor is connected to one end of the sixteenth resistor, the other end of the ninth capacitor is connected to the output end of the third operational amplifier through the tenth capacitor, the other end of the sixteenth resistor is connected to the non-inverting input end of the third operational amplifier, the inverting input end of the third operational amplifier is connected to one end of the seventeenth resistor and one end of the eighteenth resistor, the output end of the third operational amplifier is connected to one end of the twentieth resistor, one end of the twenty-first resistor and the other end of the eighteenth resistor, the other end of the twentieth resistor is connected to one end of the twenty-second resistor and the collector of the second transistor through the nineteenth resistor, and the base of the second transistor is connected to the The other end of the twenty-first resistor is connected, the emitter of the second transistor is grounded, the other end of the twenty-second resistor is connected to one end of the twenty-third resistor and the positive electrode of the first polarity capacitor, the other end of the twenty-third resistor is connected to the positive electrode of the second polarity capacitor and one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is connected to one end of the twenty-fifth resistor, one end of the eleventh capacitor, one end of the twelfth capacitor and the emitter of the third transistor, the other end of the twenty-fifth resistor is connected to the cathode of the seventh diode, the collector of the third transistor is grounded, the base of the third transistor is connected to the inverting input terminal of the fourth operational amplifier through the twenty-seventh resistor, the other end of the twelfth capacitor is connected to the output terminal of the fourth operational amplifier through the twenty-sixth resistor, and the output terminal of the fourth operational amplifier is connected to the cathode of the eighth diode, one end of the twenty-eighth resistor and the other end of the eleventh capacitor.

3. The full-duplex data communication device according to claim 1, wherein: The power supply includes twenty-ninth to thirty-ninth resistors, ninth to twelfth diodes, third to fifth polarity capacitors and fourth to seventh transistors. The thirty-eighth resistor is connected in parallel with the twenty-ninth resistor, one end of which is connected in parallel to the positive electrode of the third polarity capacitor, the negative electrode of the ninth diode and one end of the thirty-first resistor, and the other end of which is connected in parallel to one end of the thirtieth resistor. The positive electrode of the ninth diode is connected to the negative electrode of the tenth diode, the other end of the thirtieth resistor is connected to the negative electrode of the eleventh diode, the collector of the fourth transistor and one end of the thirty-third resistor, the base of the fourth transistor is connected to the positive electrode of the eleventh diode, the other end of the thirty-first resistor and the other end of the thirty-second resistor, and the emitter of the fourth transistor is connected to the positive electrode of the eleventh diode. It is connected to one end of the thirty-ninth resistor and the emitter of the seventh transistor, the base of the seventh transistor is connected to one end of the thirty-fourth resistor, the negative electrode of the twelfth diode and the positive electrode of the fourth polarity capacitor through the thirty-fifth resistor, the base of the fifth transistor is connected to the other end of the thirty-ninth resistor, the collector of the fifth transistor is connected to the other end of the thirty-third resistor, the emitter of the fifth transistor is connected to the base of the sixth transistor, the emitter of the sixth transistor is connected to the other end of the thirty-fourth resistor and one end of the thirty-sixth resistor, the other end of the thirty-sixth resistor is connected to one end of the thirty-seventh resistor and the positive electrode of the fifth polarity capacitor, and the other end of the thirty-seventh resistor is connected to the negative electrode of the thirteenth diode.

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