imaging element

Abstract

An imaging element includes: a first pixel having a first photoelectric conversion section that photoelectrically converts light to generate electric charges, and a first output section that generates and outputs a first signal based on the electric charges generated by the first photoelectric conversion section; a second pixel having a second photoelectric conversion section that photoelectrically converts light to generate electric charges, and a second output section that generates and outputs a second signal based on the electric charges generated by the second photoelectric conversion section; and an adjustment section that adjusts a capacitance of the first output section when the first signal and the second signal are output from the first output section.

Description

[0001] This invention application is a divisional application of the invention application with an international filing date of January 31, 2018, international application number PCT / JP2018 / 003302, national application number 201880009276.2 which entered the Chinese national phase, and the invention title "Camera Element and Camera Device". Technical Field

[0002] This invention relates to imaging elements and imaging devices. Background Technology

[0003] An imaging device is known to add (mix) the charges of two light-receiving elements and read out the potential corresponding to the added charge (Patent Document 1). However, conventional imaging devices suffer from the problem of conversion gain variation when converting the added charge into a potential.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-139859 Summary of the Invention

[0007] According to a first aspect of the present invention, the imaging element includes: a first pixel having a first photoelectric conversion unit that performs photoelectric conversion on light and generates charge, and a first output unit that generates and outputs a first signal based on the charge generated by the first photoelectric conversion unit; a second pixel having a second photoelectric conversion unit that performs photoelectric conversion on light and generates charge, and a second output unit that generates and outputs a second signal based on the charge generated by the second photoelectric conversion unit; and an adjustment unit that adjusts the capacitance of the first output unit when outputting the first signal and the second signal from the first output unit.

[0008] According to a second aspect of the present invention, the imaging element includes: a first pixel having a first photoelectric conversion unit that performs photoelectric conversion on light and generates charge, and a first output unit connected to a first signal line and outputting a signal based on the charge generated by the first photoelectric conversion unit; a second pixel having a second photoelectric conversion unit that performs photoelectric conversion on light and generates charge, and a second output unit connected to a second signal line and outputting a signal based on the charge generated by the second photoelectric conversion unit; and a first connecting portion disposed between the first output unit and the second output unit.

[0009] According to a third aspect of the present invention, the imaging device includes: an imaging element according to the first or second aspect; and an image generation unit that generates image data based on a signal output from the imaging element. Attached Figure Description

[0010] Figure 1 This is a block diagram showing the configuration of the camera device according to the first embodiment.

[0011] Figure 2 This is a circuit diagram showing the pixel configuration of the first embodiment.

[0012] Figure 3 This is a diagram illustrating an example of the operation of the camera element in the first embodiment.

[0013] Figure 4 This is a diagram illustrating other operational examples of the imaging element in the first embodiment.

[0014] Figure 5 This is a circuit diagram showing a portion of the imaging element in the first embodiment.

[0015] Figure 6 This is a timing diagram illustrating an example of the operation of the camera element in the first embodiment.

[0016] Figure 7 This is a timing diagram illustrating other operational examples of the camera element in the first embodiment.

[0017] Figure 8 This is a circuit diagram showing the pixel configuration of the second embodiment.

[0018] Figure 9 This is a circuit diagram showing the pixel configuration of the third embodiment.

[0019] Figure 10 This is a circuit diagram showing a portion of the imaging element in the third embodiment.

[0020] Figure 11 This is a timing diagram illustrating an example of the operation of the camera element in the third embodiment.

[0021] Figure 12 This is a timing diagram illustrating other operational examples of the camera element in the third embodiment.

[0022] Figure 13 This is a circuit diagram showing the composition of pixels in Modified Example 1. Detailed Implementation

[0023] (First Embodiment)

[0024] Figure 1 This is a block diagram showing the configuration of the camera device according to the first embodiment. Figure 1The diagram shows an example of the configuration of an electronic camera 1 (hereinafter referred to as camera 1) as an example of the imaging device according to the first embodiment. Camera 1 includes: an imaging optical system 2, an imaging element 3, a control unit 4, a memory 5, a display unit 6, and an operation unit 7. The imaging optical system 2 has multiple lenses, including a focusing lens, and an aperture stop, which enables the image of the subject to be imaged on the imaging element 3. Furthermore, the imaging optical system 2 can be configured to be detachable from camera 1.

[0025] The imaging element 3 is, for example, a CMOS image sensor. The imaging element 3 receives a light beam passing through the exit pupil of the imaging optical system 2 and captures an image of the subject. As detailed later, the imaging element 3 has multiple pixels arranged in a two-dimensional configuration (row direction and intersecting column direction), each having microlenses and multiple photoelectric conversion units (e.g., two photoelectric conversion units). The photoelectric conversion units are, for example, composed of photodiodes (PDs). The imaging element 3 performs photoelectric conversion on the incident light to generate a signal and outputs the generated signal to the control unit 4.

[0026] Regarding the imaging element 3, details will be described later. It outputs to the control unit 4 a signal for generating image data, namely an imaging signal, and a pair of focus detection signals, namely a first focus detection signal and a second focus detection signal, for performing phase difference-based focus detection on the focus of the imaging optical system 2. The first focus detection signal and the second focus detection signal are obtained by photoelectric conversion of the first image and the second image generated by the first beam and the second beam (which pass through the first region and the second region of the exit pupil of the imaging optical system 2, respectively).

[0027] The memory 5 is a storage medium such as a memory card. Image data is stored in the memory 5. The control unit 4 performs the writing and / or reading of data from the memory 5. The display unit 6 displays information related to photography, such as the image based on the image data, shutter speed and / or aperture value, and menu screens. The operation unit 7 includes various setting switches such as a release button and a power switch, and outputs operation signals corresponding to each operation to the control unit 4.

[0028] The control unit 4 consists of a CPU (Central Processing Unit), ROM (Read-Only Memory), RAM (Random Access Memory), etc., and controls various parts of the camera 1 based on the control program. The control unit 4 includes an image data generation unit 4a and a focus detection unit 4b. The image data generation unit 4a performs various image processing operations on the imaging signal output from the imaging element 3 to generate image data. Image processing includes known image processing such as grayscale conversion processing, color interpolation processing, and contour enhancement processing.

[0029] The focus detection unit 4b performs focus detection processing required for autofocus (AF) of the imaging optical system 2 using a known phase difference detection method. Specifically, the focus detection unit 4b detects the image aberration of the first image and the second image based on a pair of focus detection signals output from the imaging element 3, and calculates the defocus amount based on the detected image aberration. By driving the focusing lens according to the defocus amount, automatic focusing is possible.

[0030] The control unit 4 performs processing to read out signals individually from multiple photoelectric conversion units of each pixel of the imaging element 3 (first control mode) and processing to add and read out signals from multiple photoelectric conversion units (second control mode). In this embodiment, in the first control mode, the control unit 4 reads out the signal generated by the charge generated by the first photoelectric conversion unit and the signal generated by the charge generated by the second photoelectric conversion unit as a pair of focus detection signals separately, that is, independently, as detailed below.

[0031] In the second control mode, the control unit 4 performs a process of adding the signals from the first photoelectric conversion unit and the second photoelectric conversion unit respectively, and reads them out as an image signal. Here, "addition processing" includes averaging multiple signals, and / or weighting and adding multiple signals, etc. When performing phase difference AF, the control unit 4 performs the first control mode to read out a pair of focus detection signals from the image sensor 3, and performs the second control mode to read out the image signal from the image sensor 3 when generating image data.

[0032] Figure 2 This is a circuit diagram showing the pixel configuration of the imaging element 3 according to the first embodiment. Pixel 10 includes a microlens ML, a first photoelectric conversion unit 11a, a second photoelectric conversion unit 11b, a first transmission unit 12a, a second transmission unit 12b, a first reset unit 13a, a second reset unit 13b, a first floating diffusion unit (FD) 14a, and a second floating diffusion unit (FD) 14b. Pixel 10 also includes a first magnifying unit 15a, a second magnifying unit 15b, a first selection unit 16a, a second selection unit 16b, an addition switch unit 17, and a combination switch unit 18.

[0033] Microlenses ML will be via Figure 1 The light incident on the camera optical system 2 converges towards the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b. Furthermore, to illustrate the light beam passing through the microlens ML and incident on the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b, the microlens ML is shown with an elliptical line surrounding the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b. This elliptical shape does not represent the actual size or shape of the microlens ML.

[0034] The first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b are photodiodes PD (PDa, PDb), which convert incident light into electrical charge and store the converted charge. The first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b are configured corresponding to a microlens ML to receive light beams that have passed through different regions of the exit pupil of the imaging optical system 2. That is, the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b perform photoelectric conversion on the first image and the second image generated by the first light beam and the second light beam, respectively, where the first light beam and the second light beam are light beams that have passed through the first region and the second region of the exit pupil of the imaging optical system 2, respectively.

[0035] The first transmission section 12a, composed of transistor M1a (controlled by signal TX1), transmits the charge converted by the first photoelectric conversion section 11a to the first FD14a. That is, the first transmission section 12a forms a charge transmission path between the first photoelectric conversion section 11a and the first FD14a. Transistor M1a is the first transmission transistor. The capacitor Ca of the first FD14a stores (holds) the charge transmitted to the first FD14a and converts the charge into a voltage obtained by dividing the capacitance value by Ca. The symbol Ca, representing capacitance, schematically shows the capacitance attached to the first FD14a. Capacitor Ca includes the capacitance (parasitic capacitance) of each transistor, such as the gate capacitance of the first amplification section 15a connected to the first FD14a, and / or wiring capacitance. Furthermore, the gate capacitance is the parasitic capacitance between the gate and back gate of the transistor.

[0036] The first amplification section 15a amplifies and outputs the signal generated by the charge stored in the capacitor Ca. The first amplification section 15a is composed of a transistor M3a whose drain (terminal), gate (terminal), and source (terminal) are respectively connected to the power supply VDD, the first FD14a, and the first selection section 16a. The source of the first amplification section 15a is connected to the first vertical signal line VLa via the first selection section 16a. The first amplification section 15a amplifies and outputs the signal generated by the charge stored in the capacitor Ca. Figure 3 The first current source 25a shown functions as part of the source follower circuit as a load current source. Transistor M3a is the first amplifying transistor.

[0037] The first reset unit 13a is composed of transistor M2a (controlled by signal RS1), which resets the charge of capacitor Ca and resets the voltage of the first FD14a. Transistor M2a is the first reset transistor. The first selection unit 16a is composed of transistor M4a (controlled by signal SEL1), which outputs the signal from the first amplification unit 15a to the first vertical signal line VLa. Transistor M4a is the first selection transistor. The first output unit according to this embodiment is composed of the first amplification unit 15a and the first selection unit 16a, and generates and outputs a signal based on the charge generated by the first photoelectric conversion unit 11a.

[0038] The second transmission section 12b, composed of transistor M1b (controlled by signal TX2), transmits the charge converted by the second photoelectric conversion section 11b to the second FD14b. That is, the second transmission section 12b forms a charge transmission path between the second photoelectric conversion section 11b and the second FD14b. Transistor M1b is the second transmission transistor. The capacitor Cb of the second FD14b stores the charge transmitted to the second FD14b and converts the charge into a voltage obtained by dividing the capacitance value by Cb. The symbol Cb schematically shows the capacitance attached to the second FD14b. Capacitor Cb includes the capacitance of each transistor, such as the gate capacitance of the second amplification section 15b connected to the second FD14b, and / or wiring capacitance.

[0039] The second amplification section 15b amplifies and outputs the signal generated by the charge stored in capacitor Cb. The second amplification section 15b is composed of a transistor M3b whose drain, gate, and source are respectively connected to the power supply VDD, the second FD14b, and the second selection section 16b. The source of the second amplification section 15b is connected to the second vertical signal line VLb via the second selection section 16b. The second amplification section 15b amplifies and outputs the signal generated by the charge stored in capacitor Cb. Figure 3 The second current source 25b shown functions as part of the source follower circuit as a load current source. Transistor M3b is the second amplifying transistor.

[0040] The second reset section 13b is composed of transistor M2b (controlled by signal RS2), which resets the charge of capacitor Cb and resets the voltage of the second FD14b. Transistor M2b is the second reset transistor. The second selection section 16b is composed of transistor M4b (controlled by signal SEL2), which outputs the signal from the second amplification section 15b to the second vertical signal line VLb. Transistor M4b is the second selection transistor. The second output section according to this embodiment is composed of the second amplification section 15b and the second selection section 16b, and generates and outputs a signal based on the charge generated by the second photoelectric conversion section 11b.

[0041] The addition switch 17, composed of transistor M7 (controlled by signal ADD_FD), connects (combines) the first FD14a and the second FD14b. The combination switch 18, composed of transistor M8 (controlled by signal ADD_SF), connects the first amplification section 15a and the second amplification section 15b. More specifically, the combination switch 18 connects the source of transistor M3a of the first amplification section 15a to the source of transistor M3b of the second amplification section 15b. Furthermore, it can also be said that the combination switch 18 connects the first amplification section 15a with the first selection section 16a and the second amplification section 15b with the second selection section 16b.

[0042] In the first control mode, the control unit 4 controls the imaging element 3 to turn off transistor M7 of the addition switch unit 17 and transistor M8 of the combination switch unit 18. The charge converted by the first photoelectric conversion unit 11a is transmitted to the first FD14a by the first transmission unit 12a. Then, the signal corresponding to the charge transmitted to the first FD14a (the first pixel signal) is read out by the first amplification unit 15a and the first selection unit 16a to the first vertical signal line VLa. Furthermore, the charge converted by the second photoelectric conversion unit 11b is transmitted to the second FD14b by the second transmission unit 12b. The signal corresponding to the charge transmitted to the second FD14b (the second pixel signal) is read out by the second amplification unit 15b and the second selection unit 16b to the second vertical signal line VLb.

[0043] In this way, in the first control mode, the first pixel signal generated based on the charge from the first photoelectric conversion unit 11a is output to the first vertical signal line VLa, and the second pixel signal generated based on the charge from the second photoelectric conversion unit 11b is output to the second vertical signal line VLb. After the first pixel signal and the second pixel signal are subjected to signal processing by the column circuit and the like described later, they are output to the control unit 4 as a pair of focus detection signals.

[0044] Next, the basic operation of the second control mode will be explained. In the second control mode, the control unit 4 turns on the transistor M7 of the adder switch 17 and also turns on the transistor M8 of the combiner switch 18. Furthermore, the control unit 4, for example, turns on the transistor M4a of the first selector 16a and turns off the transistor M4b of the second selector 16b. The charges that have undergone photoelectric conversion by the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b are transmitted by the first transmission unit 12a and the second transmission unit 12b, respectively, added by the adder switch 17, and stored in the first FD14a and the second FD14b. Using the first amplification unit 15a and the second amplification unit 15b, the combiner switch 18, and the first selector 16a, an added pixel signal is generated based on the added charges and read out to the first vertical signal line VLa.

[0045] In addition, in the second control mode, when the transistor M4a of the first selection unit 16a is turned off and the transistor M4b of the second selection unit 16b is turned on, the summed pixel signal is read out to the second vertical signal line VLb.

[0046] In this embodiment, the second control mode includes: a one-line readout mode, which reads the signal according to each row of the two-dimensionally configured pixels 10; and a two-line simultaneous readout mode, which reads the signal from two rows simultaneously. Hereinafter, refer to... Figure 3 The "1-line readout mode" of the second control mode is explained below, please refer to... Figure 4 The "simultaneous reading of two lines" mode in the second control mode is explained.

[0047] Figure 3 A pixel column of a plurality of pixels 10 arranged in a two-dimensional configuration is shown. In the imaging element 3, a first vertical signal line VLa and a second vertical signal line VLb are provided for the column of pixels 10 arranged along the column direction, i.e., vertically. Furthermore, a first current source 25a and a first column circuit section 40a are provided for the first vertical signal line VLa, and a second current source 25b and a second column circuit section 40b are provided for the second vertical signal line VLb. Additionally, in… Figure 3 In the example shown, for the sake of simplicity, pixel 10 is shown as 1 pixel in the row direction and 3 pixels in the column direction, but the camera element 3 has, for example, millions to hundreds of millions of pixels, or more pixels.

[0048] A first current source 25a is connected to each pixel 10 via a first vertical signal line VLa, and a second current source 25b is connected to each pixel 10 via a second vertical signal line VLb. The first current source 25a and the second current source 25b generate current for reading signals from each pixel 10. The first current source 25a supplies the generated current to the first vertical signal line VLa and to the first selection section 16a and the first amplification section 15a of each pixel 10. Similarly, the second current source 25b supplies the generated current to the second vertical signal line VLb and to the second selection section 16b and the second amplification section 15b of each pixel 10.

[0049] The first column circuit section 40a and the second column circuit section 40b are configured to each include an analog-to-digital converter (AD converter). The first column circuit section 40a converts the signal input from each pixel 10 via the first vertical signal line VLa into a digital signal. The second column circuit section 40b converts the signal input from each pixel 10 via the second vertical signal line VLb into a digital signal. The first column circuit section 40a and the second column circuit section 40b output the converted digital signals to the horizontal transmission section described later.

[0050] In the first line readout mode of the second control mode, the imaging element 3 reads out a signal (addition pixel signal) corresponding to the charge obtained by adding the charge of the first photoelectric conversion unit 11a and the charge of the second photoelectric conversion unit 11b to, for example, the first vertical signal line VLa. Figure 3 The example shown illustrates reading the summed pixel signal from pixel 10 in the first row, i.e., the pixel 10 in the bottom row. In pixel 10 of the first row, transistor M7 of the addition switch 17 is turned on, and transistor M8 of the combination switch 18 is also turned on. Furthermore, transistor M4a of the first selection unit 16a is turned on, and transistor M4b of the second selection unit 16b is turned off. On the other hand, in pixel 10 of other rows such as the second and third rows, transistors M4a and M4b of the first selection unit 16a and the second selection unit 16b are turned off. Additionally, in... Figure 3 In this context, ON indicates that the transistor is turned on (connected state, conducting state, short-circuited state), and OFF indicates that the transistor is turned off (cut-off state, non-conducting state, open state, disconnected state).

[0051] In the first row of pixels 10, transistor M7 of the adder switch 17 is turned on, thereby electrically connecting the first FD14a and the second FD14b. Furthermore, the first transmission unit 12a and the second transmission unit 12b are electrically connected. Thus, the charge transmitted from the first photoelectric conversion unit 11a is added to the charge transmitted from the second photoelectric conversion unit 11b. This can also be described as the mixing (combination) of the charges generated by the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b respectively. Capacitors Ca and Cb are electrically connected, and the charge transmitted from the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b is distributed to capacitors Ca and Cb. The voltages of the first FD14a and the second FD14b are averaged and input to the first amplification unit 15a and the second amplification unit 15b. That is, the voltage obtained by adding the stored charge of capacitor Ca and the stored charge of capacitor Cb and dividing the result by the combined capacitance of capacitors Ca and Cb is input to the first amplification section 15a and the second amplification section 15b respectively.

[0052] Transistor M4a of the first selection section 16a is turned on, transistor M4b of the second selection section 16b is turned off, and transistor M8 of the combination switch section 18 is turned on. As a result, both the first amplification section 15a and the second amplification section 15b are supplied with current from the first current source 25a and operate in the saturation region. Since transistors M3a and M3b of the first amplification section 15a and the second amplification section 15b operate in the saturation region, the gate capacitances of both the first amplification section 15a and the second amplification section 15b become approximately constant values.

[0053] Since the gate capacitances of the first amplification section 15a and the second amplification section 15b are approximately fixed, the capacitances of the first FD14a and the second FD14b also remain at predetermined values. Therefore, the first amplification section 15a and the second amplification section 15b output amplified signals based on the voltage obtained by dividing the sum of the stored charges of capacitors Ca and Cb by the combined capacitance of capacitors Ca and Cb. The signals from the first amplification section 15a and the second amplification section 15b are transmitted as additive pixel signals to the first vertical signal line VLa via the first selection section 16a.

[0054] As described above, if the summed pixel signal is read from pixel 10 in the first row to the first vertical signal line VLa, then in the imaging element 3, pixels 10 are selected sequentially row by row, such as the second row and the third row, and the summed pixel signal from pixel 10 to the first vertical signal line VLa is read out. The summed pixel signal of pixel 10 output to the first vertical signal line VLa is converted into a digital signal by the first column circuit section 40a, and then output as an imaging signal to the control section 4.

[0055] exist Figure 3 In the example shown, the summed pixel signals of pixels 10 in each row are read out to the first vertical signal line VLa. Therefore, the imaging element 3 can stop the generation of current from the second current source 25b connected to the second vertical signal line VLb, where the summed pixel signals are not read out, thereby reducing the power consumption of the imaging element 3. Furthermore, when the transistor M4a of the first selection unit 16a is turned off and the transistor M4b of the second selection unit 16b is turned on, the summed pixel signals can be read out from the pixels 10 to the second vertical signal line VLb.

[0056] In this embodiment, the conversion gain of the first FD14a and the second FD14b when converting charge into voltage, i.e., the reciprocal of the combined capacitance of capacitors Ca and Cb, is always approximately constant. Therefore, the summed pixel signal becomes a signal with high linearity that depends on the stored charge of the first FD14a and the second FD14b. Hereinafter, by comparing with a comparative example, it will be explained that the conversion gain of the first FD14a and the second FD14b is always approximately constant.

[0057] In this embodiment, by turning on transistors M4a and M8 and turning off transistor M4b as described above, transistors M3a and M3b are both supplied with current from the first current source 25a and operate in the saturation region. Therefore, the gate capacitances of transistors M3a and M3b in the first amplification section 15a and the second amplification section 15b are both approximately constant values ​​and do not change substantially. Consequently, the capacitance Ca of the first FD14a and the capacitance Cb of the second FD14b are also unaffected by changes in the gate capacitances of transistors M3a and M3b and remain at predetermined values, i.e., approximately constant values. Therefore, the conversion gain of the first FD14a and the second FD14b is always approximately constant. With the advancement of pixel miniaturization, it is conceivable that the ratio of the gate capacitance to the combined capacitance of the first FD14a and the second FD14b will increase. In this case, it is possible to prevent changes in the gate capacitance from causing a deterioration in the linearity of the charge-voltage conversion of the first FD14a and the second FD14b.

[0058] In contrast, the comparative example is... Figure 3 The configuration of the combined switch section 18 has been removed from pixel 10. When the transistor M4a of the first selection section 16a is turned on and the transistor M4b of the second selection section 16b is turned off, current is supplied to the first amplification section 15a, but no current is supplied to the second amplification section 15b, causing the second amplification section 15b to operate in the weak inversion region. Due to the operation in this weak inversion region, the gate capacitance of the transistor M3b of the second amplification section 15b becomes a state that changes according to the signal input to the gate. Due to the change in the gate capacitance of the second amplification section 15b, the capacitances of the first FD14a and the second FD14b also change, thereby causing a change in the charge-voltage conversion gain.

[0059] Figure 4 This diagram illustrates the simultaneous two-row readout method of the second control mode. The simultaneous two-row readout method of the second control mode is as follows: For two rows of pixels, the summed pixel signal is read from one row of pixels onto the first vertical signal line VLa, and simultaneously, the summed pixel signal is read from the other row of pixels onto the second vertical signal line VLb. A detailed explanation follows.

[0060] exist Figure 4 In the first row of pixels 10 at the bottom, transistor M7 of the addition switch 17 is turned on, transistor M8 of the combination switch 18 is also turned on, transistor M4a of the first selection unit 16a is also turned on, and transistor M4b of the second selection unit 16b is turned off. Furthermore, in the second row of pixels 10 adjacent to the first row, transistor M7 of the addition switch 17 is turned on, transistor M8 of the combination switch 18 is also turned on, transistor M4a of the first selection unit 16a is turned off, and transistor M4b of the second selection unit 16b is turned on.

[0061] In each of the first and second row pixels 10, the transistor M7 of the addition switch 17 is turned on, so the charge transferred from the first photoelectric conversion unit 11a and the charge transferred from the second photoelectric conversion unit 11b are added together. Furthermore, in each of the first row pixels 10, due to the conduction of the first selection unit 16a and the conduction of the combination switch 18, the first current source 25a supplies current to the first amplification unit 15a and the second amplification unit 15b, respectively. On the other hand, in each of the second row pixels 10, due to the conduction of the second selection unit 16b and the conduction of the combination switch 18, the second current source 25b supplies current to the first amplification unit 15a and the second amplification unit 15b, respectively. In this way, in both the first and second rows, the transistors M3a and M3b of the first amplification unit 15a and the second amplification unit 15b of each pixel 10 operate in the saturation region, and the gate capacitances of the transistors M3a and M3b are approximately constant.

[0062] Simultaneously, additive pixel signals based on additive charges are read from pixel 10 in row 1 to the first vertical signal line VLa, and simultaneously, additive pixel signals based on additive charges are read from pixel 10 in row 2 to the second vertical signal line VLb. After the simultaneous readout of pixels in row 1 and row 2 is completed, simultaneous readout of pixels in row 3 and row 4 is performed, followed by simultaneous readout of pixels in adjacent odd-numbered and even-numbered rows.

[0063] Like this, in Figure 4 In the simultaneous two-line readout mode shown, the summed pixel signals of two rows of pixels can be read out simultaneously. Therefore, signals can be read out at high speed from each pixel 10 disposed on the imaging element 3. Furthermore, in the simultaneous two-line readout mode, the transistors M3a and M3b of the first amplification section 15a and the second amplification section 15b are also supplied with current from the first current source 25a or the second current source 25b, and operate in the saturation region. Therefore, the gate capacitances of transistors M3a and M3b are both approximately constant, and the summed pixel signal becomes a signal with high linearity that depends on the stored charge of the first FD14a and the second FD14b.

[0064] Reference Figures 5-7 A more detailed explanation of the circuit configuration and operation of the camera element 3 in the first embodiment will be provided. Figure 5 The diagram shows the pixels 10 of the imaging element 3 of the first embodiment in two dimensions, and also shows a circuit diagram of its more detailed circuit configuration. Figure 6 This is a timing diagram showing the operation of the camera element 3 in the case of the first line readout mode of the second control mode. Figure 7 This is a timing diagram showing the operation of the camera element 3 in the case of simultaneous reading of two lines in the second control mode.

[0065] like Figure 5 As shown, the imaging element 3 has a plurality of pixels 10 arranged in rows and columns, a first current source 25a (first current source 25a1 to first current source 25a3), and a second current source 25b (second current source 25b1 to second current source 25b3). Furthermore, the imaging element 3 has a first current control unit 30a (first current control unit 30a1 to first current control unit 30a3) and a second current control unit 30b (second current control unit 30b1 to second current control unit 30b3). The imaging element 3 also has a first column circuit unit 40a (first column circuit unit 40a1 to first column circuit unit 40a3), a second column circuit unit 40b (second column circuit unit 40b1 to second column circuit unit 40b3), a vertical transmission unit 50, and a horizontal transmission unit 60.

[0066] Corresponding to each column of pixel 10, a first vertical signal line VLa (first vertical signal line VLa1 to first vertical signal line VLa3) and a second vertical signal line VLb (second vertical signal line VLb1 to second vertical signal line VLb3) are provided. A first current source 25a, a first current control unit 30a, and a first column circuit unit 40a are provided for the first vertical signal line VLa. Furthermore, a second current source 25b, a second current control unit 30b, and a second column circuit unit 30b are provided for the second vertical signal line VLb. Additionally, in... Figure 5 In the example shown, for simplicity, pixel 10 only represents 3 pixels in the row direction × 3 pixels in the column direction. Figure 5 The bottom left pixel 10 of the multiple pixels 10 shown is designated as pixel 10(0,0) in the first row and first column. Figure 5 The diagram shows pixels 10(0,0) to 10(2,2). The first current source 25a and the second current source 25b are, for example, constructed by cascading two transistors, and generate current based on bias voltages (voltage Bias1, voltage Bias2).

[0067] The vertical transmission unit 50 supplies signals TX, RS, SEL1, SEL2, ADD_FD, ADD_SF, and power supply voltage VDD to each pixel 10, controlling each pixel 10. The first current control unit 30a includes switching units 31a and 32a and an inverter unit 33a, and the second current control unit 30b includes switching units 31b and 32b and an inverter unit 33b. The vertical transmission unit 50 supplies signals CS1_EN, CS2_EN, and voltage Vclip to the first current control unit 30a and the second current control unit 30b. Furthermore, in Figure 5 In the example shown, the first transmission unit 12a and the second transmission unit 12b of pixel 10 are controlled by the same signal TX, and the first reset unit 13a and the second reset unit 13b are controlled by the same signal RS.

[0068] The horizontal transmission unit 60 sequentially transmits the digital signals converted by the first column circuit unit 40a and the second column circuit unit 40b to a signal processing unit (not shown). The signal processing unit performs signal processing such as correlation double sampling and / or correction signal amount processing on the signals input from the horizontal transmission unit 60, and outputs them to the control unit 4 of the camera 1.

[0069] exist Figure 6 In the timing diagram shown, the horizontal axis represents time, illustrating the input to the first line of readout mode in the second control mode. Figure 5 The control signals for each part of the camera element 3. Furthermore, in Figure 6 In this circuit, when the control signal is high (e.g., power supply potential), the transistor receiving the input control signal becomes in the on state, and when the control signal is low (e.g., ground potential), the transistor receiving the input control signal becomes in the off state.

[0070] The vertical transmission unit 50 sets signals ADD_FD and ADD_SF to high level, thus setting it to the second control mode. By setting signal ADD_FD to high level, the first FD14a and the second FD14b of each pixel 10 are electrically connected to each other. Furthermore, by setting signal ADD_SF to high level, the first amplification section 15a and the second amplification section 15b of each pixel 10 are electrically connected.

[0071] The signal CS1_EN is set to a high level, and the signal CS2_EN is set to a low level. When the signal CS1_EN is set to a high level, the switch 31a of the first current control unit 30a is turned on, and the switch 32a is turned off by receiving a low level input through the inverter unit 33a. As a result, current is supplied from the first current source 25a to the first vertical signal line VLa via the switch 31a.

[0072] By making the signal CS2_EN low, the switch 31b of the second current control unit 30b is turned off, and the switch 32b is turned on. As a result, the current supply from the second current source 25b to the second vertical signal line VLb stops, and a voltage Vclip is supplied to the second vertical signal line VLb via the switch 32b. The second vertical signal line VLb is thus fixed at a predetermined voltage, preventing it from becoming floating. Furthermore, current is supplied to the second amplification unit 15b from the first current source 25a via the first selection unit 16a and the combination switch 18, thus preventing the second amplification unit 15b from operating in the weak inversion region.

[0073] exist Figure 6At time t1, the signal RS<0> becomes high, thereby turning on the transistors M2a and M2b of the first reset section 13a and the second reset section 13b in the first row of pixels, namely pixels 10(0,0) to 10(0,2), and the potentials of the first FD14a and the second FD14b become the reset potentials. In this case, as described above, the first FD14a and the second FD14b of pixel 10 are connected, therefore, the potentials of the first FD14a and the second FD14b are averaged.

[0074] Furthermore, at time t1, the signal SEL1<0> becomes high, and the signal based on the reset potential is output to the first vertical signal line VLa through the first amplification unit 15a, the second amplification unit 15b, and the first selection unit 16a. That is, the signal (noise signal) when the potentials of the first FD14a and the second FD14b are reset to the reset potential is read out to the first vertical signal line VLa. The noise signals from each pixel 10 in the first row that are output to the first vertical signal line VLa are respectively input to the first column circuit units 40a1 to 40a3 and converted into digital signals.

[0075] At time t2, the signal TX<0> becomes high, thereby turning on transistors M1a and M1b of the first transmission unit 12a and the second transmission unit 12b. The charge converted by the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b is transferred to the first FD14a and the second FD14b. In this case, the first FD14a and the second FD14b are connected, so the charge transferred from the two photoelectric conversion units is distributed to capacitors Ca and Cb.

[0076] Furthermore, at time t2, the signal SEL1<0> is high, therefore, the summed pixel signal is output to the first vertical signal line VLa through the first amplification unit 15a, the second amplification unit 15b, and the first selection unit 16a. The summed pixel signals from each pixel 10 in the first row, output to the first vertical signal line VLa, are respectively input to the first column circuit units 40a1 to 40a3 and converted into digital signals. The noise signal and the summed pixel signal, converted into digital signals, are input to the signal processing unit via the horizontal transmission unit 60. The signal processing unit performs correlation double sampling on the noise signal and the summed pixel signal of the pixel 10, performing differential processing.

[0077] From time t3 to time t5, similarly to the period from time t1 to time t3, noise signals and summed pixel signals are read from the second row of pixels. From time t5 to time t7, similarly to the period from time t1 to time 3, noise signals and summed pixel signals are read from the third row of pixels. And so on, in Figure 6In the single-row readout method shown, pixels 10 can be selected sequentially row by row, the signals generated by the two photoelectric conversion units of pixel 10 are added together, and the added pixel signal is read out to the first vertical signal line VLa. Furthermore, by stopping the current supply from the second current source 25b, the power consumption of the imaging element 3 can be reduced.

[0078] exist Figure 7 In the timing diagram shown, the horizontal axis represents time, illustrating the input to the second control mode with simultaneous reading of two lines. Figure 5 The control signals for each part of the camera element 3. The vertical transmission unit 50 and... Figure 6 Similarly, in the case of the 1-line readout method shown, signals ADD_FD and ADD_SF are set to high level. Furthermore, signal CS1_EN is set to high level, supplying current from the first current source 25a to the first vertical signal line VLa. Moreover, in... Figure 7 In the simultaneous two-line readout mode, the signal CS2_EN is set to a high level. By making the signal CS2_EN high, the switch 31b of the second current control unit 30b is turned on. As a result, current is supplied from the second current source 25b to the second vertical signal line VLb via the switch 31b.

[0079] At time t1, the signals RS<0> and RS<1> become high, and the transistors M2a and M2b of the first reset section 13a and second reset section 13b of the first row pixels and the second row pixels (pixels 10(0,0) to 10(1,2)) are turned on. As a result, the potentials of the first FD14a and the second FD14b become reset potentials. Furthermore, since the first FD14a and the second FD14b are connected, their potentials are averaged.

[0080] Furthermore, at time t1, the averaged noise signal of the first row of pixels 10 is output to the first vertical signal line VLa by making the signal SEL1<0> high. The noise signals from each pixel 10 in the first row are input to the first column circuit sections 40a1 to 40a3 and converted into digital signals. Also, at time t1, the averaged noise signal of the second row of pixels 10 is output to the second vertical signal line VLb by making the signal SEL2<1> high. The noise signals from each pixel 10 in the second row are input to the second column circuit sections 40b1 to 40b3 and converted into digital signals.

[0081] At time t2, signal TX<0> becomes high, thereby turning on transistors M1a and M1b of the first transmission section 12a and the second transmission section 12b of the first row of pixels 10, and transferring the charge of the first photoelectric conversion section 11a and the second photoelectric conversion section 11b to the first FD14a and the second FD14b. Furthermore, at time t2, signal TX<1> becomes high, thereby transferring the charge of the first photoelectric conversion section 11a and the second photoelectric conversion section 11b of the second row of pixels 10 to the first FD14a and the second FD14b. In this case, in each of the first row of pixels 10 and the second row of pixels 10, the first FD14a and the second FD14b are connected, therefore, the charge transferred from the two photoelectric conversion sections is distributed to capacitors Ca and Cb.

[0082] Furthermore, at time t2, because signals SEL1<0> and SEL2<1> are high, the summed pixel signals of pixels 10 in the first row are output to the first vertical signal line VLa, and the summed pixel signals of pixels 10 in the second row are output to the second vertical signal line VLb. The summed pixel signals from each pixel 10 in the first row output to the first vertical signal line VLa are respectively input to the first column circuit sections 40a1 to 40a3 and converted into digital signals. The summed pixel signals from each pixel 10 in the second row output to the second vertical signal line VLb are respectively input to the second column circuit sections 40b1 to 40b3 and converted into digital signals.

[0083] From time t3 to time t5, similar to the period from time t1 to time t3, the signals from the pixels in the 3rd row and the 4th row are read out simultaneously. From time t5 to time t7, similar to the period from time t1 to time t3, the signals from the pixels in the 5th row and the 6th row are read out simultaneously. And so on. Figure 7 The simultaneous two-row readout method shown allows for the simultaneous readout of signals from two rows of pixels. Therefore, signals can be read out at high speed from each pixel 10 disposed on the imaging element 3.

[0084] Next, the different uses of the first control mode, the single-line readout mode of the second control mode, and the simultaneous two-line readout mode of the second control mode will be explained. When the camera 1 is focusing, the control unit 4 controls the imaging element 3 in the first control mode. Furthermore, when the camera 1 displays a live view image (instant preview image) of the subject on the display unit 6, the control unit 4 controls the imaging element 3 in either the single-line readout mode or the simultaneous two-line readout mode of the second control mode. Therefore, when the camera 1 is displaying a live view image (instant preview image) of the subject on the display unit 6 and is focusing, the control unit 4 controls the imaging element 3 in a time-division manner using either the single-line readout mode or the simultaneous two-line readout mode of the second control mode, while also using the first control mode. When the release operation member of the operation unit 7 is activated, the control unit 4 controls the imaging element 3 in either the single-line readout mode or the simultaneous two-line readout mode of the second control mode.

[0085] Furthermore, when the camera 1 is performing high frame rate shooting, such as high-speed continuous shooting and / or video recording, the control unit 4 controls the imaging element 3 using a two-line simultaneous readout method in the second control mode to read out the summed pixel signal at high speed. Additionally, when the subject movement speed detection unit installed on the camera 1 detects that the subject is moving at a high speed, the control unit 4 also controls the imaging element 3 using a two-line simultaneous readout method in the second control mode to read out the summed pixel signal at high speed and reduce image shake. On the other hand, when the battery level detection unit detects that the remaining amount of the camera 1's drive battery is decreasing, the control unit 4 controls the imaging element 3 using a one-line readout method in the second control mode to reduce battery consumption.

[0086] According to the above implementation method, the following effects can be obtained.

[0087] (1) The camera element 3 has a pixel 10 and a first signal line (first vertical signal line VLa). The aforementioned pixel 10 includes: a first photoelectric conversion unit 11a and a second photoelectric conversion unit 11b, which performs photoelectric conversion on incident light and generates charge; a first storage unit (first FD 14a) that stores the charge generated by the first photoelectric conversion unit 11a; a second storage unit (second FD 14b) that stores the charge generated by the second photoelectric conversion unit 11b; a first output unit (first amplification unit 15a and first selection unit 16a) that generates and outputs a signal based on the charge generated by the first photoelectric conversion unit 11a; a second output unit (second amplification unit 15b and second selection unit 16b) that generates and outputs a signal based on the charge generated by the second photoelectric conversion unit 11b; a first connection unit (connection switch unit 18) disposed between the first output unit and the second output unit; and a second connection unit (addition switch unit 17) which includes a second switch that electrically connects and disconnects the first photoelectric conversion unit 11a and the second photoelectric conversion unit 11b. The first signal line (first vertical signal line VLa) is connected to the first output unit, and a signal from the first output unit is output. In this embodiment, by connecting the first amplification unit 15a and the second amplification unit 15b via the connection switch unit 18, fluctuations in the gate capacitance of the second amplification unit 15b can be suppressed. Therefore, fluctuations in the conversion gain of the charge voltage can be suppressed. As a result, a highly linear additive pixel signal can be obtained.

[0088] (2) The imaging element 3 also includes a control unit (vertical transmission unit 50). The control unit connects the first selection switch (first selection unit 16a) and the first connection unit (connection switch unit 18), disconnects the second selection switch (second selection unit 16b), and outputs the signals from the first output unit and the second output unit to the first signal line (first vertical signal line VLa) via the first selection switch (first selection unit 16a). In this embodiment, by turning on the transistor M8 of the connection switch unit 18, current is supplied from the first current source 25a to the second amplification unit 15b. Therefore, the transistor M3b of the second amplification unit 15b can operate in the saturation region, and the gate capacitance of the second amplification unit 15b can be kept approximately constant. As a result, fluctuations in the charge-voltage conversion gain can be suppressed.

[0089] (Second Implementation)

[0090] Reference Figure 8 The imaging element of the second embodiment will be described. Figure 8 This is a circuit diagram showing the configuration of pixels 10 of the imaging element 3 in the second embodiment. In the first embodiment, as... Figure 2 As shown, an addition switch 17 is disposed in pixel 10. In the second embodiment, as... Figure 8As shown, pixel 10 is configured without the addition switch section 17. Other configurations are the same as in the first embodiment.

[0091] In the first control mode, the transistor M8 of the switching unit 18 is turned off, resulting in the same operation as in the first embodiment. That is, the charge converted by the first photoelectric conversion unit 11a is transferred to the first FD14a, and the charge converted by the second photoelectric conversion unit 11b is transferred to the second FD14b. Furthermore, the first pixel signal generated based on the charge from the first photoelectric conversion unit 11a is output to the first vertical signal line VLa, and the second pixel signal generated based on the charge from the second photoelectric conversion unit 11b is output to the second vertical signal line VLb.

[0092] In the second control mode, the transistor M8 of the switching unit 18 is turned on, and the first amplification unit 15a and the second amplification unit 15b are connected. As a result, an averaged pixel signal from the signals of the first amplification unit 15a and the second amplification unit 15b is output to, for example, the first vertical signal line VL1. The averaged pixel signal output to the first vertical signal line VL1 corresponds to the signal generated by the first amplification unit 15a based on the potential of the first FD14a and the signal generated by the second amplification unit 15b based on the potential of the second FD14b.

[0093] In this embodiment, by interconnecting the first amplification section 15a and the second amplification section 15b via a connecting switch section 18, the signals from the two photoelectric conversion sections are added and output to a vertical signal line. The addition (mixing) of the signals from the first amplification section 15a and the second amplification section 15b occurs at the source of transistor M3a in the first amplification section 15a and the source of transistor M3b in the second amplification section 15b. Therefore, the addition switch section 17 for adding the charges from the two photoelectric conversion sections and the wiring connected to the addition switch section 17 are not required, which reduces the number of elements and / or wiring disposed in each pixel 10. As a result, pixel miniaturization and / or reduction of the chip area of ​​the imaging element can be achieved. Furthermore, it is possible to avoid the reduction in the area of ​​the photoelectric conversion section due to the placement of multiple elements within the pixel.

[0094] Furthermore, in this embodiment, the conversion gain is the reciprocal of the capacitance value of one FD (Function Diode). Therefore, compared to the case where the conversion gain is the reciprocal of the combined capacitance value of two FDs, the conversion gain can be increased. As a result, noise mixed into the summed pixel signals can be relatively reduced, and the S / N ratio can be increased.

[0095] (Third Implementation)

[0096] Reference Figure 9 The imaging element of the third embodiment will be described. Figure 9This is a conceptual diagram illustrating an example of the pixel configuration of the imaging element 3 according to the third embodiment. In the first embodiment, an example was described where multiple photoelectric conversion units are arranged for each pixel 10. In the third embodiment, as... Figure 9 As shown, pixel 10 is configured to have a photoelectric conversion unit. Other configurations are the same as in the first embodiment.

[0097] Pixel 10 includes a microlens ML, a photoelectric conversion unit 11, a transmission unit 12, a reset unit 13, a floating diffuser (FD) 14, a magnifying unit 15, a selection unit 16, an addition switch unit 17, and a combination switch unit 18. The microlens ML converges light incident via the imaging optical system 2 to the photoelectric conversion unit 11. The photoelectric conversion unit 11 is configured corresponding to one microlens ML. The addition switch unit 17 connects, for example, the FD 14 of each of the plurality of pixels 10 arranged in the row direction, and the combination switch unit 18 connects, for example, the magnifying units 15 of each of the plurality of pixels 10 arranged in the row direction.

[0098] In this embodiment, the control unit 4, for example, operates in a first control mode when capturing still images, reading out the signals of each pixel 10 of the imaging element 3, and operates in a second control mode when capturing moving images, adding and reading out the signals of multiple pixels 10. In the first control mode, the control unit 4 controls the imaging element 3 to turn off the transistor M7 of the addition switch unit 17 of each pixel 10, and also turns off the transistor M8 of the combination switch unit 18. In each pixel 10, the charge converted by the photoelectric conversion unit 11 is transmitted to the FD14 through the transmission unit 12. Furthermore, the pixel signal corresponding to the charge transmitted to the FD14 is read out by the amplification unit 15 and the selection unit 16 to the vertical signal line VL. In this way, in the first control mode, the pixel signal of each pixel is read out to the vertical signal line VL.

[0099] In the second control mode, the control unit 4 turns on the addition switch unit 17 and the combination switch unit 18, and the charges converted by the photoelectric conversion unit 11 of each pixel 10 are added together. Furthermore, using the amplification unit 15, the selection unit 16, and the combination switch unit 18, an added pixel signal is generated based on the added charges and read out to the vertical signal line VL. Hereinafter, refer to... Figure 10 and Figure 11 The reading method for line 1 of the second control mode is explained below, please refer to... Figure 10 and Figure 12 The method of reading two lines simultaneously in the second control mode is explained.

[0100] Figure 10 This is a circuit diagram showing a portion of the imaging element in the third embodiment. Figure 11 This is a timing diagram showing the operation of the camera element 3 in the case of the first line readout mode of the second control mode. Figure 12 This is a timing diagram illustrating the operation of the camera element 3 in the case of simultaneous readout of two lines in the second control mode. Additionally, in Figure 10 In the example shown, for simplicity, pixel 10 only represents 4 pixels in the row direction and 3 pixels in the column direction. Figure 10 The bottom left pixel 10 among the multiple pixels 10 shown is designated as pixel 10(0,0) in the first row and first column. Figure 10 The image shows pixels 10(0,0) to 10(2,3).

[0101] like Figure 10 As shown, the imaging element 3 includes: a plurality of pixels 10 arranged in rows and columns, current sources 25 (current sources 25a to 25d), current control units 30 (current control units 30a to 30d), column circuit units 40 (column circuit units 40a to 40d), a vertical transmission unit 50, and a horizontal transmission unit 60. Vertical signal lines VL (vertical signal lines VLa to VLd) are provided corresponding to each column of pixels 10. Current sources 25, current control units 30, and column circuit units 40 are provided on the vertical signal lines VL.

[0102] exist Figure 11 In the single-line readout mode shown, the vertical transmission unit 50 sets signals ADD_FD2 and ADD_SF2 to high level. Meanwhile, signals ADD_FD1 and ADD_SF1 are set to low level. With signal ADD_FD2 high, FD14 of pixel 10 (0,0) is electrically connected to FD14 of pixel 10 (0,1), and FD14 of pixel 10 (0,2) is electrically connected to FD14 of pixel 10 (0,3). Furthermore, FD14 of pixel 10 (1,0) is electrically connected to FD14 of pixel 10 (1,1), and FD14 of pixel 10 (1,2) is electrically connected to FD14 of pixel 10 (1,3). Moreover, FD14 of pixel 10 (2,0) is electrically connected to FD14 of pixel 10 (2,1), and FD14 of pixel 10 (2,2) is electrically connected to FD14 of pixel 10 (2,3).

[0103] When the signal ADD_SF2 goes high, the amplification section 15 of pixel 10 (0,0) is electrically connected to the amplification section 15 of pixel 10 (0,1), and the amplification section 15 of pixel 10 (0,2) is electrically connected to the amplification section 15 of pixel 10 (0,3). Furthermore, the amplification section 15 of pixel 10 (1,0) is electrically connected to the amplification section 15 of pixel 10 (1,1), and the amplification section 15 of pixel 10 (1,2) is electrically connected to the amplification section 15 of pixel 10 (1,3). Also, the amplification section 15 of pixel 10 (2,0) is electrically connected to the amplification section 15 of pixel 10 (2,1), and the amplification section 15 of pixel 10 (2,2) is electrically connected to the amplification section 15 of pixel 10 (2,3).

[0104] The signal CS1_EN is set to a high level, and the signal CS2_EN is set to a low level. When the signal CS1_EN is high, the switching sections 31 of the current control units 30a and 30c are turned on. This supplies current from the current sources 25a and 25c to the vertical signal lines VLa and VLc, respectively. Conversely, when the signal CS2_EN is low, the switching sections 31 of the current control units 30b and 30d are turned off, and the switching section 32 is turned on. This supplies voltage Vclip to the vertical signal lines VLb and VLd, respectively.

[0105] exist Figure 11 At time t1, the signal RS<0> becomes high, thereby turning on the transistor M2 of the reset section 13 of each of the first row of pixels, namely pixels 10(0,0) to 10(0,3), and the potential of FD14 becomes the reset potential. In this case, the potential of FD14 is averaged between the electrically connected FD14s of pixels 10(0,0) and 10(0,1). Furthermore, the potential of FD14 is averaged between the electrically connected FD14s of pixels 10(0,2) and 10(0,3).

[0106] Furthermore, at time t1, the signal SEL1<0> becomes high, and the averaged noise signals of pixels 10(0,0) and 10(0,1) are output to the vertical signal line VLa via the selection unit 16 of pixel 10(0,0). Additionally, the averaged noise signals of pixels 10(0,2) and 10(0,3) are output to the vertical signal line VLc via the selection unit 16 of pixel 10(0,2). The noise signals from each pixel 10 in the first row, output to the vertical signal lines VLa and VLc, are respectively input to the column circuit units 40a and 40c and converted into digital signals.

[0107] At time t2, the signal TX<0> becomes high, thereby turning on the transistor M1 of the transmission unit 12 in pixels 10(0,0), 10(0,1), 10(0,2), and 10(0,3), and the charge converted by the photoelectric conversion unit 11 is transferred to FD14. In this case, the charge transferred from the photoelectric conversion units 11 of pixels 10(0,0) and 10(0,1) is distributed to the capacitor C of FD14 of pixel 10(0,0) and the capacitor C of FD14 of pixel 10(0,1). In addition, the charge transferred from the photoelectric conversion units 11 of pixels 10(0,2) and 10(0,3) is distributed to the capacitor C of FD14 of pixel 10(0,2) and the capacitor C of FD14 of pixel 10(0,3).

[0108] Furthermore, at time t2, since signal SEL1<0> is high, the summed pixel signal obtained by averaging the signals of pixels 10(0,0) and 10(0,1) is output to the vertical signal line VLa via the selection unit 16 of pixel 10(0,0). Similarly, the summed pixel signal obtained by averaging the signals of pixels 10(0,2) and 10(0,3) is output to the vertical signal line VLc via the selection unit 16 of pixel 10(0,2). The summed pixel signals from each pixel 10 in the first row output to the vertical signal lines VLa and VLc are respectively input to the column circuit units 40a and 40c and converted into digital signals.

[0109] From time t3 to time t5, similar to the period from time t1 to time t3, noise signals and summed pixel signals are read from the pixels in the second row. From time t5 to time t7, similar to the period from time t1 to time t3, noise signals and summed pixel signals are read from the pixels in the third row. In this way, in the single-row readout mode, pixels 10 can be selected sequentially row by row, the signals generated by the photoelectric conversion units of two pixels 10 are added together, and the summed pixel signal is read out to the first vertical signal line VLa. Furthermore, by stopping the current supply from the second current source 25b, the power consumption of the imaging element 3 can be reduced.

[0110] exist Figure 12 In the simultaneous reading of two lines shown, the vertical transmission unit 50 and the above-mentioned Figure 11Similarly, in the case of reading line 1, signals ADD_FD2 and ADD_SF2 are set to high level. Additionally, signals ADD_FD1 and ADD_SF1 are set to low level. Furthermore, signals CS1_EN and CS2_EN are also set to high level. With CS1_EN high, current is supplied from current sources 25a and 25c to the vertical signal lines VLa and VLc, respectively. Similarly, with CS2_EN high, current is supplied from current sources 25b and 25d to the vertical signal lines VLb and VLd, respectively.

[0111] exist Figure 12 At time t1, the signals RS<0> and RS<1> become high, and the transistors M2 of the reset units 13 of the first row pixels and the second row pixels (pixels 10(0,0) to 10(1,3)) are turned on. In this case, the potential of FD14 is averaged between the electrically connected FD14.

[0112] Furthermore, at time t1, when signal SEL1 < 0 > becomes high, the averaged noise signals of pixels 10(0,0) and 10(0,1) are output to the vertical signal line VLa via the selection unit 16 of pixel 10(0,0). Similarly, the averaged noise signals of pixels 10(0,2) and 10(0,3) are output to the vertical signal line VLc via the selection unit 16 of pixel 10(0,2). Also at time t1, when signal SEL2 < 1 > becomes high, the averaged noise signals of pixels 10(1,0) and 10(1,1) are output to the vertical signal line VLb via the selection unit 16 of pixel 10(1,1). Finally, the averaged noise signals of pixels 10(1,2) and 10(1,3) are output to the vertical signal line VLd via the selection unit 16 of pixel 10(1,3). The noise signals from each pixel 10 in the first and second rows, which are output to the vertical signal lines VLa to VLd, are respectively output to the column circuit sections 40a to 40d and converted into digital signals.

[0113] At time t2, the signal TX<0> becomes high, and in pixels 10(0,0) to 10(0,3), the transistor M1 of the transmission unit 12 is turned on, and the charge converted by the photoelectric conversion unit 11 is transferred to FD14. Furthermore, at time t2, the signal TX<1> becomes high, and in pixels 10(1,0) to 10(1,3), the transistor M1 of the transmission unit 12 is turned on, and the charge converted by the photoelectric conversion unit 11 is transferred to FD14.

[0114] Furthermore, at time t2, because signal SEL1<0> is high, the sum of pixel signals of pixels 10(0,0) and 10(0,1) is output to the vertical signal line VLa via the selection unit 16 of pixel 10(0,0). Similarly, the sum of pixel signals of pixels 10(0,2) and 10(0,3) is output to the vertical signal line VLc via the selection unit 16 of pixel 10(0,2). Also at time t2, because signal SEL2<1> is high, the sum of pixel signals of pixels 10(1,0) and 10(1,1) is output to the vertical signal line VLb via the selection unit 16 of pixel 10(1,1). Finally, the sum of pixel signals of pixels 10(1,2) and 10(1,3) is output to the vertical signal line VLd via the selection unit 16 of pixel 10(1,3). The summed pixel signals from each pixel 10 in the first and second rows, which are output to the vertical signal lines VLa to VLd, are respectively input to the column circuit sections 40a to 40d and converted into digital signals.

[0115] From time t3 to time t5, similar to the period from time t1 to time t3, signals from the pixels in the third row and from the pixels in the fourth row are read out simultaneously. From time t5 to time t7, similar to the period from time t1 to time 3, signals from the pixels in the fifth row and from the pixels in the sixth row are read out simultaneously. In this way, the two-row simultaneous readout method can read out signals from the pixels in two rows at the same time. Therefore, signals can be read out at high speed from each pixel 10 disposed on the imaging element 3.

[0116] The following modifications are also within the scope of the present invention, and one or more modifications can be combined with the above-described embodiments.

[0117] (Variation Example 1)

[0118] In the third embodiment described above, an example in which an addition switch 17 is provided in pixel 10 was described. However, as... Figure 13As shown, the pixel configuration can also be configured without the addition switch section 17. In this case, in the first control mode, the transistor M8 of the combination switch section 18 is turned off, operating in the same manner as in the third embodiment. Furthermore, in the second control mode, the transistor M8 of the combination switch section 18 is turned on, and the amplification sections 15 of each pixel 10 are electrically connected to each other. As a result, the summed pixel signal, which is averaged by summing the signals of the amplification sections 15 of each pixel 10, is output to the vertical signal line VL. Thus, in Modification 1, by connecting the amplification sections 15 of multiple pixels 10 to each other via the combination switch section 18, signals from multiple photoelectric conversion sections can be summed and output to the vertical signal line. In addition, the combination switch section 18 can be configured for each pixel 10. Alternatively, the combination switch section 18 can be configured for each of multiple pixels, forming a configuration shared by multiple pixels. Furthermore, the addition switch section 17 can be configured for each of multiple pixels, forming a configuration shared by multiple pixels.

[0119] (Variation Example 2)

[0120] In the first embodiment described above, an example of configuring two photoelectric conversion units in one pixel was given, but the pixel configuration is not limited to this. The pixel configuration may also include a configuration where each pixel has three or more photoelectric conversion units. In this case, for example, in the first control mode, signals from multiple photoelectric conversion units may be read out separately, and in the second control mode, signals from two or more of the multiple photoelectric conversion units may be added together and read out.

[0121] (Variation Example 3)

[0122] In the above embodiments and variations, an example using a photodiode as the photoelectric conversion unit has been described. However, a photoelectric conversion film may also be used as the photoelectric conversion unit.

[0123] (Variation Example 4)

[0124] The imaging element 3 described in the above embodiments and variations can also be applied to cameras, smartphones, tablets, cameras built into PCs, vehicle cameras, cameras mounted on drones (unmanned aerial vehicles, radio controllers, etc.).

[0125] Various embodiments and modifications have been described above, but the present invention is not limited to these descriptions. Other embodiments conceivable within the scope of the technical concept of the present invention are also included within the scope of the present invention.

[0126] The disclosure of the following priority-based application is incorporated herein by reference.

[0127] Japanese Patent Application No. 16285 of 2017 (filed on January 31, 2017)

[0128] Explanation of reference numerals in the attached figures

[0129] 3. Camera element, 4. Control unit, 10. Pixel, 11a. First photoelectric conversion unit, 11b. Second photoelectric conversion unit, 17. Addition switch unit, 18. Combination switch unit, 50. Vertical transmission unit.

Claims

1. A camera element, characterized in that, have: The first floating diffuser is used to transfer the charge obtained from the light conversion of the first microlens. The second floating diffuser is used to transfer charge obtained from the light converted by the second microlens, which is different from the first microlens. The first amplification section has a transistor including a gate section connected to the first floating diffusion section, and outputs a first signal based on the charge transferred to the first floating diffusion section; The second amplification section has a transistor including a gate section connected to the second floating diffusion section, and outputs a second signal based on the charge transferred to the second floating diffusion section; The first signal line is connected to the first amplification section and outputs the first signal; The second signal line is connected to the second amplifier section and outputs the second signal; as well as The first connection switch is capable of connecting a connection path for electrically connecting the first amplification section to the first signal line and a connection path for electrically connecting the second amplification section to the second signal line.

2. The imaging element as claimed in claim 1, characterized in that, have: A first photoelectric conversion unit performs photoelectric conversion on light transmitted through the first microlens; and The second photoelectric conversion unit performs photoelectric conversion on the light transmitted through the second microlens, wherein the second microlens is different from the first microlens.

3. The imaging element as described in claim 1, characterized in that, have: A first selection unit, which is connected to the first amplification unit and the first signal line; and The second selection unit is connected to the second amplification unit and the second signal line. The first amplification section is connected to the first signal line via the first selection section. The second amplification section is connected to the second signal line via the second selection section. The first connection switch can connect a connection path for connecting the first amplification part and the first selection part, and a connection path for connecting the second amplification part and the second selection part.

4. The imaging element as described in claim 3, characterized in that, When the first selection unit connects the first amplification unit to the first signal line, and the second selection unit disconnects the second amplification unit from the second signal line, the first connection switch becomes connected.

5. The imaging element as described in claim 3, characterized in that, When the first selection unit connects the first amplification unit to the first signal line, and the second selection unit connects the second amplification unit to the second signal line, the first connection switch is turned off.

6. The imaging element as described in claim 3, characterized in that, It has a second connection switch for connecting the first floating diffuser and the second floating diffuser.

7. The imaging element as described in claim 6, characterized in that, When the second connection switch is in the connected state, the first selection unit connects the first amplification unit to the first signal line, and the second selection unit disconnects the second amplification unit from the second signal line, the first connection switch becomes connected.

8. The imaging element as claimed in claim 6, characterized in that, When the second connection switch is in the off state, the first selection unit connects the first amplification unit to the first signal line, and the second selection unit connects the second amplification unit to the second signal line, the first connection switch is in the off state.

9. The imaging element as claimed in claim 2, characterized in that, It has a second connection switch for connecting the first floating diffuser and the second floating diffuser.

10. The imaging element as claimed in claim 9, characterized in that, When the second connection switch is in the connected state, the charge obtained by photoelectric conversion by the first photoelectric conversion unit and the charge obtained by photoelectric conversion by the second photoelectric conversion unit are stored in the first floating diffusion unit and the second floating diffusion unit, and a signal based on the charge stored in the first floating diffusion unit and the charge stored in the second floating diffusion unit is output from the first amplification unit to the first signal line, the first connection switch becomes connected.

11. The imaging element as claimed in claim 2, characterized in that, When the charge obtained by photoelectric conversion by the first photoelectric conversion unit is stored in the first floating diffusion unit, and the charge obtained by photoelectric conversion by the second photoelectric conversion unit is stored in the second floating diffusion unit, and a signal based on the charge stored in the first floating diffusion unit is output from the first amplification unit to the first signal line, and a signal based on the charge stored in the second floating diffusion unit is output from the second amplification unit to the first signal line, the first connection switch becomes connected.

12. The imaging element as claimed in claim 9, characterized in that, When the second connection switch is in the off state, the charge obtained by photoelectric conversion by the first photoelectric conversion unit is stored in the first floating diffusion unit, the charge obtained by photoelectric conversion by the second photoelectric conversion unit is stored in the second floating diffusion unit, and a signal based on the charge stored in the first floating diffusion unit is output from the first amplification unit to the first signal line, and a signal based on the charge stored in the second floating diffusion unit is output from the second amplification unit to the second signal line, the first connection switch becomes the off state.

13. The imaging element as claimed in claim 1, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. The first current source and the second amplifier can be connected via the first connection switch.

14. The imaging element as claimed in claim 4, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. When the first selection unit connects the first amplifier and the first signal line, and the second selection unit disconnects the second amplifier and the second signal line, the first connection switch is connected, and current is supplied from the first current source to the second amplifier via the first connection switch.

15. The imaging element as claimed in claim 5, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. When the first selection unit connects the first amplifier and the first signal line, and the second selection unit connects the second amplifier and the second signal line, the first connection switch is turned off, and current is supplied from the first current source to the first amplifier and from the second current source to the second amplifier.

16. The imaging element as claimed in claim 7, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. When the second connection switch is in the connected state, the first selection unit connects the first amplification unit and the first signal line, and the second selection unit disconnects the second amplification unit and the second signal line, the first connection switch is connected, and current is supplied from the first current source to the second amplification unit via the first connection switch.

17. The imaging element as claimed in claim 8, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. When the second connection switch is in the off state, the first selection unit connects the first amplification unit and the first signal line, and the second selection unit connects the second amplification unit and the second signal line, the first connection switch is in the off state, current is supplied from the first current source to the first amplification unit, and current is supplied from the second current source to the second amplification unit.

18. The imaging element as claimed in claim 10, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. When the second connection switch is in the connected state, the charge obtained by photoelectric conversion by the first photoelectric conversion unit and the charge obtained by photoelectric conversion by the second photoelectric conversion unit are stored in the first floating diffusion unit and the second floating diffusion unit, and a signal based on the charge stored in the first floating diffusion unit and the charge stored in the second floating diffusion unit is output from the first amplification unit to the first signal line, the first connection switch becomes connected, and current is supplied from the first current source to the second amplification unit via the first connection switch.

19. The imaging element as claimed in claim 11, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. The charge obtained by photoelectric conversion by the first photoelectric conversion unit is stored in the first floating diffusion unit, and the charge obtained by photoelectric conversion by the second photoelectric conversion unit is stored in the second floating diffusion unit. When the first amplification unit outputs a signal based on the charge stored in the first floating diffusion unit to the first signal line, and the second amplification unit outputs a signal based on the charge stored in the second floating diffusion unit to the first signal line, the first connection switch is in a connected state, and current is supplied from the first current source to the second amplification unit via the first connection switch.

20. The imaging element as claimed in claim 12, characterized in that, have: A first current source, which is connected to the first amplification section via the first signal line; and The second current source is connected to the second amplifier via the second signal line. When the second connection switch is in the off state, the charge obtained by photoelectric conversion by the first photoelectric conversion unit is stored in the first floating diffusion unit, the charge obtained by photoelectric conversion by the second photoelectric conversion unit is stored in the second floating diffusion unit, and a signal based on the charge stored in the first floating diffusion unit is output from the first amplification unit to the first signal line, and a signal based on the charge stored in the second floating diffusion unit is output from the second amplification unit to the second signal line, the first connection switch becomes the off state, current is supplied from the first current source to the first amplification unit, and current is supplied from the second current source to the second amplification unit.

21. The imaging element as claimed in any one of claims 2, 9 to 12, 18 to 20, characterized in that, have: A first transmission unit, which is connected to the first photoelectric conversion unit; and The second transmission unit is connected to the second photoelectric conversion unit. The first photoelectric conversion unit is connected to the first floating diffusion unit via the first transmission unit, and the second photoelectric conversion unit is connected to the second floating diffusion unit via the second transmission unit.

22. The imaging element as claimed in any one of claims 1 to 20, characterized in that, have: A first reset section, which is connected to the first floating diffusion section; and The second reset section is connected to the second floating diffusion section. The first floating diffusion section is connected to the first amplification section via the first reset section. The second floating diffusion section is connected to the second amplification section via the second reset section.

23. A camera device comprising the camera element according to any one of claims 1 to 22.

Images