In-device symbol data movement system

Abstract

An in-device symbolic data movement system has a housing including a processing system configured to provide a first thread and a second thread. A data mover subsystem within the housing is coupled to the processing system. In communications transmitted by the first thread, the data mover subsystem recognizes a request to transfer data to the second thread, the data being stored in a first portion of the memory system associated with the first thread in a memory architecture management database. The data mover subsystem then modifies symbolic reference information in the memory architecture management database to deassociate the first portion of the memory system from the first thread and associate the first portion of the memory system with the second thread, allowing the second thread to reference the data using request / response operations.

Description

Technical Field

[0001] The embodiments disclosed in this application relate to data movement in a storage system. More specifically, the embodiments disclosed in this application relate to an in-device symbol data movement system. Background Technology

[0002] This disclosure generally relates to information processing systems, and more specifically, to data movement within information processing systems via symbolic reference information modification techniques.

[0003] As the value and use of information continue to increase, individuals and businesses seek additional methods for processing and storing information. One option available to users is an information processing system. Information processing systems typically process, compile, store, and / or deliver information or data for business, personal, or other purposes, enabling users to leverage the value of information. Because technology and information processing needs vary across different users or applications, information processing systems can also differ in what information they process, how they process it, how much information they process, store, or deliver, and the speed and efficiency with which they process, store, or deliver information. This variability in information processing systems allows them to be general-purpose or configured for specific users or purposes, such as financial transaction processing, airline ticket booking, enterprise data storage, or global communications. Furthermore, information processing systems can include a variety of hardware and software components that can be configured to process, store, and deliver information, and can include one or more computer systems, data storage systems, and network systems.

[0004] Information processing systems, such as server devices, typically operate to facilitate the movement of data. For example, the processor system included in a server device may operate to provide multiple virtual machines and / or other applications, and these virtual machines may include threads that transfer data to each other. Data transfer between threads included on virtual machines provided by a server device is relatively slow, consumes memory bandwidth, and / or introduces other data transfer inefficiencies known in the art.

[0005] Furthermore, as network and storage systems catch up to the speed of processing / memory system pairs, the traditional processing / memory system pairings, based on the paradigm that processing / memory system pairs are "fast" while network and storage systems are "slow," are being rethought. For example, memory architectures such as the Gen-Z memory architecture have been introduced to eliminate bottlenecks and improve efficiency relative to traditional systems by unifying communication paths and simplifying the software required for processing / memory system communication. As those skilled in the art who have mastered this disclosure will understand, such memory architectures extend the byte-addressable load / store model of processing / memory systems to the entire system by decoupling processing / computing functions from memory / media functions. This allows the processing and memory systems to act as peers using the same language and communicating through simplified, high-performance, low-latency communication paths that do not incur the translation penalties and software overhead associated with traditional systems.

[0006] However, the inventors of this disclosure have discovered that data transfer between threads included on a virtual machine provided by a server device and via such memory configuration remains inefficient. For example, data transfer from a first thread included on a first virtual machine provided by the server device to a second thread included on a second virtual machine provided by the same server device may include the first thread generating a memory load instruction and transmitting the memory load instruction to a memory configuration requester associated with the processing system providing the first virtual machine. In response to receiving the memory load instruction, the memory configuration requester then transmits a memory configuration request to a memory configuration responder associated with the memory system. The memory configuration responder then retrieves the data requested in the memory configuration request from a memory device in the memory system and transmits that data as a payload in the memory configuration response to the memory configuration requester. The memory configuration requester then loads the data in the memory configuration response into the local memory system utilized by the processing system providing the first virtual machine, which allows the first thread to transfer the data (e.g., via a copy engine) to the second thread (e.g., by copying the data to the local memory system utilized by the processing system providing the second virtual machine). Therefore, data movement between threads on a virtual machine provided by the same server device and via memory architecture requires several read, write, copy and / or other data transfer operations, which the inventors of this disclosure have found to be unnecessary.

[0007] Therefore, it is desirable to provide an improved in-device data movement system. Summary of the Invention

[0008] According to one embodiment, an Information Processing System (IHS) includes a processing system; and a memory system coupled to the processing system and including instructions, which, when executed by the processing system, cause the processing system to provide a data mover engine, the data mover engine being configured to: identify, in communication transmitted by a first thread provided by at least one processing system included in a housing, a request to transfer data to a second thread provided by the at least one processing system included in the housing, wherein the data is stored in a first portion of the memory system associated with the first thread in a memory architecture management database; and modify symbolic reference information in the memory architecture management database to deassociate the first portion of the memory system from the first thread and associate the first portion of the memory system with the second thread, wherein associating the first portion of the memory system with the second thread allows the second thread to reference the data using a request / response operation. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating one embodiment of an Information Processing System (IHS).

[0010] Figure 2 This is a schematic diagram illustrating one embodiment of a network system.

[0011] Figure 3 It shows that it can be included in Figure 2 A schematic diagram of an embodiment of a server device for a device-in-device symbol data movement system disclosed herein may be provided in a networked system.

[0012] Figure 4 It shows that it can be included in Figure 2 A schematic diagram of an embodiment of a memory system in a network system.

[0013] Figure 5 This is a flowchart illustrating one embodiment of a method for providing symbolic data movement within a device.

[0014] Figure 6A It shows Figure 3 The server equipment in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0015] Figure 6B It shows Figure 4 Memory systems in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0016] Figure 7 It shows Figure 3The server equipment in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0017] Figure 8 It shows Figure 3 The server equipment in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0018] Figure 9 It shows Figure 4 Memory systems in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0019] Figure 10A It shows Figure 3 The server equipment in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0020] Figure 10B It shows Figure 4 Memory systems in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0021] Figure 10C It shows Figure 4 Memory systems in Figure 5 A schematic diagram of an embodiment of the operation during the method.

[0022] Figure 10D It shows Figure 3 The server equipment in Figure 5 A schematic diagram of an embodiment of the operation during the method. Detailed Implementation

[0023] For the purposes of this disclosure, an information processing system may include any tool or set of tools operable for computing, calculating, determining, classifying, disposing of, transmitting, receiving, retrieving, initiating, switching, storing, displaying, transmitting, exhibiting, detecting, recording, reproducing, processing, or utilizing any form of information, intelligence, or data for commercial, scientific, control, or other purposes. For example, an information processing system may be a personal computer (e.g., a desktop or laptop computer), a tablet computer, a mobile device (e.g., a personal digital assistant (PDA) or smartphone), a server (e.g., a blade server or rack server), a network storage device, or any other suitable device, and may vary in size, shape, performance, functionality, and price. An information processing system may include random access memory (RAM), one or more processing resources (such as a central processing unit (CPU) or hardware or software control logic), ROM, and / or other types of non-volatile memory. Additional components of the information processing system may include one or more disk drives, one or more network ports for communicating with external devices, and various input and output (I / O) devices such as a keyboard, mouse, touchscreen, and / or video display. The information processing system may also include one or more buses operable for transmitting communication between various hardware components.

[0024] In one embodiment, Figure 1 The IHS 100 includes a processor 102 connected to a bus 104. The bus 104 acts as a connection between the processor 102 and other components of the IHS 100. An input device 106 is coupled to the processor 102 to provide input to the processor 102. Examples of input devices may include a keyboard, a touchscreen, pointing devices (such as a mouse, trackball, and touchpad), and / or various other input devices known in the art. Program and data are stored on a mass storage device 108, which is coupled to the processor 102. Examples of mass storage devices may include hard disks, optical disks, magneto-optical disks, solid-state storage devices, and / or various other mass storage devices known in the art. The IHS 100 also includes a display 110, which is coupled to the processor 102 via a video controller 112. System memory 114 is coupled to the processor 102 to provide fast storage for the processor, thereby facilitating the execution of computer programs by the processor 102. Examples of system memory may include random access memory (RAM) devices (such as dynamic RAM (DRAM), synchronous DRAM (SDRAM)), solid-state memory devices, and / or various other memory devices known in the art. In one embodiment, housing 116 houses some or all of the components of IHS 100. It should be understood that additional buses and intermediate circuitry may be deployed between the aforementioned components and processor 102 to facilitate interconnection between these components and processor 102.

[0025] Now for reference Figure 2 This illustrates one embodiment of a network system 200. In the illustrated embodiment, the network system 200 includes multiple server devices 202a, 202b, up to 202c. In one embodiment, any or all of the server devices 202a-c may be referenced above. Figure 1 The IHS 100 discussed may provide, and / or may include, some or all of the components of the IHS 100. However, although shown and discussed as server devices, those skilled in the art will recognize that the server devices 202a-c provided in network system 200 may be provided by any device that can be configured to operate similarly to those discussed below. While only three server devices 202a-c are shown and discussed below, those skilled in the art will recognize that more server devices may (and typically will) be provided in network system 200 (e.g., a data center) while remaining within the scope of this disclosure.

[0026] In the illustrated embodiment, server devices 202a-c are each coupled to network 204, which is included in network system 200 and may be provided by, for example, a local area network (LAN), the Internet, and / or any other network (or combination of networks) that is obvious to those skilled in the art possessing this disclosure. Furthermore, the illustrated embodiment of network system 200 includes a memory system 206 coupled to server devices 202a-c via network 204. In one embodiment, memory system 206 may be provided by the aforementioned reference... Figure 1 The IHS 100 discussed herein provides, and / or may include some or all of the components of IHS 100. In a specific example, memory system 206 may be provided by one or more separate server devices as a logical part of one or more of server devices 202, 204, and 206, and / or in various other ways that will be obvious to those skilled in the art to have mastered this disclosure. In the embodiments discussed below, memory system 206 provides a memory architecture connected to a network, which may be utilized by any of the server devices 202a-c via network 204.

[0027] For example, the memory architecture connected to the network could be a Gen-Z memory architecture created and commercialized by the Gen-Z Consortium. Those skilled in the art will recognize that the Gen-Z memory architecture extends the byte-addressable load / store model of the processing system / memory system to the entire network system 200 by decoupling the processing system / computing functions in server devices 202a-c from the memory system / media functions in memory system 206. This allows the processing system and memory system to act as peers communicating using the same language and through simplified, high-performance, low-latency communication paths that do not incur the translation penalties and software overhead associated with legacy systems. Therefore, bottlenecks are eliminated and efficiency is improved by unifying communication paths and simplifying the software required for processing system / memory system communication. However, those skilled in the art will recognize that other types of memory architectures also fall within the scope of this disclosure. Furthermore, although server devices 202a-c are shown as each coupled to memory system 206 via network 204, those skilled in the art will recognize that in other embodiments, memory system 206 may be provided within the server devices while still implementing the functionality described below, and remaining within the scope of this disclosure. Therefore, although a specific network system 200 has been shown and described, those skilled in the art will recognize that the in-device symbol data movement system of this disclosure may utilize various other components and component configurations, while also remaining within the scope of this disclosure.

[0028] Now for reference Figure 3 An embodiment of server device 300 is shown, which can provide the above reference. Figure 2 The discussion refers to any server equipment 202a-c. Therefore, server equipment 300 can be referenced from the above. Figure 1 The IHS 100 discussed herein provides, and / or may include some or all of the components of the IHS 100. Furthermore, although shown and discussed as server device 300, those skilled in the art who have mastered this disclosure will recognize that the functionality of the server device 300 discussed below can be provided by any device configured to operate in a similar manner as discussed below. In the illustrated embodiment, server device 300 includes a housing 302 that houses the components of server device 300, only some of which will be discussed below.

[0029] For example, such as Figure 3As shown, the housing 302 can accommodate multiple processing systems 304, 306, up to 308, wherein each processing system 304, 306, and 308 includes its own memory configuration logic subsystems 304a, 306a, and 308a. Specifically, processing systems 304, 306, and 308 can be provided by a central processing unit (CPU) device, a system-on-a-chip (SOC) device, and / or other processing systems excluding a media controller device (which, as described below, may be provided in a memory configuration memory system utilized by the processing systems). Therefore, the memory configuration logic subsystems 304a, 306a, and 308a included in processing systems 304, 306, and 308, respectively, can implement at least some of the memory configuration functions discussed below. In one specific example, the memory architecture is a Gen-Z memory architecture, and the memory architecture logic subsystem operates to provide Gen-Z logic for utilizing the Gen-Z memory architecture. However, those skilled in the art who have mastered this disclosure will recognize that the teachings of this disclosure can utilize other memory architectures and memory architecture logic subsystems while remaining within their scope. Although not shown, each of the processing systems 304, 306, and 308 may be coupled to one or more local memory systems provided in the server device 300 and including instructions that, when executed by the processing systems 304, 306, and 308, allow the processing systems 304, 306, and 308 to perform any of the functions discussed below (e.g., providing virtual machines, applications, threads, data mover engines, etc.).

[0030] In some embodiments, housing 302 may house a data mover processing system (not shown, but may include the above-mentioned references) Figure 1 The processor 102 discussed herein and the data mover memory system (not shown, but which may include the above references) Figure 1The discussed memory 114, the data mover memory system coupled to the data mover processing system, includes instructions that, when executed by the data mover processing system, cause the data mover processing system to provide a data mover engine 310, which is configured to perform the functions of the data mover engine and / or server device discussed below. In the illustrated embodiment, the data mover engine 310 is shown as separate from the processing systems 304, 306, and 308, and therefore can be provided by separate data mover hardware and software (e.g., provided as a field-programmable gate array (FPGA) on a peripheral component interconnect high-speed (PCIe) card and / or other subsystems known in the art) coupled to these processing systems 304, 306, and 308. However, in other embodiments, the data mover engine 310 may be integrated with, included in, and / or otherwise part of any one or each of the processing systems 304, 306, and 308. Therefore, in these embodiments, the data mover engine 310 may be provided by instructions on a local memory system in the server device 300, which is utilized by any or each of the processing systems 304, 306 and 308, provided as part of an FPGA of any or each of the processing systems 304, 306 and 308, and / or provided in various ways that are obvious to those skilled in the art who have mastered this disclosure.

[0031] In some embodiments, in addition to the in-device symbolic data movement operations discussed below, the data mover engine 310 may also be configured to perform read, write, copy, and / or other data movement operations on processing systems 304, 306, and 308 (e.g., to their local memory systems) to, for example, alleviate the problem that processing systems 304, 306, and 308 have to use processing cycles to perform these operations. However, those skilled in the art will recognize that the functionality of the data mover engine 310 discussed below may be provided by itself and / or in conjunction with other functionality, while remaining within the scope of this disclosure. Although several examples of data mover engine implementations and functions have been described, those skilled in the art will recognize that various different functions of the data mover engine 310 may be implemented in various ways, and these ways will also fall within the scope of this disclosure.

[0032] In the illustrated embodiment, housing 302 houses a memory architecture management subsystem 312 configured to provide memory architecture management operations to server device 300. For example, when the memory architecture is the Gen-Z memory architecture described above, memory architecture management subsystem 312 may include a Gen-Z memory management unit (Gen-ZZMMU), which, in the example provided below, operates as a Gen-Z ZMMU requester providing access to the Gen-Z memory architecture to processing systems 304, 306, and 308. However, those skilled in the art, upon receiving this disclosure, will recognize that the teachings of this disclosure can be utilized with other memory architecture management subsystems for other memory architectures, while remaining within their scope.

[0033] The housing 302 may also accommodate a storage system (not shown, but it may include the above-mentioned references). Figure 1 The storage system discussed (108) is coupled to the data mover engine 310 (e.g., via coupling between the storage system and the data mover processing system) and to the memory structure management subsystem 312, and includes a memory structure management database 314 configured to store any information utilized by the data mover engine 310 and / or the memory structure management subsystem 312 discussed below (e.g., memory structure reference pointers, memory structure page ownership information, etc.). While a specific server device 300 has been shown, those skilled in the art, upon receiving this disclosure, will recognize that a server device (or other device operating in a manner similar to that described below for server device 300 in accordance with the teachings of this disclosure) may include various components and / or component configurations for providing conventional server device functionality as well as the functionality discussed below, while remaining within the scope of this disclosure.

[0034] Now for reference Figure 4 An embodiment of the memory system 400 is shown, which may be provided for the above reference. Figure 2 The memory system 206 is discussed. Therefore, this memory system can be referenced above. Figure 1The IHS 100 discussed herein provides, and / or may include some or all of the components of the IHS 100, and in specific examples may be provided by one or more separate server devices, one or more server devices 202, 204, and 206, and / or in various other ways that will be obvious to those skilled in the art upon which this disclosure is known. Furthermore, although shown and discussed as a memory system, those skilled in the art upon which this disclosure is known will recognize that the functionality of the memory system discussed below can be provided by any device configured to operate in a manner similar to that discussed below. In the illustrated embodiment, the memory system 400 includes a housing 402 that houses the components of the memory system 400, some of which will only be discussed below.

[0035] For example, housing 402 may house one or more memory devices 404, which may be provided by dynamic random access memory (DRAM) devices, storage class memory (SCM) devices, solid-state drive (SSD) device arrays, and / or any other memory devices that are obvious to those skilled in the art upon which this disclosure is known. In the illustrated embodiment, housing 402 houses a media controller device 406 coupled to the memory device 404. Although shown as a single media controller device 406 coupled to one or more memory devices 404, those skilled in the art will recognize that multiple media controller devices may be provided for the memory device 404 while remaining within the scope of this disclosure. For example, a separate media controller device may be provided for each memory device technology (e.g., a first media controller device may be provided for a DRAM device, a second media controller device may be provided for an SCM device, etc.). However, while several specific examples of memory devices and media controller devices have been discussed, those skilled in the art will recognize that a wide variety of memory device and / or media controller device components and / or configurations will also fall within the scope of this disclosure.

[0036] In the illustrated embodiment, housing 402 houses a memory architecture management subsystem 408 configured to provide memory architecture management operations to memory system 400. For example, when the memory architecture is a Gen-Z memory architecture as discussed above, memory architecture management subsystem 408 may include a Gen-Z memory management unit (Gen-Z ZMMU), which, in the example provided below, operates as a Gen-Z ZMMU responder, operating in conjunction with a Gen-Z ZMMU requester that provides access to the Gen-Z memory architecture to processing systems 304, 306, and 308. However, those skilled in the art, upon receiving this disclosure, will recognize that the teachings of this disclosure can be utilized with other memory architecture management subsystems for other memory architectures, while remaining within their scope. Although a specific memory system 400 has been shown, those skilled in the art who have mastered this disclosure will recognize that a memory system (or other systems that operate in a manner similar to that described below for memory system 400 in accordance with the teachings of this disclosure) may include various components and / or component configurations for providing conventional memory system functions as well as the functions discussed below, while also remaining within the scope of this disclosure.

[0037] Now for reference Figure 5An embodiment of a method for providing symbolic data movement within a device is illustrated. As described below, the systems and methods of this disclosure provide data "transfer" while avoiding the need to perform read, write, copy, and / or other conventional data transfer operations, which actually move data between memory architecture address spaces by changing the allocation of portions of the memory system in the memory architecture between the thread requesting the transfer and the thread to which the data is requested. For example, a first thread included in a first virtual machine provided by a processing system in a server device may request data transfer to a second thread included in a second virtual machine provided by the processing system in the server device, and a data mover engine (e.g., included in the processing system providing the first thread, included in the hardware / software coupled to the processing system providing the first thread, etc.) can recognize the request to transfer data. In response, the data mover engine modifies symbolic reference information in a database to deassociate a first portion of the memory architecture memory system with the first thread and associate the first portion of the memory architecture memory system with the second thread, allowing the second thread to reference the data in the memory architecture memory system using request / response operations. Therefore, it provides more efficient in-device data transfer based on memory architecture, eliminating the need for traditional data transfer operations that actually move data between memory architecture address spaces, while providing the effect of such data movement by modifying symbolic reference information to reallocate parts of the memory architecture.

[0038] Method 500 begins at block 502, in which threads included in the various virtual machines are assigned to corresponding portions of the memory system in the memory architecture. In one embodiment, at block 502, any or all of the processing systems 304, 306, and 308 may operate to provide virtual machines or other applications (e.g., by executing instructions on the local memory system to which they are attached), and as will be understood by those skilled in the art with knowledge of this disclosure, those virtual machines / applications may include threads or other virtual machine / application components configured to utilize portions of the memory system in a manner similar to those discussed below. References Figure 6AFurthermore, for the purposes of the examples provided below, processing system 304 is shown as providing a virtual machine (VM) 600 including thread 600a (e.g., by executing instructions included on a local memory system), and processing system 306 is shown as providing a virtual machine (VM) 602 including thread 602a (e.g., by executing instructions included on a local memory system). However, although the two virtual machines including the respective threads are shown as being provided by different processing systems, those skilled in the art will recognize that those virtual machines and their threads can be provided on the same processing system while remaining within the scope of this disclosure.

[0039] In one embodiment, at block 502, any or all virtual machines, applications, threads, and / or other virtual machine / application components can be allocated to portions of the memory system within the memory architecture. For example, the memory architecture management subsystem 312 in server device 300 can operate, for example, by communicating with the memory architecture management subsystem 408 in memory systems 206 / 400, to enable media controller device 406 to provide threads 600a and 602a with allocations of memory system address spaces included in memory device 404, thereby allocating different portions of memory systems 206 / 400 to threads 600a and 602a.

[0040] In a specific example, the Gen-Z ZMMU can provide Gen-Z holes for individual pages in the memory architecture. These Gen-Z holes essentially operate as a page directory for the memory architecture, managed / programmed by the memory architecture manager and advertised using Gen-Z holes, specific memory architecture resources, and memory regions. Furthermore, once mapped and advertised to a server device, the server device can discover the memory as part of its normal startup memory discovery process (e.g., using firmware and mapping via e820 / ACPI tables) and provide its address regions in the server device's physical address space mapping, thus making the memory discoverable by its operating system. The operating system's memory manager then allocates one or more virtual machine threads from various regions within the system's physical address space (including the space discovered through the Gen-Z ZMMU holes).

[0041] In addition, the memory architecture management subsystem 312 in server device 300 may store the following: symbolic reference information regarding the allocation of various parts of the memory system in the memory architecture management database 314 (which may include, for example, reference pointers mapping a first thread to a first part of the memory system 206 / 400 and reference pointers mapping a second thread to a second part of the memory system 206 / 400); page ownership information providing ownership of the first thread in the first part of the memory system 206 / 400 and page ownership information providing ownership of the second thread in the second part of the memory system 206 / 400; and / or any other symbolic reference information that a person skilled in the art with knowledge of this disclosure would identify as providing the allocation of various parts of the memory architecture memory system to threads.

[0042] refer to Figure 6B For the purposes of the examples provided below, thread 600a is shown as having been allocated a first thread memory space 604 (e.g., by media controller device 406 in response to communication between memory architecture management subsystems 312 and 408 as described above), and thread 602a is shown as having been allocated a second thread memory space 606 (e.g., by media controller device 406 in response to communication between memory architecture management subsystems 312 and 408 as described above). As will be understood by those skilled in the art, the first thread memory space 604 and the second thread memory space 606 can be defined by different memory address ranges provided by memory device 404, different memory pages provided by memory device 404, and / or other different portions of memory device 404 that are obvious to those skilled in the art. In the examples below, the first thread memory space 604 and the second thread memory space 606 are memory spaces of equal size; however, those skilled in the art will recognize that threads can be allocated memory spaces of different sizes, and the following discussion of memory spaces of equal size applies to specific embodiments of the present disclosure. Specifically, the portion of memory system 400 allocated to thread 602a may be larger than the second thread memory space 606, which provides a subset of the portion of memory system 400 allocated to thread 602a, storing the data “transferred” during method 500.

[0043] Then, method 500 proceeds to block 504, in which the first thread transmits communication including a request to transfer data stored in its allocated memory system portion to a second thread. In one embodiment, at or before block 504, any thread included in a virtual machine provided by the processing system in server device 300 may request to transfer data to another thread included in another virtual machine provided by the processing system in server device 300. Those skilled in the art, having mastered this disclosure, will recognize that a wide variety of scenarios may require data transfer between threads included in virtual machines provided by the processing system in server device 300, and data transfer requests arising from any of these scenarios are contemplated to fall within the scope of this disclosure. Continuing with the example above and referring to… Figure 7 Thread 602a is shown as transmitting a data transfer request 700 via a memory configuration logic subsystem 306a included in processing system 306, which is accessible to data mover engine 310. In one embodiment, the data transfer request provided by the first thread at block 504 may be provided in inter-process communication (IPC), which includes a data descriptor-only transfer message that identifies the second thread and, as understood by those skilled in the art with this disclosure, does not include the data to be transferred, but includes a reference to the location of that data in the memory configuration memory system. For example, the data transfer request 700 provided by thread 602a at block 504 may include an IPC that identifies thread 600a and, instead of the data to be transferred, includes a reference to the second thread's memory space 606 in memory device 404 where the data is stored in memory system 400.

[0044] Then, method 500 proceeds to block 506, where the data mover subsystem identifies a request to transfer data in communication transmitted by the first thread. In one embodiment, at block 506, the data mover engine 310 may be operable to identify a request to transfer data transmitted by any thread included in any virtual machine provided by any processing systems 304, 306, and 308. Continuing with the example provided above, and referring to… Figure 7The data mover engine 310 is operable to identify a request 700 for data transfer transmitted by thread 602a. In some embodiments, the data mover engine 310 may be configured to listen for communications transmitted by any thread included in any virtual machine provided by any processing systems 304, 306, and 308 in order to identify a request for data transfer. For example, the data mover engine 310 may be operable to listen for a request 700 for data transfer transmitted by thread 602a in order to identify the thread 600a to which the data will be transferred, the data address for the data to be transferred, the data reference for the data to be transferred, and / or any other data transfer information that is obvious to those skilled in the art. However, while specific examples of identifying requests for data transfer have been described, those skilled in the art will recognize that requests for data transfer can be identified in various ways, and these methods will also fall within the scope of this disclosure.

[0045] Then, method 500 proceeds to decision block 508, where it is determined whether the requested data transfer is between portions of the memory system in the memory architecture. In one embodiment, at decision block 508, the data mover engine 310 may operate to determine whether information included in the data transfer request identified at block 506 specifies data transfer between portions of the memory architecture's memory system (e.g., memory system 206 / 400). For example, at decision block 508, the data mover engine 310 may use information included in the data transfer request identified at block 506 to determine the current location of the data to be transferred and the location to which the data will be transferred. In some examples, the data transfer request may identify the current location of the data to be transferred and the location to which the data will be transferred. However, in other examples, the current location of the data to be transferred can be determined by identifying the thread requesting the data transfer and accessing the memory architecture management database 314 to determine the portion of memory system 206 / 400 allocated to that thread, while the location to which the data will be transferred can be determined by identifying the thread to which the data will be transferred and accessing the memory architecture management database 314 to determine the portion of memory system 206 / 400 allocated to that thread. However, while some specific examples have been provided, those skilled in the art, upon receiving this disclosure, will recognize that determining whether a requested data transfer is to be performed between portions of the memory system in the memory architecture can be done in various ways, and these methods will also fall within the scope of this disclosure.

[0046] If it is determined at decision block 508 that the requested data transfer is not between portions of the memory systems in the memory architecture, method 500 proceeds to block 510, where the data mover subsystem performs a conventional copy operation. In one embodiment, data mover engine 310 may determine that the requested data transfer is to and / or from a local memory system (i.e., the local memory system included in server device 300), and at block 510, data mover engine 310 may operate to perform a conventional copy operation. For example, if it is determined at decision block 508 that the requested data transfer is between local memory systems in server device 300, then at block 510, data mover engine 310 may read and copy the data from a local memory system in server device 300 (e.g., utilized by thread 602a), and write the data to a local memory system in server device 300 (e.g., utilized by thread 600a). In another example, if it is determined at decision block 508 that the requested data transfer is from the local memory system in server device 300 to the memory architecture memory system (e.g., memory system 206 / 400), then at block 510, the data mover engine 310 can read and copy the data from the local memory system in server device 300 (e.g., utilized by thread 602a) and provide the data to the memory architecture management subsystem 312 for writing to memory system 206 / 400 (e.g., the first thread memory space 604 utilized by thread 600a). In another example, if it is determined at decision block 508 that the requested data transfer is from a memory architecture memory system (e.g., memory system 206 / 400) to a local memory system in server device 300, then at block 510, data mover engine 310 can request and receive the data from memory architecture management subsystem 312 via memory system 206 / 400 (e.g., second thread memory space 606 utilized by thread 602a), and write the data from the local memory system in server device 300 (e.g., utilized by thread 600a). However, while several examples have been provided, those skilled in the art, upon mastering this disclosure, will recognize that various conventional copy operations can be performed at block 510 while remaining within the scope of this disclosure.

[0047] If it is determined at decision block 508 that the requested data transfer is between different parts of the memory system in the memory architecture, then method 500 proceeds to block 512, in which the data mover subsystem modifies symbolic reference information to disconnect the first part of the memory system from the first thread and associate the first part of the memory system with the second thread. For example, if it is determined at decision block 508 that the requested data transfer is between the second thread memory space 606 allocated to thread 602a and the second thread memory space 606 allocated to thread 602a, then at block 512, the data mover engine 310 can operate to access the memory architecture management database 314 and perform symbolic reference information modification operation 800 in the memory architecture management database 314, such as... Figure 8 As shown. In one embodiment, symbolic reference information modification operation 800 may be performed on the following: symbolic reference information associated with the allocation of various parts of the memory system and stored at block 502 in a memory architecture management database 314 (as described above, the memory architecture management database may include reference pointers mapping thread 600a to a first thread memory space 604 in memory device 404 included in memory system 206 / 400 and reference pointers mapping thread 602a to a second thread memory space 606 in memory device 404 included in memory system 206 / 400); information providing ownership of thread 600a of the first thread memory space 604 in memory device 404 included in memory system 206 / 400 and providing ownership of thread 602a of the second thread memory space 606 in page ownership memory device 404 included in memory system 206 / 400; and / or any other symbolic reference information that a person skilled in the art with this disclosure would recognize as providing allocation of various parts of the memory architecture memory system to threads.

[0048] For example, at block 512, modification of symbolic reference information in the memory configuration management database 314 may include: the data mover engine 310 disconnecting thread 602a from its allocated second thread memory space 606 in the memory device 404 included in memory system 206 / 400 at block 502, and associating thread 600a with the second thread memory space 606 in the memory device 404 included in memory system 206 / 400. In a specific example, disconnecting thread 602a from the second thread memory space 606 and associating thread 600a with the second thread memory space 606 may include: changing the reference pointer that maps thread 602a to the second thread memory space 606 so that the reference pointer maps thread 600a to the second thread memory space 606, and changing the ownership page ownership information of thread 602a that provides the second thread memory space 606 so that thread 600a owns the second thread memory space 606. However, although specific symbolic reference information modification operations have been described, those skilled in the art who have mastered this disclosure will recognize that the second thread memory space 606 can be disconnected from thread 602a and associated with thread 600a in various ways, and these ways will also fall within the scope of this disclosure.

[0049] Method 500 proceeds to block 514, in which the data mover subsystem modifies the symbolic reference information to disconnect the second part of the memory system from the second thread and associate the second part of the memory system with the first thread. Continuing the example provided above, at block 514, the modification of the symbolic reference information in the memory configuration management database 314 may include: the data mover engine 310 disconnecting thread 600a from the first thread memory space 604 allocated in the memory device 404 included in the memory system 206 / 400 at block 502, and associating thread 602a with the first thread memory space 604 in the memory device 404 included in the memory system 206 / 400. In a specific example, disconnecting thread 600a from the first thread memory space 604 and associating thread 602a with the first thread memory space 604 may include: changing the reference pointer that maps thread 600a to the first thread memory space 604 so that the reference pointer maps thread 602a to the first thread memory space 604; and changing the page ownership information that provides ownership of the first thread memory space 600a so that thread 602a owns the first thread memory space 604. However, although specific symbolic reference information modification operations have been described, those skilled in the art will recognize that the first thread memory space 604 can be disconnected from thread 600a and associated with thread 602a in various ways, and these ways will also fall within the scope of this disclosure.

[0050] As those skilled in the art who have mastered this disclosure will understand, the modification of symbolic reference information performed at blocks 512 and 514 can be performed substantially simultaneously and / or as part of a similar operation, such that the allocation of the first thread memory space 604 and the second thread memory space 606 in memory device 404 of the memory system (i.e., allocated to threads 600a and 602a respectively) is "swapped," as Figure 9As shown (those skilled in the art who have mastered this disclosure will recognize that this is accomplished entirely by modifying the symbolic reference information in the memory architecture management database 314, and does not require data movement within the memory system 206 / 400). Therefore, blocks 512 and 514 can specify: swapping the reference pointers in the memory architecture management database 314 that map thread 600a to the first thread memory space 604 and the reference pointers that map thread 602a to the second thread memory space 606, such that thread 600a is mapped to the second thread memory space 606 and thread 602a is mapped to the first thread memory space 604; and swapping the page ownership information that provides ownership of the first thread memory space 600a and the page ownership information that provides ownership of the second thread memory space 606, such that thread 600a owns the second thread memory space 604 and thread 602a owns the first thread memory space 604.

[0051] In many embodiments, the portions of memory system 206 / 400 being swapped may be portions of memory system 206 / 400 of equal size, such that the first thread transferring data to the second thread does not lose allocated memory due to method 500. Therefore, the first thread memory space 604 may be equal in size to the second thread memory space 606, such that thread 602a does not lose allocated memory when “transferring” data from the second thread memory space 606 to thread 600a. In some embodiments, the portion of memory previously allocated to the second thread provided to the first thread that is “transferring” data during method 500 may be selected to have the same size as the portion of memory previously allocated to the first thread that stored the data before the “transfer” (e.g., the second thread memory space 606 in the example above). Therefore, based on the fact that the first thread memory space 604 is currently allocated to thread 600a and is equal in size to the second thread memory space 606 storing data being “transferred” by thread 602a, the first thread memory space can be identified during method 500 for reallocation to thread 602a. However, while specific examples of swapping memory space allocations of equal size have been described, those skilled in the art will recognize that memory spaces of different sizes can be swapped. Furthermore, in some embodiments, box 514 can be skipped, causing the first thread (e.g., thread 602a in the embodiments below) to eventually lose its allocated memory as part of the symbolic reference information modification data "transfer".

[0052] Method 500 proceeds to block 516, in which the second thread accesses data in the first portion of the memory system. In one embodiment, at block 516, thread 600a can now access data in the second thread's memory space 606 via, for example, a request / response operation. Figure 10A The diagram illustrates how thread 600a generates a memory load instruction and transmits it to memory configuration management subsystem 312 via memory configuration logic subsystem 304a in processing system 304 and data mover engine 310. This memory load instruction requests data “transmitted” by thread 602a, as discussed above. Memory configuration management subsystem 312 can then act as a memory configuration requester (e.g., a Gen-Z requester) and generate a memory configuration request (e.g., a Gen-Z request) using symbolic reference information in memory configuration management database 314. This request is transmitted to memory system 206 via network 204. Figure 10B and 10C As shown, the memory architecture management subsystem 408 can act as a memory architecture responder (e.g., a Gen-Z responder) and retrieve data from the second thread memory space 606 in the memory device 404 via the media controller device 406, generate a memory architecture response (e.g., a Gen-Z response) that includes the data retrieved from the second thread memory space 606 as its payload, and transmit the memory architecture response to the server device 300 via the network 204. Figure 10D This illustrates how the memory configuration management subsystem 312 can act as a memory configuration requester to load data retrieved from the second thread memory space 606 (via the data mover engine 310 and the memory configuration logic subsystem 304a in the processing system 304) into a local memory system provided for the virtual machine 600 and accessible to thread 600a. However, while specific examples of data accessed in the first part of the memory system by a second thread have been described, those skilled in the art will recognize that data transferred via symbolic reference information modified herein can be accessed in various ways, and these methods will also fall within the scope of this disclosure.

[0053] Therefore, various systems and methods have been described that provide data "transfer" while avoiding the need for reading, writing, copying, and / or performing other conventional data transfer operations, which actually move data between memory architecture address spaces by changing the allocation of portions of the memory system in the memory architecture between the thread requesting the transfer and the thread to which the data is requested. Thus, a first thread included in a first virtual machine provided by a processing system in a server device can request data transfer to a second thread included in a second virtual machine provided by the processing system in the server device, and a data mover subsystem can recognize this data transfer request. In response, the data mover subsystem can modify symbolic reference information in a database to swap a first portion of the memory architecture memory system allocated to the first thread and storing the data to be transferred with an equal-sized portion of the memory architecture memory system allocated to the second thread. This allows the second thread to reference data in the first portion of the memory architecture memory system using request / response operations. Therefore, it provides more efficient in-device data transfer based on memory architecture, which eliminates the need for traditional data transfer operations that actually move data between memory architecture address spaces, while providing the effect of such data movement through symbolic reference modification that reallocates parts of the memory architecture.

[0054] In addition, this disclosure is filed together with the following U.S. patent applications: U.S. Patent Application No. 16 / 395,902 (Attorney-in-charge No. 16356.2039US01), filed April 26, 2019, relating to controller-based inter-device symbolic data movement technology; and U.S. Patent Application No. 16 / 396,140 (Attorney-in-charge No. 16356.2041US01), filed April 26, 2019, relating to handover-based inter-device symbolic data movement technology; each of these U.S. patent applications includes embodiments utilizing symbolic data movement systems similar to those described in some embodiments included in this disclosure. Those skilled in the art who have acquired this disclosure will recognize how embodiments of this disclosure can be combined with some or all of the disclosure discussed above, and therefore, this disclosure is incorporated herein by reference in its entirety.

[0055] Although illustrative embodiments have been shown and described, extensive modifications, alterations, and substitutions are contemplated in the foregoing disclosure, and in some cases, some features of the embodiments may be employed without the corresponding use of other features. Therefore, it should be understood that the appended claims are to be interpreted broadly and in a manner consistent with the scope of the embodiments disclosed herein.

Claims

1. An in-device symbol data movement system, comprising: chassis; At least one processing system, included within the housing, is configured to: Provide the first thread; as well as Provide a second thread; A data mover subsystem, included within the housing and coupled to the at least one processing system, wherein the data mover subsystem is configured to: In the communication transmitted by the first thread, a request to transmit data to the second thread is identified, wherein the data is stored in a first part of the memory system associated with the first thread in the memory architecture management database; as well as Modify symbolic reference information in the memory architecture management database to disconnect the first part of the memory system from the first thread and associate the first part of the memory system with the second thread, wherein associating the first part of the memory system with the second thread allows the second thread to reference the data using request / response operations.

2. The system of claim 1, wherein the data mover subsystem is configured to: Modify the symbol reference information in the memory architecture management database to disconnect the second part of the memory system from the second thread and associate the second part of the memory system with the first thread.

3. The system of claim 2, wherein the first portion of the memory system and the second portion of the memory system have the same size.

4. The system of claim 2, wherein disconnecting the first portion of the memory system from the first thread, associating the first portion of the memory system with the second thread, disconnecting the second portion of the memory system from the second thread, and associating the second portion of the memory system with the first thread comprises: Swap the reference pointers that map the first thread to the first part of the memory system and the reference pointers that map the second thread to the second part of the memory system.

5. The system of claim 2, wherein disconnecting the first portion of the memory system from the first thread, associating the first portion of the memory system with the second thread, disconnecting the second portion of the memory system from the second thread, and associating the second portion of the memory system with the first thread comprises: The page ownership of the first thread that provides ownership of the first part of the memory system and the page ownership of the second thread that provides ownership of the second part of the memory system are swapped, such that the second thread owns the first part of the memory system and the first thread owns the second part of the memory system.

6. The system of claim 1, wherein the memory system is coupled to the housing via a network.

7. An information processing system (IHS) comprising: Processing system; as well as A memory system coupled to the processing system and including instructions, which, when executed by the processing system, cause the processing system to provide a data mover engine, the data mover engine being configured to: In communications transmitted by a first thread provided by at least one processing system included within a housing, a request to transmit data to a second thread provided by the at least one processing system included within the housing is identified, wherein the data is stored in a first portion of the memory system associated with the first thread in a memory architecture management database; as well as Modify symbolic reference information in the memory architecture management database to disconnect the first part of the memory system from the first thread and associate the first part of the memory system with the second thread, wherein associating the first part of the memory system with the second thread allows the second thread to reference the data using request / response operations.

8. The IHS of claim 7, wherein the data mover subsystem is configured to: Modify the symbol reference information in the memory architecture management database to disconnect the second part of the memory system from the second thread and associate the second part of the memory system with the first thread.

9. The IHS of claim 8, wherein the first portion of the memory system and the second portion of the memory system have the same size.

10. The IHS of claim 8, wherein disconnecting the first portion of the memory system from the first thread, associating the first portion of the memory system with the second thread, disconnecting the second portion of the memory system from the second thread, and associating the second portion of the memory system with the first thread comprises: Swap the reference pointers that map the first thread to the first part of the memory system and the reference pointers that map the second thread to the second part of the memory system.

11. The IHS of claim 8, wherein disconnecting the first portion of the memory system from the first thread, associating the first portion of the memory system with the second thread, disconnecting the second portion of the memory system from the second thread, and associating the second portion of the memory system with the first thread comprises: The page ownership of the first thread that provides ownership of the first part of the memory system and the page ownership of the second thread that provides ownership of the second part of the memory system are swapped, such that the second thread owns the first part of the memory system and the first thread owns the second part of the memory system.

12. The IHS of claim 7, wherein the memory system is coupled to the housing via a network.

13. The IHS of claim 7, wherein the data mover subsystem is configured to: The request to transfer data to the second thread is determined to be a request to transfer the data from the first memory architecture location to the second memory architecture location, and in response, the symbol reference information in the memory architecture management database is modified.

14. A method for providing symbol data movement within a device, comprising: The data mover subsystem identifies, in communications transmitted by a first thread provided by at least one processing system included within the chassis, a request to transmit data to a second thread provided by the at least one processing system included within the chassis, wherein the data is stored in a first portion of the memory system associated with the first thread in a memory architecture management database; as well as The data mover subsystem modifies symbolic reference information in the memory architecture management database to disconnect the first part of the memory system from the first thread and associate the first part of the memory system with the second thread, wherein associating the first part of the memory system with the second thread allows the second thread to reference the data using request / response operations.

15. The method of claim 14, further comprising: The data mover subsystem modifies the symbolic reference information in the memory architecture management database to disconnect the second part of the memory system from the second thread and associate the second part of the memory system with the first thread.

16. The method of claim 15, wherein the first portion of the memory system and the second portion of the memory system have the same size.

17. The method of claim 15, wherein disconnecting the first portion of the memory system from the first thread, associating the first portion of the memory system with the second thread, disconnecting the second portion of the memory system from the second thread, and associating the second portion of the memory system with the first thread comprises: Swap the reference pointers that map the first thread to the first part of the memory system and the reference pointers that map the second thread to the second part of the memory system.

18. The method of claim 15, wherein disconnecting the first portion of the memory system from the first thread, associating the first portion of the memory system with the second thread, disconnecting the second portion of the memory system from the second thread, and associating the second portion of the memory system with the first thread comprises: The page ownership of the first thread that provides ownership of the first part of the memory system and the page ownership of the second thread that provides ownership of the second part of the memory system are swapped, such that the second thread owns the first part of the memory system and the first thread owns the second part of the memory system.

19. The method of claim 14, wherein the memory system is coupled to the housing via a network.

20. The method of claim 14, further comprising: The data mover subsystem determines that the request to transfer data to the second thread is a request to transfer the data from the first memory architecture location to the second memory architecture location, and in response, modifies the symbol reference information in the memory architecture management database.

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