Data transmission method, processor system, readable storage medium and electronic device

Abstract

The present disclosure relates to a data transmission method, a processor system, a readable storage medium, and an electronic device. The method comprises: in a first working cycle, a computing core cluster transmits computation result data to a cache core cluster, which in turn transmits first data of the computation result data to a receiving core cluster; in a second working cycle, the computing core cluster performs a computation task, and the cache core cluster transmits second data of the computation result data to the receiving core cluster, where the second data includes data in the computation result data other than the first data. This method can reduce the idle time and waiting time of the functional cores of each chip in the processor system, thereby improving the efficiency and execution speed of the processor system.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data transmission method, a processor system, a readable storage medium, and an electronic device. Background Art

[0002] With the continuous development of artificial intelligence technology, users are demanding higher and higher chip processing capabilities. Due to the limited processing power of single-core chips, the use of many-core chips is becoming increasingly widespread. By distributing computing tasks across multiple cores for parallel execution, chip processing capabilities can be improved. In a many-core chip architecture, not only does each core need to execute its assigned computing tasks, but data transmission between cores and between chips is also required. The execution mechanism of computing tasks and inter-chip data transmission in a many-core chip affects the chip's overall performance. Summary of the Invention

[0003] In view of this, the present disclosure proposes a data transmission method, a processor system, a readable storage medium, and an electronic device.

[0004] According to one aspect of the present disclosure, a data transmission method is provided. The method is applied to a processor system, wherein the processor system includes multiple chips, each chip includes multiple functional cores, and the data transmission speed between functional cores in the same chip is higher than the data transmission speed between functional cores in different chips. The multiple functional cores of each chip are divided into multiple core clusters according to different tasks. When data is transmitted from a first chip to a second chip, the first chip includes a computing core cluster for performing computing tasks and a cache core cluster for performing data caching and transmission tasks, and the second chip includes a receiving core cluster for performing data receiving tasks. The first chip and the second chip are any two chips of the processor system. The method includes:

[0005] In a first working cycle, the computing core cluster transmits the calculation result data to the cache core cluster, and the cache core cluster transmits the first data of the calculation result data to the receiving core cluster; in a second working cycle, the computing core cluster performs the computing task, and the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, where the second data includes data in the calculation result data other than the first data.

[0006] In one possible implementation, in the first working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are timing-synchronized; in the second working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are timing-asynchronous, and the cache core cluster and the receiving core cluster are timing-synchronized.

[0007] In a possible implementation, in a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, including: when the computing result data transmission is completed, the first working cycle ends.

[0008] In one possible implementation, data is transmitted serially between different chips of the processor system, wherein in a first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: the first functional core in the cache core cluster transmits the first sub-data of the first data to the receiving core cluster; the second functional core in the cache core cluster transmits the second sub-data of the first data to the multicast core cluster of a third chip, so that the multicast core cluster transmits the second sub-data to the receiving core cluster, wherein the third chip is at least one chip in the processor system other than the first chip and the second chip.

[0009] In one possible implementation, in the second working cycle, the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, including: the first functional core in the cache core cluster transmits the third sub-data of the second data to the receiving core cluster; the second functional core in the cache core cluster transmits the fourth sub-data of the second data to the multicast core cluster of the third chip, so that the multicast core cluster transmits the fourth sub-data to the receiving core cluster.

[0010] In one possible implementation, the method further includes: in a first working cycle, the multicast core cluster of the third chip transmits the second sub-data to the receiving core cluster of the second chip; in a second working cycle, the multicast core cluster of the third chip transmits the fourth sub-data to the receiving core cluster of the second chip.

[0011] In one possible implementation, the first working cycle includes N first sub-cycles, where N is an integer greater than 1, wherein in the first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: in the first first sub-cycle, the cache core cluster does not transmit data to the receiving core cluster; in the second first sub-cycle to the Nth first sub-cycle, the cache core cluster transmits the first data to the receiving core cluster.

[0012] According to another aspect of the present disclosure, a processor system is provided, comprising multiple chips, each chip comprising multiple functional cores, wherein a data transmission speed between functional cores located in the same chip is higher than a data transmission speed between functional cores located in different chips, wherein the multiple functional cores of each chip are divided into multiple core clusters according to different tasks, and when data is transmitted from a first chip to a second chip, the first chip comprises a computing core cluster for performing computing tasks and a cache core cluster for performing data caching and transmission tasks, and the second chip comprises a receiving core cluster for performing data receiving tasks, wherein the first chip and the second chip are any two chips of the processor system, wherein the first chip is configured as follows:

[0013] In a first working cycle, the computing core cluster transmits the calculation result data to the cache core cluster, and the cache core cluster transmits the first data of the calculation result data to the receiving core cluster; in a second working cycle, the computing core cluster performs the computing task, and the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, where the second data includes data in the calculation result data other than the first data.

[0014] In one possible implementation, in the first working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are timing-synchronized; in the second working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are timing-asynchronous, and the cache core cluster and the receiving core cluster are timing-synchronized.

[0015] In a possible implementation, in a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, including: when the computing result data transmission is completed, the first working cycle ends.

[0016] In one possible implementation, data is transmitted serially between different chips of the processor system, wherein in a first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: the first functional core in the cache core cluster transmits the first sub-data of the first data to the receiving core cluster; the second functional core in the cache core cluster transmits the second sub-data of the first data to the multicast core cluster of a third chip, so that the multicast core cluster transmits the second sub-data to the receiving core cluster, wherein the third chip is at least one chip in the processor system other than the first chip and the second chip.

[0017] In one possible implementation, in the second working cycle, the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, including: the first functional core in the cache core cluster transmits the third sub-data of the second data to the receiving core cluster; the second functional core in the cache core cluster transmits the fourth sub-data of the second data to the multicast core cluster of the third chip, so that the multicast core cluster transmits the fourth sub-data to the receiving core cluster.

[0018] In one possible implementation, the system also includes: in a first working cycle, the multicast core cluster of the third chip transmits the second sub-data to the receiving core cluster of the second chip; in a second working cycle, the multicast core cluster of the third chip transmits the fourth sub-data to the receiving core cluster of the second chip.

[0019] In one possible implementation, the first working cycle includes N first sub-cycles, where N is an integer greater than 1, wherein in the first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: in the first first sub-cycle, the cache core cluster does not transmit data to the receiving core cluster; in the second first sub-cycle to the Nth first sub-cycle, the cache core cluster transmits the first data to the receiving core cluster.

[0020] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0021] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned processor system.

[0022] According to the data transmission method of the embodiment of the present disclosure, the system can be divided into multiple core clusters according to different tasks. In the first working cycle, the calculation result data stored in the calculation core cluster is transferred to the cache core cluster, and the cache core cluster then transfers part of the calculation result data to the receiving core cluster. Then, in the second working cycle, the calculation core cluster can perform the calculation task, and at the same time, the cache core cluster can transfer the remaining data of the calculation result data to the receiving core cluster. This can avoid the situation where the multi-core chips in the processor system execute the calculation task of each core and transmit data between cores according to the global synchronization timing, effectively reduce the idling and waiting time of each functional core between chips in the processor system, and improve the computing efficiency and execution speed of the processor system.

[0023] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0025] Figure 1 A schematic diagram illustrating a data transmission execution mechanism based on a many-core architecture in related technologies;

[0026] Figure 2 A schematic diagram illustrating a processor system according to an embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram illustrating a chip core cluster executing a computing task according to an embodiment of the present disclosure;

[0028] Figure 4 A flow chart showing a data transmission method according to an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram showing a data transmission method in related art;

[0030] Figure 6 A schematic diagram illustrating a data transmission method according to an embodiment of the present disclosure;

[0031] Figure 7 A schematic diagram showing a method for transmitting data between chips in the related art;

[0032] Figure 8 A schematic diagram illustrating an inter-chip data transmission method according to an embodiment of the present disclosure is shown;

[0033] Figure 9 A block diagram illustrating an electronic device according to an embodiment of the present disclosure is shown;

[0034] Figure 10 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0036] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0037] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0038] In a many-core chip system, the execution mechanism of computing tasks within a functional core and data transmission tasks between functional cores will affect the overall operating performance of the many-core chip. To solve the above problems, a bulk synchronous parallel (BSP) mechanism is provided in the related art. In this mechanism, the basic operation of the many-core chip mainly includes three stages: (1) Local computing stage, in which each functional core only performs local computing on data stored in local memory. (2) Global communication stage, in which each functional core operates on non-local data, including data transmission between functional cores. (3) Fence synchronization stage, waiting for the completion of all communication behaviors.

[0039] Another execution mechanism also exists in related technologies: the execution of a many-core chip is divided into multiple synchronized execution cycles by a global synchronization signal. In each execution cycle, each functional core simultaneously performs local computing tasks and inter-core communication tasks. While performing local computing, each functional core also transmits the obtained calculation results.

[0040] Figure 1 Schematic diagram showing a data transmission execution mechanism based on a multi-core architecture in related technologies. Figure 1 As shown, the multi-function cores need to perform local computing and inter-core communication tasks according to the global synchronization work cycle. In one example, Figure 1 It includes three timing clusters, each capable of performing inter-core data transmission (including data sending and receiving) and computing tasks. For example, timing cluster 1 can include data receiving A1, data sending B1, and data computing C1; timing cluster 2 can include data receiving A2, data sending B2, and data computing C2; and timing cluster 3 can include data receiving A3, data sending B3, and data computing C3. The data transmission and data computing components of the same timing cluster can be completed in different working cycles.

[0041] like Figure 1As shown, timing clusters 1, 2, and 3 begin data transmission tasks synchronously and end synchronously after data transmission is complete. After the functional core in timing cluster 1 completes data reception A1 and data transmission B1, it needs to idle or wait for data transmission B2 in timing cluster 2 to complete and data reception A3 in timing cluster 3 to complete before synchronizing and starting data calculation C1. The functional cores in timing clusters 1, 2, and 3 all start and end data transmission synchronously, causing the timing clusters to idle or wait before performing data calculations. This wastes the limited resources of the many-core processor and reduces its utilization and execution efficiency.

[0042] Therefore, in order to address the technical problems that many-core chips need to perform local inter-chip communication tasks according to a globally synchronized working cycle, and that the local calculations and inter-chip communications of the chips are performed in a serial manner, which reduces the execution efficiency, the embodiments of the present disclosure provide a data transmission method. By setting a cache core cluster, the calculation result data of the chip calculation core cluster is first sent to the cache core cluster of the chip, and then sent to the receiving core cluster outside the chip through the cache core cluster, so that the many-core chip does not need to perform the calculation tasks of each functional core and the data interaction tasks between the cores according to the globally synchronized timing, thereby effectively reducing the idling and waiting time of each functional core between the chips in the processor system, and improving the computing efficiency and execution speed of the processor system.

[0043] Figure 2 A schematic diagram of a processor system according to an embodiment of the present disclosure is shown. The data transmission method according to the embodiment of the present disclosure is applied to a processor system, wherein the processor system includes multiple chips, and each chip includes multiple functional cores.

[0044] In one possible implementation, Figure 2 As shown, each chip may include multiple functional cores, and data can be transmitted between the functional cores within each chip and between the functional cores of different chips; wherein, each functional core may include a storage component for storing data transmitted with other functional cores.

[0045] In one possible implementation, Figure 2 As shown, each functional core may include a processing component and a storage component. The processing component may include a dendrite unit, an axon unit, a cell body unit, and a routing unit; and the storage component may include multiple storage units.

[0046] In one possible implementation, the processor system includes multiple chips that can be brain-inspired computing chips, that is, neuromorphic circuits that integrate storage and computing. These chips, based on the brain's processing model, improve processing efficiency and reduce power consumption by simulating the transmission and processing of information by neurons in the brain. Each brain-inspired computing chip can include multiple functional cores, which can independently process different tasks or process the same task in parallel to improve processing efficiency. Inter-core information transmission can be carried out between functional cores through routing units within the functional cores.

[0047] For example, a storage component and a processing component may be provided within the functional core. The storage component may include multiple storage units, wherein the storage unit may be a static random access memory (SRAM). For example, an SRAM with a read / write width of 16B and a capacity of 12KB may be included. This disclosure does not limit the capacity and bit width of the storage unit.

[0048] The processing component may include a dendritic unit, an axonal unit, a soma unit, and a routing unit. The processing component may simulate the information processing mode of neurons in the brain, wherein the dendritic unit is used to receive signals, the axonal unit is used to send spike signals, the soma unit is used for integrated transformation of signals, and the routing unit is used to transmit information with other functional cores. The processing component within the functional core may read and write to multiple storage units of the storage component to interact with data within the storage component within the functional core, and may respectively undertake respective data processing tasks and / or data transmission tasks to obtain data processing results, or communicate with other functional cores. Communicating with other functional cores includes communicating with other functional cores within the chip, as well as communicating with functional cores within other chips.

[0049] In a possible implementation, a data transmission speed between functional cores located in the same chip is higher than a data transmission speed between functional cores located in different chips.

[0050] For example, assume that a processor system may include chip E and chip F, where chip E includes functional cores E1 and E2, and chip F includes functional cores F1 and F2. Data transmission between functional cores E1 and E2, and between functional cores F1 and F2, is between functional cores of the same chip and is relatively fast. In contrast, data transmission between functional cores E1 and F1 (or F2), and between functional cores E2 and F1 (or F2), is between functional cores of different chips and is relatively slow. For example, the data transmission speed between functional cores within the same chip can be three times that between functional cores of different chips.

[0051] It should be understood that the data transmission speed between functional cores in the same chip and the data transmission speed between functional cores in different chips are related to the performance of the specific processor system hardware. The present disclosure does not limit the data transmission speed between specific cores.

[0052] In a possible implementation, the multiple functional cores of each chip are divided into multiple core clusters according to different tasks.

[0053] For example, functional cores can be divided into different asynchronous core clusters based on the tasks they perform or the execution time of the tasks. Each core cluster can contain one or more functional cores. Functional cores belonging to the same asynchronous core cluster have synchronous local processing and inter-core communication cycles. For each core cluster, it can cyclically and continuously execute multiple task cycles in time. Each task corresponds to an execution cycle. The time lengths (number of clocks) corresponding to these different task cycles may be equal or unequal. Different core clusters execute according to their own internal synchronization signals, so their execution cycles are asynchronous.

[0054] Figure 3 A schematic diagram showing a chip core cluster executing a computing task according to an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the chip acquires a total computing task consisting of four computing tasks (Task 1, Task 2, Task 3, and Task 4). Based on the total computing tasks to be executed, the chip's 16 cores are split into two core clusters: Cluster 1 and Cluster 2. Cluster 1 contains nine cores, each responsible for executing Tasks 1 and 2. Cluster 1 executes Task 1 in its first operating cycle and Task 2 in its second. Cluster 2 contains seven cores, each responsible for executing Tasks 3 and 4. Cluster 2 executes Task 3 in its first operating cycle and Task 4 in its second. The two clusters execute asynchronously.

[0055] It should be understood that the tasks in the above process may be computing tasks, or other tasks such as transmission tasks and cache tasks, and the present disclosure does not limit the specific types of tasks.

[0056] For any two chips of the processor system (which may be referred to as the first chip and the second chip), when data is transmitted from the first chip to the second chip, the first chip includes a computing core cluster for performing computing tasks, and a cache core cluster for performing data caching and transmission tasks, and the second chip includes a receiving core cluster for performing data receiving tasks.

[0057] Figure 4 FIG. 1 is a flow chart showing a data transmission method according to an embodiment of the present disclosure. Figure 4As shown, the method includes:

[0058] In step S11, in a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, and the cache core cluster transmits first data of the computing result data to the receiving core cluster;

[0059] In step S12, in a second working cycle, the computing core cluster performs a computing task, and the cache core cluster transmits second data of the computing result data to the receiving core cluster, where the second data includes data in the computing result data except the first data.

[0060] For example, a first chip can cluster its multiple functional cores based on received computing and transmission tasks. For example, nine functional cores can be used as a computing core cluster to process computing tasks, and three functional cores can be used as a cache core cluster to process transmission tasks. A second chip can cluster its multiple functional cores based on received data reception tasks. For example, three functional cores can be used as a receiving core cluster to process data reception tasks.

[0061] The first chip and the second chip may be any two different chips in the processor system. The specific number of functional cores included in each divided core cluster may be determined according to specific tasks and performance of the functional cores, and this disclosure does not impose any restrictions on this.

[0062] In step S11, during the first working cycle, the computing core cluster in the first chip does not perform computing tasks, but instead transmits computing result data acquired before the first working cycle to the second chip. The computing result data stored in the computing core cluster of the first chip can be transmitted to the cache core cluster of the first chip, which then transmits the first data of the computing result data to the receiving core cluster of the second chip.

[0063] Due to the limitations of the processor system's hardware structure and operating mode, data transmission speeds between functional cores within a chip are higher than those between functional cores located on different chips. Therefore, the data transmission speed between the compute core cluster of a first chip and the cache core cluster of the first chip is higher than the data transmission speed between the cache core cluster of the first chip and the receiving core cluster of the second chip.

[0064] All the computation result data stored in the computing core cluster of the first chip is transferred to the cache core cluster of the first chip, and the first working cycle ends. In this case, because the intra-chip transmission speed is greater than the inter-chip transmission speed, the cache core cluster of the first chip cannot transmit all the computation result data to the receiving core cluster of the second chip. Instead, it can only transmit a portion of the computation result data, namely the first data, to the receiving core cluster of the second chip.

[0065] In step S12, in the second working cycle, since the computing core cluster of the first chip has already transmitted all the calculation result data to the cache core cluster of the first chip in the first working cycle, the computing core cluster can end the transmission task and perform the computing task to obtain the calculation result data to be transmitted in the next cycle.

[0066] The cache core cluster of the first chip has already transmitted the first data to the receiving core cluster of the second chip in the first working cycle. However, the cache core cluster still stores some computation result data, namely, the second data, that has not been sent to the receiving core cluster of the second chip. The cache core cluster of the first chip can continue to perform the transmission task and transmit the second data in the computation result data, excluding the first data, to the receiving core cluster of the second chip.

[0067] After the computing core cluster of the first chip completes the computing task, it obtains the next round of computing result data to be sent, and the cache core cluster of the first chip transmits the second data to the receiving core cluster of the second chip. The second working cycle ends and the next cycle can begin.

[0068] In this way, different core clusters can complete different tasks. When completing the same task within a core cluster, during the first working cycle, the computational result data stored in the computing core cluster can be transferred to the cache core cluster, which then transfers a portion of the computational result data to the receiving core cluster. Then, during the second working cycle, the computing core cluster can execute the computational task while the cache core cluster transfers the remaining computational result data to the receiving core cluster. This method can effectively reduce the idle and waiting time of the functional cores between chips within the processor system, thereby improving the computing efficiency and execution speed of the processor system.

[0069] The data transmission method according to the embodiment of the present disclosure is described below.

[0070] Figure 5 Schematic diagram showing a data transmission method in related art. Figure 5 As shown, assuming that the computing core cluster of the first chip includes functional cores 2,7, 2,8, 3,7, and 3,8, and the receiving core cluster of the second chip includes functional cores 0,11, the four functional cores in the computing core cluster of the first chip need to send a total of 28KB of calculation result data to functional cores 0,11 in the receiving core cluster of the second chip.

[0071] It should be understood that the computing core cluster and the receiving core cluster may include multiple functional cores. The present disclosure only takes the functional cores 2,7, functional core 2,8, functional core 3,7, and functional core 3,8 included in the computing core cluster and the functional core 0,11 included in the receiving core cluster as examples. The computing core cluster and the receiving core cluster may also include other functional cores. The present disclosure does not limit the specific number of functional cores included in the core cluster. The specific working mode of the other functional cores included in the cluster can be parameterized by the working mode of the above-mentioned functional cores, and the present disclosure will not go into details.

[0072] like Figure 5 As shown, the four functional cores (2,7, 2,8, 3,7, 3,8) of the computing core cluster of the first chip transmit 28KB of calculation result data to the functional core 0,11 of the receiving core cluster of the second chip within 7 working sub-cycles (P1 to P7) at a transmission rate of 4KB per working sub-cycle.

[0073] Afterwards, in the working sub-cycle (P8-P10), the four functional cores of the computing core cluster of the first chip perform computing tasks and do not perform data transmission tasks; the functional cores 0 and 11 of the receiving core cluster of the second chip idle and wait.

[0074] It can be seen that when the computing core cluster of the first chip performs a computing task, the receiving core cluster of the second chip needs to wait in idle mode. The receiving core cluster of the second chip needs to wait until the computing core cluster's computing task is completed before it can start receiving data. Moreover, while the receiving core cluster of the second chip is receiving the computing result data, the computing core cluster of the first chip is sending the computing result data, and the computing core cluster cannot perform other tasks. Therefore, Figure 5 The method shown needs to wait for the global synchronization signal to perform cycle switching and data transmission, which will cause some functional cores to idle and wait, greatly reducing the chip utilization and execution efficiency.

[0075] against Figure 5 The data transmission method shown has the problem of low efficiency. Figure 6 Schematic diagram showing a data transmission method according to an embodiment of the present disclosure. Figure 6 As shown, assume that the computing core cluster of the first chip includes functional cores 2,7, 2,8, 3,7, and 3,8; the cache core cluster of the first chip includes functional cores 2,9; and the receiving core cluster of the second chip includes functional cores 0,11. These four functional cores in the computing core cluster of the first chip need to send a total of 28KB of computational result data to functional cores 0,11 in the receiving core cluster of the second chip.

[0076] In step S11, Figure 6As shown, in the first working cycle (T1-T3), the four functional cores (2,7, 2,8, 3,7, 3,8) of the first chip computing core cluster transmit 28KB (i.e., 12KB+12KB+4KB) of the calculation result data to the functional cores 2,9 of the on-chip cache core cluster, and the functional cores 2,9 of the first chip cache core cluster transmit the first data 8KB (4KB+4KB) of the calculation result data to the functional cores 0,11 of the second chip receiving core cluster;

[0077] It should be understood that the computing core cluster, cache core cluster and receiving core cluster may include multiple functional cores. The present disclosure only takes the functional cores 2,7, functional core 2,8, functional core 3,7, functional core 3,8 included in the computing core cluster, the functional core 2,9 included in the cache core cluster, and the functional core 0,11 included in the receiving core cluster as examples. The computing core cluster, cache core cluster and receiving core cluster may also include other functional cores. The present disclosure does not limit the specific number of functional cores included in the core cluster. The specific working mode of the other functional cores included in the cluster can be parameterized by the working mode of the above-mentioned functional cores, and the present disclosure will not go into details.

[0078] In a possible implementation, the first working cycle includes N first sub-cycles, where N is an integer greater than 1. In the first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including:

[0079] In the first sub-cycle, the cache core cluster does not transmit data to the receiving core cluster;

[0080] In the 2nd first sub-period to the Nth first sub-period, the cache core cluster transmits the first data to the receiving core cluster.

[0081] For example, if Figure 6 As shown, the first working cycle includes three first sub-cycles T1 to T3. The present disclosure does not limit the number of first sub-cycles included in the first working cycle, and the number of first sub-cycles can be determined according to the specific tasks to be processed.

[0082] In the first sub-cycle T1, the functional cores 2 and 9 of the first chip cache core cluster run idle and do not transmit data to the functional cores 0 and 11 of the second chip receiving core cluster;

[0083] In the second first sub-cycle T2 , the functional cores 2 , 9 of the first chip cache core cluster transmit 4 KB of data to the functional cores 0 , 11 of the first chip receiving core cluster.

[0084] In the third first sub-cycle T3 , the functional cores 2 , 9 of the first chip cache core cluster transmit 4 KB of data to the functional cores 0 , 11 of the first chip receiving core cluster.

[0085] In the second first sub-period and the third first sub-period, the functional cores 2 and 9 of the first chip cache core cluster transmit a total of 8 KB of first data to the functional cores 0 and 11 of the first chip receiving core cluster.

[0086] In this way, the cache core cluster of the first chip and the receiving core cluster of the second chip idle only during the first sub-cycle of the first working cycle. Furthermore, because the inter-core data transmission rate is greater than the inter-chip data transmission rate, the computing core cluster of the first chip quickly enters the second working cycle and executes computing tasks, while the cache core cluster and the receiving core cluster can continue data transmission tasks asynchronously. This effectively reduces the idle and waiting time of the functional cores between chips within the processor system, improving the computing efficiency and execution speed of the processor system.

[0087] In a possible implementation, in a first working cycle, the computing core cluster transmits the computing result data to the cache core cluster, including:

[0088] When the calculation result data transmission is completed, the first working cycle ends.

[0089] For example, if Figure 6 As shown, in the third sub-cycle T3 of the first working cycle, the four functional cores (2,7, 2,8, 3,7, 3,8) of the first chip computing core cluster transfer the last 4KB of the calculation result data 28KB to the functional core 2,9 of the on-chip cache core cluster, and the first working cycle ends.

[0090] In this way, the cache core cluster of the first chip still stores some computational result data (i.e., the second data) that has not yet been transmitted to the second chip, while the computing core cluster has already transmitted all computational result data. This helps the computing core cluster of the first chip quickly enter the second working cycle and execute computing tasks, while the cache core cluster and the receiving core cluster can continue data transmission tasks asynchronously during the second working cycle. This effectively reduces the idle and waiting time of the functional cores between chips within the processor system, improving the computing efficiency and execution speed of the processor system.

[0091] In a possible implementation, in the first working cycle, the computing core cluster, the cache core cluster, and the receiving core cluster are time-synchronized;

[0092] For example, if Figure 6 As shown, the timing between the four functional cores (2,7, 2,8, 3,7, 3,8) of the computing core cluster of the first chip, the functional cores 2,9 of the cache core cluster of the first chip, and the functional cores 0,11 of the receiving core cluster of the second chip is synchronized.

[0093] For example, in the first sub-period T1, the four functional cores (2,7, 2,8, 3,7, 3,8) of the computing core cluster of the first chip send a total of 12KB of calculation result data to the functional core 2,9 of the cache core cluster on the chip. At the same time, the functional core 2,9 of the cache core cluster runs idle and does not transmit data to the functional core 0,11 of the receiving core cluster of the second chip.

[0094] In the second first sub-period T2, the four functional cores (2,7, 2,8, 3,7, 3,8) of the computing core cluster of the first chip continue to send 12KB of calculation result data to the functional core 2,9 of the cache core cluster within the chip. At the same time, the functional core 2,9 of the cache core cluster of the first chip transmits 4KB of calculation result data to the functional core 0,11 of the receiving core cluster of the first chip.

[0095] Among them, the 4KB calculation result data is 4KB of the 12KB data received by the functional core 2,9 of the cache core cluster in the first sub-period T1, plus the 12KB of calculation result data received in the first sub-period T2. At the end of the first sub-period T2, a total of 20KB of calculation result data is cached in the functional core 2,9 of the cache core cluster.

[0096] In the third first sub-cycle T3, the four functional cores (2,7, 2,8, 3,7, 3,8) of the computing core cluster of the first chip send the last 4KB of calculation result data to the functional core 2,9 of the cache core cluster within the chip. At the same time, the functional core 2,9 of the cache core cluster of the first chip transmits 4KB of calculation result data to the functional core 0,11 of the receiving core cluster of the first chip.

[0097] At the end of the third first sub-period T3, a total of 20 KB of calculation result data is cached in the functional cores 2 and 9 of the cache core cluster.

[0098] This method synchronizes the timing of the compute core cluster, cache core cluster, and receiving core cluster. Within a chip, the transmission speed between the compute core cluster and cache core cluster is much higher than the transmission speed between the cache core cluster and receiving core cluster between chips. Data transmission between chip core clusters is completed earlier than data transmission between inter-chip core clusters. This helps the compute core cluster enter the computing state earlier, improving the efficiency of the processor system.

[0099] In step S12, as Figure 6 As shown, in the second working cycle (i.e., T4 to T7), the four functional cores (2,7, 2,8, 3,7, 3,8) of the first chip computing core cluster perform computing tasks, and the functional core 2,9 of the first chip cache core cluster transmits the remaining calculation result data 20KB (28KB-8KB), that is, the second data, to the functional core 0,11 of the second chip receiving core cluster.

[0100] In a possible implementation, in the second working cycle, the computing core cluster, the cache core cluster, and the receiving core cluster are time-synchronized, and the cache core cluster and the receiving core cluster are time-synchronized.

[0101] For example, if Figure 6 As shown, at the end of the third first sub-cycle T3, intra-chip data transmission is complete. During the second working cycle (i.e., second sub-cycles T4 to T7), the computing core cluster of the first chip enters the computing state, while the inter-chip cache core cluster and receiving core cluster continue to perform transmission tasks. In other words, during the second working cycle, the cache core cluster of the first chip and the receiving core cluster of the second chip are synchronized, but both are asynchronous with the computing core cluster.

[0102] The cache core cluster of the first chip and the receiving core cluster of the second chip are synchronized in timing, and the duration of each second sub-cycle can be set according to transmission needs, for example, Figure 6 As shown, the first second sub-period T4 and the second second sub-period T5 can be set to a shorter duration, allowing the cache core cluster of the first chip to transmit 4KB of computational result data to the receiving core cluster of the second chip. The third second sub-period T6 and the fourth second sub-period T7 can be set to a longer duration, allowing the cache core cluster of the first chip to transmit 6KB of computational result data to the receiving core cluster of the second chip. Furthermore, the timing of the computational core cluster is asynchronous with that of the cache core cluster (or receiving core cluster), allowing the computational core cluster's operating sequence to be adjusted based on the computational task.

[0103] It should be understood that the cache core cluster and the receiving core cluster between chips can be set with synchronized timing according to the needs of the transmission task, and the computing core cluster can be set with asynchronous timing with the cache core cluster (or receiving core cluster) according to the needs of its own computing task. The present disclosure does not limit the specific timing settings of each core cluster.

[0104] In this way, in the second working cycle, the computing core cluster can asynchronously execute computing tasks. At the same time, the cache core cluster and the receiving core cluster continue to execute transmission tasks synchronously, which can effectively reduce the idle and waiting time of each functional core between chips in the processor system and improve the computing efficiency and execution speed of the processor system.

[0105] Therefore, the comparison Figure 5 In the data transmission method shown in the related art, the computing core cluster directly sends data to the receiving core cluster outside the chip. Due to the low inter-chip data transmission speed, the computing core cluster will always transmit data at a low speed. Moreover, while the computing core cluster is performing a computing task, the receiving core cluster needs to idle and wait, which is relatively inefficient.

[0106] In the data transmission method of the embodiment of the present disclosure, by setting a cache core cluster, the calculation result data of the computing core cluster can be first transmitted to the cache core cluster, and then transmitted to the receiving core cluster through the cache core cluster. Since the data transmission speed within the chip is relatively high, the computing core cluster can enter the calculation state in advance; and when the computing core cluster performs a calculation task, the receiving core cluster does not need to idle and wait, and can continue to receive the calculation result data of the cache core cluster, thereby improving the computing efficiency and execution speed of the processor system.

[0107] In such Figure 6 Based on the data transmission method shown, the present disclosure can also utilize a multicast transmission method to further improve inter-chip data transmission efficiency. The multicast transmission method of the embodiment of the present disclosure will be introduced below by comparing the related technical methods with the embodiment of the present disclosure.

[0108] Figure 7 FIG. 1 is a schematic diagram showing a method for transmitting data between chips in the related art. Figure 7 As shown, the computing core cluster in chip 1 may include 28 functional cores (2,7 to 15,7, 2,8 to 15,8), and the receiving core cluster in chip 2 may include 7 functional cores (15,0 to 15,6).

[0109] The computing core cluster of chip 1 directly sends the calculation result data to the receiving core cluster of chip 2 outside the chip. Among them, the calculation result data of every 4 functional cores in chip 1 corresponds to 1 functional core in chip 2. For example, functional cores 2,7, 2,8, 3,7, and 3,8 can transmit the calculation results to the same functional core 15,0 outside the chip.

[0110] Since the output transmission volume between chips is relatively small, and the data transmission between the two chips is in a one-directional serial mode, transmitting only in one direction will cause the computing core cluster to always transmit data at an extremely low speed, resulting in a huge transmission time and reducing chip efficiency.

[0111] For example Figure 7 The problem of low inter-chip transmission efficiency shown in Figure 8 FIG. 1 is a schematic diagram showing a method for transmitting data between chips according to an embodiment of the present disclosure. Figure 8 As shown, the functional cores included in chips 1 to 4 are divided into multiple parts, for example, they can be clustered according to computing tasks, caching tasks, receiving tasks, and multicast tasks.

[0112] Different core clusters perform different tasks, while core clusters within a cluster can also perform the same tasks. Data can be transferred between different core clusters, and this data transfer can be related to upstream and downstream core clusters. Data transfer tasks can include both data reception and data transmission. Each core cluster can perform data transfer first, followed by data computation.

[0113] like Figure 8As shown, chip 1 (i.e., the first chip) may include a computing core cluster and a cache core cluster. The computing core cluster may include 28 functional cores (2,7 to 15,7, 2,8 to 15,8), and the cache core cluster may include 7 functional cores (2,9, 4,9, 6,9, 8,9, 10,9, 12,9, 14,9); the receiving core cluster in chip 2 (i.e., the second chip) may include 7 functional cores (15,0 to 15,6); the multicast core cluster in chip 3 (i.e., the third chip) includes 2 functional cores (0,11, 1,11); and the multicast core cluster in chip 4 (i.e., the third chip) includes 3 functional cores (0,11, 1,11, 2,11).

[0114] The 7 functional cores in the cache core cluster of chip 1 can be directly sent to the core clusters of chips 2 to 4. They can be multicasted to the receiving core cluster of chip 2 through multiple core clusters of chips 3 and 4. Figure 8 As shown, the chip 2 can receive three parts of data from the bottom, left and right respectively, and these three parts of data are transmitted in parallel.

[0115] In a possible implementation, data is transmitted serially between different chips of the processor system, wherein, in a first working cycle, the cache core cluster transmits first data of the calculation result data to the receiving core cluster, including:

[0116] The first functional core in the cache core cluster transmits the first sub-data of the first data to the receiving core cluster; the second functional core in the cache core cluster transmits the second sub-data of the first data to the multicast core cluster of a third chip, so that the multicast core cluster transmits the second sub-data to the receiving core cluster, wherein the third chip is at least one chip in the processor system other than the first chip and the second chip.

[0117] For example, in the first working cycle, if Figure 8 As shown, the first functional core (6,9,8,9) in the cache core cluster transmits the first sub-data of the first data to the functional core (15,2,15,3) of the receiving core cluster;

[0118] Among them, the first sub-data represents part of the first data transmitted by the first functional core (6,9, 8,9) in the first working cycle, that is, part of the calculation result data sent by the functional cores (6,7, 6,8, 7,7, 7,8, 8,7, 8,8, 9,7, 9,8) in the computing core cluster and received by the first functional core (6,9, 8,9).

[0119] At the same time, the second functional core (2,9, 4,9, 10,9, 12,9, 14,9) in the cache core cluster transmits the second sub-data of the first data to the multicast core cluster (chip 3, chip 4) of the third chip (chip 3, chip 4) (chip 3 functional core 0,11, 1,11; chip 4 functional core 0,11, 1,11, 2,11), so that the multicast core cluster can transmit the second sub-data to the receiving core cluster.

[0120] The second sub-data represents data in the first data other than the first sub-data, and the third chip may include multiple chips. The present disclosure does not limit the number of the third chips. For example, Figure 8 The third chips may include chip 3 and chip 4, and each third chip may include a multicast core cluster.

[0121] The multicast core cluster (0, 11, 1, 11) in chip 3 can receive part of the calculation result data (i.e., the second sub-data corresponding to the multicast core cluster of chip 3) sent by the second functional core (2, 9, 4, 9) of the cache core cluster, and can transmit the data to the functional core (15, 0, 15, 1) of the receiving core cluster of chip 2;

[0122] The multicast core cluster (0,11, 1,11, 2,11) in chip 4 can receive part of the calculation result data (i.e., the second sub-data corresponding to the multicast core cluster of chip 4) sent by the second functional core (10,9, 12,9, 14,9) of the cache core cluster, and can transmit the data to the functional core (15,4, 15,5, 15,6) of the receiving core cluster of chip 2.

[0123] Since data is transmitted serially between different chips and the routing bandwidth between any two chips is fixed, in this case, the comparison Figure 7 Chip 1 directly transmits the calculation result data to chip 2. Figure 8 By setting up a multicast core cluster, it is helpful to enable chip 1, chip 3 and chip 4 to transmit calculation result data to chip 2 in parallel during the first working cycle, which can increase the data transmission speed between chips by 3 times.

[0124] In this way, by setting a multicast core cluster, parallel transmission between chips can be achieved in the first working cycle, thereby improving the data transmission speed of the chips.

[0125] In a possible implementation, in the second working cycle, the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, including:

[0126] The first functional core in the cache core cluster transmits the third sub-data of the second data to the receiving core cluster;

[0127] The second functional core in the cache core cluster transmits the fourth sub-data of the second data to the multicast core cluster of the third chip, so that the multicast core cluster transmits the fourth sub-data to the receiving core cluster.

[0128] For example, in the second working cycle, if Figure 8 As shown, the first functional core (6,9,8,9) in the cache core cluster transmits the third sub-data of the second data to the functional core (15,2,15,3) of the receiving core cluster;

[0129] Among them, the third sub-data represents part of the second data transmitted by the first functional core (6,9, 8,9) in the second working cycle, that is, the data other than the first sub-data in the calculation result data sent by the functional cores (6,7, 6,8, 7,7, 7,8, 8,7, 8,8, 9,7, 9,8) in the computing core cluster.

[0130] At the same time, the second functional core (2,9, 4,9, 10,9, 12,9, 14,9) in the cache core cluster transmits the fourth sub-data of the second data to the multicast core cluster (chip 3, chip 4) of the third chip (chip 3, chip 4) (chip 3 functional core 0,11, 1,11; chip 4 functional core 0,11, 1,11, 2,11), so that the multicast core cluster can transmit the fourth sub-data to the receiving core cluster.

[0131] The fourth sub-data represents part of the second data excluding the third sub-data. The third chip may include multiple chips, and the present disclosure does not limit the number of the third chips. For example, Figure 8 The third chips may include chip 3 and chip 4, and each third chip may include a multicast core cluster.

[0132] The multicast core cluster (0, 11, 1, 11) in chip 3 can receive the remaining calculation result data (i.e., the fourth sub-data corresponding to the multicast core cluster of chip 3) sent by the second functional core (2, 9, 4, 9) of the cache core cluster, and can transmit the data to the functional core (15, 0, 15, 1) of the receiving core cluster of chip 2;

[0133] The multicast core cluster (0, 11, 1, 11, 2, 11) in chip 4 can receive the remaining calculation result data (i.e., the fourth sub-data corresponding to the multicast core cluster of chip 4) sent by the second functional core (10, 9, 12, 9, 14, 9) of the cache core cluster, and can transmit the data to the functional core (15, 4, 15, 5, 15, 6) of the receiving core cluster of chip 2.

[0134] Since data is transmitted serially between different chips and the routing bandwidth between any two chips is fixed, in this case, the comparison Figure 7 Chip 1 directly transmits the calculation result data to chip 2. Figure 8 By setting up a multicast core cluster, it is helpful to enable chip 1, chip 3 and chip 4 to transmit the calculation result data to chip 2 in parallel during the second working cycle, which can increase the data transmission speed between chips by 3 times.

[0135] In this way, by setting up a multicast core cluster, parallel transmission between chips can be achieved in the second working cycle, thereby improving the data transmission speed of the chips.

[0136] In one possible implementation, the method further includes: in a first working cycle, the multicast core cluster of the third chip transmits the second sub-data to the receiving core cluster of the second chip; in a second working cycle, the multicast core cluster of the third chip transmits the fourth sub-data to the receiving core cluster of the second chip.

[0137] For example, if Figure 8 As shown, the third chip may include chip 3 and chip 4. The present disclosure does not limit the number of the third chips.

[0138] In the first working cycle, the multicast core clusters of the third chip may transmit the second sub-data to the receiving core cluster of the second chip in parallel.

[0139] For example, the multicast core cluster (0, 11, 1, 11) in chip 3 can transmit the corresponding second sub-data (i.e., sent by the second functional core 2, 9, 4, 9) to the functional core (15, 0, 15, 1) of the receiving core cluster of chip 2; the multicast core cluster (0, 11, 1, 11, 2, 11) in chip 4 can transmit the corresponding second sub-data (i.e., sent by the second functional core 10, 9, 12, 9, 14, 9) to the functional core (15, 4, 15, 5, 15, 6) of the receiving core cluster of chip 2.

[0140] In the second working cycle, the multicast core clusters of the third chip may transmit the fourth sub-data to the receiving core cluster of the second chip in parallel.

[0141] For example, the multicast core cluster (0, 11, 1, 11) in chip 3 can transmit the corresponding fourth sub-data (i.e., sent by the second functional core 2, 9, 4, 9) to the functional core (15, 0, 15, 1) of the receiving core cluster of chip 2; the multicast core cluster (0, 11, 1, 11, 2, 11) in chip 4 can transmit the corresponding fourth sub-data (i.e., sent by the second functional core 10, 9, 12, 9, 14, 9) to the functional core (15, 4, 15, 5, 15, 6) of the receiving core cluster of chip 2.

[0142] In this way, parallel transmission between chips can be achieved through multicast core clusters, thereby improving the data transmission speed of the chips.

[0143] Therefore, according to the data transmission method of the disclosed embodiment, by setting up a cache core cluster on-chip, it is possible to avoid executing each functional core's local computing tasks and inter-core data exchange according to a globally synchronized timing. This allows data transmission between the computing core cluster and the cache core cluster to start synchronously and end asynchronously. The data computing task is asynchronously started and executed immediately after the transmission task ends. This can greatly improve the chip's execution efficiency and reduce the idle waiting time of the computing cores in the processor system. Furthermore, by setting up a multicast core cluster off-chip, parallel data transmission between chips can be achieved, further improving the efficiency of inter-chip data transmission.

[0144] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0145] In one possible implementation, Figure 2 As shown, a processor system is provided, the processor system including multiple chips, each chip including multiple functional cores, the data transmission speed between functional cores located in the same chip is higher than the data transmission speed between functional cores located in different chips, wherein the multiple functional cores of each chip are divided into multiple core clusters according to different tasks, when data is transmitted from a first chip to a second chip, the first chip includes a computing core cluster for performing computing tasks and a cache core cluster for performing data caching and transmission tasks, and the second chip includes a receiving core cluster for performing data receiving tasks, the first chip and the second chip are any two chips of the processor system, wherein the first chip is configured as follows:

[0146] In a first working cycle, the computing core cluster transmits the calculation result data to the cache core cluster, and the cache core cluster transmits the first data of the calculation result data to the receiving core cluster; in a second working cycle, the computing core cluster performs the computing task, and the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, where the second data includes data in the calculation result data other than the first data.

[0147] In one possible implementation, in the first working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are timing-synchronized; in the second working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are timing-asynchronous, and the cache core cluster and the receiving core cluster are timing-synchronized.

[0148] In a possible implementation, in a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, including: when the computing result data transmission is completed, the first working cycle ends.

[0149] In one possible implementation, data is transmitted serially between different chips of the processor system, wherein in a first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: the first functional core in the cache core cluster transmits the first sub-data of the first data to the receiving core cluster; the second functional core in the cache core cluster transmits the second sub-data of the first data to the multicast core cluster of a third chip, so that the multicast core cluster transmits the second sub-data to the receiving core cluster, wherein the third chip is at least one chip in the processor system other than the first chip and the second chip.

[0150] In one possible implementation, in the second working cycle, the cache core cluster transmits the second data of the calculation result data to the receiving core cluster, including: the first functional core in the cache core cluster transmits the third sub-data of the second data to the receiving core cluster; the second functional core in the cache core cluster transmits the fourth sub-data of the second data to the multicast core cluster of the third chip, so that the multicast core cluster transmits the fourth sub-data to the receiving core cluster.

[0151] In one possible implementation, the system also includes: in a first working cycle, the multicast core cluster of the third chip transmits the second sub-data to the receiving core cluster of the second chip; in a second working cycle, the multicast core cluster of the third chip transmits the fourth sub-data to the receiving core cluster of the second chip.

[0152] In one possible implementation, the first working cycle includes N first sub-cycles, where N is an integer greater than 1, wherein in the first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: in the first first sub-cycle, the cache core cluster does not transmit data to the receiving core cluster; in the second first sub-cycle to the Nth first sub-cycle, the cache core cluster transmits the first data to the receiving core cluster.

[0153] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0154] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned processor system.

[0155] Figure 9 FIG. 1 is a block diagram of an electronic device 1200 according to an embodiment of the present disclosure. Figure 9 As shown in FIG, the electronic device 1200 includes a computing processing device 1202 (e.g., the aforementioned processor system including multiple artificial intelligence chips), an interface device 1204, other processing devices 1206, and a storage device 1208. Depending on different application scenarios, the computing processing device may include one or more computing devices 1210 (e.g., artificial intelligence chips, each of which may include multiple functional cores).

[0156] In one possible implementation, the computing and processing device of the present disclosure can be configured to perform user-specified operations. In an exemplary application, the computing and processing device can be implemented as a single-chip artificial intelligence processor or a multi-chip artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device can be implemented as an artificial intelligence chip or a partial hardware structure of an artificial intelligence chip. When multiple computing devices are implemented as an artificial intelligence chip or a partial hardware structure of an artificial intelligence chip, with respect to the computing and processing device of the present disclosure, it can be regarded as having a single-chip structure or a homogeneous multi-chip structure.

[0157] In exemplary operation, the computing processing device of the present invention can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present invention may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present invention, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0158] In one or more embodiments, the other processing device may serve as an interface between the computing processing device of the present disclosure (which may be embodied as a computing device related to artificial intelligence, such as neural network computing) and external data and control, performing basic control including but not limited to data transfer, starting and / or stopping the computing device, etc. In other embodiments, the other processing device may also collaborate with the computing processing device to jointly complete computing tasks.

[0159] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it to the storage device (or memory) on the computing and processing device chip. Furthermore, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them to the control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0160] Additionally or optionally, the electronic device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing and processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing and processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing and processing device or other processing device.

[0161] Depending on the application scenario, the artificial intelligence chip disclosed herein can be used in servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, driving recorders, navigation systems, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, household appliances, and / or medical devices. The vehicles include airplanes, ships, and / or cars; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; and the medical devices include magnetic resonance imaging (MRI) machines, ultrasound machines, and / or electrocardiographs.

[0162] Figure 10 FIG1 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server. Figure 10, electronic device 1900 includes a processing component 1922 (e.g., a processor system including multiple functional cores), which further includes one or more functional cores, and a memory resource represented by memory 1932 for storing instructions executable by processing component 1922, such as applications. The application stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, processing component 1922 is configured to execute instructions to perform the above-described method.

[0163] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or the like.

[0164] In the present disclosure, the spaces described as separate components may or may not be physically separated, and the components shown as spaces may or may not be physical spaces. The aforementioned components or spaces may be located in the same location or distributed across multiple network spaces. In addition, according to actual needs, some or all of the spaces may be selected to achieve the purpose of the solution described in the embodiments of the present disclosure. In addition, in some scenarios, multiple spaces in the embodiments of the present disclosure may be integrated into one space or each space may exist physically separately.

[0165] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] The electronic device or processor disclosed in the present invention can also be applied to the fields of the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care, etc. Furthermore, the electronic device or processor disclosed in the present invention can also be used in application scenarios related to artificial intelligence, big data and / or cloud computing, such as the cloud, edge, and terminal. In one or more embodiments, the electronic device or processor with high computing power according to the solution disclosed in the present invention can be applied to cloud devices (such as cloud servers), while the electronic device or processor with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-end integration.

[0167] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data transmission method, characterized in that: The method is applied to a processor system, wherein the processor system includes multiple chips, each chip includes multiple functional cores, and the data transmission speed between functional cores located in the same chip is higher than the data transmission speed between functional cores located in different chips. The multiple functional cores of each chip are divided into multiple core clusters according to different tasks. When data is transmitted from a first chip to a second chip, the first chip includes a computing core cluster for performing computing tasks and a cache core cluster for performing data caching and transmission tasks. The second chip includes a receiving core cluster for performing data receiving tasks. The first chip and the second chip are any two chips of the processor system. The method comprises: In a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, and the cache core cluster transmits first data of the computing result data to the receiving core cluster; In a second working cycle, the computing core cluster performs a computing task, and the cache core cluster transmits second data of the computing result data to the receiving core cluster, where the second data includes data in the computing result data except the first data; Wherein, in the first working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are time-synchronized; In the second working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are time-synchronized, and the cache core cluster and the receiving core cluster are time-synchronized.

2. The method according to claim 1, characterized in that In a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, including: When the calculation result data transmission is completed, the first working cycle ends.

3. The method according to claim 1, characterized in that Data is transmitted serially between different chips in the processor system. In the first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: The first functional core in the cache core cluster transmits the first sub-data of the first data to the receiving core cluster; The second functional core in the cache core cluster transmits the second sub-data of the first data to the multicast core cluster of the third chip, so that the multicast core cluster transmits the second sub-data to the receiving core cluster. The third chip is at least one chip in the processor system except the first chip and the second chip.

4. The method according to claim 3, characterized in that In a second working cycle, the cache core cluster transmits second data of the calculation result data to the receiving core cluster, including: The first functional core in the cache core cluster transmits the third sub-data of the second data to the receiving core cluster; The second functional core in the cache core cluster transmits the fourth sub-data of the second data to the multicast core cluster of the third chip, so that the multicast core cluster transmits the fourth sub-data to the receiving core cluster.

5. The method according to claim 4, characterized in that The method further comprises: In a first working cycle, the multicast core cluster of the third chip transmits the second sub-data to the receiving core cluster of the second chip; In a second working cycle, the multicast core cluster of the third chip transmits the fourth sub-data to the receiving core cluster of the second chip.

6. The method according to claim 1, characterized in that The first working cycle includes N first sub-cycles, where N is an integer greater than 1. In the first working cycle, the cache core cluster transmits the first data of the calculation result data to the receiving core cluster, including: In the first sub-cycle, the cache core cluster does not transmit data to the receiving core cluster; In the 2nd first sub-period to the Nth first sub-period, the cache core cluster transmits the first data to the receiving core cluster.

7. A processor system, characterized in that: The processor system includes multiple chips, each chip includes multiple functional cores, and the data transmission speed between functional cores in the same chip is higher than the data transmission speed between functional cores in different chips. The multiple functional cores of each chip are divided into multiple core clusters according to different tasks. When data is transmitted from a first chip to a second chip, the first chip includes a computing core cluster for performing computing tasks and a cache core cluster for performing data caching and transmission tasks. The second chip includes a receiving core cluster for performing data receiving tasks. The first chip and the second chip are any two chips of the processor system. The first chip is configured as follows: In a first working cycle, the computing core cluster transmits computing result data to the cache core cluster, and the cache core cluster transmits first data of the computing result data to the receiving core cluster; In a second working cycle, the computing core cluster performs a computing task, and the cache core cluster transmits second data of the computing result data to the receiving core cluster, where the second data includes data in the computing result data except the first data; Wherein, in the first working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are time-synchronized; In the second working cycle, the computing core cluster, the cache core cluster and the receiving core cluster are time-synchronized, and the cache core cluster and the receiving core cluster are time-synchronized.

8. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

9. An electronic device, characterized in that: The electronic device comprises the processor system according to claim 7.

Images