Power components with Zener diodes

Abstract

The present invention discloses a power component with a Zener diode, which includes a substrate structure, an insulating layer, a dielectric layer, a transistor, and a plurality of Zener diodes. The transistor is located in the transistor forming region of the substrate structure. The plurality of Zener diodes are all located in the circuit element forming region of the substrate structure and are connected in series with each other. Each Zener diode includes a Zener diode doping structure and a Zener diode metal structure. The Zener diode doping structure is formed on the insulating layer and covered by the dielectric layer. The Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other. The Zener diode metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the P-type doping region and the N-type doping region of the Zener diode doping structure. The present invention can design various power component products with different output voltages by adjusting the number of Zener diodes.

Description

Technical Field

[0001] The present invention relates to a power element, in particular to a power element with a Zener diode. Background Art

[0002] If existing power devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs), need to be added to a circuit design to form an electronic circuit with specific functions (such as resistors or Zener diodes), these circuit components must be electrically connected to the power device through soldering. However, this method of connecting circuit components to the power device increases product manufacturing complexity and fails to effectively reduce product size. Furthermore, the output voltage design range of existing power devices is limited.

[0003] Therefore, the inventors felt that the above-mentioned deficiencies could be improved, and therefore devoted themselves to research and applied scientific theories, and finally proposed a present invention that has a reasonable design and effectively improves the above-mentioned deficiencies. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a power element with a Zener diode in view of the deficiencies in the prior art.

[0005] An embodiment of the present invention discloses a power device having a Zener diode, comprising: a substrate structure including a substrate layer and an epitaxial layer formed on the substrate layer; wherein the substrate structure defines a transistor formation region and a circuit element formation region adjacent to the transistor formation region along its length; an insulating layer formed on the epitaxial layer; a dielectric layer formed on the insulating layer; a transistor located in the transistor formation region, wherein the transistor is formed on the substrate structure and partially formed in the substrate structure, the insulating layer, and the dielectric layer; and a plurality of Zener diodes. The diodes are all located in the circuit element formation area and are connected in series with each other, and each of the Zener diodes includes: a Zener diode doping structure formed on the insulating layer and covered by the dielectric layer; wherein the Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other; and a Zener diode metal structure formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect to the P-type doping region and the N-type doping region of the Zener diode doping structure; wherein each of the Zener diodes is configured to receive a reverse bias when the power element is energized.

[0006] Preferably, the transistor is a metal oxide semiconductor field effect transistor (MOSFET), the epitaxial layer is recessed with at least one groove, the groove is located in the transistor formation area, the insulating layer is extendedly formed on the epitaxial layer and on the inner wall of the groove, the portion of the insulating layer located on the inner wall of the groove is defined as a trench insulating layer, which surrounds a groove, and the remaining portion of the insulating layer is defined as a covering insulating layer; wherein the metal oxide semiconductor field effect transistor includes: a gate filling structure formed in the groove of the trench insulating layer; a base doping structure formed in the epitaxial layer and located in the surrounding area of ​​the groove; a source metal structure formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect the base doping structure; and a drain metal structure formed on a bottom surface of the base layer.

[0007] Preferably, the transistor is a bipolar junction transistor (BJT) and includes: an emitter-doped structure, a base-doped structure, a collector-doped structure, an emitter metal structure, and a collector metal structure; wherein the emitter-doped structure and the base-doped structure are both formed in the epitaxial layer, the inner side of the base-doped structure surrounds the emitter-doped structure, the outer side of the base-doped structure abuts the epitaxial layer, the upper surface of the emitter-doped structure and the upper surface of the base-doped structure are both flush with the upper surface of the epitaxial layer and are both covered by the insulating layer, the remaining part of the epitaxial layer is defined as the collector-doped structure, the emitter metal structure is formed on the dielectric layer and partially penetrates the dielectric layer and the insulating layer to electrically connect the emitter-doped structure, and the collector metal structure is formed on the bottom surface of the base layer.

[0008] Preferably, each of the Zener diode metal structures includes two metal pins, which are spaced apart from each other and partially penetrate the dielectric layer to be electrically connected to the N-type doped region and the P-type doped region of the Zener diode doping structure, respectively; wherein, when the power element is energized, the potential of the metal pin connected to the P-type doped region is lower than the potential of the metal pin connected to the N-type doped region, thereby generating the reverse bias.

[0009] Preferably, a plurality of the Zener diodes are formed on the insulating layer in a manner of being connected in series with each other; wherein, among any two adjacent Zener diodes connected in series with each other, the metal pin of one of the Zener diodes connected to the P-type doping region is directly in contact with and electrically connected to the metal pin of the other Zener diode connected to the N-type doping region; and the Zener diode doping structure of one of the Zener diodes is not directly in contact with the Zener diode doping structure of the other Zener diode.

[0010] Preferably, the power element further includes a plurality of ordinary diodes, wherein the plurality of ordinary diodes are formed on the insulating layer in a manner of being connected in series with each other, and the plurality of ordinary diodes are further connected in series with the plurality of Zener diodes.

[0011] Preferably, each of the ordinary diodes includes: a ordinary diode doping structure and a ordinary diode metal structure, each of the ordinary diode doping structures is formed on the insulating layer and covered by the dielectric layer, each of the ordinary diode doping structures includes a P-type doping region and an N-type doping region connected to each other, and two metal pins of each of the ordinary diode metal structures are respectively formed on the dielectric layer and partially penetrate the dielectric layer to be electrically connected to the P-type doping region and the N-type doping region of the ordinary diode doping structure respectively; wherein each of the ordinary diodes is configured to receive a forward bias.

[0012] Preferably, each of the ordinary diodes can withstand a voltage between 0 volts and 0.7 volts, and each of the Zener diodes can withstand a voltage between 5 volts and 6 volts.

[0013] Preferably, the power element further includes a plurality of ordinary diodes, and the plurality of ordinary diodes and the plurality of Zener diodes are formed on the insulating layer in an alternating series sequence.

[0014] Preferably, the power element further includes: a resistor located in the circuit element formation area and spaced apart from the plurality of Zener diodes, and the resistor includes: a resistor doping structure formed on the insulating layer and covered by the dielectric layer; wherein the resistor doping structure is a P-type doped semiconductor or an N-type doped semiconductor; and a resistor metal structure formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the resistor doping structure, and the resistor is configured to generate a resistance when the power element is energized.

[0015] Preferably, the power element further includes a plurality of conventional diodes, which are formed in series on the insulating layer and located in the circuit element formation area. The plurality of conventional diodes and the plurality of Zener diodes are arranged at intervals, and each of the conventional diodes is configured to receive a forward bias when the power element is powered on.

[0016] The beneficial effect of the present invention is that the power element provided by the present invention can simplify the process complexity and reduce the size of the terminal product by embedding transistors and different electronic components (such as Zener diodes, resistors, and conventional diodes) into a single power element.

[0017] Furthermore, since the power device of the embodiment of the present invention can be designed with multiple Zener diodes (and multiple ordinary diodes or conventional diodes) connected in series, the output voltage V of the power device can be changed by adjusting the number of Zener diodes (and the number of multiple ordinary diodes or conventional diodes) in the product design of the power device. OUT , thus enabling the design of various power component products with different output voltages. This architecture allows for a wider output voltage design range and higher variability.

[0018] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and are not intended to limit the scope of protection of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1A to 1H FIG. 1 is a flow chart of a method for manufacturing a power device according to a first embodiment of the present invention.

[0020] Figure 2 FIG. 1 is a cross-sectional diagram of a power device according to a first embodiment of the present invention, and illustrates an equivalent circuit corresponding to the device structure.

[0021] Figure 3 FIG. 4 is an equivalent circuit diagram of a power element according to the first embodiment of the present invention.

[0022] Figure 4 FIG. 1 is a partial schematic diagram of a power component according to a second embodiment of the present invention.

[0023] Figure 5 FIG. 4 is an equivalent circuit diagram of a power element according to a second embodiment of the present invention.

[0024] Figure 6 FIG. 1 is a partial schematic diagram of a power component according to a third embodiment of the present invention.

[0025] Figure 7 FIG. 4 is an equivalent circuit diagram of a power element according to a third embodiment of the present invention.

[0026] Figure 8 FIG. 4 is a partial schematic diagram of a power device according to a fourth embodiment of the present invention.

[0027] Figure 9 FIG. 4 is an equivalent circuit diagram of a power element according to a fourth embodiment of the present invention.

[0028] Figure 10 FIG. 4 is a schematic cross-sectional view of a power component according to a fifth embodiment of the present invention.

[0029] Figure 11 FIG. 4 is a cross-sectional diagram of a power device according to a fifth embodiment of the present invention, and illustrates an equivalent circuit corresponding to the device structure.

[0030] Figure 12 FIG. 4 is an equivalent circuit diagram of a power element according to a fifth embodiment of the present invention.

[0031] Figure 13 FIG. 4 is an equivalent circuit diagram of a power element according to a sixth embodiment of the present invention.

[0032] Figure 14 FIG. 4 is an equivalent circuit diagram of a power element according to a seventh embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following is an explanation of the disclosed embodiments of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted in actual size. It is stated in advance. The following embodiments will further explain the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention.

[0034] It should be understood that although terms such as "first," "second," and "third" may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. In addition, the term "or" as used herein may include any one or more combinations of the associated listed items, depending on the actual situation.

[0035] [First embodiment]

[0036] See also Figures 1A to 1H 、 Figure 2 and Figure 3 As shown, the first embodiment of the present invention provides a method for manufacturing a power device 100. The method for manufacturing a power device includes steps S110 to S180. Figures 1A to 1H This is a flow chart of a method for manufacturing a power element according to a first embodiment of the present invention. Figure 2 is a cross-sectional schematic diagram of a power element according to a first embodiment of the present invention (indicating an equivalent circuit corresponding to the element structure), and Figure 3FIG. 4 is an equivalent circuit diagram of a power element according to the first embodiment of the present invention.

[0037] It must be noted that the sequence of the steps and the actual operation method described in this embodiment can be adjusted according to needs and are not limited to those described in this embodiment.

[0038] The power device 100 of this embodiment is a power device based on a metal-oxide-semiconductor field-effect transistor (MOSFET). In other words, the power device 100 of this embodiment is an improved power device based on the MOSFET architecture. Furthermore, the power device 100 of this embodiment can be used, for example, in a high-voltage regulator, but the present invention is not limited thereto.

[0039] This embodiment first describes a method for manufacturing a power device. For ease of understanding, this embodiment uses a unit region of the power device manufacturing method as an example, with cross-sectional views provided for illustration. Please refer primarily to the corresponding drawings for each step, and to drawings for other steps as needed. The specific steps of the power device manufacturing method are described below.

[0040] like Figure 1A As shown, step S110 includes providing a substrate structure 1. The substrate structure 1 includes a substrate layer 11 and an epitaxial layer 12 formed on the substrate layer 11. Two opposite surfaces of the substrate structure 1 are defined as a top surface 101 and a bottom surface 102. More specifically, the surface of the epitaxial layer 12 opposite to the substrate layer 11 is the top surface 101, and the surface of the substrate layer 11 opposite to the epitaxial layer 12 is the bottom surface 102.

[0041] The material of the base layer 11 can be, for example, N + Type doped semiconductor or P + The epitaxial layer 12 can be formed on the base layer 11 by an epitaxial process, and the conductivity type of the epitaxial layer 12 can be different from the conductivity type of the base layer 11 (e.g. N + Type doping or P + type doping) is the same.

[0042] In this embodiment, the base layer 11 is N + Type doped semiconductors (i.e., N + Substrate), and the epitaxial layer 12 is N -Type doped semiconductors (i.e., N - EPI). The doping concentration of the base layer 11 is higher than the doping concentration of the epitaxial layer 12. That is, the base layer 11 is a heavily doped region, and the epitaxial layer 12 is a lightly doped region, but the present invention is not limited thereto.

[0043] Specifically, the substrate structure 1 defines a transistor forming region A and a circuit element forming region B adjacent to the transistor forming region A along its length D. The circuit element forming region B can be further divided into a Zener diode forming region B1, a resistor forming region B2, and a normal diode forming region B3.

[0044] In this embodiment, the resistor forming region B2 is located between the Zener diode forming region B1 and the conventional diode forming region B3. The Zener diode forming region B1 is farther away from the transistor forming region A than the resistor forming region B2, and the conventional diode forming region B3 is closer to the transistor forming region A than the resistor forming region B2, but the present invention is not limited to this.

[0045] like Figure 1B As shown, step S120 includes: forming a plurality of grooves 13 in a recessed manner on the epitaxial layer 12, and the plurality of grooves 13 are all located in the transistor formation region A. The plurality of grooves 13 can be formed, for example, by etching. More specifically, the plurality of grooves 13 are recessed at intervals along the length direction D on the surface of the epitaxial layer 12 opposite to the base layer 11, and the bottoms of the plurality of grooves 13 do not contact the base layer 11 but are spaced a distance from the base layer 11. From another perspective, the plurality of grooves 13 are recessed from the top surface 101 of the substrate structure 1 and do not contact the base layer 11 of the substrate structure 1.

[0046] In this embodiment, a trench depth of each of the trenches 13 is typically between 0.5 micrometers and 3 micrometers, and preferably between 1 micrometer and 2 micrometers, but the present invention is not limited thereto.

[0047] It should be noted that the above-mentioned trenches 13 are described from a cross-sectional perspective with respect to trenches 13 at different locations within the epitaxial layer 12. From a holistic perspective, the trenches 13 may be interconnected or separated, and the present invention is not limited thereto.

[0048] like Figure 1C As shown, step S130 includes extending an insulating layer 2 on a surface of the epitaxial layer 12 opposite to the base layer 11 (i.e., the top surface 101 of the substrate structure 1) and on the inner walls of the plurality of trenches 13. The insulating layer 2 can be formed, for example, by a low temperature oxide deposition (LTO) process or a thermal oxidation process, but the present invention is not limited thereto.

[0049] In this embodiment, the thickness of the insulating layer 2 is approximately between 5 nanometers and 100 nanometers, and the insulating layer 2 may be made of a silicon compound, for example, silicon dioxide, but the present invention is not limited thereto.

[0050] Furthermore, the portion of the insulating layer 2 located on the inner wall of each trench 13 is defined as a trench insulating layer 21, and each trench insulating layer 21 surrounds a recess 22. In other words, multiple trench insulating layers 21 are formed on the inner walls of multiple trenches 13, and each trench insulating layer 21 surrounds a plurality of recesses 22. Furthermore, the remaining portion of the insulating layer 2 (i.e., the portion of the insulating layer 2 located on the top surface 101 of the epitaxial layer 12) is defined as a capping insulating layer 23.

[0051] The plurality of trench insulating layers 21 are all located in the transistor forming region A, and the cap insulating layer 23 is extendedly located in the transistor forming region A and the circuit element forming region B.

[0052] like Figure 1D As shown, step S140 includes forming a polysilicon material M on a surface of the insulating layer 2 opposite to the epitaxial layer 12, such that the polysilicon material M covers the capping insulating layer 23 and fills the plurality of recesses 22 surrounded by the plurality of trench insulating layers 21. The polysilicon material M can be formed, for example, from silane (SiH4) by a low pressure chemical vapor deposition (LPCVD) process, but the present invention is not limited thereto.

[0053] In this embodiment, the polysilicon material M is deposited on the insulating layer 2 to a certain thickness such that the outer surface of the polysilicon material M (i.e., the surface of the polysilicon material M opposite to the base layer 11) is a flat surface. More specifically, the outer surface of the polysilicon material M located above the plurality of grooves 22 and above the covering insulating layer 23 is substantially flush with each other, but the present invention is not limited thereto.

[0054] like Figure 1E As shown, the step S150 includes: performing a lithography imaging operation and an etching operation on the polysilicon material M to remove a portion of the polysilicon material M, thereby forming a plurality of polysilicon filled structures M1 (poly-silicon filled structures) in the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21, and forming a plurality of polysilicon block structures M2 (poly-silicon block structures) on the covering insulating layer 23.

[0055] In this embodiment, the polysilicon filling structures M1 are respectively formed in the grooves 22 surrounded by the trench insulating layers 21. Therefore, the polysilicon filling structures M1 are similar to the trench insulating layers 21 and are both located in the transistor forming region A.

[0056] Furthermore, after the etching operation, the exposed surfaces of the polysilicon filling structures M1 (ie, Figure 1E The top surface of the polysilicon filling structure M1 in the embodiment is lower than the outer surface of the capping insulating layer 23 (ie, Figure 1E The surface of the covering insulating layer 23 opposite to the epitaxial layer 12 is used as the cover insulating layer 23, but the present invention is not limited thereto.

[0057] Furthermore, the multiple polysilicon block structures M2 are all formed on the surface of the side of the covering insulating layer 23 opposite to the epitaxial layer 12, and the multiple polysilicon block structures M2 are all located in the above-mentioned circuit element formation area B, so as to be made into different circuit elements (such as: Zener diodes, resistors, and conventional diodes...etc.) in the subsequent manufacturing process.

[0058] Specifically, the plurality of polysilicon block structures M2 are spaced apart from each other on the cover insulating layer 23. In this embodiment, the number of the plurality of polysilicon block structures M2 is three, and the three polysilicon block structures M2 are respectively located in the Zener diode formation region B1, the resistor formation region B2, and the normal diode formation region B3 of the circuit element formation region B.

[0059] It is also worth mentioning that in this embodiment, the raw material M of the polysilicon filling structure M1 and the polysilicon block structure M2 are formed in the same polysilicon deposition process, but the present invention is not limited thereto. The raw material M of the polysilicon filling structure M1 and the polysilicon block structure M2 can also be formed through multiple polysilicon deposition processes (e.g., 2, 3, or more passes) based on process requirements.

[0060] like Figure 1F As shown, step S160 includes: performing an ion implantation process so that the plurality of polysilicon filling structures M1 located in the transistor forming region A are respectively formed into a plurality of gate filling structures 31 (or doped polysilicon filling structures), the portion of the epitaxial layer 12 located between any two adjacent trenches 13 is formed into a matrix doped structure 32 (matrix doped structure), the polysilicon block structure M2 located in the Zener diode forming region B1 is formed into a Zener diode doped structure 41, the polysilicon block structure M2 located in the resistor forming region B2 is formed into a resistor doped structure 51, and the polysilicon block structure M2 located in the conventional diode forming region B3 is formed into a conventional diode doped structure 61. It is worth mentioning that in this embodiment, in order to perform different doping (e.g., P-type doping or N-type doping) on ​​the polysilicon material and the epitaxial layer, the ion implantation process may, for example, include multiple ion implantation procedures (e.g., a P-type doping ion implantation procedure and an N-type doping ion implantation procedure).

[0061] Furthermore, each of the gate filling structures 31 can be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor, which is not limited in the present invention.

[0062] Each of the base doping structures 32 includes a P-type doping region 32P and an N-type doping region 32N formed on the P-type doping region 32P. That is, in each of the base doping structures 32, the N-type doping region 32N and the P-type doping region 32P are stacked one above the other. The P-type doping region 32P is located on the lower side and abuts against the epitaxial layer 12, and the N-type doping region 32N is located on the upper side and abuts against the covering insulating layer 23. It is worth mentioning that the conductive type of the P-type doping region 32P is different from the conductive type of the above-mentioned base layer 11 (N+ type doped semiconductor), which is also different from the conductivity type of the epitaxial layer 12 (N - That is, the plurality of P-type doped regions 32P of this embodiment are P-type doped semiconductors, and the implanted ion species may be, for example, boron ions (B + ), but the present invention is not limited thereto.

[0063] The Zener diode doping structure 41 includes a P-type doping region 41P and a P-type doping region 41P located on one side (eg, Figure 1F An N-type doping region 41N is formed on the left side of the P-type doping region 41P in the Zener diode doping structure 41. That is, in the Zener diode doping structure 41, the N-type doping region 41N and the P-type doping region 41P are arranged side by side and connected to each other. Furthermore, both the N-type doping region 41N and the P-type doping region 41P are formed on the cover insulating layer 23 and are in contact with the cover insulating layer 23.

[0064] The resistor doping structure 51 can be, for example, a P-type doped semiconductor or an N-type doped semiconductor. In this embodiment, a P-type doped semiconductor is preferred, but the present invention is not limited thereto. Furthermore, the doping concentration of the resistor doping structure 51 is lower than the doping concentration of the Zener diode doping structure 41 or the doping concentration of the conventional diode doping structure 61 to produce a resistance effect.

[0065] The conventional diode doping structure 61 is similar to the Zener diode doping structure 41 and includes a P-type doping region 61P and a P-type doping region 61P located on one side (e.g., Figure 1F An N-type doping region 61N is formed on the left side of the P-type doping region 61P in the conventional diode doping structure 61. That is, in the conventional diode doping structure 61, the N-type doping region 61N and the P-type doping region 61P are arranged side by side and connected to each other. Furthermore, both the N-type doping region 61N and the P-type doping region 61P are formed on the cover insulating layer 23 and are in contact with the cover insulating layer 23.

[0066] It should be noted that the ion types used in the ion implantation process described herein may be, for example, boron ions (B + ), zinc ions (Zn 2+ ), fluoride ion (F - ), nitrogen ions (N - ), oxygen ions (O 2- ), carbon ions (C 4+ ), argon ions (Ar + ), phosphorus ions (P + ), arsenic ions (As + ), or antimony ions (Sb 2+ ).

[0067] like Figure 1GAs shown, the step S170 includes: forming a dielectric layer 8 (inter layer dielectric, ILD) on the substrate structure 1, so that the insulating layer 2, multiple gate filling structures 31, the base doping structure 32, the Zener diode doping structure 41, the resistor doping structure 51, and the conventional diode doping structure 61 are covered by the dielectric layer 8.

[0068] The dielectric layer 8 can be formed, for example, by a chemical vapor deposition process, but the present invention is not limited thereto. For example, the dielectric layer 8 can also be formed by a physical vapor deposition process or other suitable deposition process. Furthermore, the material of the dielectric layer 8 can be, for example, a silicon compound or other dielectric material.

[0069] Furthermore, the outer surface of the dielectric layer 8 may be planarized by, for example, a chemical mechanical polishing (CMP) process, but the present invention is not limited thereto.

[0070] like Figure 1H As shown, step S180 includes performing a metallization process to form a source metal structure 33, a Zener diode metal structure 42, a resistor metal structure 52, and a conventional diode metal structure 62 on the dielectric layer 8, and forming a drain metal structure 34 on the bottom surface 102 of the substrate structure 1. It should be noted that the "metal structure" mentioned herein can be formed, for example, by deposition, and can be an integrated structure formed of an aluminum / silicon / copper alloy, but is not limited thereto in practical applications.

[0071] The source metal structure 33 is located in the transistor formation region A. The source metal structure 33 is formed on a surface of the dielectric layer 8 opposite to the base layer 11 and partially penetrates the dielectric layer 8 to be electrically connected to at least one of the plurality of base doping structures 32 .

[0072] In this embodiment, the source metal structure 33 includes a source metal conductive portion 331 and two source metal contact plugs 332 connected to the source metal conductive portion 331. The source metal conductive portion 331 is formed on a surface of the dielectric layer 8 opposite to the base layer 11. The two source metal contact plugs 332 are spaced apart from each other and extend through the dielectric layer 8, respectively, so that the source metal conductive portion 331 can be electrically connected to two adjacent base doping structures 32 among the plurality of base doping structures 32 through the two source metal contact plugs 332.

[0073] Furthermore, the width of each source metal contact plug 332 is smaller than the width of the base doping structure 32 to which it is connected, and each source metal contact plug 332 passes through the N-type doping region 32N of its corresponding base doping structure 32 and partially extends into the P-type doping region 32P. Thus, the two source metal contact plugs 332 are arranged at the same potential as the two base doping structures 32 to which they are electrically connected.

[0074] The drain metal structure 34 is formed on the bottom surface 102 of the substrate structure 1. In other words, the drain metal structure 34 is formed on the surface of the base layer 11 opposite the epitaxial layer 12. In this embodiment, the drain metal structure 34 completely covers the bottom surface 102 of the substrate structure 1, but the present invention is not limited to this.

[0075] According to the above configuration, if Figure 2 As shown, the source metal structure 33 can be used to electrically connect a source wire 33L (or source pin) to define the source S (source) of the MOSFET. The drain metal structure 34 can be used to electrically connect a drain wire 34L (or drain pin) to define the drain D (drain) of the MOSFET. Furthermore, one of the gate filling structures 31 (such as Figure 2 The gate filling structure on the right of the figure can be used to electrically connect a gate wire 31L (or gate pin) to define the gate G of the MOSFET. The various components located in the transistor formation area A (such as the source metal structure 33, the drain metal structure 34, the gate filling structure 31, etc.) can form a MOSFET 3, and its equivalent circuit is shown as follows: Figure 3 shown.

[0076] Please continue reading Figure 1H As shown, the Zener diode metal structure 42 , the resistor metal structure 52 , and the conventional diode metal structure 62 are all located in the circuit element forming region B.

[0077] The Zener diode metal structure 42 is located in the Zener diode forming region B1 and is formed on the surface of the dielectric layer 8 opposite to the base layer 11 and partially penetrates the dielectric layer 8 to be electrically connected to the Zener diode doping structure 41. The Zener diode metal structure 42 and the Zener diode doping structure 41 can be matched with each other to form a Zener diode 4 (V z The Zener diode 4 is configured to receive a reverse bias voltage, and the Zener diode 4 can withstand a voltage between 5V and 6V.

[0078] In this embodiment, the Zener diode metal structure 42 includes two metal pins 421. The two metal pins 421 of the Zener diode metal structure 42 are spaced apart from each other and partially penetrate the dielectric layer 8 to electrically connect to the N-type doping region 41N and the P-type doping region 41P of the Zener diode doping structure 41, respectively, thereby forming the Zener diode 4. In the Zener diode 4, the potential of the metal pin 421 connected to the P-type doping region 41P is lower than the potential of the metal pin 421 connected to the N-type doping region 41N, thereby generating a "reverse bias" when the power device is energized.

[0079] The resistor metal structure 52 is located in the resistor formation region B2 and is formed on the surface of the dielectric layer 8 opposite to the base layer 11. The resistor metal structure 52 partially penetrates the dielectric layer 8 to be electrically connected to the resistor doped structure 51. The resistor metal structure 52 and the resistor doped structure 51 can be combined to form a resistor 5 (resistor, R).

[0080] In this embodiment, the resistor metal structure 52 includes two metal pins 521. The two metal pins 521 of the resistor metal structure 52 are spaced apart from each other and partially penetrate the dielectric layer 8 to electrically connect to the resistor doped structure 51 (e.g., a P-type doped semiconductor). The doping concentration of the resistor doped structure 51 is lower than the doping concentration of the Zener diode doped structure 41 and the doping concentration of the conventional diode doped structure 61, thereby generating a resistance effect when the power device is energized.

[0081] The normal diode metal structure 62 is located in the normal diode forming area B3 and is formed on the surface of the dielectric layer 8 opposite to the base layer 11 and partially penetrates the dielectric layer 8 to be electrically connected to the normal diode doping structure 61. The normal diode metal structure 62 and the normal diode doping structure 61 can be matched with each other to form a normal diode 6 (V D The conventional diode 6 is configured to receive a forward bias, and the conventional diode 6 can withstand a voltage between 0V and 0.7V.

[0082] In this embodiment, the conventional diode metal structure 62 includes two metal pins 621. The two metal pins 621 of the conventional diode metal structure 62 are spaced apart from each other and partially penetrate the dielectric layer 8 to electrically connect to the N-type doping region 61N and the P-type doping region 61P of the conventional diode doping structure 61, respectively, thereby forming the conventional diode 6. In the conventional diode 6, the potential of the metal pin 621 connected to the P-type doping region 61P is higher than the potential of the metal pin 621 connected to the N-type doping region 61N, thereby generating a "forward bias" when the power device is energized.

[0083] It is worth mentioning that in this embodiment, in the conventional diode 6, the metal pin 621 connected to the P-type doping region 61P can be electrically connected to one of the gate filling structures 31 (such as Figure 2 Furthermore, the metal pin 621 connected to the N-type doped region 61N can be electrically connected to the source metal structure 33 of the MOSFET 3 via a conductive wire (not shown), but the present invention is not limited thereto.

[0084] It is worth mentioning that in this embodiment, the N-type doping region 32N of the substrate doping structure 32 , the N-type doping region 41N of the Zener diode 4 , and the N-type doping region 61N of the conventional diode are completed in the same ion implantation process, but the present invention is not limited thereto.

[0085] After executing the above steps S110 to S180, the following steps can be completed: Figure 1H and Figure 2 The power device 100 (or trench power device) shown in FIG. 1 is an equivalent circuit diagram of the power device 100 of this embodiment. Figure 3 It should be emphasized that in actual application, each step may be replaced by a reasonable variation.

[0086] Furthermore, it should be emphasized that the above steps are described from a cross-sectional perspective. As long as the above steps are followed, the present invention can be implemented with various design layouts. In other words, the power device 100 of this embodiment can have different design layouts when viewed from above.

[0087] According to the above configuration, the manufacturing method of the power element provided by the embodiment of the present invention can integrate the formation of different electronic components (such as Zener diodes, resistors, conventional diodes) into the process of metal oxide semiconductor field effect transistors (especially the process after depositing polysilicon) to form the required power elements, without adding additional processes, thereby simplifying the process complexity.

[0088] The above describes the manufacturing method of the power device according to an embodiment of the present invention. The following describes the specific structure of the power device according to this embodiment. It should be noted that while the power device according to this embodiment is manufactured using the above manufacturing method, the present invention is not limited thereto. In other words, the power device according to the present invention may also be manufactured using other manufacturing methods.

[0089] like Figure 1H Please match with Figure 2 and Figure 3 This embodiment further discloses a power device 100, which includes: a substrate structure 1, an insulating layer 2, a dielectric layer 8, a metal oxide semiconductor field effect transistor 3 (MOSFET), a Zener diode 4 (V Z ), a resistor 5 (R), and a conventional diode 6 (V D ).

[0090] The substrate structure 1 includes a base layer 11 and an epitaxial layer 12 formed on the base layer 11. The epitaxial layer 12 is recessed with at least one trench 13. The substrate structure 1 defines a transistor formation region A and a circuit element formation region B adjacent to the transistor formation region A along its length D. The trench 13 is located in the transistor formation region A.

[0091] The insulating layer 2 is formed extending over the epitaxial layer 12 and the inner wall of the trench 13. The portion of the insulating layer 2 located on the inner wall of the trench 13 is defined as a trench insulating layer 21, which surrounds a recess 22. The remaining portion of the insulating layer 2 is defined as a covering insulating layer 23. Furthermore, the dielectric layer 8 is formed on the insulating layer 2.

[0092] The MOSFET 3 is located in the transistor formation region A and includes a gate fill structure 31, a base doping structure 32, a source metal structure 33, and a drain metal structure 34. The gate fill structure 31 is formed in the recess 22 of the trench insulating layer 21. The base doping structure 32 is formed in the epitaxial layer 12 and is located in the area surrounding the trench 13. The source metal structure 33 is formed on the dielectric layer 8 and partially penetrates the dielectric layer 8 to electrically connect to the base doping structure 32. The drain metal structure 34 is formed on a bottom surface of the base layer 11.

[0093] The Zener diode 4 is located in the circuit element formation area B and includes: a Zener diode doping structure 41 and a Zener diode metal structure 42. The Zener diode doping structure 41 is formed on the cover insulating layer 23 and is covered by the dielectric layer 8. The Zener diode doping structure 41 includes a P-type doping region 41P and an N-type doping region 41N connected to each other. The Zener diode metal structure 42 is formed on the dielectric layer 8 and partially penetrates the dielectric layer 8 to electrically connect to the P-type doping region 41P and the N-type doping region 41N of the Zener diode doping structure 41. The Zener diode 4 is configured to receive a reverse bias when the power device 100 is powered.

[0094] The resistor 5 is located in the circuit element formation region B and is spaced apart from the Zener diode 4. The resistor 5 includes a resistor doping structure 51 and a resistor metal structure 52. The resistor doping structure 51 is formed on the capping insulating layer 23 and covered by the dielectric layer 8. The resistor doping structure 51 is a P-type doped semiconductor or an N-type doped semiconductor. The resistor metal structure 52 is formed on the dielectric layer and partially penetrates the dielectric layer 8 to electrically connect to the resistor doping structure 51. The resistor 5 is configured to generate a resistance when the power device 100 is energized.

[0095] The conventional diode 6 is located in the circuit element forming area B and is spaced apart from the Zener diode 4. The conventional diode 6 includes: a conventional diode doping structure 61 and a conventional diode metal structure 62. The conventional diode doping structure 61 is formed on the covering insulating layer 23 and is covered by the dielectric layer 8. The conventional diode doping structure 61 includes a P-type doping region 61P and an N-type doping region 61N connected to each other. The conventional diode metal structure 62 is formed on the dielectric layer 8 and partially penetrates the dielectric layer 8 to electrically connect to the P-type doping region 61P and the N-type doping region 61N of the conventional diode doping structure 61. The conventional diode 6 is configured to receive a forward bias. The conventional diode 6 is arranged adjacent to the above-mentioned metal oxide semiconductor field effect transistor 3.

[0096] [Second embodiment]

[0097] See also Figure 4 and Figure 5 As shown, the second embodiment of the present invention also provides a power device 100 ′. Figure 4 is a partial schematic diagram of a power element according to a second embodiment of the present invention, and Figure 5 FIG. 4 is an equivalent circuit diagram of a power element according to a second embodiment of the present invention.

[0098] The structure of the power element 100' in the second embodiment of the present invention is substantially the same as that of the first embodiment, except that the power element 100' in this embodiment includes a plurality of Zener diodes 4 (V Z1 To V ZN ), which is configured to receive a reverse bias voltage.

[0099] like Figure 4 As shown, the plurality of Zener diodes 4 (V Z1 To V ZN ) are formed in series on the covering insulating layer 23 of the insulating layer 2 and are located in the Zener diode forming area B1 of the circuit element forming area B.

[0100] More specifically, the plurality of Zener diodes 4 connected in series are arranged in a staggered pattern of "P-type doping region 41P / N-type doping region 41N...P-type doping region 41P / N-type doping region 41N." Among these, among any two adjacent Zener diodes 4 connected in series, the metal pin 421 of one Zener diode 4 connected to the P-type doping region 41P is directly in contact with and electrically connected to the metal pin 421 of the other Zener diode 4 connected to the N-type doping region 41N. Furthermore, the Zener diode doping structure 41 of one Zener diode 4 is spaced apart from and not in direct contact with the Zener diode doping structure 41 of the other Zener diode 4.

[0101] Further, if Figure 4 As shown, among the plurality of Zener diodes 4 connected in series, the first Zener diode V Z1 (like Figure 4 The leftmost Zener diode V Z1 ) connected to the P-type doped region 41P, can be electrically connected to a ground terminal (potential is 0 volts) of the power element through a wire (not shown). ZN (like Figure 4 The rightmost Zener diode V ZN ) connected to the N-type doped region 41N, can be electrically connected to the gate filling structure 31 (such as Figure 2 The rightmost gate filling structure is shown in FIG. 3 , but the present invention is not limited thereto.

[0102] like Figure 5 As shown, the power element 100' of this embodiment has a plurality of Zener diodes 4 (V Z1 To V ZN), so in the product design of power components, the number of Zener diodes 4 can be adjusted (such as two, three, four, etc.) to change V G , thereby changing the output voltage V of the power element OUT , thereby designing various power component products with different output voltages.

[0103] Therefore, the concept of this structural design can arbitrarily integrate various power MOSFETs with different voltages / currents according to the output voltage requirements of the terminal product. OUT =V G -V D , and V G =(V Z1 +V Z2 +…V ZN ).

[0104] [Third embodiment]

[0105] See also Figure 6 and Figure 7 As shown, the third embodiment of the present invention also provides a power device 100. Figure 6 is a partial schematic diagram of a power element according to a third embodiment of the present invention, and Figure 7 FIG. 4 is an equivalent circuit diagram of a power element according to a third embodiment of the present invention.

[0106] The structure of the power element 100" in the third embodiment of the present invention is substantially the same as that of the second embodiment, except that the power element 100" in this embodiment further includes a plurality of ordinary diodes 7 (V F1 To V FN ), and a plurality of the common diodes 7 (V F1 To V FN ) is further connected in series with the above-mentioned plurality of Zener diodes 4 (V Z1 To V ZN ).

[0107] In this embodiment, the plurality of ordinary diodes 7 (V F1 To V FN ) are also formed in series on the insulating layer 23 of the insulating layer 2 and are connected in series to the plurality of Zener diodes 4 (V Z1 To V ZN ).

[0108] More specifically, each of the common diodes 7 includes a common diode doping structure 71 and a common diode metal structure 72. Each of the common diode doping structures 71 is formed on the capping insulating layer 23 of the insulating layer 2 and is covered by the dielectric layer 8. Each of the common diode doping structures 71 includes a P-type doping region 71P and an N-type doping region 71N connected to each other. Each of the two metal pins 721 of the common diode metal structure 72 is formed on the dielectric layer 8 and partially penetrates the dielectric layer 8 to electrically connect to the P-type doping region 71P and the N-type doping region 71N of the common diode doping structure 71, respectively. Each of the common diodes 7 is configured to receive a forward bias.

[0109] That is, in each of the common diodes 7, the potential of the metal pin 721 connected to the P-type doping region 71P is higher than the potential of the metal pin 721 connected to the N-type doping region 71N, thereby generating a "forward bias" when the power element is powered on. F1 To V FN ) are connected in series in a manner similar to the plurality of Zener diodes 4 in the second embodiment described above, and will not be described in detail here.

[0110] According to this, when the power element 100" is powered on, the plurality of ordinary diodes 7 (V F1 To V FN ) is configured to receive a forward bias and to be coupled with a plurality of the common diodes 7 (V F1 To V FN ) a plurality of the Zener diodes 4 (V Z1 To V ZN ) is configured to receive a reverse bias voltage.

[0111] Please continue reading Figure 6 As shown, the plurality of common diodes 7 connected in series are arranged in a staggered manner in the form of "N-type doping region 71N / P-type doping region 71P ... N-type doping region 71N / P-type doping region 71P". Z1 To V ZN ) and a plurality of said common diodes 7 (V F1 To V FN ), the Nth Zener diode V ZN (like Figure 6 The rightmost Zener diode V ZN ) is connected to the metal pin 421 of the N-type doped region 41N, which is directly in contact with and electrically connected to the first common diode V F1 The metal pin 721 is connected to the N-type doping region 71N.

[0112] Furthermore, the first Zener diode V Z1 (like Figure 6 The leftmost Zener diode V Z1 ) connected to the P-type doped region 41P, can be electrically connected to a ground terminal (potential is 0 volts) of the power element through a wire (not shown). FN (like Figure 6 The rightmost common diode V FN ) connected to the P-type doped region 71P, can be electrically connected to the gate filling structure 31 (such as Figure 2 The rightmost gate filling structure is shown in FIG. 3 , but the present invention is not limited thereto.

[0113] like Figure 7 As shown, the power element 100 of this embodiment has a plurality of Zener diodes 4 (V Z1 To V ZN ) and multiple common diodes 7 (V F1 To V FN ), so in the product design of power components, the number of Zener diodes 4 and ordinary diodes 7 can be adjusted to change V G , thereby changing the output voltage V of the power element OUT , thereby designing various power component products with different output voltages. This architecture allows the design range of output voltage to be wider and more variable. Among them, the output voltage can be, for example, V OUT =V G -V D , and V G =(V Z1 +V Z2 +…V ZN )+(V F1 +V F2 +…V FN ).

[0114] It should be noted that although the series connection order of multiple electronic components in this embodiment is based on V Z1 ~V ZN To V F1 ~V FN For example, in an embodiment not shown in the drawing, the series connection order of multiple electronic components may also be V F1 ~V FN To V Z1 ~V ZN ; Or, it can also be, for example, V Z1 、V F1 、VZ2 、V F2 ,…,V ZN 、V FN , any staggered series order. The series order of multiple electronic components does not affect the final V G (The total voltage that all electronic components can withstand).

[0115] [Fourth embodiment]

[0116] See also Figure 8 and Figure 9 As shown, the fourth embodiment of the present invention also provides a power device 100 ″′. Figure 8 is a partial schematic diagram of a power element according to a fourth embodiment of the present invention, and Figure 9 FIG. 4 is an equivalent circuit diagram of a power element according to a fourth embodiment of the present invention.

[0117] The structure of the power element 100'' in the fourth embodiment of the present invention is substantially the same as that of the third embodiment, except that the power element 100'' in this embodiment further includes a plurality of conventional diodes 6 (V D1 To V DN ), which is configured to receive a forward bias.

[0118] like Figure 8 As shown, a plurality of conventional diodes 6 (V D1 To V DN ) are formed in series with each other on the covering insulating layer 23 of the insulating layer 2 and are located in the conventional diode forming area B3 of the circuit element forming area B.

[0119] Furthermore, the plurality of conventional diodes 6 connected in series are spaced apart from the resistor 5 and are also spaced apart from the plurality of Zener diodes 4 (V Z1 To V ZN ) and multiple common diodes 7 (V F1 To V FN ) interval settings.

[0120] More specifically, the plurality of conventional diodes 6 connected in series are arranged in an alternating pattern of "N-type doping region 61N / P-type doping region 61P...N-type doping region 61N / P-type doping region 61P." Among these, among any two adjacent conventional diodes 6 connected in series, the metal pin 621 of one conventional diode 6 connected to the P-type doping region 61P directly contacts and is electrically connected to the metal pin 621 of the other conventional diode 6 connected to the N-type doping region 61N. Furthermore, the conventional diode doping structure 61 of one conventional diode 6 does not directly contact the conventional diode doping structure 61 of the other conventional diode 6.

[0121] Further, if Figure 8 As shown, among the plurality of conventional diodes 6 connected in series, the Nth conventional diode V DN (like Figure 8 The rightmost conventional diode V DN ) connected to the P-type doped region 61P can be electrically connected to one of the gate filling structures 31 (such as Figure 2 Furthermore, the first conventional diode V D1 (like Figure 8 The metal pin 621 of the leftmost conventional diode 6) connected to the N-type doped region 61N can be electrically connected to the source metal structure 33 of the MOSFET 3 through a wire (not shown), but the present invention is not limited thereto. In other words, the plurality of conventional diodes 6 (V D1 To V DN ) is connected in series between the gate (G) and source (S) of the metal oxide semiconductor field effect transistor 3 (MOSFET).

[0122] like Figure 9 As shown, the power element 100'' of this embodiment not only has a plurality of Zener diodes 4 (V Z1 To V ZN ) and multiple common diodes 7 (V F1 To V FN ), further having a plurality of conventional diodes 6 (V D1 To V DN ), so this architecture can make the output voltage design range wider and more variable. Wherein, the output voltage can be, for example, V OUT =V G -V D , and V G =(V Z1 +V Z2 +…V ZN )+(V F1 +V F2 +…V FN ), and V D =(V D1 +V D2 +…V DN ).

[0123] [Fifth embodiment]

[0124] See also Figures 10 to 12 As shown, a fifth embodiment of the present invention provides a power device 200 . Figure 10 is a schematic cross-sectional view of a power element according to a fifth embodiment of the present invention, Figure 11 is a cross-sectional view of a power element according to a fifth embodiment of the present invention, and indicates an equivalent circuit corresponding to the element structure, and Figure 12 FIG. 4 is an equivalent circuit diagram of a power element according to a fifth embodiment of the present invention.

[0125] The power device 200 of this embodiment is a power device based on a bipolar junction transistor (BJT). In other words, the power device 200 of this embodiment is an improved power device based on a BJT architecture. Furthermore, the power device 200 of this embodiment can be used, for example, in a high-voltage regulator, but the present invention is not limited thereto.

[0126] The power device 200 includes a substrate structure 1', an insulating layer 2', a dielectric layer 8', a bipolar junction transistor 3' (BJT), a Zener diode 4' (V Z ), and a resistor 5' (R).

[0127] It is worth mentioning that, since the bipolar junction transistor 3 ′ (BJT) itself has a built-in diode, the power device 200 of this embodiment preferably does not include an additional conventional diode, but the present invention is not limited thereto.

[0128] The substrate structure 1' comprises a base layer 11' (eg, N + substrate) and an epitaxial layer 12' (eg, N - EPI). The substrate structure 1' defines a transistor formation region A' and a circuit element formation region B' adjacent to the transistor formation region A' along its length D'. The circuit element formation region B' can be further divided into a Zener diode formation region B1' and a resistor formation region B2'.

[0129] Specifically, the insulating layer 2 ′ is formed on the epitaxial layer 12 ′, and the dielectric layer 8 ′ is formed on the insulating layer 2 ′.

[0130] Furthermore, the bipolar junction transistor 3 ′ is located in the transistor forming region A′ and includes an emitter doping structure 31 ′, a base doping structure 32 ′, a collector doping structure 33 ′, an emitter metal structure 34 ′, and a collector metal structure 35 ′.

[0131] The emitter doping structure 31' and the base doping structure 32' are both formed in the epitaxial layer 12' and are both located in the upper half of the epitaxial layer 12'. The inner side of the base doping structure 32' surrounds the emitter doping structure 31', and the outer side of the base doping structure 32' abuts the epitaxial layer 12'. The upper surface of the emitter doping structure 31' and the upper surface of the base doping structure 32' are both flush with the upper surface of the epitaxial layer 12' and are both covered by the insulating layer 2'. The remaining portion of the epitaxial layer 12' (that is, the portion not covered by the emitter doping structure 31' and the base doping structure 32') is defined as the collector doping structure 33'.

[0132] In this embodiment, the emitter doping structure 31', the base doping structure 32', and the collector doping structure 33' are sequentially composed of an N-type doped semiconductor, a P-type doped semiconductor, and an N-type doped semiconductor to form an NPN transistor, but the present invention is not limited thereto. For example, the emitter doping structure 31', the base doping structure 32', and the collector doping structure 33' may also be sequentially composed of a P-type doped semiconductor, an N-type doped semiconductor, and a P-type doped semiconductor to form a PNP transistor.

[0133] The emitter metal structure 34' is formed on the dielectric layer 8' and partially penetrates the dielectric layer 8' and the insulating layer 2' to electrically connect the emitter doping structure 31'. The collector metal structure 35' is formed on a bottom surface of the base layer 11'.

[0134] According to the above configuration, if Figure 10 and Figure 11 As shown, the base doping structure 32' can be used to electrically connect a base wire 32L' (or base pin) to define the base B (base) of the bipolar junction transistor. The emitter metal structure 34' can be used to electrically connect an emitter wire 34L' (or emitter pin) to define the emitter E (emitter) of the bipolar junction transistor. The collector metal structure 35' can be used to electrically connect a collector wire 35L' (or collector pin) to define the collector C (collector) of the bipolar junction transistor. The above-mentioned various components located in the transistor formation area A' (such as: emitter doping structure 31', base doping structure 32', collector doping structure 33'... etc.) can form a bipolar junction transistor 3', and its equivalent circuit is shown as follows. Figure 12 shown.

[0135] The Zener diode 4' (V Z) is located in the Zener diode forming area B1' of the circuit element forming area B', and includes: a Zener diode doping structure 41' and a Zener diode metal structure 42'. The Zener diode doping structure 41' is formed on the insulating layer 2' and is covered by the dielectric layer 8'. The Zener diode doping structure 41' includes a P-type doping region 41P' and an N-type doping region 41N' connected to each other. The Zener diode metal structure 42' includes two metal pins 421' separated from each other. The two metal pins 421' of the Zener diode metal structure 42' are both formed on the dielectric layer 8' and both partially penetrate the dielectric layer 8' to be electrically connected to the P-type doping region 41P' and the N-type doping region 41N' of the Zener diode doping structure 41' respectively. The Zener diode 4' is configured to receive a reverse bias when the power element 200 is powered on.

[0136] The resistor 5'(R) is located in the resistor forming area B2' of the circuit element forming area B' and is spaced apart from the Zener diode 4'. The resistor 5' includes: a resistor doping structure 51' and a resistor metal structure 52'. The resistor doping structure 51' is formed on the insulating layer 2' and is covered by the dielectric layer 8'. The resistor doping structure 51' is a P-type doped semiconductor or an N-type doped semiconductor. The resistor metal structure 52' includes two metal pins 521' separated from each other. The two metal pins 521' of the resistor metal structure 52' are both formed on the dielectric layer 8' and both partially penetrate the dielectric layer 8' to be electrically connected to the resistor doping structure 51' respectively. The resistor 5' is configured to generate a resistance when the power element 200 is energized.

[0137] [Sixth embodiment]

[0138] See also Figure 13 As shown, the sixth embodiment of the present invention also provides a power element 200'. The structure design of the power element 200' of the sixth embodiment of the present invention is substantially the same as that of the fifth embodiment, except that the power element 200' of this embodiment includes a plurality of Zener diodes 4' (V Z1 To V ZN ), which is configured to receive a reverse bias voltage. Z1 To V ZN ) is similar to the concatenation of Figure 4 , I won’t go into details here. Figure 13 FIG. 4 is an equivalent circuit diagram of a power element according to a sixth embodiment of the present invention.

[0139] [Seventh embodiment]

[0140] See also Figure 14 As shown, the seventh embodiment of the present invention also provides a power element 200". The structural design of the power element 200" of the seventh embodiment of the present invention is substantially the same as that of the sixth embodiment, except that the power element 200" of this embodiment further includes a plurality of ordinary diodes (V F1 To V FN ), and a plurality of the ordinary diodes (V F1 To V FN ) is further connected in series with the above-mentioned plurality of Zener diodes 4' (V Z1 To V ZN ). A plurality of said ordinary diodes (V F1 To V FN ) and Zener diode (V Z1 To V ZN ) is similar to the concatenation of Figure 6 , I won’t go into details here. Figure 14 FIG. 1 is an equivalent circuit diagram of a power element according to the seventh embodiment of the present invention. It should be noted that although the series connection order of multiple electronic elements in this embodiment is V Z1 ~V ZN To V F1 ~V FN For example, in an embodiment not shown in the drawing, the series connection order of multiple electronic components may also be V F1 ~V FN To V Z1 ~V ZN ; Or, it can also be, for example, V Z1 、V F1 、V Z2 、V F2 ,…,V ZN 、V FN , any staggered series order. The series order of multiple electronic components does not affect the final V G (The total voltage that all electronic components can withstand).

[0141] [Beneficial Effects of Embodiments]

[0142] The power device provided by the embodiment of the present invention can simplify the manufacturing process complexity and reduce the size of the terminal product by embedding transistors and different electronic components (such as Zener diodes, resistors, and conventional diodes) into a single power device.

[0143] Furthermore, since the power device of the embodiment of the present invention can be designed with multiple Zener diodes (and multiple ordinary diodes or conventional diodes) connected in series, the output voltage V of the power device can be changed by adjusting the number of Zener diodes (and the number of multiple ordinary diodes or conventional diodes) in the product design of the power device. OUT , thereby designing various power component products with different output voltages. This architecture allows for a wider range of output voltage design and higher variability. In other words, the output voltage V of the power component of the embodiment of the present invention is OUT It is positively correlated with the number of Zener diodes, ordinary diodes, and conventional diodes.

[0144] In addition, the structural design of the power element of this embodiment can reduce the number of electronic components required to be placed on the system circuit board because some of the electronic components are integrated into the integrated component manufacturing process of the present invention, thereby reducing the size of the terminal product.

[0145] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of protection of the claims of the present invention.

Claims

1. A power element having a Zener diode, characterized in that: The power element includes: A substrate structure comprising a base layer and an epitaxial layer formed on the base layer; wherein the base structure defines a transistor formation region and a circuit element formation region adjacent to the transistor formation region along its length direction; an insulating layer formed on the epitaxial layer; a dielectric layer formed on the insulating layer; a transistor located in the transistor formation region, wherein the transistor is formed on the substrate structure and partially formed in the substrate structure, the insulating layer, and the dielectric layer; and A plurality of Zener diodes are located in the circuit element forming region and are connected in series with each other. The plurality of Zener diodes are formed in series with each other on the insulating layer and are spaced apart from the transistors. Each of the Zener diodes includes: a Zener diode doping structure formed on the insulating layer and covered by the dielectric layer; The Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other; and a Zener diode metal structure formed on the dielectric layer and partially extending through the dielectric layer to electrically connect the P-type doped region and the N-type doped region of the Zener diode doping structure; wherein each of the Zener diodes is configured to receive a reverse bias when the power device is energized; Each of the Zener diode metal structures includes two metal pins spaced apart from each other and partially extending through the dielectric layer to electrically connect to and contact the N-type doped region and the P-type doped region of the Zener diode doping structure, respectively. When the power device is energized, the potential of the metal pin connected to the P-type doped region is lower than the potential of the metal pin connected to the N-type doped region, thereby generating the reverse bias voltage. Among any two adjacent Zener diodes connected in series, the metal pin of one Zener diode connected to the P-type doped region is directly in contact with and electrically connected to the metal pin of the other Zener diode connected to the N-type doped region; and the Zener diode doping structure of one Zener diode is not directly in contact with the Zener diode doping structure of the other Zener diode. The transistor is a metal oxide semiconductor field effect transistor (MOSFET), the epitaxial layer is recessed with at least one trench, the trench is located in the transistor formation region, the insulating layer is extendedly formed on the epitaxial layer and on the inner wall of the trench, the portion of the insulating layer located on the inner wall of the trench is defined as a trench insulating layer, which surrounds a recess, and the remaining portion of the insulating layer is defined as a covering insulating layer; wherein the metal oxide semiconductor field effect transistor comprises: a gate filling structure formed in the groove of the trench insulating layer; a substrate doping structure formed in the epitaxial layer and located in a peripheral area of ​​the trench; a source metal structure formed on the dielectric layer and partially penetrating the dielectric layer to electrically connect to the base doping structure; and A drain metal structure is formed on a bottom surface of the base layer.

2. The power element according to claim 1, wherein: The power element further includes a plurality of ordinary diodes, which are formed on the insulating layer in a manner of being connected in series, and the plurality of ordinary diodes are further connected in series to the plurality of Zener diodes.

3. The power element according to claim 2, wherein: Each of the ordinary diodes includes: a ordinary diode doping structure and a ordinary diode metal structure. Each of the ordinary diode doping structures is formed on the insulating layer and covered by the dielectric layer. Each of the ordinary diode doping structures includes a P-type doping region and an N-type doping region connected to each other. Two metal pins of each of the ordinary diode metal structures are respectively formed on the dielectric layer and partially penetrate the dielectric layer to be electrically connected to the P-type doping region and the N-type doping region of the ordinary diode doping structure respectively; wherein each of the ordinary diodes is configured to receive a forward bias.

4. The power element according to claim 3, characterized in that Each of the ordinary diodes can withstand a voltage between 0 volts and 0.7 volts, and each of the Zener diodes can withstand a voltage between 5 volts and 6 volts.

5. The power element according to claim 1, wherein: The power element further includes a plurality of common diodes. The plurality of common diodes and the plurality of Zener diodes are formed on the insulating layer in an alternating series sequence.

6. The power element according to claim 1, wherein: The power element further includes: a resistor located in the circuit element forming region and spaced apart from the plurality of Zener diodes, wherein the resistor includes: a resistor doping structure formed on the insulating layer and covered by the dielectric layer; wherein, The resistor doping structure is a P-type doped semiconductor or an N-type doped semiconductor; and A resistor metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the resistor doping structure. The resistor is configured to generate a resistance when the power device is powered on.

7. The power element according to claim 1, wherein: The power element further includes a plurality of conventional diodes, which are formed in series on the insulating layer and located in the circuit element formation area. The plurality of conventional diodes and the plurality of Zener diodes are arranged at intervals, and each of the conventional diodes is configured to receive a forward bias when the power element is powered on.

8. A power element having a Zener diode, characterized in that: The power element includes: A substrate structure comprising a base layer and an epitaxial layer formed on the base layer; wherein the base structure defines a transistor formation region and a circuit element formation region adjacent to the transistor formation region along its length direction; an insulating layer formed on the epitaxial layer; a dielectric layer formed on the insulating layer; a transistor located in the transistor formation region, wherein the transistor is formed on the substrate structure and partially formed in the substrate structure, the insulating layer, and the dielectric layer; and A plurality of Zener diodes are located in the circuit element forming region and are connected in series with each other. The plurality of Zener diodes are formed in series with each other on the insulating layer and are spaced apart from the transistors. Each of the Zener diodes includes: a Zener diode doping structure formed on the insulating layer and covered by the dielectric layer; The Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other; and a Zener diode metal structure formed on the dielectric layer and partially extending through the dielectric layer to electrically connect the P-type doped region and the N-type doped region of the Zener diode doping structure; wherein each of the Zener diodes is configured to receive a reverse bias when the power device is energized; Each of the Zener diode metal structures includes two metal pins spaced apart from each other and partially extending through the dielectric layer to electrically connect to and contact the N-type doped region and the P-type doped region of the Zener diode doping structure, respectively. When the power device is energized, the potential of the metal pin connected to the P-type doped region is lower than the potential of the metal pin connected to the N-type doped region, thereby generating the reverse bias voltage. Among any two adjacent Zener diodes connected in series, the metal pin of one of the Zener diodes connected to the P-type doping region is directly in contact with and electrically connected to the metal pin of the other Zener diode connected to the N-type doping region; and the Zener diode doping structure of one of the Zener diodes is not directly in contact with the Zener diode of the other Zener diode. Diode doping structure, The transistor is a bipolar junction transistor (BJT) and includes: an emitter-doped structure, a base-doped structure, a collector-doped structure, an emitter metal structure, and a collector metal structure; wherein the emitter-doped structure and the base-doped structure are both formed in the epitaxial layer, the inner side of the base-doped structure surrounds the emitter-doped structure, the outer side of the base-doped structure abuts the epitaxial layer, the upper surface of the emitter-doped structure and the upper surface of the base-doped structure are both flush with the upper surface of the epitaxial layer and are both covered by the insulating layer, the remaining portion of the epitaxial layer is defined as the collector-doped structure, the emitter metal structure is formed on the dielectric layer and partially penetrates the dielectric layer and the insulating layer to electrically connect the emitter-doped structure, and the collector metal structure is formed on the bottom surface of the base layer.

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