Multi-control quantum state inversion gate

Abstract

In a quantum circuit, a reversal gate is implemented to have two controls, each connected to a control qubit. In the quantum circuit, in response to determining that each control of the reversal gate is currently connected to a control qubit, an auxiliary gate is implemented, a first control of the auxiliary gate is connected to a control qubit moved from the first control of the reversal gate, a second control of the auxiliary gate is connected to a control qubit selected from the set of unplaced control qubits, and a target of the auxiliary gate is connected to the first control of the reversal gate. At a gate implemented in the quantum circuit, in response to determining that the gate has the maximum number of controls not connected to a control qubit, the control of the gate is connected to a control qubit selected from the set of unplaced control qubits.

Description

Technical Field

[0001] The present invention generally relates to methods, systems and computer program products for quantum programming. More specifically, the present invention relates to methods, systems and computer program products for multi-control quantum state inversion gates. Background Art

[0002] Molecules and subatomic particles obey the laws of quantum mechanics, the branch of physics that explores how the physical world works at the most fundamental level. At this level, particles behave in strange ways, assume more than one state at the same time, and interact with other particles that are very far away. Quantum computing exploits these quantum phenomena to process information.

[0003] The computers we use today are called classical computers (also referred to herein as "conventional" computers or conventional nodes, or "CNs"). Conventional computers use conventional processors, semiconductor memories, and magnetic or solid-state storage devices, manufactured using semiconductor materials and techniques, in the so-called Von Neumann architecture. Specifically, the processors in conventional computers are binary processors, i.e., they operate on binary data represented in 1s and 0s.

[0004] A quantum processor (q-processor) uses the odd properties of entangled quantum bit devices (compactly referred to herein as "qubits", multiple "qubits") to perform computing operations. In the specific field where quantum mechanics operates, material particles can exist in multiple states, such as an "on" state, an "off" state, and a simultaneous "on" and "off" state. When binary computing using semiconductors, processors are limited to using only on and off states (equivalent to 1 and 0 in binary code), quantum processors use these quantum states of matter to output signals that can be used in data computing. Here, qubits are physical carriers of quantum information. Qubits are the quantum version of bits in classical computing, and can have quantum states of |0>, |1>, or a linear combination of the two.

[0005] Quantum computing can often be used to solve problems faster than conventional computing. For example, one quantum algorithm is Grover search, which searches through an unordered list of N items using fewer lookups than would be possible in conventional computing.

[0006] Quantum gates are fundamental building blocks for quantum computing, acting on qubits the way classical logic gates act on bits one and two at a time to change the state of the qubit in a controllable way. An X-gate inverts the state of a single qubit, much like a non-gate inverts the state of a single bit in classical computing. An H-gate or Hadamard gate puts a single qubit in a superposition state, a combination of 0 and 1 quantum states. When measured, the qubit resolves to only one definite state. For example, when provided with an input having a quantum state of 0, within the Hadamard gate the quantum states are in superposition, but the output has a 50% probability of being in the quantum 0 state and a 50% probability of being in the quantum 1 state. Other single-qubit gates change the qubit state in other defined ways.

[0007] Multi-qubit gates implement gates that perform conditional logic between qubits, meaning that the state of one qubit depends on the state of another qubit. For example, a controlled NOT gate, or CNOT gate, has two qubit inputs, a target qubit and a control qubit. If the control qubit is in the |1> quantum state, the CNOT gate inverts the state of the target qubit. If the control qubit is in the |0> quantum state, the CNOT gate does not change the state of the target qubit.

[0008] Multiple qubits can also be entangled. This is when two or more qubits, despite being too far apart to influence each other, behave in individually random ways, but also in ways that are too strongly correlated to be explained by assuming each object is independent of the other. As a result, the combined properties of an entangled multi-qubit system can be predicted, but the individual results of measuring each individual qubit in such a system cannot be predicted.

[0009] Similar to conventional computing, quantum computing gates can be assembled into larger groups (called quantum circuits) to perform more complex operations. For example, a SWAP gate that swaps the states of a pair of qubits can be constructed from three CNOT gates.

[0010] A quantum circuit may execute some operations in parallel, and some operations in series. The length of the longest series in a program is also called the depth of the quantum circuit. For example, three CNOT gates including a SWAP gate are arranged in series, giving a depth of 3. Programs with shallower depths take less execution time and provide better performance, and are therefore preferred.

[0011] A multiple control inversion gate (also referred to herein as an inversion gate) is a generalization of a CNOT gate. A CNOT gate has one control qubit that controls the state of a target qubit. In contrast, a multiple control inversion gate has more than one control qubit. If all of the control qubits are in the |1> quantum state, the multiple control inversion gate inverts the state of the target qubit. If any of the control qubits is not in the |1> quantum state, the gate does not change the state of the target qubit. Multiple control inversion gates are also known as Toffoli gates. Inversion gates are key components in Grover's search and other useful quantum processing algorithms. Summary of the invention

[0012] Illustrative embodiments provide a method, system, and computer program product. Embodiments include a method that implements a reversal gate in a quantum circuit, the reversal gate configured to invert a quantum state of a target input if each control is in a |1> quantum state, the reversal gate having two controls, each of which is connected to a control qubit selected from a set of unplaced control qubits. Embodiments are implemented in the quantum circuit in response to determining that each control of the reversal gate is currently connected to a control qubit, a first auxiliary gate, the first auxiliary gate including a reversal gate, a first control of the first auxiliary gate connected to a control qubit moved from the first control of the reversal gate, a second control of the first auxiliary gate, the second control connected to a control qubit selected from the set of unplaced control qubits, and a target of the first auxiliary gate connected to the first control of the reversal gate. Embodiments connect the control of the gate to a control qubit selected from the set of unplaced control qubits at a gate implemented in the quantum circuit in response to determining that the gate has a maximum number of controls not connected to a control qubit.

[0013] Embodiments include a computer usable program product. A computer usable program product includes one or more computer readable storage devices and program instructions stored on at least one of the one or more storage devices.

[0014] Embodiments include a computer system comprising one or more processors, one or more computer-readable memories, and one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Certain novel features which are believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, as well as the preferred mode of use, further objects and advantages thereof, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings in which:

[0016] Figure 1 depicts a block diagram of a network of data processing systems in which the illustrative embodiments may be implemented;

[0017] Figure 2 depicts a block diagram of a conventional data processing system in which the illustrative embodiments may be implemented;

[0018] FIG3 depicts a prior art quantum circuit implementing multiple control inversion gates;

[0019] Figure 4 depicts a block diagram of an exemplary configuration of a multiple control quantum state inversion gate in accordance with an illustrative embodiment;

[0020] Figure 5 depicts an example of a dual-control symbol layout and a corresponding dual-control quantum circuit in accordance with an illustrative embodiment;

[0021] Figure 6 depicts an example of a three-control symbol layout and a corresponding three-control quantum circuit in accordance with an illustrative embodiment;

[0022] Figure 7 depicts an example of a four-control symbol layout and a corresponding four-control quantum circuit in accordance with an illustrative embodiment;

[0023] Figure 8 depicts another example of a four-control symbol layout and a corresponding four-control quantum circuit in accordance with an illustrative embodiment;

[0024] Fig. 9 depicts an implementation of a four-control quantum circuit according to an illustrative embodiment;

[0025] Fig.10 depicts another implementation of a four-control quantum circuit according to an illustrative embodiment;

[0026] Fig.11 depicts additional examples of symbol layouts according to illustrative embodiments;

[0027] Fig.12 depicts another example of a six-control symbol layout and a corresponding six-control quantum circuit in accordance with an illustrative embodiment;

[0028] Fig.13 depicts an implementation of a six-control quantum circuit according to an illustrative embodiment;

[0029] Fig.14 depicts additional examples of symbol layouts according to illustrative embodiments; and

[0030] Fig.15 A flow chart is depicted of an exemplary application of a multiple control quantum state inversion gate in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0031] The illustrative embodiments recognize that the currently used implementation of multiple control reversal gates in quantum circuits relies on decomposing multiple control gates into physically realizable single-qubit gates and two-qubit CNOT gates to create paired entangled interactions between the control qubits and the target. However, in currently used quantum processor architectures, not all qubits can interact with each other. As a result, implementing paired entangled interactions may require additional operations (such as SWAP gates) to move quantum signals from one qubit to another qubit. Additional operations add both additional gates and additional circuit depth to the resulting quantum circuit. However, quantum circuits with a larger number of gates and a higher depth generally take longer to execute on the same quantum processor than circuits with fewer gates and a smaller depth.

[0032] The illustrative embodiments also recognize that because current quantum processors do not include an error correction capability, qubit errors caused by circuit noise accumulate during circuit execution, where the errors increase with execution time. Thus, quantum circuits must have a small enough gate count and a small enough depth to complete execution before noise-induced qubit errors render the results unusable.

[0033] The currently used implementations and configurations of one or more Toffoli gates are used as some non-limiting examples to describe certain operations and functions of different embodiments. Based on this disclosure, a person of ordinary skill in the art will be able to adapt the embodiments to other similar proposed implementations or configurations, and such adaptations are contemplated within the scope of the illustrative embodiments.

[0034] For example, one currently available multi-control inversion gate implementation decomposes the gate into a series of dual-control Toffoli gates arranged in a V shape. The first part of the series (e.g., the left arm of the V) calculates partial products that are held as auxiliary (ancilla) qubits, which are then calculated into the desired product output. Ancillary qubits (plural ancillae) are qubits used to temporarily hold information, much like processor registers temporarily hold information in a classical processor. However, the entanglement of the ancillae has a final result. In order to obtain the correct result, this entanglement must be removed before measuring the final result. Therefore, the second part of the series (e.g., the right arm of the V) simulates or untangles the ancillae, removes the ancillae to their original state and allows the correct measurement of the desired final result. This implementation is arranged in series, where the calculation of each successive ancillae depends on the calculation result of the previous ancillae. The result is a deep quantum circuit. Circuit depth and series execution require additional execution time of the quantum circuit, thereby limiting the number of controls that can be used with this implementation.

[0035] Other current reversal gate implementations use no auxiliary qubits, or only one auxiliary qubit. However, such quantum circuit implementations are even deeper than the V-shaped implementation, and also limit the amount of control that can be done using this implementation.

[0036] Because inversion gates are key components in Grover searches and other useful quantum processing algorithms, the illustrative embodiments recognize that improving the efficiency of inversion gate implementations in quantum circuits also improves the efficiency of algorithms using such improved inversion gates. Furthermore, a quantum circuit that cannot be fully executed before uncorrected errors accumulate above a threshold does not produce usable results at all. Therefore, the illustrative embodiments recognize that what is needed in the art is a multiple control inversion gate implementation that is not executed in series and is less deep and uses fewer gates than currently used implementations.

[0037] The illustrative embodiments recognize that currently available tools or solutions do not address these needs or provide adequate solutions to these needs.The illustrative embodiments used to describe the present invention generally address and solve the above-mentioned problems and other problems associated with multiple control quantum state inversion gates.

[0038] Embodiments may be implemented as software applications. An application implementing an embodiment may be configured as a modification of an existing system that converts a logical representation of a quantum circuit into a form executable by a q-processor, as a separate application that runs in conjunction with such a conversion system, as a stand-alone application, or some combination thereof.

[0039] In particular, some demonstrative embodiments provide a method by which multiple controlled inversion gates are implemented in quantum circuits with improved performance relative to current implementations.

[0040] The H-tree layout helps to visualize the quantum circuit implementation of multi-controlled inversion gates. The H-tree layout depicts a binary tree in two dimensions. In particular, the H-tree represents the decomposition of the multi-controlled inversion gate into a configuration of dual-controlled or dual- and triple-controlled inversion gates. The central node of the H-tree represents the target of the multi-controlled inversion gate. The leaf nodes of the H-tree represent the control of the gate. The intermediate nodes of the H-tree represent auxiliary qubits used to implement the gate. The line segments connecting the H-tree nodes represent subtrees that can be implemented in one or more dual-controlled or dual- and triple-controlled inversion gates. For example, the H-tree layout ctc represents a dual-controlled inversion gate, where each "c" represents the control of the gate and "t" represents the target of the gate.

[0041] Due to the binary tree structure, any assistance (result of any subtree) can be executed in parallel instead of serially, reducing the circuit depth from linear (in the prior art V-shaped implementation) to square root depth.

[0042] An embodiment receives a specification of a multi-controlled inversion gate to be implemented in a quantum circuit. The specification specifies a set of control qubits and a target qubit for the inversion gate. The goal of this embodiment is to implement a specified multi-controlled inversion gate in a quantum circuit using a set of small inversion gates. As used herein, a small inversion gate has a number of control inputs that is less than the number of control inputs of the multi-controlled inversion gate being implemented. In one embodiment, each small inversion gate has two control inputs. In another embodiment, each small inversion gate has two or three control inputs. Thus, in order to implement the specified multi-controlled inversion gate, an embodiment uses auxiliary qubits, when necessary, to connect each of these specified control qubits to a control input of a small inversion gate.

[0043] In the constructed quantum circuit, one embodiment connects two of the set of control qubits and the target qubit to corresponding inputs of a dual control inversion gate.

[0044] An embodiment selects a control qubit from the set of control qubits that has not been connected to a control input of a small inversion gate. If there is no currently implemented small inversion gate with an unconnected input, additional assistance must be calculated. To calculate the additional assistance, an embodiment implements an additional small inversion gate in the quantum circuit. To implement a new gate, an embodiment moves a control input from a control input of a previously implemented gate to a control input of a new gate. The embodiment connects the control qubit to be placed at another control input of the new gate. The target of the new gate is the auxiliary gate, which now serves as the control input of the previously implemented gate, replacing the moved control input.

[0045] Conversely, if there are currently implemented small inversion gates with unconnected inputs, no additional assistance is needed yet. Instead, one embodiment determines the small inversion gate with the most control inputs that are not yet connected to a control qubit. If more than one small inversion gate has the same number of unconnected control inputs, an embodiment selects any gate using the numerical order of the gates, the reverse numerical order, a random or pseudo-random selection process, or another selection method. One embodiment connects the control qubit that needs to be placed to the unconnected control input of the selected gate.

[0046] One embodiment continues in this manner, connecting control qubits from the set of control qubits that require placement and optionally adding auxiliary qubits, until each control qubit in the set has been connected to an input of a small inversion gate in the quantum circuit. At this point, the first portion of the specified multiple control inversion gates is complete.

[0047] However, any auxiliary qubits in the circuit must still be unccomputed, i.e., unwrap from the target qubit that is the final result. Thus, one embodiment implements a mirrored small inversion gate in the quantum circuit after the small inversion gate that produces the target qubit. A mirrored small inversion gate has the same control and target qubits as the one to which the mirror corresponds. The mirrored small inversion gate is used to compute the auxiliary computed by the corresponding original gate. Another embodiment implements the computation gate while implementing the original gate, rather than waiting until the first portion of a specified multiple control inversion gates is complete.

[0048] Once both the original and parallel computation gates are implemented in the quantum circuit, the circuit is considered complete. The embodiment then replaces each small inversion gate in the circuit with an implementation of a small inversion gate that uses even smaller quantum circuit cells. One implementation of the small inversion gate uses SWAP and CNOT. A non-limiting example implementation of such a small inversion gate has two controls and ten CNOTs, involves a 2-qubit interaction between only one control and the target, and is also referred to as a dual-control conventional Toffoli gate or a dual-control true Toffoli gate.

[0049] Another embodiment of a small inversion gate does not use SWAP. A non-limiting example implementation of such a small inversion gate has two controls and three CNOTs, involving a 2-qubit interaction between only one control and the target, and is also referred to as a dual-control relative phase Toffoli gate. Another example implementation of such a small inversion gate has three controls and six CNOTs, involving a 2-qubit interaction between only the control and the target, and is also referred to as a triple-control relative phase Toffoli gate. The relative phase implementation of a small inversion gate cannot be used to calculate the target qubit of a multi-control inversion gate. However, the relative phase implementation can be used to calculate each of the eagle eagles. When significantly fewer CNOT gates can be used (e.g., 3 gates versus 10 gates for a conventional dual-control implementation), the relative phase implementation is used instead of the conventional implementation, and is therefore a more efficient circuit.

[0050] Another embodiment, instead of replacing each small inversion gate in the circuit with an implementation once the circuit is complete, replace each small inversion gate in the circuit with an implementation as the circuit is constructed. Other variations in the order of steps in the quantum circuit implementation are possible and are contemplated within the scope of the illustrative embodiments.

[0051] The manner in which multiple control quantum states are reversed gated as described herein is not available in currently available methods. A method of one embodiment described herein, when implemented to be executed on a device or data processing system, includes substantially advancing the functionality of a quantum circuit by generating a more optimized quantum circuit that produces the same result as the original result in a shorter time, has faster execution and uses fewer resources.

[0052] Merely by way of example, the illustrative embodiments are described with respect to certain types of quantum circuits, quantum gates, qubits, quantum processors, controls, targets, thresholds, constraints, operations, execution parameters, terminal standards, devices, data processing systems, environments, components, and applications. Any particular representation of these and other similar products is not intended to limit the invention. Any suitable representation of these and other similar products may be selected within the scope of the illustrative embodiments.

[0053] Furthermore, the illustrative embodiments may be implemented with respect to any type of data, data source, or access to a data source over a data network. Any type of data storage device may provide data to embodiments of the present invention locally at a data processing system or over a data network within the scope of the present invention. Where embodiments are described using a mobile device, any type of data storage device suitable for use with a mobile device may provide data to such embodiments locally at the mobile device or via a data network within the scope of the illustrative embodiments.

[0054] The illustrative embodiments are described only as examples using specific codes, designs, architectures, protocols, layouts, schematics, and tools, and the illustrative embodiments are not limited to the illustrative embodiments. In addition, for the sake of clarity of description, only specific software, tools, and data processing environments are used as examples to describe the illustrative embodiments in some instances. The illustrative embodiments can be used in conjunction with other comparable or similarly used structures, systems, applications, or architectures. For example, within the scope of the present invention, other similar mobile devices, structures, systems, applications, or their architectures can be used in conjunction with such embodiments of the present invention. The illustrative embodiments can be implemented in hardware, software, or a combination thereof.

[0055] The examples in this disclosure are only for clarity of description and are not limited to the illustrative embodiments. Additional data, operations, actions, operations, activities and manipulations can be imagined from this disclosure, and these additional data, operations, actions, activities and manipulations are contemplated within the scope of the illustrative embodiments.

[0056] Any advantages listed herein are examples only and are not intended to limit these illustrative embodiments. Additional or different advantages may be achieved by specific illustrative embodiments. In addition, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0057] With reference to the drawings, in particular to Figure 1 and 2 , these figures are exemplary diagrams of data processing environments in which illustrative embodiments may be implemented. Figure 1 and 2These are examples only and are not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Specific embodiments may make numerous modifications to the depicted environments based on the following description.

[0058] Figure 1 A block diagram of a network of data processing systems in which the illustrative embodiments may be implemented is depicted. Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium used to provide communication links between different devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0059] Client or server are merely example roles for certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles for these data processing systems. Server 104 and server 106 are coupled to network 102 along with storage device 108. Software applications may be executed on any computer in data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as servers 104 or 106 or clients 110, 112, or 114 may contain data and may have software applications or software tools executed thereon.

[0060] This is for example purposes only and does not imply any limitation on such architecture. Figure 1 Certain components that may be used in an example implementation of an embodiment are depicted. For example, servers 104 and 106 and clients 110, 112, 114 are depicted as servers and clients only as an example, without implying limitation to a client-server architecture. As another example, an embodiment may be distributed across several data processing systems and data networks as shown, while another embodiment may be implemented on a single data processing system within the scope of the illustrative embodiments. Data processing systems 104, 106, 110, 112, and 114 also represent example nodes in a cluster, partitions, and other configurations suitable for implementing an embodiment.

[0061] Device 132 is an example of a device described herein. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a fixed or portable form of client 110, a wearable computing device, or any other suitable device. Figure 1 Any software application executed in another data processing system in may be configured to execute in device 132 in a similar manner. Figure 1 Any data or information stored or generated in another data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0062] QCE140 is an example of a QCE described herein. For example, QCE140 includes CN104, 106 and many other similar CN142. As an example, CN106 and 142 can be configured as a cluster 144 of CNs. QCE140 further includes one or more QCNs, such as QCN146. A QCN (such as QCN146) includes one or more q processors 148. A currently feasible qubit is an instance of a q processor 148. Application 105 implements the embodiments described herein. Application 105 operates on a CN, such as server 104 in QCE140. Application 105 stores operation libraries, circuits, and metadata in storage device 108 or in any other suitable storage device.

[0063] QCE 140 may be coupled to network 102 using a wired connection, a wireless communication protocol, or other suitable data connection. Clients 110, 112, and 114 may be, for example, personal computers or network computers. Network 102 may represent a collection of networks and gateways that communicate with each other using Transmission Control Protocol / Internet Protocol (TCP / IP) and other protocols. Figure 1 This is intended as an example, and not as an architectural limitation for the different illustrative embodiments.

[0064] The data processing environment 100 as a whole may also take the form of a cloud and employ a cloud computing model of service delivery to enable convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be quickly provisioned and released with minimal management effort or interaction with a service provider.

[0065] See also Figure 2 , which depicts a block diagram of a conventional data processing system in which the illustrative embodiments may be implemented. Data processing system 200 is an example of a classical computer, such as Figure 1 Servers 104 and 106, or clients 110, 112, and 114, or another type of device in which computer usable program code or instructions implementing the processes may be located for use in the illustrative embodiments.

[0066] Data processing system 200 also represents a data processing system or configuration thereof, such as Figure 1 The computer program code or instructions for implementing the processes of the illustrative embodiments may be located in the server 104. Data processing system 200 is described as a computer only as an example and is not limited to this. Implementations in other device forms (such as Figure 1The server 104 in FIG. 1 may modify the data processing system 200 , such as by adding a touch interface, and even eliminating certain depicted components from the data processing system 200 , without departing from the general description of the operation and functionality of the data processing system 200 described herein.

[0067] In the depicted example, data processing system 200 employs a hub architecture including north bridge and memory controller hub (NB / MCH) 202 and south bridge and input / output (I / O) controller hub (SB / ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled to north bridge and memory controller hub (NB / MCH) 202. Processing unit 206 may include one or more processors and may be implemented using one or more heterogeneous processor systems. Processing unit 206 may be a multi-core processor. In some implementations, graphics processor 210 may be coupled to NB / MCH 202 via an accelerated graphics port (AGP).

[0068] In the depicted example, a local area network (LAN) adapter 212 is coupled to the south bridge and I / O controller hub (SB / ICH) 204. An audio adapter 216, a keyboard and mouse adapter 220, a modem 222, a read-only memory (ROM) 224, a universal serial bus (USB) and other ports 232, and a PCI / PCIe device 234 are coupled to the south bridge and I / O controller hub 204 via a bus 238. A hard disk drive (HDD) or solid state drive (SSD) 226 and a CD-ROM 230 are coupled to the south bridge and I / O controller hub 204 via a bus 240. The PCI / PCIe devices 234 may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not. ROM 224 may be, for example, a flash binary input / output system (BIOS). Hard disk drive 226 and CD-ROM 230 may use, for example, an integrated drive electronics (IDE), a serial advanced technology attachment (SATA) interface, or variations such as external SATA (eSATA) and micro SATA (mSATA). Super I / O (SIO) device 236 may be coupled to south bridge and I / O controller hub (SB / ICH) 204 via bus 238.

[0069] Memories such as main memory 208, ROM 224, or flash memory (not shown) are some examples of computer usable storage devices. Hard disk drives or solid state drives 226, CD-ROMs 230, and other similarly available devices are some examples of computer usable storage devices, including computer usable storage media.

[0070] An operating system runs on processing unit 206. The operating system coordinates and provides Figure 2 The operating system may be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices. Object-oriented or other types of programming systems may operate in conjunction with the operating system and provide calls to the operating system from programs or applications executing on data processing system 200.

[0071] for operating systems, object-oriented programming systems, and applications or programs such as Figure 1 205) are located on a storage device, such as in the form of code 226A on hard drive 226, and may be loaded into at least one of one or more memories, such as main memory 208, for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer-implemented instructions, which may be located in a memory, such as main memory 208, read-only memory 224, or one or more peripheral devices.

[0072] In addition, in one case, code 226A can be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another case, code 226A can be downloaded to remote system 201B via network 201A, where downloaded code 201C is stored on storage device 201D.

[0073] Figure 1-2 The hardware in may vary depending on the implementation. Figure 1-2 In addition to or in lieu of the hardware depicted Figure 1-2 In addition to the hardware depicted in the drawings, other internal hardware or peripheral devices may be used, such as flash memory, equivalent non-volatile memory, or optical disk drives, etc. In addition, the processes of the illustrative embodiments may be applied to a multi-processor data processing system.

[0074] In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA), which is typically configured with flash memory to provide non-volatile memory for storing operating system files and / or user-generated data. The bus system may include one or more buses, such as a system bus, an I / O bus, and a PCI bus. Of course, the bus system may be implemented using any type of communication structure or architecture that provides data transfer between different components or devices attached to the structure or architecture.

[0075] The communications unit may include one or more devices for sending and receiving data, such as a modem or a network adapter. A memory may be, for example, main memory 208 or a cache, such as that found in north bridge and memory controller hub 202. A processing unit may include one or more processors or CPUs.

[0076] Figure 1-2 The examples depicted in and above-described are not meant to imply architectural limitations. For example, data processing system 200 may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile or wearable device.

[0077] Where a computer or data processing system is depicted as a virtual machine, virtual device, or virtual component, the virtual machine, virtual device, or virtual component uses virtualized representations of some or all of the components depicted in data processing system 200 to operate in the manner of data processing system 200. For example, in the virtual machine, virtual device, or virtual component, processing unit 206 is represented as a virtualized instance of all or some number of hardware processing units 206 available in a host data processing system, main memory 208 is represented as a virtualized instance of all or some portion of main memory 208 available in the host data processing system, and disk 226 is represented as a virtualized instance of all or some portion of disk 226 available in the host data processing system. In this case, the host data processing system is represented by data processing system 200.

[0078] See Figure 3, which depicts a prior art quantum circuit implementing multiple control inversion gates. Circuit 300 can be Figure 1 Executed in QCE140 in .

[0079] Circuit 300 has six controls C1-C6 for controlling the state of target T. Circuit 300 also uses four auxiliary qubits (A1-A4), and circuit 300 includes a series of double control top gates arranged in a V shape. The first part of the series (the left arm of the V) uses C1-C6 to calculate A1-A4, which are a plurality of auxiliary qubits that hold partial products. The circuit then uses A1-A4 to calculate T, the desired product output. The second part of the series (the right arm of the V) calculates A1-A4, cleaving A1-A4 from T. This implementation is arranged in series, where each successive auxiliary result depends on the calculation of the previous auxiliary, resulting in a deep quantum circuit.

[0080] See also Figure 4 , which depicts a block diagram of an example configuration of a multi-control quantum state inversion gate according to an illustrative embodiment. Application 400 may be used at Figure 1Executed in any of the systems 104, 106, 110, 112, and 114 and the device 132 in.

[0081] Application 400 receives a specification of a multi-controlled inversion gate to be implemented in a quantum circuit. The specification specifies a set of control qubits and a target qubit for the inversion gate. The goal of application 400 is to implement the specified multi-controlled inversion gate in a quantum circuit using a set of small inversion gates.

[0082] In the constructed quantum circuit, the control connector module 420 connects two of the set of control qubits and the target qubit to corresponding input terminals of the dual control inversion gates.

[0083] The application 400 selects a control qubit from the set of control qubits that has not been connected to a control input of a small inversion gate. The empty control determination module 410 determines whether there is a currently implemented small inversion gate with an unconnected input. If there is no currently implemented small inversion gate with an unconnected input, additional assistance must be calculated. In order to calculate the additional assistance, the assistance implementation module 430 implements the additional small inversion gate in the quantum circuit. In order to implement a new gate, the module 430 moves a control input from the control input of the previously implemented gate to the control input of the new gate. The module 430 connects the control qubit to be placed at another control input of the new gate. The target of the new gate is the auxiliary gate, which is now used as the control input of the previously implemented gate, replacing the moved control input.

[0084] Conversely, if there are currently implemented small inversion gates with unconnected inputs, no additional assistance is needed yet. Instead, module 410 determines the small inversion gate with the most control inputs that are not yet connected to a control qubit. If more than one small inversion gate has the same number of unconnected control inputs, module 410 selects any gate using any suitable selection method. Module 420 connects the control qubit to be placed to an unconnected control input of the selected gate.

[0085] Application 400 continues in this manner, connecting control qubits from the set of control qubits that require placement and optionally adding a plurality of auxiliary qubits until each control qubit in the set has been connected to an input of a small inversion gate in the quantum circuit. In addition, for each auxiliary implemented, mirrored auxiliary module 440 implements a mirrored small inversion gate in the quantum circuit after the small inversion gate that produced the target qubit. Each original and mirrored small inversion gate has the same control and target qubits. The mirrored small inversion gate is used to compute the auxiliary computed by the corresponding original gate.

[0086] See also Figure 5 , which depicts an example of a dual control symbol layout and a corresponding dual control quantum circuit according to an illustrative embodiment. Figure 4 The application 400 in is used to implement the dual-control quantum circuit.

[0087] Dual control symbol layout 510 depicts a dual control layout where each "c" represents a control of a gate and "t" represents a target of the gate. Dual control symbol circuit 520 depicts a quantum circuit corresponding to layout 510. Circuit 520 includes a dual control inversion gate with controls C1 and C2 and a target T.

[0088] See also Figure 6 , which depicts an example of a three-control symbol layout and a corresponding three-control quantum circuit according to an illustrative embodiment. Figure 4 The application 400 in implements the three-control quantum circuit.

[0089] Three control symbol layout 610 depicts a three control layout where each "c" represents a control of a gate and "t" represents a target for the gate. Here, one of the controls of the two control symbol layout 510 has been replaced with "a" and an additional control, "a" representing an auxiliary qubit. Three control symbol circuit 620 depicts a quantum circuit corresponding to layout 610. Circuit 620 includes an additional control C3 and an additional auxiliary coil A1. Circuit 620 also includes a dual control inversion gate 622 with controls A1 and C3 and a target T. Gate 622 corresponds to region 612 of layout 610.

[0090] See also Figure 7 , which depicts an example of a four-control symbol layout and a corresponding four-control quantum circuit according to an illustrative embodiment. Figure 4 The application 400 in implements the four-control quantum circuit.

[0091] Four control symbol layout 710 depicts a four control layout where each "c" represents a control, each "a" represents an auxiliary qubit, and "t" represents the target of a gate. Here, one of the controls of three control symbol layout 610 has been replaced by an "a" and an additional control.

[0092] Four control symbol circuit 720 depicts a quantum circuit corresponding to layout 710. Circuit 720 includes an additional control C4 and an additional auxiliary controller A2. Circuit 720 also includes a dual control inversion gate 722 with controls A1 and A2 and target T. Gate 722 corresponds to region 712 of layout 710.

[0093] See also Figure 8 , which depicts another example of a four-control symbol layout and a corresponding four-control quantum circuit according to an illustrative embodiment. Figure 4 The application 400 in the embodiment of the present invention implements the four-control quantum circuit. The layout 710 and the circuit 720 are similar to Figure 7 The layout 710 and circuit 720 in are the same.

[0094] Circuit 720 also includes inversion gates 822 and 824. Each of inversion gates 822 and 824 is a dual control inversion gate with controls C3 and C4 and target A2. Gate 822 corresponds to region 812 of layout 710. Gate 824 is a mirror image of gate 822.

[0095] See also Fig. 9 , which depicts an implementation of a four-control quantum circuit according to an illustrative embodiment. Circuit 720 and gate 722 are Figure 7 The circuit 720 and gate 722 in are the same.

[0096] Circuit 720 includes a dual control inversion gate 722 with controls A1 and A2 and a target T. Gate 722 is an example of a small inversion gate that can be implemented using embodiment 930. In implementation 930 (as in other quantum circuits depicted herein), the plus sign in a circle with one input represents a CNOT, and the boxed H represents a Hadamard gate. The boxed T represents a quantum gate that applies a pi / 4 phase change to the qubit. The boxed T-dagger represents the conjugation of T (i.e., applying a pi / 4 phase change). Implementation 930 has two controls A1 and A2 and ten CNOTs, involves a 2-qubit interaction between only one control and the target, and is an example of a dual control conventional Toffoli gate.

[0097] See also Fig.10 , which depicts another implementation of a four-control quantum circuit according to an illustrative embodiment. Circuit 720 and Figure 7 The gate 822 is the same as the circuit 720 in FIG. Figure 8 The gate 822 in is the same.

[0098] Circuit 720 includes a dual control inversion gate 822 with controls C3 and C4 and target A2. Gate 822 is an example of a small inversion gate that can be implemented using implementation 1030 and can be used to compute each of a plurality of auxiliary qubits. Implementation 1030 has two controls C3 and C4 and only three CNOTs, involves a 2-qubit interaction between only one control and the target, and is an example of a dual control relative phase Toffoli gate.

[0099] See also Fig.11 , which depicts additional examples of symbol layouts according to an illustrative embodiment. Each symbol layout corresponds to a symbol that can be used Figure 4 The quantum circuit implemented in the application 400. The four control symbol layout 710 and Figure 7 The four control symbol layout 710 is the same.

[0100] Four-control symbol layout 710 depicts a four-control layout where each "c" represents a control, each "a" represents an auxiliary qubit, and a "t" represents a target for a gate. Here, one of the controls of three-control symbol layout 610 has been replaced by an auxiliary and additional control.

[0101] Six-control symbol layout 1120 depicts a six-control layout where each "c" represents a control, each "a" represents an auxiliary qubit, and a "t" represents a target for a gate. Here, two additional auxiliary and controls have been added, and two of the existing controls of the four-control symbol layout 710 are now input to the added auxiliary. The layout is also rotated relative to layout 710.

[0102] Eight control symbol layout 1130 depicts eight control inversion gates, where each "c" represents a control, each "a" represents an auxiliary qubit, and a "t" represents the target of the gate. Here, two additional auxiliary and controls have been added, and two of the existing controls of layout 1120 are now inputs to the added auxiliary.

[0103] N control symbol layout 1140 depicts an extension of layout 1130. Layout 1140 has N controls, with a corresponding plurality of auxiliary qubits and a target (not shown) at the center of the layout. Here, N can be any integer greater than 8. Application 400 can implement a corresponding quantum circuit of any depth executable on a quantum processor.

[0104] See also Fig.12 , which depicts another example of a six-control symbol layout and a corresponding six-control quantum circuit according to an illustrative embodiment. The six-control quantum circuit can be used Figure 4 The application 400 is implemented in the embodiment.

[0105] Layout 1212 depicts the symbolic layout of a multiple control inversion gate that can be implemented using a small inversion gate with three controls and a small inversion gate with two controls. Area 1212 depicts an auxiliary qubit A1 with three controls C1-C3.

[0106] Circuit 1220 includes inversion gates 1222 and 1224. Each of inversion gates 1222 and 1224 is a three-control inversion gate with controls C1, C2, and C3 and target A1. Gate 1222 corresponds to region 1212 of layout 1210. Gate 1224 is a mirror image of gate 1222.

[0107] See also Fig.13 , which depicts an implementation of a six-control quantum circuit according to an illustrative embodiment. Circuit 1220 and Fig.12 The gate 1222 is the same as the circuit 1220 in FIG. Fig.12 The gate 1222 in is the same.

[0108] Circuit 1220 includes a three-control inversion gate 1222 with controls C1, C2, and C3 and a target A1. Gate 1222 is an example of a small inversion gate that can be implemented using implementation 1330 and can be used to compute each of the plurality of auxiliary qubits. Implementation 1330 has three controls C1, C2, and C3, and only six CNOTs, involves a 2-qubit interaction between only one control and the target, and is an example of a three-control relative phase Toffoli gate.

[0109] See also Fig.14 , which depicts additional examples of symbol layouts according to an illustrative embodiment. Each symbol layout corresponds to a symbol that can be used Figure 4 The quantum circuit implemented in the application 400. The four control symbol layout 710 and Figure 7 The four control symbol layout 710 is the same.

[0110] Six control symbol layout 1410 depicts a six control layout where each "c" represents a control, each "a" represents an auxiliary qubit, and a "t" represents a target for a gate. Here, unlike six control layout 1120, each auxiliary qubit has three controls.

[0111] Twelve control symbol layout 1420 depicts a twelve control layout where each "c" represents a control, each "a" represents an auxiliary qubit, and a "t" represents a target for a gate. Here, four additional auxiliary qubits and six additional controls have been added, and four of the existing controls of the six control symbol layout 1410 are now input to the added auxiliary qubits. The layout is also rotated relative to layout 1410.

[0112] See also Fig.15 , which depicts a flow chart of an example application 1500 of a multi-control quantum state inversion gate according to an exemplary embodiment. Process 1500 may be performed at Figure 4 The application 400 is implemented in the embodiment.

[0113] In block 1502, the application receives a specification of a multi-control inversion gate having a set of n control qubits, where n can be any positive integer. In block 1504, the application implements the inversion gate having two controls in a quantum circuit, each of which is connected to a control qubit selected from the set of n control qubits. In block 1506, the application selects a control qubit that is not already connected to a gate in the quantum circuit. In block 1508, the application determines whether each gate control of all currently implemented gates is connected to a control qubit. If so ("yes" path of block 1508), in block 1510, the application implements an auxiliary gate in the quantum circuit, wherein the control of the auxiliary gate connected to the control qubit is moved from the currently connected gate control, a second control is connected to the selected control qubit, and the target replaces the moved control. If not ("No" path of block 1508), in block 1512, the application connects control of the gate already implemented in the quantum circuit to the selected control qubit. In block 1514, the application determines if there is another control qubit to place. If yes ("Yes" path of block 1514), the application returns to block 1506. If not ("No" path of block 1514), the application ends.

[0114] Thus, computer-implemented methods, systems or apparatus, and computer program products for multiple control quantum state inversion gates and other related features, functions or operations are provided in illustrative embodiments. Where embodiments or portions thereof are described with respect to one type of device, the computer-implemented methods, systems or apparatus, computer program products, or portions thereof are adapted or configured for use with appropriate and comparable representations of that type of device.

[0115] Where embodiments are described as being implemented in an application, delivery of the application in a Software as a Service (SaaS) model is contemplated within the scope of the illustrative embodiments. In the SaaS model, the ability to implement the application of the embodiments is provided to the user by executing the application in a cloud infrastructure. The user can access the application using a variety of client devices through a thin client interface such as a web browser (e.g., web-based email) or other lightweight client applications. The user does not manage or control the underlying cloud infrastructure including the network, servers, operating system, or storage of the cloud infrastructure. In some cases, the user may not even manage or control the capabilities of the SaaS application. In some other cases, the SaaS implementation of the application may allow for limited possible exceptions to user-specific application configuration settings.

[0116] The present invention may be a system, method and / or computer program product of any possible integrated technical detail level. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform aspects of the present invention.

[0117] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punch card) or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0118] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0119] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA)) may execute computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit so as to perform aspects of the present invention.

[0120] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0121] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine that, when executed by a processor of a computer or other programmable data processing apparatus, creates a device for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing apparatus, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored therein includes an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0122] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus that causes a series of operating steps to be performed on a computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0123] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to different embodiments of the present invention.To this end, each box in the flow chart or block diagram can represent a part of a module, segment or instruction, which includes one or more executable instructions for realizing the logical function of the specification.In some alternative embodiments, the function marked in the box may not occur in the order marked in the figure.For example, depending on the function involved, the two boxes shown in succession can actually be performed substantially at the same time, or these boxes can sometimes be performed in reverse order.It will also be noted that each box in the block diagram and / or flow chart and the combination of the boxes in the block diagram and / or flow chart can be realized by a system based on special-purpose hardware, and the system based on special-purpose hardware performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

Claims

1. A method comprising: implementing a reversal gate in the quantum circuit, the reversal gate being configured to invert the quantum state of the target input if each control is in the |1〉 quantum state, the reversal gate having two controls each connected to a control qubit selected from a set of unpopulated control qubits; In the quantum circuit, in response to determining that each control of the inversion gate is currently connected to a control qubit, implementing a first auxiliary gate, the first auxiliary gate comprising an inversion gate, a first control of the first auxiliary gate connected to a control qubit moved from the first control of the inversion gate, a second control of the first auxiliary gate, the second control connected to a control qubit selected from the set of unplaced control qubits, and a target of the first auxiliary gate connected to the first control of the inversion gate; as well as Connecting the control of the gate to a control qubit selected from the set of unpopulated control qubits at a gate implemented in the quantum circuit in response to determining that the gate has a maximum number of controls not connected to control qubits.

2. The method according to claim 1, further comprising: A mirror auxiliary gate is implemented in the quantum circuit, the mirror auxiliary gate having the same control and target as the first auxiliary gate, the mirror auxiliary gate being placed after the inversion gate.

3. The method according to any one of claims 1 to 2, wherein: The inversion gate includes a regular inversion gate.

4. The method according to claim 3, wherein: The regular inversion gate includes two controls.

5. The method according to claim 3, wherein: The regular inversion gate includes a SWAP and ten CNOTs.

6. The method according to any one of claims 1 to 2, wherein: The first auxiliary gate includes a regular inversion gate.

7. The method according to claim 6, wherein: The regular inversion gate includes two controls.

8. The method according to any one of claims 1 to 2, wherein: The first auxiliary gate includes oppositely-inverted gates.

9. The method according to claim 8, wherein: The opposing phase transfer gate includes two controls.

10. The method according to claim 8, wherein: The opposing phase transversion gate includes three CNOTs and no SWAP.

11. The method according to claim 8, wherein: The opposing phase transfer gate includes three controls.

12. The method according to claim 8, wherein: The opposing phase transversion gate includes six CNOTs and no SWAP.

13. A computer usable program product comprising one or more computer readable storage devices and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising: implementing program instructions for a reversal gate in a quantum circuit, the reversal gate being configured to invert the quantum state of a target input if each control is in a |1〉 quantum state, the reversal gate having two controls each connected to a control qubit selected from a set of unpopulated control qubits; program instructions to implement a first auxiliary gate in the quantum circuit in response to determining that each control of the inversion gate is currently connected to a control qubit, the first auxiliary gate comprising an inversion gate, a first control of the first auxiliary gate connected to a control qubit moved from the first control of the inversion gate, a second control of the first auxiliary gate, the second control connected to a control qubit selected from the set of unplaced control qubits, a target of the first auxiliary gate connected to the first control of the inversion gate; as well as Program instructions connect the control of the gate to a control qubit selected from the set of unpopulated control qubits at a gate implemented in the quantum circuit in response to determining that the gate has a maximum number of controls not connected to control qubits.

14. The computer usable program product of claim 13, wherein the inversion gate comprises a regular inversion gate.

15. The computer usable program product of claim 14, wherein: The regular inversion gate includes two controls.

16. A computer usable program product according to any one of claims 14 or 15, wherein: The regular reversal gate includes the SWAP and ten CNOT resource requirements for the first analysis operation.

17. A computer usable program product according to any one of claims 13 or 14, wherein: The first auxiliary gate includes a regular inversion gate.

18. A computer usable program product according to any one of claims 13 or 14, wherein the computer usable code is stored in a computer readable storage device in a data processing system, and wherein the computer usable code is transmitted from a remote data processing system over a network.

19. A computer usable program product according to any one of claims 13 or 14, wherein: The computer usable code is stored in a computer readable storage device in a server data processing system and wherein the computer usable code is downloaded over a network to a remote data processing system for use in a computer readable storage device associated with the remote data processing system.

20. A computer system comprising one or more processors, one or more computer-readable memories, and one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising: implementing program instructions for a reversal gate in a quantum circuit, the reversal gate being configured to invert the quantum state of a target input if each control is in a |1〉 quantum state, the reversal gate having two controls each connected to a control qubit selected from a set of unpopulated control qubits; program instructions to implement a first auxiliary gate in the quantum circuit in response to determining that each control of the reversal gate is currently connected to a control qubit, the first auxiliary gate comprising a reversal gate, a first control of the first auxiliary gate connected to a control qubit moved from the first control of the reversal gate, a second control of the first auxiliary gate, the second control connected to a control qubit selected from the set of unplaced control qubits, a target of the first auxiliary gate connected to the first control of the reversal gate; and Program instructions connect the control of the gate to a control qubit selected from the set of unpopulated control qubits at a gate implemented in the quantum circuit in response to determining that the gate has a maximum number of controls not connected to control qubits.

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