Error suppression compilation optimization method for quantum computer

Abstract

The invention relates to the technical field of quantum compilation, and discloses an error suppression compilation optimization method for a quantum computer, which comprises the following steps of: capturing a physical quantum gate operation error rate and a hardware topological structure of a quantum processor for executing a mapping task, and constructing a hardware feature matrix; capturing gate interaction attributes of a to-be-compiled quantum logic circuit, and constructing a circuit characteristic matrix; according to the constructed hardware feature matrix and circuit feature matrix, establishing a mapping scheme representation model and a corresponding overhead function; solving the overhead function by using a genetic algorithm, and searching a mapping scheme which minimizes the overhead function value under the condition of meeting the resource constraint of the quantum processor; applying the optimized mapping scheme to the quantum logic circuit to be compiled, and compiling and optimizing the quantum logic circuit to be compiled; according to the method, the problems of poor adaptability, insufficient error rate optimization and the like of a quantum bit allocation scheme in the prior art are solved, and low-error and reliable quantum circuit mapping processing is realized.

Description

Technical Field

[0001] The present invention relates to the field of quantum compilation technology, and in particular to an error suppression compilation optimization method for quantum computers. Background Art

[0002] Modern quantum systems are often classified as noisy intermediate-scale quantum (NISQ) devices because they are susceptible to quantum decoherence and noise. Unlike stable classical computing systems, quantum computers are extremely sensitive to various forms of error interference, which becomes more pronounced as the running time of quantum programs increases and the number of operations increases. This poses a huge challenge to maintaining the accuracy and reliability of quantum computing. Therefore, since existing quantum computers were not designed with noise and physical hardware limitations in mind, executing quantum programs on these quantum processors is a difficult task.

[0003] To solve this problem, quantum compilers play a key role by adjusting quantum circuits to adapt to real quantum devices, thereby improving fault tolerance. Among them, quantum mapping is a crucial step in the quantum compilation process, and its core goal is to map the logical qubits in the quantum circuit to the physical qubits in the quantum hardware. Since quantum hardware usually has a fixed topological structure, there are certain restrictions on the connection between physical qubits, and there are significant differences in the position and operation error rate of different physical qubits. Therefore, a reasonable quantum mapping strategy is of great significance to the execution efficiency and reliability of quantum computing. Quantum mapping not only directly affects the success rate of quantum programs, but also determines the size of the overhead in the subsequent compilation process. For example, in the initial mapping of qubits, if the number of additional gates required for the mismatch between the logical gates and the hardware topology can be effectively reduced, the accumulated errors and delays in the program operation can be reduced. In addition, by giving priority to physical qubits with lower error rates, the accuracy and robustness of quantum circuit operation can be further improved. Therefore, quantum mapping is an important link in improving quantum computing performance and making full use of existing hardware resources, laying the foundation for achieving efficient and low-error quantum computing.

[0004] With the development of technology, more and more quantum bit mapping methods have been proposed. These methods usually only focus on the basic mapping problems under the constraints of hardware topology, and fail to fully consider hardware errors, dynamic interactions between quantum bits, and diverse hardware characteristics during the mapping process. Most traditional mapping methods use fixed rules or simple heuristic algorithms. Although this method can solve some hardware constraint problems, it lacks sufficient adaptability to complex quantum circuits and diverse hardware environments. In addition, existing mapping algorithms usually rely too much on manually designed rules during the optimization process and lack autonomous optimization capabilities. This makes it difficult for the algorithm to achieve comprehensive performance improvements when facing new hardware architectures or complex circuits, ultimately affecting the running accuracy of quantum programs and the utilization efficiency of hardware resources.

[0005] Therefore, a qubit mapping method that can efficiently adapt to different quantum hardware topologies and error characteristics is needed to improve the reliability and flexibility of the mapping. The new mapping method should be able to dynamically analyze the qubit error rate and connectivity in the hardware environment, and optimize the initial mapping scheme in real time to reduce the insertion overhead and accumulated errors of additional gates. In addition, the mapping method must have stronger adaptability and be able to flexibly adjust strategies in different quantum circuits and hardware environments, thereby achieving a more efficient and accurate quantum program compilation process. Summary of the invention

[0006] The purpose of the present invention is to solve the above problems and to design an error suppression compilation optimization method for quantum computers to achieve a more efficient and reliable quantum program compilation process.

[0007] The present invention provides an error suppression compilation optimization method for a quantum computer, and the error suppression compilation optimization method for a quantum computer comprises: Capture the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task, and construct a hardware feature matrix; Capture the gate interaction properties of the quantum logic circuit to be compiled and construct the circuit feature matrix; According to the constructed hardware feature matrix and circuit feature matrix, a mapping scheme representation model and a corresponding cost function are established; The cost function is solved by using a genetic algorithm, and a mapping scheme that minimizes the cost function value is found under the condition that the resource constraints of the quantum processor are met; The optimized mapping scheme is applied to the quantum logic circuit to be compiled, and the compilation optimization is performed on the quantum logic circuit to be compiled.

[0008] Optionally, in a first implementation of the present invention, capturing the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task and constructing a hardware feature matrix includes: Identify the physical qubits in the quantum processor and construct a Hardware feature matrix , for the physical quantum bit And when the physical quantum bit The expected error rate of constructing a CNOT gate can be estimated as: ; in, Is connecting and For each connected relationship path on the path between Is the path Error rate on the hardware feature matrix and The value of is equal to , It is physical quantum bits, It is A physical quantum bit.

[0009] Optionally, in a second implementation of the present invention, capturing the gate interaction properties of the quantum logic circuit to be compiled and constructing a circuit feature matrix includes: Parse the quantum logic circuit to be compiled, traverse the parsed quantum logic circuit, and determine the logical quantum bits corresponding to each CNOT gate control bit and target bit and ; Construct a size of The circuit characteristic matrix , for each element of the circuit characteristic matrix , get the logical qubit and logical qubits The number of CNOT gates executed between .

[0010] Optionally, in a third implementation of the present invention, establishing a mapping scheme representation model and a corresponding cost function according to the constructed hardware feature matrix and circuit feature matrix includes: Defining Boolean variables , if and only if the logical qubit Mapped to physical qubits Previous time variable , otherwise there is ; For all logical bits and all physical bits, the overhead function of the mapping is completed for: ; Among them, the hardware feature matrix Represented in physical quantum bits and The expected error rate of the CNOT gate is constructed between Represented in logical qubits and The number of CNOT gates that need to be executed between Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a collection of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor.

[0011] Optionally, in a fourth implementation of the present invention, the Boolean variable and Used to judge logical qubits Whether it is mapped to a physical qubit , and logical qubits Whether it is mapped to a physical qubit ,The product of the hardware error rate and the number of circuit gates is included in the overhead cost calculation only when a logical qubit pair is mapped to the corresponding physical qubit pair.

[0012] Optionally, in a fifth implementation of the present invention, when calculating the overhead cost, double summation is performed. Traversing all possible logical qubit pairs and physical qubit pairs combination.

[0013] Optionally, in a sixth implementation of the present invention, solving the cost function by using a genetic algorithm to find a mapping scheme that minimizes the cost function value under the condition that the resource constraints of the quantum processor are satisfied includes: S1, representing the solution structure of the mapping scheme representation model as individuals of the genetic algorithm, and using the cost function of the mapping scheme representation model to calculate the fitness of each individual; S2. Generate an initial population and use the 2-opt operator of local nearest neighbor search to try to improve each individual in the population. The specific details are: starting from the first gene of the individual, cyclically exchange with adjacent genes. If the individual fitness is improved, the exchange is retained; S3, executing the following steps S4 to S8 in a loop until a specified iteration round is reached; S4, executing the following steps S5 to S6 in a loop until the number of offspring individuals is not less than the set value; S5. Execute the tournament strategy on the existing population to obtain the parent generation; S6, execute the elite crossover strategy on the parent generation, obtain new offspring individuals, and add them to the offspring population; S7. Update the individuals in the existing population according to the existing population and the new population; S8. When the optimal individual of the population has not been updated for a long time, disturb the existing population; S9. Return the optimal individual, whose chromosome arrangement is the optimal solution to the mapping optimization problem.

[0014] Optionally, in a seventh implementation of the present invention, executing the elite crossover strategy on the parent generation to obtain new offspring individuals and adding them to the offspring population includes: When two parents have identical genes at the same position, all identical genes are copied to the corresponding positions of the offspring; For the unassigned positions in the offspring, one is randomly and uniformly selected from the positional genes of the two parents for replication if there is no conflict with the genes in the offspring; For the still vacant positions, randomly select unused genes for allocation to obtain chromosomes for generating offspring, repeat the above operation to generate several offspring, and execute the bidding strategy among the offspring to select the best elite offspring.

[0015] Optionally, in an eighth implementation of the present invention, updating individuals in the existing population according to the existing population and the new population includes: Sort in descending order according to fitness, and select the first few individuals with the highest fitness as the new existing population.

[0016] Optionally, in a ninth implementation of the present invention, when the optimal individual of the population has not been updated for a long time, disturbing the existing population includes: Perform mutation operations on the chromosomes of each individual in the population, cut the gene from the specified cutting position, exchange the positions of the two gene fragments and splice them into a new gene.

[0017] Minimizing the accumulated error in quantum circuit operations is the core goal of the quantum bit mapping problem. Since the solution process of this problem is NP-hard, and the error characteristics, topological structure of quantum hardware and dynamic characteristics of quantum circuits may change at any time; compared with the prior art, the advantages of the present invention are: by capturing the physical quantum gate operation error rate and hardware topological structure of the quantum processor and other factors to construct a hardware feature matrix, by capturing the gate interaction properties of the quantum logic circuit to be compiled to construct a circuit feature matrix, according to the hardware feature matrix and the circuit feature matrix, the mapping task is remodeled into a mathematical optimization model based on the quadratic assignment problem to find a more reliable mapping strategy; in order to improve the optimization performance, the error rate of the physical quantum bit is modeled using an error model, and it is embedded in the mapping optimization process to dynamically adapt to different hardware topologies and error distributions. The proposed method is verified by experiments. The method can significantly reduce the impact of hardware errors on quantum circuits; it combines the global exploration ability of genetic algorithms and the individual development ability of local search strategies, and introduces an elite crossover strategy to effectively balance the inheritance of excellent characteristics and the maintenance of offspring diversity, and finally obtains the optimal mapping layout with the minimum error expectation. The quantum compilation decision is optimized according to the obtained optimal mapping layout, and the operational errors caused by hardware errors are reduced; the present invention solves the problems of poor adaptability of quantum bit allocation schemes and insufficient error rate optimization in the prior art, realizes low-error and reliable quantum circuit mapping processing, can fully adapt to the characteristic limitations of quantum hardware, and effectively meet the operation requirements of complex quantum circuits. At the same time, it realizes efficient mapping of quantum bits with lower overhead, and improves the overall performance and reliability of the quantum compilation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the following detailed description of the preferred embodiment.The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the invention.

[0019] Figure 1 is a flow chart of an error suppression compilation optimization method for quantum computers provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a topological structure of a quantum processor that needs to be compiled according to an embodiment of the present invention; Figure 3 is a schematic diagram of the overhead of the mapping solution under different numbers of CNOT gates provided by the embodiment of the present invention; Figure 4 It is a schematic diagram of the overall overhead of the mapping solution under 8 random circuits provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of the overall overhead of the mapping solution under 9 real circuit conditions provided by the embodiment of the present invention; Figure 6 It is a schematic diagram of the average gate overhead of the mapping scheme under 9 real circuit conditions provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0020] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 A flowchart of an error suppression compilation optimization method for a quantum computer provided by an embodiment of the present invention, the method specifically comprises the following steps: Step 101: Capture the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task, and construct a hardware feature matrix; In this embodiment, the physical quantum bits in the quantum processor are identified and a quantum computer with a size of Hardware feature matrix , for the physical quantum bit And when the physical quantum bit The expected error rate of constructing a CNOT gate can be estimated as: ; in, Is connecting and For each connected relationship path on the path between Is the path Error rate on the hardware feature matrix and The value of is equal to , It is physical quantum bits, It is A physical quantum bit.

[0022] Step 102: Capture the gate interaction properties of the quantum logic circuit to be compiled and construct a circuit feature matrix; In this embodiment, the quantum logic circuit to be compiled is parsed, and the parsed quantum logic circuit is traversed to determine the logical quantum bits corresponding to each CNOT gate control bit and target bit. and ; Construct a size of The circuit characteristic matrix , for each element of the circuit characteristic matrix , get the logical qubit and logical qubits The number of CNOT gates executed between .

[0023] Step 103: Establish a mapping scheme representation model and a corresponding cost function according to the constructed hardware feature matrix and circuit feature matrix; In this embodiment, define a Boolean variable , if and only if the logical qubit Mapped to physical qubits Previous time variable , otherwise there is ; For all logical bits and all physical bits, the overhead function of the mapping is completed for: ; Among them, the hardware feature matrix Represented in physical quantum bits and The expected error rate of the CNOT gate is constructed between Represented in logical qubits and The number of CNOT gates that need to be executed between Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a collection of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor; Boolean variable and Used to judge logical qubits Whether it is mapped to a physical qubit , and logical qubits Whether it is mapped to a physical qubit , the product of the hardware error rate and the number of circuit gates is included in the overhead cost calculation only when the logical qubit pair is mapped to the corresponding physical qubit pair; when calculating the overhead cost, the double summation Traversing all possible logical qubit pairs and physical qubit pairs combination.

[0024] Step 104: solving the cost function using a genetic algorithm, and finding a mapping solution that minimizes the cost function value while satisfying the resource constraints of the quantum processor; In this embodiment, the conditions of quantum processor resource constraints include quantum bit-related constraints, connection relationship constraints and operation resource constraints; quantity constraints: the number of physical quantum bits in a quantum processor is limited. For example, the number of quantum bits in many quantum processors currently ranges from dozens to hundreds. The mapping scheme needs to ensure that the logical quantum bits are reasonably mapped to these limited physical quantum bits and cannot exceed their quantity range; quality differences: the performance of different physical quantum bits varies, such as coherence time (the time to maintain a quantum state), decoherence rate (the rate of losing quantum coherence), error rate and other indicators are different; quantum bits with short coherence time cannot undertake long-term computing tasks, and quantum bits with high error rates need to be used with caution in key computing steps. These characteristics should be comprehensively considered during mapping; hardware topology constraints: quantum bits in quantum processors have specific connection methods and topological structures, such as two-dimensional grids, linear, etc.; two-bit gate operations (such as CNOT gates) can usually only be performed between quantum bits that are directly connected; the mapping scheme must follow this connection relationship to ensure that the gate operations between logical quantum bits can be realized on physical hardware, and avoid mapping logical quantum bits that need to interact frequently to physical quantum bits that are not directly connected. =Different coupling strengths: Even if there are connections between quantum bits, the coupling strengths between them may be different, affecting the fidelity and execution efficiency of gate operations. This factor needs to be considered during mapping, so that logic gate operations with high coupling strength requirements correspond to physical quantum bit pairs with appropriate coupling strengths. Gate operation error rate limit: Each physical quantum bit has a certain error rate when performing single-bit gate operations, two-bit gate operations, etc. To ensure the accuracy of the calculation results, the mapping scheme should try to assign logic gate operations to physical quantum bits with low error rates, or make the error accumulation of the overall operation within an acceptable range. Operation time limit: It takes a certain amount of time for quantum bits to perform gate operations, and different types of gate operations take different amounts of time. If the quantum logic circuit has strict requirements on the operation time (such as real-time computing scenarios), the mapping scheme should consider the operation time characteristics of the physical quantum bits, and reasonably arrange the logic gate operation sequence and mapping position to avoid calculation timeouts or task failures due to long operation time. In some quantum processor architectures, there are resource sharing mechanisms such as classical instrument sharing, and multiple quantum bits are connected to the same instrument and need to be time-division multiplexed. The mapping scheme should consider this resource sharing method to avoid the inability to execute operations due to resource conflicts.

[0025] In this embodiment, a hybrid genetic algorithm suitable for solving a mapping scheme with a minimum cost function value includes the following steps: S1, representing the solution structure of the mapping scheme representation model as individuals of the genetic algorithm, and using the cost function of the mapping scheme representation model to calculate the fitness of each individual; S2. Generate an initial population and use the 2-opt operator of local nearest neighbor search to try to improve each individual in the population. The specific details are: starting from the first gene of the individual, cyclically exchange with adjacent genes. If the individual fitness is improved, the exchange is retained; S3, executing the following steps S4 to S8 in a loop until a specified iteration round is reached; S4, executing the following steps S5 to S6 in a loop until the number of offspring individuals is not less than the set value; S5. Execute the tournament strategy on the existing population to obtain the parent generation; S6, execute the elite crossover strategy on the parent generation, obtain new offspring individuals, and add them to the offspring population; S7. Update the individuals in the existing population according to the existing population and the new population; S8. When the optimal individual of the population has not been updated for a long time, disturb the existing population; S9. Return the optimal individual, whose chromosome arrangement is the optimal solution to the mapping optimization problem.

[0026] The specific process of step S6 is as follows: when two parents have consistent genes at the same position, all consistent genes are copied to the corresponding positions of the offspring; for the unallocated positions in the offspring, one is randomly and uniformly selected from the positional genes of the two parents for copying without any gene conflict with the offspring; for the still vacant positions, an unused gene is randomly selected for allocation to obtain the chromosomes for generating the offspring, the above operations are repeated to generate several offspring, and a bidding competition strategy is executed among the offspring to select the best elite offspring.

[0027] The specific process of step S7 is: sorting in descending order according to fitness, and selecting the first several individuals with the highest fitness as the new existing population; The specific process of step S8 is: perform mutation operation on the chromosome of each individual in the population, cut the gene from the specified cutting position, exchange the positions of the two gene fragments and splice them into a new gene.

[0028] Step 105: Apply the optimized mapping scheme to the quantum logic circuit to be compiled, and perform compilation optimization on the quantum logic circuit to be compiled.

[0029] The performance of the experimental platform used in the embodiment of the present invention is as follows: AMD Ryzen 7 5800H CPU, 16GB memory, and the software environment is Windows 10, Python 3.7.

[0030] In order to verify the mapping capability of the compilation optimization algorithm proposed in this invention for different circuits, mapping tests were performed on randomly generated circuit data sets and real quantum circuit data sets. The 7-qubit processor IBM_Nairobi was selected as the quantum processor to be compiled. Its architecture topology is shown in the figure below. Figure 2 As shown; the expected error overhead generated by the mapping layout is used as the key indicator for the performance evaluation of this experiment; through experimental tests, we compare the expected error overhead of the compilation optimization method of the present invention with algorithms such as trivial, dense and sabre under different environment settings.

[0031] Figure 3 The mapping performance of all mapping algorithms on circuits with different numbers of CNOT gates is compared. Figure 3 "Different Gates" means different numbers of CNOT gates, "Overhead" means overhead, "trivial", "dense" and "sabre" are three benchmark algorithms for comparison, and "QHGA" is the method of this embodiment; we randomly generate quantum circuits with 15 to 150 CNOT gates for testing. In order to eliminate the contingency caused by the random distribution of CNOT gates in the circuit as much as possible, the test is repeated 3 times at each quantum gate scale. The final result is the average of these repetitions. It can be observed that the overall prediction trend of the four layouts under different numbers of quantum gates is basically the same, that is, the circuit error overhead increases linearly with the increase in the number of CNOT gates. The three benchmark mapping methods have similar overheads, and the compilation optimization method proposed in the present invention always shows the best performance among the compared methods. On average, the overhead is reduced by 13.3% compared with other mapping algorithms. And when we increase the number of CNOT gates in the test circuit, it can still be predicted well.

[0032] Figure 4 Eight random circuit sets were generated, each containing five circuits with the same number of two-qubit gates. Figure 4"Different Random Circuits" means different random circuits, "Overhead" means overhead, and the subgraph annotation indicates the number of CNOT gates owned by the circuit, for example, "(a) 112 gates" means that the circuit in the random circuit set has 112 CNOT gates; the figure lists the performance comparison of the compilation optimization method proposed by the present invention and the three benchmark mapping methods on 8 different numbers of two-qubit gates, where each subgraph is the overall overhead generated by all random circuits in the corresponding data set. Observing the experimental results, it can be found that the other three benchmark mapping methods all have obvious fluctuations in predicted performance at the same scale of the number of two-qubit gates, which shows that it is difficult for them to make targeted adjustments according to changes in circuit design. In contrast, the compilation optimization method proposed by the present invention has achieved the best performance in all subgraphs and maintained good stability at each scale. Regardless of how the number and arrangement of two-qubit gates in the quantum circuit change, the mapping layout generated by the compilation optimization method proposed by the present invention always maintains significantly less error overhead than the benchmark method.

[0033] Figure 5 The present invention selects 9 7-qubit circuits with different numbers of two-qubit gates for testing, and compares the overall error overhead of each circuit using different mapping methods. Figure 5 "DifferentCircuits" means different circuits, and "Overhead" means overhead; due to the large differences in circuit characteristics in the data set, the average performance of the mapping method fluctuates greatly. In circuits with more CNOT gates, the overhead differences caused by different mapping methods are more significant. It can be seen that the compilation optimization method proposed in the present invention still shows significant superiority, and its average overhead is far lower than the other three mapping methods. At the same time, the compilation optimization method proposed in the present invention significantly reduces the error overhead caused by the mapping method in most real circuits, and even in the worst case, it has achieved performance comparable to that of the suboptimal compilation optimization method. In the entire data set, the compilation optimization method proposed in the present invention relatively reduced the overhead by 23.6%.

[0034] Figure 6 The present invention selects 9 7-qubit circuits with different numbers of two-qubit gates for testing, and compares the average gate error overhead of each circuit using different compilation optimization methods. Figure 6"Different Circuits" means different circuits, and "Overhead" means overhead; by dividing the total overhead by the number of CNOT gates in the circuit, we can focus on the mapping performance of different compilation optimization methods for circuits with different gate arrangement characteristics. The comparison results show that no benchmark method can adapt well to the differences in circuit characteristics, which is reflected in the fact that no benchmark method can always outperform other benchmark methods. In contrast, the compilation optimization method proposed in the present invention shows excellent performance in each circuit test case and always maintains a low average gate overhead.

[0035] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An error suppression compilation optimization method for quantum computers, characterized in that: The error suppression compilation optimization method for quantum computers comprises: Capture the physical quantum gate operation error rate and hardware topology of the quantum processor that performs the mapping task, and construct a hardware feature matrix; Capture the gate interaction properties of the quantum logic circuit to be compiled and construct the circuit feature matrix; According to the constructed hardware feature matrix and circuit feature matrix, a mapping scheme representation model and a corresponding cost function are established; The cost function is solved by using a genetic algorithm, and a mapping scheme that minimizes the cost function value is found under the condition that the resource constraints of the quantum processor are met; The optimized mapping scheme is applied to the quantum logic circuit to be compiled, and the compilation optimization is performed on the quantum logic circuit to be compiled.

2. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The capturing of the physical quantum gate operation error rate and the hardware topology of the quantum processor performing the mapping task and the construction of the hardware feature matrix include: Identify the physical qubits in the quantum processor and construct a Hardware feature matrix , for the physical quantum bit And when the physical quantum bit The expected error rate of constructing a CNOT gate can be estimated as: ； in, Is connecting and For each connected relationship path on the path between Is the path Error rate on the hardware feature matrix and The value of is equal to , It is physical quantum bits, It is A physical quantum bit.

3. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The capturing of the gate interaction properties of the quantum logic circuit to be compiled and the construction of the circuit feature matrix include: Parse the quantum logic circuit to be compiled, traverse the parsed quantum logic circuit, and determine the logical quantum bits corresponding to each CNOT gate control bit and target bit and ; Construct a size of The circuit characteristic matrix , for each element of the circuit characteristic matrix , get the logical qubit and logical qubits The number of CNOT gates executed between .

4. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The step of establishing a mapping scheme representation model and a corresponding cost function according to the constructed hardware feature matrix and circuit feature matrix includes: Defining Boolean variables , if and only if the logical qubit Mapped to physical qubits Previous time variable , otherwise there is ; For all logical bits and all physical bits, the overhead function of the mapping is completed for: ； Among them, the hardware feature matrix Represented in physical quantum bits and The expected error rate of the CNOT gate is constructed between Represented in logical qubits and The number of CNOT gates that need to be executed between Represents a set of logical qubits, including all logical qubits in the quantum logic circuit to be compiled; Represents a collection of physical quantum bits, including the physical quantum bits that actually exist in the quantum processor.

5. The error suppression compilation optimization method for quantum computers according to claim 4, characterized in that: Boolean variables and Used to judge logical qubits Whether it is mapped to a physical qubit , and logical qubits Whether it is mapped to a physical qubit ,The product of the hardware error rate and the number of circuit gates is included in the overhead cost calculation only when a logical qubit pair is mapped to the corresponding physical qubit pair.

6. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: When calculating overhead costs, double sum Traversing all possible logical qubit pairs and physical qubit pairs combination.

7. The error suppression compilation optimization method for quantum computers according to claim 1, characterized in that: The method of solving the cost function by using a genetic algorithm and finding a mapping scheme that minimizes the cost function value under the condition of satisfying the resource constraints of the quantum processor includes: S1, representing the solution structure of the mapping scheme representation model as individuals of the genetic algorithm, and using the cost function of the mapping scheme representation model to calculate the fitness of each individual; S2. Generate an initial population and use the 2-opt operator of local nearest neighbor search to try to improve each individual in the population. The specific details are: starting from the first gene of the individual, cyclically exchange with adjacent genes. If the individual fitness is improved, the exchange is retained; S3, executing the following steps S4 to S8 in a loop until a specified iteration round is reached; S4, executing the following steps S5 to S6 in a loop until the number of offspring individuals is not less than the set value; S5. Execute the tournament strategy on the existing population to obtain the parent generation; S6, execute the elite crossover strategy on the parent generation, obtain new offspring individuals, and add them to the offspring population; S7. Update the individuals in the existing population according to the existing population and the new population; S8. When the optimal individual of the population has not been updated for a long time, disturb the existing population; S9. Return the optimal individual, whose chromosome arrangement is the optimal solution to the mapping optimization problem.

8. The error suppression compilation optimization method for quantum computers according to claim 7, characterized in that: The method of executing the elite crossover strategy on the parent generation to obtain new offspring individuals and add them to the offspring population includes: When two parents have identical genes at the same position, all identical genes are copied to the corresponding positions of the offspring; For the unassigned positions in the offspring, one is randomly and uniformly selected from the positional genes of the two parents for replication if there is no conflict with the genes in the offspring; For the still vacant positions, randomly select unused genes for allocation to obtain chromosomes for generating offspring, repeat the above operation to generate several offspring, and execute the bidding strategy among the offspring to select the best elite offspring.

9. The error suppression compilation optimization method for quantum computers according to claim 7, characterized in that: The step of updating individuals in the existing population according to the existing population and the new population comprises: Sort in descending order according to fitness, and select the first few individuals with the highest fitness as the new existing population.

10. The error suppression compilation optimization method for quantum computers according to claim 7, characterized in that: When the optimal individual of the population has not been updated for a long time, the existing population is disturbed, including: Perform mutation operations on the chromosomes of each individual in the population, cut the gene from the specified cutting position, exchange the positions of the two gene fragments and splice them into a new gene.

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