Display device

Abstract

A display device is provided. The display device includes a pixel unit including a pixel connected to a data line, a data driver providing a sensing reference voltage to the data line during a sensing period and providing a data signal to the data line during a display period, and a sensing unit receiving a sensing current corresponding to the sensing reference voltage during the sensing period and generating correction data based on the provided sensing current. The sensing unit includes a current integrator outputting a sensing voltage based on the sensing current input to the current integrator through a first input terminal and based on the sensing reference voltage input to the current integrator through a second input terminal.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2020-0061889, filed on May 22, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure generally relates to display devices. Background Art

[0003] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0004] Among display devices, organic light emitting display devices use organic light emitting diodes (OLEDs) to display images. OLEDs generate light through the recombination of electrons and holes. OLEDs have a high response speed and can be driven with low power consumption.

[0005] An organic light-emitting display device may include pixels connected to data lines and scan lines. Each pixel typically includes an organic light-emitting diode (OLED) and a drive transistor for controlling the amount of current flowing through the OLED. When current is supplied from the drive transistor to the OLED, the pixel generates light having a predetermined brightness corresponding to the data signal. Summary of the Invention

[0006] In an organic light-emitting display device, each pixel containing a light-emitting diode may degrade. For example, the light-emitting diode in a pixel may degrade, or the threshold voltage and mobility of the driving transistor may change over time. Therefore, a technique for sensing characteristic information of a pixel (i.e., the driving transistor and light-emitting diode) through an external sensing circuit can be used to compensate for pixel degradation.

[0007] When sensing characteristic information of a pixel, a data signal from a data driver may be applied to the pixel unit, and the sensing unit may receive a current corresponding to the data signal from the pixel unit and output a sensing voltage corresponding to the current.

[0008] However, when the voltage of the applied data signal and the sensing reference voltage applied to the sensing unit are different from each other, a capacitive coupling phenomenon may occur in the pixel unit, and thus the sensing unit may output a sensing voltage that does not correspond to the applied data signal.

[0009] Embodiments provide a display device in which an accurate sensing voltage corresponding to a data signal is generated at the time of sensing.

[0010] According to an embodiment of the present disclosure, a display device includes: a pixel unit including pixels connected to data lines; a data driver that provides a sensing reference voltage to the data lines during a sensing period and provides a data signal to the data lines during a display period; and a sensing unit that receives a sensing current corresponding to the sensing reference voltage during the sensing period and generates correction data based on the provided sensing current. In this embodiment, the sensing unit includes a current integrator that outputs a sensing voltage based on a sensing current input to the current integrator via a first input terminal and a sensing reference voltage input to the current integrator via a second input terminal.

[0011] In an embodiment, the current integrator may include: a current integrating amplifier including a first input terminal and a second input terminal; and an integrating capacitor including one terminal connected to the first input terminal and the other terminal connected to an output terminal of the current integrating amplifier.

[0012] In an embodiment, the sensing unit may further include an initialization switch including one end connected to the first input end and the other end connected to the output end of the current integrating amplifier.

[0013] In an embodiment, the data driver may include a buffer including a buffer amplifier that provides a sensing reference voltage or a data signal to a data output line.

[0014] In an embodiment, the second input terminal of the current integrating amplifier may be connected to the a-th node through a connection line, and the a-th node is connected to the output terminal of the buffer.

[0015] In an embodiment, the b-th node connected to the data line may be connected between the a-th node and the first input terminal of the current integrating amplifier. In this embodiment, the sensing unit may further include a first switch connected between the a-th node and the b-th node and a second switch connected between the b-th node and the first input terminal of the current integrating amplifier.

[0016] In an embodiment, when a sensing reference voltage is supplied to the pixel, the first switch may be turned on, and when a sensing current is supplied to the sensing unit, the second switch may be turned on.

[0017] In an embodiment, the sensing unit may further include a third switch connected between the a-th node and the second input terminal of the current integrating amplifier, the third switch being provided in the connection line and being turned on when the sensing current is supplied to the sensing unit.

[0018] In an embodiment, the sensing unit may further include a reference voltage storage capacitor connected between the a-th node and the ground terminal, the reference voltage storage capacitor being provided in the connection line.

[0019] In an embodiment, the sensing unit may further include: a fourth switch including one end connected to the a-th node and the other end connected to the ground; and a fifth switch connected between one end of the reference voltage storage capacitor connected to the a-th node and the second input terminal of the current integrating amplifier.

[0020] In an embodiment, the fourth switch may be turned on in a predetermined period before the sensing reference voltage is supplied to the pixel, and the fifth switch may be turned on when the sensing current is supplied to the sensing unit.

[0021] In an embodiment, the sensing unit may further include a sixth switch connected between the a-th node and one end of the reference voltage storage capacitor connected to the connection line.

[0022] In an embodiment, the sixth switch may be turned on when the sensing reference voltage is supplied to the pixel.

[0023] In an embodiment, the sensing unit may generate compensation data based on the sensing voltage, the compensation data including degradation information of the pixel.

[0024] In an embodiment, the display device may further include a timing controller configured to receive first image data from the outside and provide second image data obtained by adding the first image data and the compensation data to the data driver.

[0025] In an embodiment, the sensing unit may further include an analog-to-digital converter connected between an output terminal of the current integrating amplifier of the current integrator and the timing controller, wherein the analog-to-digital converter may convert the sensing voltage from an analog form to a digital form.

[0026] In an embodiment, the pixel may be connected to a first scan line, a second scan line, and an emission control line. In this embodiment, the pixel may include: a light emitting diode connected to a second power supply; a first transistor including a first electrode connected to a first node electrically connected to the first power supply, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the second node, wherein the gate electrode of the second transistor may be connected to the first scan line; and a third transistor connected between the third node and the third power supply, wherein the gate electrode of the third transistor may be connected to the second scan line.

[0027] In an embodiment, the pixel may further include a fourth transistor connected between the first power source and the first node, wherein a gate electrode of the fourth transistor may be connected to the emission control line.

[0028] In an embodiment, the pixel may further include a storage capacitor connected between the second node and the third node.

[0029] In an embodiment, the second transistor and the third transistor may be turned on when a sensing reference voltage or a data signal is supplied to the pixel.

[0030] In an embodiment, the second transistor and the fourth transistor may be turned on when the sensing current is supplied to the sensing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will become more apparent by describing in further detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0033] Figure 2A and Figure 2B It shows Figure 1 A circuit diagram of an embodiment of a pixel included in a display device shown in FIG;

[0034] Figure 3 It shows Figure 1 FIGURE 1 shows an embodiment of a data driver as shown in FIGURE 2;

[0035] Figure 4 The embodiment according to the present disclosure is shown Figure 1 FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG.

[0036] Figure 5 and Figure 6 is shown during the sensing period Figure 1 ; A diagram showing the operation of the timing controller, data driver, sensing unit, and pixel shown in FIG;

[0037] Figure 7 is provided during the sensing period according to an embodiment of the present disclosure Figure 1 ; A timing diagram of control signals of the timing controller, data driver, sensing unit and pixel shown in ;

[0038] Figure 8 is a diagram showing a coupling phenomenon occurring due to parasitic capacitors;

[0039] Figure 9A and Figure 9B is a graph showing a capacitive coupling phenomenon occurring in a pixel during sensing and its effects;

[0040] Figure 10 is an illustration of an alternative embodiment according to the present disclosure Figure 1 FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG.

[0041] Figure 11 is provided to during the sensing period according to an alternative embodiment of the present disclosure Figure 1 ; A timing diagram of control signals of the timing controller, data driver, sensing unit and pixel shown in ;

[0042] Figure 12 Another alternative embodiment of the present disclosure is shown. Figure 1 FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG.

[0043] Figure 13 is provided during the sensing period according to another alternative embodiment of the present disclosure Figure 1 ; A timing diagram of control signals of the timing controller, data driver, sensing unit and pixel shown in ;

[0044] Figure 14 Another alternative embodiment of the present disclosure is shown. Figure 1 A diagram of a connection structure of a timing controller, a data driver, a sensing unit, and a pixel shown in FIG; and

[0045] Figure 15 is provided during the sensing period according to another alternative embodiment of the present disclosure Figure 1 1 is a timing diagram of control signals for the timing controller, data driver, sensing unit, and pixel shown in FIG. DETAILED DESCRIPTION

[0046] The present invention will now be described more fully below with reference to the accompanying drawings showing various embodiments. However, the present invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals throughout refer to like elements.

[0047] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0048] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0049] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, “a”, “an”, “the” and “at least one” do not represent a limitation on quantity and are intended to include both the singular and the plural, except where the context clearly indicates otherwise. For example, “element” and “at least one element” have the same meaning, except where the context clearly indicates otherwise. “At least one” should not be interpreted as limiting “one” or “an”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that the terms “comprise” and / or “comprising”, or “include” and / or “including”, when used in this specification, indicate the presence of the features, regions, integers, steps, operations, elements and / or components mentioned, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0050] Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of a device in addition to the orientation depicted in the figures. For example, if the device in one figure is flipped, an element described as being "below" the other elements would then be oriented "above" the other elements. Thus, depending on the particular orientation of the figure, the term "lower" can encompass both "lower" and "upper" orientations. Similarly, if the device in one figure is flipped, an element described as being "below" or "beneath" the other elements would then be oriented "above" the other elements. Thus, the terms "below" or "below" can encompass both "above" and "below" orientations.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0052] The embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners shown may be rounded. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0055] refer to Figure 1 , an embodiment of a display device 1000 may include a pixel unit 100 , a scan driver 200 , a data driver 300 , a sensing unit 400 , an emission control driver 500 , and a timing controller 600 .

[0056] The display device 1000 may be a flat panel display device, a flexible display device, a curved display device, a foldable display device, or a bendable display device. In embodiments, the display device 1000 may be a transparent display device, a head-mounted display device, a wearable display device, or the like. In embodiments, the display device 1000 may be applied to various electronic devices such as smartphones, tablet personal computers ("PCs"), smart tablets, televisions ("TVs"), and monitors.

[0057] In an embodiment, the display device 1000 may be implemented as an organic light-emitting display device, a liquid crystal display device, etc. However, these are merely exemplary, and the configuration of the display device 1000 is not limited thereto. In one embodiment, for example, the display device 1000 may be a self-luminous display device including an inorganic light-emitting diode.

[0058] In an embodiment, the display device 1000 may be driven in a display period for displaying an image and a sensing period for sensing characteristics of a driving transistor included in each pixel PX.

[0059] The pixel unit 100 includes pixels PX, which are connected to data lines DL1 to DLm (m is a natural number), first scan lines SL11 to SL1n (n is a natural number), second scan lines SL21 to SL2n, and emission control lines EML1 to EMLn. A first power supply VDD, a second power supply VSS, and a third power supply (or initialization power supply) VINT can be externally supplied to the pixels PX. In an embodiment, the first power supply VDD can determine the voltage of the first electrode of the driving transistor (e.g., the drain voltage), and the second power supply VSS can determine the cathode voltage of the light-emitting diode.

[0060] Figure 1 An embodiment including n first scan lines SL11 to SL1n, n second scan lines SL21 to SL2n, and n emission control lines EML1 to EMLn is shown, but the present disclosure is not limited thereto. In the embodiment, the number of scan lines, the number of emission control lines, etc. may be variously modified based on the circuit structure of the pixel PX.

[0061] The timing controller 600 may generate a data drive control signal DCS and a scan drive control signal SCS based on a synchronization signal provided from the outside. The data drive control signal DCS generated by the timing controller 600 may be provided to the data driver 300, and the scan drive control signal SCS generated by the timing controller 600 may be provided to the scan driver 200.

[0062] In an embodiment, the timing controller 600 may provide second image data DATA2 generated by compensating the first image data DATA1 to the data driver 300. The first image data DATA1 and the compensated second image data DATA2 may include grayscale information included in a grayscale range set in the display device.

[0063] The data drive control signal DCS may include a source start signal and a clock signal. The source start signal may control the start time of data sampling. The clock signal may control the sampling operation.

[0064] The scan drive control signal SCS may include a scan start signal, a control start signal, and a clock signal. The scan start signal may control the timing of the scan signal. The control start signal may control the timing of the control signal. The scan start signal and / or the control start signal may be offset based on the clock signal.

[0065] The timing controller 600 may control the operation of the sensing unit 400 through the sensing control signal TCS. In one embodiment, for example, the timing controller 600 may control the timing of providing a data signal for sensing to the pixel PX through the data lines DL1 to DLm and the timing of sensing a current generated in the pixel PX through the data lines DL1 to DLm.

[0066] The scan driver 200 may receive a scan driving control signal SCS from the timing controller 600. The scan driver 200 receiving the scan driving control signal SCS may provide first and second scan signals to the first and second scan lines SL11 to SL1n and SL21 to SL2n.

[0067] In an embodiment, the scan driver 200 may sequentially supply scan signals to the first scan lines SL11 to SL1n and the second scan lines SL21 to SL2n. When the scan signals are sequentially supplied to the first scan lines SL11 to SL1n and the second scan lines SL21 to SL2n, the pixels PX may be selected in units of horizontal lines. In an embodiment, the first scan signal and the second scan signal may be set to have a gate-on voltage (e.g., a logic high level) when a transistor included in the pixel PX is turned on.

[0068] The emission control driver 500 can sequentially provide emission control signals to the pixels PX through the emission control lines EML1 to EMLn based on the emission drive control signal EMCS. The emission control driver 500 receives the emission drive control signal EMCS, a clock signal, and the like from the timing controller 600. For pixels located in the same horizontal line (the same pixel row), the emission control signal can divide one frame period into an emission period and a non-emission period.

[0069] In an embodiment, Figure 1 As shown in FIG, a single scan driver 200 outputs a first scan signal and a second scan signal, however, the present disclosure is not limited thereto. In an alternative embodiment, for example, the scan driver 200 may include a first scan driver that provides the first scan signal to the pixel unit 100, and a second scan driver that provides the second scan signal to the pixel unit 100.

[0070] The data driver 300 may be provided with a data driving control signal DCS from the timing controller 600. During the sensing period, the data driver 300 may provide a data signal for pixel characteristic detection to the pixel unit 100. During the display period, the data driver 300 may provide a data signal for image display to the pixel unit 100 based on the compensated second image data DATA2.

[0071] The sensing unit 400 may be connected between the data driver 300 and the pixel unit 100. The sensing unit 400 connects the data output lines O1 to Om and the data lines DL1 to DLm. During a sensing period, the sensing unit 400 may sense degradation information of the light-emitting diode included in each pixel PX and / or threshold voltage / mobility information of the drive transistor included in each pixel PX. The sensing unit 400 may store compensation data CD including degradation information of the light-emitting diode and threshold voltage / mobility information of the drive transistor, and provide the stored compensation data CD to the timing controller 600.

[0072] In an embodiment, the sensing unit 400 may include an analog-to-digital converter 420 (see Figure 4 ), the analog-to-digital converter 420 converts the sensed values ​​provided through the data lines DL1 to DLm into current codes in digital form.

[0073] In an embodiment, Figure 1 As shown in , the sensing unit 400 may be a component separate from the timing controller 600 or arranged outside the timing controller 600, but is not limited thereto. Alternatively, at least a portion of the sensing unit 400 may be included in the timing controller 600. In one embodiment, for example, the sensing unit 400 and the timing controller 600 may be formed as a single driver integrated circuit ("IC"). In an embodiment, the data driver 300 may also be included in the timing controller 600. Therefore, at least some of the sensing unit 400, the data driver 300, and the timing controller 600 may be formed as a single driver IC.

[0074] Figure 2A and Figure 2B It shows Figure 1 1 is a circuit diagram of an embodiment of a pixel included in a display device shown in .

[0075] refer to Figure 1 and Figure 2A , an embodiment of the pixel PX may include a light emitting diode LD and a pixel circuit PC connected to the light emitting diode LD.

[0076] Figure 2A The pixel PX shown in FIG is a pixel located in the i-th row and the k-th column (i and k are natural numbers), which is connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th emission control line EMLi and the k-th data line DLk.

[0077] An anode of the light emitting diode LD may be connected to the pixel circuit PC, and a cathode of the light emitting diode LD may be connected to a second power source VSS. The light emitting diode LD may generate light having predetermined brightness corresponding to an amount of current supplied from the pixel circuit PC.

[0078] The light emitting diode LD may be configured as an organic light emitting diode or an inorganic light emitting diode, such as a micro light emitting diode ("LED") or a quantum dot light emitting diode. In an embodiment, the light emitting diode LD may be a light emitting diode including or made of a combination of an organic material and an inorganic material. In an embodiment, as Figure 2A and Figure 2B As shown in FIG, the pixel PX may include a single light emitting diode LD, but is not limited thereto. In alternative embodiments, each pixel PX may include a plurality of light emitting diodes, and the plurality of light emitting diodes may be connected to each other in parallel or in series.

[0079] The pixel circuit PC controls the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting diode LD based on the data signal (or data voltage) Vdata. In this embodiment, the first power source VDD may be set to a voltage higher than the second power source VSS.

[0080] In an embodiment, Figure 2A As shown, the pixel circuit PC may include first to fourth transistors T1 to T4 and a storage capacitor Cst.

[0081] In this embodiment, the first transistor T1 may be connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first power supply VDD (or a first power line PL1), and the second node N2 is electrically connected to an anode of a light-emitting diode LD. The gate electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may provide a driving current corresponding to a voltage at the third node N3 to the light-emitting diode LD. The first transistor T1 functions as a driving transistor for the pixel PX.

[0082] The second transistor T2 may be connected between the kth data line DLk and the second node N2. The second transistor T2 may include a gate electrode receiving the first scan signal S1[i]. When the second transistor T2 is turned on, the data signal Vdata may be transmitted to the second node N2.

[0083] The third transistor T3 may be connected between the third node N3 and the third power supply VINT (or the third power line PL3). The third transistor T3 may include a gate electrode that receives the second scan signal S2[i]. When the second scan signal S2[i] is provided, the third transistor T3 may be turned on to provide the voltage of the third power supply VINT to the third node N3.

[0084] The fourth transistor T4 may be connected between the first power supply VDD and the first node N1. The fourth transistor T4 may include a gate electrode that receives the emission control signal EM[i]. The fourth transistor T4 may be turned on during a gate-on period of the emission control signal EM[i] and turned off during a gate-off period of the emission control signal EM[i].

[0085] The light emitting diode LD may be connected between the second node N2 and the second power supply VSS (or the second power supply line PL2). The second power supply VSS may be applied to the cathode of the light emitting diode LD. The first power supply VDD and the second power supply VSS may have different potentials. In an embodiment, the first power supply VDD may be set to a high potential power supply, and the second power supply VSS may be set to a low potential power supply. The potential difference between the first power supply VDD and the second power supply VSS may be set to be equal to or greater than the threshold voltage of the light emitting diode LD during the emission period of the pixel PX. In an embodiment, as Figure 2A As shown in FIG, the first transistor T1, the second transistor T2, and the third transistor T3 included in the pixel PX may be implemented as N-type transistors, and the fourth transistor T4 may be implemented as a P-type transistor. However, the present disclosure is not limited thereto.

[0086] In the embodiment of the present invention, the pixel circuit PC is not limited to Figure 2A In an alternative embodiment, for example, Figure 2B As shown in FIG, the pixel circuit PC may be configured with first to third transistors T1 to T3 and a storage capacitor Cst. Figure 2B In the embodiment of the pixel circuit PC shown in FIG, except that the fourth transistor T4 for controlling the emission time of the light emitting diode LD is omitted, the configuration or operation of the first transistor T1, the second transistor T2 and the third transistor T3 and the storage capacitor Cst are the same as those of FIG. Figure 2A The configuration or operation of the pixel circuit PC shown in FIG. 1 is similar. Therefore, any repetitive detailed description of the same or similar elements will be omitted.

[0087] Figure 3 It shows Figure 1 FIG. 4 is a diagram of an embodiment of a data driver shown in FIG.

[0088] refer to Figure 3 , an embodiment of the data driver 300 may include a shift register unit 321 , a sampling latch unit 322 , a holding latch unit 323 , a signal generating unit 324 , and a buffer 325 .

[0089] The shift register unit 321 can sequentially generate m (m is a natural number greater than 0) sampling signals in response to the source start pulse SSP and the source shift clock SSC output from the timing controller 600. In an embodiment, for each cycle of the source shift clock SSC, the shift register unit 321 can sequentially output m sampling signals while shifting the source start pulse SSP. The shift register unit 321 can include m shift registers 3211 to 321m or be implemented as m shift registers 3211 to 321m.

[0090] The sampling latch unit 322 may sequentially store the second image data DATA2 in response to sampling signals sequentially provided from the shift register unit 321. The sampling latch unit 322 may include or be implemented with m sampling latches 3221 to 322m for storing the m second image data DATA2.

[0091] The holding latch unit 323 may store the second image data DATA2 provided from the sampling latch unit 322 in response to the source output enable signal SOE output from the timing controller 600. The holding latch unit 323 may provide the second image data DATA2 stored therein to the signal generating unit 324. The holding latch unit 323 may include m holding latches 3231 to 323m or be implemented as m holding latches 3231 to 323m.

[0092] The signal generation unit 324 may convert the second image data DATA2 output from the holding latch unit 323 into an analog signal and output the converted analog signal as a data signal to the buffer 325. The signal generation unit 324 may include m digital-to-analog converters 3241 to 324m or be implemented as m digital-to-analog converters 3241 to 324m. In this embodiment, the signal generation unit 324 may generate m data signals based on the plurality of digital-to-analog converters 3241 to 324m arranged in a plurality of channels, respectively, and provide the generated data signals to the buffer 325.

[0093] The buffer 325 may provide the m data signals provided from the signal generating unit 324 to the m data output lines O1 to Om, respectively. The buffer 325 may include or be implemented with m buffer amplifiers 3251 to 325m.

[0094] Figure 4 The embodiment according to the present disclosure is shown Figure 1 FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG.

[0095] For ease of illustration and description, Figure 4The timing controller 600 and the data driver 300 are schematically shown in FIG. Figure 4 , which shows the connection structure of one pixel PX.

[0096] refer to Figure 1 、 Figure 3 and Figure 4 In an embodiment, the timing controller 600 may generate second image data DATA2 by converting first image data DATA1 provided externally in response to compensation data CD provided from the sensing unit 400 and output the generated second image data DATA2 to the data driver 300 .

[0097] The data driver 300 may convert the second image data DATA2 output from the timing controller 600 into an analog signal and provide the converted analog signal as a data signal to the data output line Oi.

[0098] In an embodiment, the sampling latch 322 i may latch data corresponding to the i-th channel among the second image data DATA2 output from the timing controller 600 and output the latched data to the holding latch 323 i.

[0099] The holding latch 323 i may latch the data output from the sampling latch 322 i in response to the source output enable signal SOE and output the latched data to the digital-to-analog converter 324 i .

[0100] A digital-to-analog converter ("DAC") 324i may convert the second image data DATA2 output from the holding latch 323i into an analog signal and output the converted analog signal to the buffer amplifier 325i.

[0101] The buffer amplifier 325i can provide the analog signal output from the digital-to-analog converter 324i as a data signal to the data output line Oi. A first input terminal of the buffer amplifier 325i can be connected to the a-th node Na (i.e., the output terminal of the buffer amplifier 325i), a second input terminal of the buffer amplifier 325i can be connected to the digital-to-analog converter 324i, and an output terminal of the buffer amplifier 325i can be connected to the a-th node Na, i.e., the data output line Oi of the data driver 300.

[0102] The sensing unit 400 may include a first switch SW1 , a second switch SW2 , a current integrator ITG, an initialization switch SWi, and an analog-to-digital converter (“ADC”) 420 .

[0103] The first switch SW1 may be connected between the a-th node Na and the b-th node Nb. The a-th node Na may be the output terminal of the buffer amplifier 325i, and the b-th node Nb may be a node connected to the data line DLk. In this embodiment, the first switch SW1 may be connected between the data output line Oi and the data line DLk. The first switch SW1 may be turned on in response to a corresponding switch control signal output from the timing controller 600.

[0104] The second switch SW2 may be connected between the b-th node Nb and the first input terminal of the current integrating amplifier 410. In this embodiment, the second switch SW2 may be connected between the data line DLk and the first input terminal of the current integrating amplifier 410. The second switch SW2 may be turned on in response to a corresponding switch control signal output from the timing controller 600.

[0105] According to an embodiment, the current integrator ITG may be connected between the b-th node Nb and the c-th node Nc (ie, the input terminal of the ADC 420 ).

[0106] The current integrator ITG may have a first input terminal for receiving a sensing current Is of the pixel PX corresponding to the data signal through the data line DLk, and output a sensing voltage corresponding to the sensing current Is. The current integrator ITG may have a second input terminal for receiving a sensing reference voltage, and sense the current characteristics of the pixel PX based on the sensing reference voltage. The second input terminal may be directly connected to the a-th node Na through the connection line CNL. Figures 5 to 7 The sensing reference voltage is described in more detail.

[0107] In an embodiment, the current integrator ITG may include a current integrating amplifier 410 and an integrating capacitor Cf. One end of the integrating capacitor Cf may be connected to a first input terminal (e.g., an inverting input terminal) of the current integrating amplifier 410, and the other end of the integrating capacitor Cf may be connected to an output terminal (i.e., a c-th node Nc) of the current integrating amplifier 410.

[0108] In an embodiment, the current integrator ITG may further include an initialization switch SWi including one end connected to the first input end of the current integrating amplifier 410 and the other end connected to the output end of the current integrating amplifier 410. The integration capacitor Cf may be initialized by turning on the initialization switch SWi when sensing is completed.

[0109] The ADC 420 may be connected between the c-th node Nc and the input terminal of the timing controller 600. The input terminal of the ADC 420 may be connected to the c-th node Nc. The node voltage of the c-th node Nc, that is, the output voltage (or sensed voltage) Vo of the current integrating amplifier 410, may be applied to the ADC 420.

[0110] The ADC 420 may convert the voltage provided to the input terminal (i.e., the c-th node Nc) (i.e., the output voltage Vo of the current integrating amplifier 410) into a digital code. In this embodiment, the sensing unit 400 may convert the output voltage Vo of the current integrating amplifier 410 into a digital code and provide the converted digital code as compensation data CD to the timing controller 600.

[0111] Figure 5 and Figure 6 is shown during the sensing period Figure 1 2 is a diagram illustrating the operations of the timing controller, data driver, sensing unit, and pixel shown in FIG. Figure 7 is provided to during the sensing period according to an embodiment of the present disclosure Figure 1 1 is a timing diagram of control signals for the timing controller, data driver, sensing unit, and pixel shown in FIG. Figure 8 is a diagram showing a coupling phenomenon that occurs due to parasitic capacitors. Figure 9A and Figure 9B is a diagram illustrating a capacitive coupling phenomenon occurring in a pixel during sensing and its effects.

[0112] refer to Figure 1 and Figures 5 to 7 During the sensing period, a signal for sensing may be provided from the timing controller 600 to the pixel PX. The sensing period may include a period in which a sensing reference voltage is provided from the data driver 300 to the pixel PX and a period in which a sensing voltage Vo corresponding to the sensing current Is is output by providing the sensing current Is corresponding to the sensing reference voltage from the pixel PX to the sensing unit 400.

[0113] In an embodiment, the on-level voltage of the first scan signal S1[i] and the second scan signal S2[i] may be defined as a logic high voltage. In this embodiment, the on-level voltage of the emission control signal EM[i] may be defined as a logic low voltage. However, this is merely exemplary, and the pulse widths and logic levels of the scan signals and the emission control signal are not limited thereto. The pulse widths and logic levels of the scan signals and the emission control signal may be modified in various ways to correspond to pixel structures, transistor types, and the like.

[0114] In an embodiment, Figure 7 As shown in FIG, during a period from a first time (or time point) t1 to a fourth time t4, an emission control signal EM[i] having a logic high level may be provided to the emission control line EMLi. When the emission control signal EM[i] having a logic high level is provided to the emission control line EMLi, the fourth transistor T4 may be turned off.

[0115] During a period between the second time t2 and the third time t3 , the first scan signal S1 [ i ] and the second scan signal S2 [ i ] may be provided, and the first switch SW1 may be turned on.

[0116] When the first switch SW1 is turned on, the data output line Oi and the data line DLk may be connected to each other.

[0117] The second transistor T2 may be turned on when the first scan signal S1[i] is provided, and the third transistor T3 may be turned on when the second scan signal S2[i] is provided. When the third transistor T3 is turned on, the third power supply VINT and the third node N3 may be connected to each other. In this embodiment, when the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be initialized to the third power supply VINT. In this embodiment, when the second transistor T2 is turned on, as shown in FIG. Figure 5 As shown in FIG, the a-th node Na and the second node N2 may be connected to each other. Therefore, a sensing reference voltage may be applied to the source electrode of the first transistor T1. The sensing reference voltage may be a voltage having a level lower than that of the third power supply VINT. The storage capacitor Cst is charged with a voltage corresponding to the sensing reference voltage. In this embodiment, since the sensing reference voltage is the same as the data voltage Vdata output from the data driver 300, the sensing reference voltage may be labeled with the reference numeral "Vdata."

[0118] During the period between the fourth time t4 and the fifth time t5, the emission control signal EM[i] having a logic low level and the first scan signal S1[i] having a logic high level may be provided. In addition, during the period between the fourth time t4 and the fifth time t5, the second switch SW2 may be turned on.

[0119] When the emission control signal EM[i] having a logic low level is supplied, the fourth transistor T4 may be turned on. In addition, when the first scan signal S1[i] having a logic high level is supplied, the second transistor T2 may be turned on.

[0120] When the second switch SW2 is turned on and the second transistor T2 is turned on, a current path may be formed between the second node N2 and the first input terminal of the current integrating amplifier 410 .

[0121] When the fourth transistor T4 is turned on, a current path may be formed between the first power supply VDD and the second node N2 through the fourth transistor T4 connected to the first power supply VDD and the first transistor T1 connected to the second node N2. Then, the first transistor T1 may provide a current (i.e., a sensing current Is corresponding to the sensing reference voltage Vdata stored in the storage capacitor Cst) from the first power supply VDD to the first input terminal of the current integrating amplifier 410 via the second node N2. Figure 6 As shown in .

[0122] In an embodiment, during a period in which the sensing current Is is supplied to the current integrating amplifier 410 , the second input terminal of the current integrating amplifier 410 may be connected to the a-th node Na through the connection line CNL. A sensing reference voltage Vdata may be supplied to the a-th node Na.

[0123] In the following, reference will be made to Figure 8 、 Figure 9A and Figure 9B A problem that occurs in a case where no connection line CNL is provided between the a-th node Na and the second input terminal of the current integrating amplifier 410 is described.

[0124] refer to Figure 8 In the case where the connection line CNL is not provided between the a-th node Na and the second input terminal of the current integrating amplifier 410, a parasitic capacitor Cpara may be formed between the third node N3 and the first power supply VDD in the pixel PX. Although the case where the parasitic capacitor Cpara is formed between the third node N3 and the first power supply VDD is shown for ease of description, the parasitic capacitor Cpara may be further formed between the third node N3 and the third power supply VINT, between the third node N3 and the gate electrode of the third transistor T3, and so on.

[0125] In this case, the storage capacitor Cst may be charged to a difference voltage Vgs (see FIG. 1 ) between the voltage Vint of the third power source VINT and the sensing reference voltage Vdata. Figure 9A ).

[0126] like Figure 8 As shown, when the virtual ground voltage VGND is applied to the second input terminal of the current integrating amplifier 410 by a separate voltage source at the time of sensing, the voltage of the second node N2 may change from the sensing reference voltage Vdata to the virtual ground voltage VGND.

[0127] When the voltage of the second node N2 changes from the sensing reference voltage Vdata to the virtual ground voltage VGND, a coupling phenomenon occurs even in the storage capacitor Cst in a floating state. However, due to the parasitic capacitor Cpara formed at the third node N3, the voltage charged in the storage capacitor Cst may change to a voltage Vgs' different from the difference voltage Vgs between the voltage Vint of the third power source VINT and the sensing reference voltage Vdata (see Figure 9A ). Therefore, a sensing result different from the current characteristic of the pixel PX to be measured initially may be obtained.

[0128] In this case, reference Figure 9A, the sensing reference voltage Vdata may have a voltage level lower than the voltage level of the third power supply VINT. In this case, if the virtual ground voltage VGND is higher than the sensing reference voltage Vdata, the voltage Vgs' applied across the storage capacitor Cst due to the parasitic capacitor Cpara may be lower than the difference voltage Vgs between the voltage Vint of the third power supply VINT and the sensing reference voltage Vdata. Therefore, the sensing current Is flowing in the current path formed between the second node N2 and the first input terminal of the current integrating amplifier 410 is reduced, and thus the current integrator ITG outputs a sensing voltage Vo' that does not correspond to the data signal applied to the pixel PX (see Figure 9B ).

[0129] In this case, if the virtual ground voltage VGND is lower than the sensing reference voltage Vdata, the voltage Vgs′ applied across the storage capacitor Cst due to the parasitic capacitor Cpara is higher than the difference voltage Vgs between the voltage Vint of the third power supply VINT and the sensing reference voltage Vdata. Therefore, the sensing current Is flowing in the current path formed between the second node N2 and the first input terminal of the current integrating amplifier 410 is increased, and thus the current integrator ITG outputs a sensing voltage (not shown) that does not correspond to the data signal applied to the pixel PX.

[0130] refer to Figures 5 to 7 and Figure 9B In an embodiment of the present disclosure, the a-th node Na and the current integrating amplifier 410 are connected to each other via the connection line CNL, so that the second input terminal of the current integrating amplifier 410 can receive the sensing reference voltage Vdata. Therefore, between a first period P1 in which the sensing reference voltage Vdata is applied from the data driver 300 to the pixel PX and a second period P2 in which the sensing current Is corresponding to the sensing reference voltage Vdata is supplied from the pixel PX to the sensing unit 400, the voltage of the second node N2 can be effectively maintained at the sensing reference voltage Vdata.

[0131] When the voltage of the second node N2 is maintained at the sensing reference voltage Vdata, no coupling phenomenon may occur in the storage capacitor Cst. Therefore, before and after the sensing reference voltage Vdata is applied, the sensing current Is flowing in the current path between the second node N2 and the first input terminal of the current integrating amplifier 410 is effectively maintained, and thus the current integrator ITG can accurately output the sensing voltage Vo corresponding to the data signal applied to the pixel PX. In this embodiment, the sensing unit 400 can obtain a sensing result consistent with the current characteristics of the pixel PX to be measured.

[0132] like Figure 9BAs shown in FIG, in an embodiment of the present disclosure, in the first period P1 and the second period P2, the voltage of the second node N2 is maintained at the sensing reference voltage Vdata, and the output voltage Vo of the current integrating amplifier 410 decreases at a first slope (see the solid line graph). In the case where no connection line CNL is provided between the a-th node Na and the second input terminal of the current integrating amplifier 410, as shown in FIG. Figure 8 As shown in FIG, when the virtual ground voltage VGND is higher than the sensing reference voltage Vdata, the sensing current Is flowing in the current path formed between the second node N2 and the first input terminal of the current integrating amplifier 410 decreases, and thus the output voltage Vo' decreases at a second slope (see the alternating long and short dashed line graph) that is less than the first slope. In this case, due to the parasitic capacitor Cpara, the sensing unit 400 may output an inaccurate sensing voltage Vo' that does not correspond to the sensing reference voltage Vdata applied to the pixel PX.

[0133] Return Reference Figures 5 to 7 , then, during a period between the sixth time t6 and the seventh time t7, the initialization switch SWi may be turned on. When the initialization switch SWi is turned on, the integration capacitor Cf may be initialized.

[0134] Subsequently, during the display period, the timing controller 600 may provide the data driver 300 with second image data DATA2 obtained by adding the first image data DATA1 and the compensation data CD, and the data driver 300 may provide a data signal corresponding to the second image data DATA2 to the pixel PX. In this embodiment, the display device 1000 may be provided with a data signal obtained or compensated by taking into account the degradation of the pixel PX. Therefore, despite the degradation of the pixel PX, the display device 1000 can emit light with accurate brightness.

[0135] Hereinafter, an alternative embodiment will be described in which any repetitive detailed description of components identical or similar to those of the above embodiment will be omitted or simplified, and elements or features different from those of the above embodiment will be mainly described.

[0136] Figure 10 is an illustration of an alternative embodiment according to the present disclosure Figure 1 FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG. Figure 11 is provided to during the sensing period according to an alternative embodiment of the present disclosure Figure 1 1 is a timing diagram of control signals for the timing controller, data driver, sensing unit, and pixel shown in FIG.

[0137] refer to Figure 10In addition to the sensing unit 400_1 further including a third switch SW3 to allow the sensing reference voltage to be selectively provided to the second input terminal of the current integrating amplifier 410, the sensing unit 400_1 and the Figure 4 The sensing unit 400 of the embodiment shown in FIG. 1 is substantially the same.

[0138] In an embodiment, Figure 10 As shown, the sensing unit 400_1 may include a first switch SW1 , a second switch SW2 , a third switch SW3 , a current integrator ITG, an initialization switch SWi, and an ADC 420 .

[0139] The first switch SW1, the second switch SW2, the current integrator ITG and the initialization switch SWi are connected to Figure 4 , and thus any repetitive detailed description thereof will be omitted. Therefore, the third switch SW3 will be described in detail.

[0140] In this embodiment, the third switch SW3 may be connected between the a-th node Na and the second input terminal of the current integrating amplifier 410. In this embodiment, the third switch SW3 may be provided in the connection line CNL. The third switch SW3 may be turned on in response to a corresponding switch control signal output from the timing controller 600.

[0141] When the third switch SW3 is turned on, the second input terminal of the current integrator ITG can be directly connected to the a-th node Na through the connection line CNL. That is, when the third switch SW3 is turned on, the second input terminal of the current integrator ITG can receive the sensing reference voltage Vdata from the data driver 300, and stop receiving the sensing reference voltage Vdata from the data driver 300 when the third switch SW3 is turned off.

[0142] refer to Figure 11 During a period from the first time t1 to the fourth time t4, the emission control signal EM[i] having a logic high level may be provided to the emission control line EMLi. When the emission control signal EM[i] having a logic high level is provided to the emission control line EMLi, the fourth transistor T4 may be turned off.

[0143] During a period between the second time t2 and the third time t3, the first scan signal S1[i] and the second scan signal S2[i] may be provided and the first switch SW1 may be turned on. When the first switch SW1 is turned on, the data output line Oi and the data line DLk may be connected to each other.

[0144] When the first scan signal S1[i] is provided, the second transistor T2 may be turned on, and when the second scan signal S2[i] is provided, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the third power supply VINT and the third node N3 may be connected to each other. Therefore, when the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be initialized to the third power supply VINT. In this embodiment, when the second transistor T2 is turned on, the a-th node Na and the second node N2 may be connected to each other. That is, the sensing reference voltage Vdata may be applied to the source electrode of the first transistor T1. The sensing reference voltage Vdata may be a voltage having a level lower than the level of the third power supply VINT. The third switch SW3 may remain in an off state. That is, the sensing reference voltage Vdata may not be applied to the second input terminal of the current integrating amplifier 410.

[0145] During the period between the fourth time t4 and the fifth time t5, the emission control signal EM[i] having a logic low level and the first scan signal S1[i] having a logic high level may be provided. Furthermore, during the period between the fourth time t4 and the fifth time t5, the second switch SW2 and the third switch SW3 may be turned on. When the third switch SW3 is turned on, the a-th node Na and the second input terminal of the current integrating amplifier 410 may be connected to each other. The sensing reference voltage Vdata may be provided to the a-th node Na.

[0146] When the emission control signal EM[i] having a logic low level is supplied, the fourth transistor T4 may be turned on. When the first scan signal S1[i] having a logic high level is supplied, the second transistor T2 may be turned on.

[0147] When the second switch SW2 is turned on and the second transistor T2 is turned on, a current path may be formed between the second node N2 and the first input terminal of the current integrating amplifier 410 .

[0148] When the fourth transistor T4 is turned on, a current path is formed between the first power supply VDD and the second node N2 through the fourth transistor T4 and the first transistor T1. The first transistor T1 can then provide a current from the first power supply VDD to the first input terminal of the current integrating amplifier 410 via the second node N2, that is, a sensing current Is corresponding to the sensing reference voltage Vdata stored in the storage capacitor Cst.

[0149] Subsequently, during a period between the sixth time t6 and the seventh time t7, the initialization switch SWi may be turned on. When the initialization switch SWi is turned on, the integration capacitor Cf may be initialized.

[0150] Figure 12 Another alternative embodiment of the present disclosure is shown. Figure 1FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG. Figure 13 According to another alternative embodiment of the present disclosure, during the sensing period, Figure 1 1 is a timing diagram of control signals for the timing controller, data driver, sensing unit, and pixel shown in FIG.

[0151] refer to Figure 12 In an embodiment, the sensing unit 400_2 may further include a fourth switch SW4, a fifth switch SW5, and a reference voltage storage capacitor Cref. In this embodiment, the sensing unit 400_2 is connected to the current integrating amplifier 410, except that the sensing reference voltage may be provided to the second input terminal of the current integrating amplifier 410 only during the sensing period. Figure 4 The sensing unit 400 of the embodiment shown in FIG. 1 is substantially the same.

[0152] In this embodiment, if Figure 12 As shown in , the sensing unit 400_2 may include a first switch SW1 , a second switch SW2 , a fourth switch SW4 , a fifth switch SW5 , a current integrator ITG, an initialization switch SWi, and an ADC 420 .

[0153] The first switch SW1, the second switch SW2, the current integrator ITG and the initialization switch SWi are connected to Figure 4 , and thus any repetitive detailed description thereof will be omitted. Therefore, the fourth switch SW4, the fifth switch SW5, and the reference voltage storage capacitor Cref will be described in detail.

[0154] In this embodiment, the reference voltage storage capacitor Cref may be connected between the a-th node Na and the ground terminal. When the sensing reference voltage Vdata is supplied from the data driver 300, the sensing reference voltage Vdata may be applied across the reference voltage storage capacitor Cref.

[0155] The fourth switch SW4 may be connected in parallel to both ends of the reference voltage storage capacitor Cref. When the fourth switch SW4 is turned on, the reference voltage storage capacitor Cref may be initialized. The fourth switch SW4 may be turned on in response to a corresponding switch control signal output from the timing controller 600.

[0156] The fifth switch SW5 may be connected between one end of the reference voltage storage capacitor Cref connected to the a-th node Na and the second input terminal of the current integrating amplifier 410. In other words, the fifth switch SW5 may be provided in a region of the connection line CNL. The fifth switch SW5 may be turned on in response to a corresponding switch control signal output from the timing controller 600.

[0157] refer to Figure 13First, during a period from the first time t1 to the sixth time t6, the emission control signal EM[i] having a logic high level may be provided to the emission control line EMLi. When the emission control signal EM[i] having a logic high level is provided to the emission control line EMLi, the fourth transistor T4 may be turned off.

[0158] During a period between the second time t2 and the third time t3, the fourth switch SW4 may be turned on. When the fourth switch SW4 is turned on, the reference voltage storage capacitor Cref may be initialized.

[0159] During a period between fourth time t4 and fifth time t5, the first scan signal S1[i] and the second scan signal S2[i] may be provided and the first switch SW1 may be turned on. When the first switch SW1 is turned on, the data output line Oi and the data line DLk may be connected to each other.

[0160] The second transistor T2 may be turned on when the first scan signal S1[i] is provided, and the third transistor T3 may be turned on when the second scan signal S2[i] is provided. When the third transistor T3 is turned on, the third power supply VINT and the third node N3 may be connected to each other. That is, when the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be initialized to the third power supply VINT. In addition, when the second transistor T2 is turned on, the a-th node Na and the second node N2 may be connected to each other. That is, a sensing reference voltage Vdata may be applied to the source electrode of the first transistor T1. The sensing reference voltage Vdata may be a voltage having a level lower than that of the third power supply VINT.

[0161] During a period between the sixth time t6 and the seventh time t7 , the emission control signal EM[i] having a logic low level and the first scan signal S1[i] having a logic high level may be provided. In addition, the second switch SW2 and the fifth switch SW5 may be turned on.

[0162] When the second switch SW2 is turned on, the second node N2 and the first input terminal of the current integrating amplifier 410 may be connected to each other.

[0163] When the emission control signal EM[i] having a logic low level is supplied, the fourth transistor T4 may be turned on. In addition, when the first scan signal S1[i] having a logic high level is supplied, the second transistor T2 may be turned on.

[0164] When the second switch SW2 is turned on and the second transistor T2 is turned on, a current path may be formed between the second node N2 and the first input terminal of the current integrating amplifier 410 .

[0165] When the fourth transistor T4 is turned on, a current path is formed between the first power supply VDD and the second node N2 through the fourth transistor T4 and the first transistor T1. The first transistor T1 can then provide a current from the first power supply VDD to the first input terminal of the current integrating amplifier 410 via the second node N2, that is, a sensing current Is corresponding to the sensing reference voltage Vdata stored in the storage capacitor Cst.

[0166] When the fifth switch SW5 is turned on, the a-th node Na and the second input terminal of the current integrating amplifier 410 may be connected to each other. That is, the sensing reference voltage Vdata stored in the reference voltage storage capacitor Cref may be applied to the second input terminal of the current integrating amplifier 410.

[0167] During a period between the seventh time t7 and the tenth time t10, the emission control signal EM[i] having a logic high level may be provided to the emission control line EMLi. During a period between the eighth time t8 and the ninth time t9, the initialization switch SWi may be turned on. When the initialization switch SWi is turned on, the integration capacitor Cf may be initialized.

[0168] Figure 14 Another alternative embodiment of the present disclosure is shown. Figure 1 FIG. 1 is a diagram showing a connection structure of a timing controller, a data driver, a sensing unit, and a pixel as shown in FIG. Figure 15 According to another alternative embodiment of the present disclosure, during the sensing period, Figure 1 1 is a timing diagram of control signals for the timing controller, data driver, sensing unit, and pixel shown in FIG.

[0169] refer to Figure 14 , the sensing unit 400_3 may further include a sixth switch SW6. In this embodiment, in addition to the data signal being blocked from being provided from the data driver 300 during the sensing period, the sensing unit 400_3 and the data driver 300 are connected. Figure 12 The sensing unit 400_2 of the embodiment shown in FIG. 1 is substantially the same.

[0170] In this embodiment, if Figure 14 As shown in , the sensing unit 400_3 may include a first switch SW1 , a second switch SW2 , a fourth switch SW4 , a fifth switch SW5 , a sixth switch SW6 , a current integrator ITG, an initialization switch SWi, and an ADC 420 .

[0171] In this embodiment, the first switch SW1, the second switch SW2, the fourth switch SW4, the fifth switch SW5, the current integrator ITG and the initialization switch SWi are connected to the Figure 12Those shown in , and thus any repetitive detailed description thereof will be omitted. Hereinafter, the sixth switch SW6 will be described in detail.

[0172] In this embodiment, if Figure 14 As shown in , the sixth switch SW6 may be connected between the a-th node Na and the d-th node Nd. In this embodiment, the sixth switch SW6 may be provided in the connection line CNL. The sixth switch SW6 may be turned on in response to a corresponding switch control signal output from the timing controller 600.

[0173] refer to Figure 15 First, during a period from the first time t1 to the sixth time t6, the emission control signal EM[i] having a logic high level may be supplied to the emission control line EMLi. When the emission control signal EM[i] having a logic high level may be supplied to the emission control line EMLi, the fourth transistor T4 may be turned off.

[0174] During a period between the second time t2 and the third time t3, the fourth switch SW4 may be turned on. When the fourth switch SW4 is turned on, the reference voltage storage capacitor Cref may be initialized.

[0175] During a period between the fourth time t4 and the fifth time t5 , the first scan signal S1 [i] and the second scan signal S2 [i] may be provided. Simultaneously, the first switch SW1 and the sixth switch SW6 may be turned on.

[0176] When the first switch SW1 is turned on, the data output line Oi and the data line DLk may be connected to each other. When the sixth switch SW6 is turned on, the a-th node Na and the d-th node Nd may be connected to each other. Therefore, the sensing reference voltage Vdata provided from the data driver 300 may be applied to both ends of the reference voltage storage capacitor Cref.

[0177] The second transistor T2 may be turned on when the first scan signal S1[i] is provided, and the third transistor T3 may be turned on when the second scan signal S2[i] is provided. When the third transistor T3 is turned on, the third power supply VINT and the third node N3 may be connected to each other. That is, when the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be initialized to the third power supply VINT. In addition, when the second transistor T2 is turned on, the a-th node Na and the second node N2 may be connected to each other. That is, a sensing reference voltage Vdata may be applied to the source electrode of the first transistor T1. The sensing reference voltage Vdata may be a voltage having a level lower than that of the third power supply VINT.

[0178] During the period between the sixth time t6 and the seventh time t7, the emission control signal EM[i] having a logic low level and the first scan signal S1[i] having a logic high level may be provided. During the period between the sixth time t6 and the seventh time t7, the second switch SW2 and the fifth switch SW5 may be turned on.

[0179] When the second switch SW2 is turned on, the second node N2 and the first input terminal of the current integrating amplifier 410 may be connected to each other.

[0180] When the emission control signal EM[i] having a logic low level is supplied, the fourth transistor T4 may be turned on. In addition, when the first scan signal S1[i] having a logic high level is supplied, the second transistor T2 may be turned on.

[0181] When the second switch SW2 is turned on and the second transistor T2 is turned on, a current path may be formed between the second node N2 and the first input terminal of the current integrating amplifier 410 .

[0182] When the fourth transistor T4 is turned on, a current path is formed between the first power supply VDD and the second node N2 through the fourth transistor T4 and the first transistor T1. The first transistor T1 can then provide a current from the first power supply VDD to the first input terminal of the current integrating amplifier 410 via the second node N2, that is, a sensing current Is corresponding to the sensing reference voltage Vdata stored in the storage capacitor Cst.

[0183] When the fifth switch SW5 is turned on, the dth node Nd and the second input terminal of the current integrating amplifier 410 may be connected to each other. That is, the sensing reference voltage Vdata stored in the reference voltage storage capacitor Cref may be applied to the second input terminal of the current integrating amplifier 410.

[0184] During a period between the seventh time t7 and the tenth time t10, the emission control signal EM[i] having a logic high level may be provided to the emission control line EMLi. During a period between the eighth time t8 and the ninth time t9, the initialization switch SWi may be turned on. When the initialization switch SWi is turned on, the integration capacitor Cf may be initialized.

[0185] According to an embodiment of the present disclosure, a display device reduces a capacitive coupling phenomenon occurring in a pixel unit during sensing, so that an accurate sensing voltage corresponding to a data signal can be output.

[0186] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0187] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: a pixel unit including pixels connected to a data line; a data driver that supplies a sensing reference voltage to the data line during a sensing period and supplies a data signal to the data line during a display period; as well as a sensing unit that receives a sensing current corresponding to the sensing reference voltage during the sensing period and generates correction data based on the sensing current, The sensing unit includes a current integrator, which outputs a sensing voltage based on the sensing current input to the current integrator through a first input terminal and based on the sensing reference voltage input to the current integrator through a second input terminal. Wherein, the current integrator includes: a current integrating amplifier, including the first input terminal and the second input terminal, The data driver includes a buffer, the buffer includes a buffer amplifier, the buffer amplifier provides the sensing reference voltage or the data signal to a data output line, and The second input terminal of the current integrating amplifier is connected to the a-th node connected to the output terminal of the buffer through a connecting line.

2. The display device according to claim 1, wherein The current integrator further includes: An integrating capacitor includes one end connected to the first input end and the other end connected to the output end of the current integrating amplifier.

3. The display device according to claim 2, wherein the sensing unit further comprises: An initialization switch includes one end connected to the first input end and the other end connected to the output end of the current integrating amplifier.

4. The display device according to claim 2, wherein The b-th node connected to the data line is connected between the a-th node and the first input terminal of the current integrating amplifier, and The sensing unit further includes a first switch and a second switch, the first switch being connected between the a-th node and the b-th node, and the second switch being connected between the b-th node and the first input terminal of the current integrating amplifier.

5. The display device according to claim 4, wherein When the sensing reference voltage is supplied to the pixel, the first switch is turned on, and When the sensing current is provided to the sensing unit, the second switch is turned on. The display device according to claim 4 , wherein: The sensing unit includes a third switch connected between the a-th node and the second input terminal of the current integrating amplifier, the third switch being provided in the connecting line, and The third switch is turned on when the sensing current is supplied to the sensing unit.

7. The display device according to claim 2, wherein: The sensing unit further includes a reference voltage storage capacitor connected between the a-th node and a ground terminal, and the reference voltage storage capacitor is provided in the connection line.

8. The display device according to claim 7, wherein: The sensing unit further includes: a fourth switch comprising one end connected to the node a and the other end connected to the ground; and a fifth switch connected between one end of the reference voltage storage capacitor connected to the a-th node and the second input end of the current integrating amplifier.

9. The display device according to claim 8, wherein The fourth switch is turned on in a predetermined period before the sensing reference voltage is supplied to the pixel, and The fifth switch is turned on when the sensing current is supplied to the sensing unit.

10. The display device according to claim 8, wherein the sensing unit further comprises: A sixth switch is connected between the a-th node and one end of the reference voltage storage capacitor connected to the connection line.

11. The display device according to claim 10, wherein: The sixth switch is turned on when the sensing reference voltage is supplied to the pixel.

12. The display device according to claim 1, wherein The sensing unit generates compensation data based on the sensing voltage, the compensation data including degradation information of the pixel.

13. The display device according to claim 12, wherein: The display device further includes: The timing controller receives first image data from the outside and provides the data driver with second image data obtained by adding the first image data and the compensation data.

14. The display device according to claim 13, wherein: The sensing unit further includes: an analog-to-digital converter connected between the output end of the current integrating amplifier of the current integrator and the timing controller, The analog-to-digital converter converts the sensing voltage from an analog form to a digital form.

15. The display device according to claim 1, wherein The pixel is connected to a first scan line, a second scan line and an emission control line, The pixels include: a light emitting diode connected to a second power source; a first transistor comprising: a first electrode connected to a first node electrically connected to a first power source, a second electrode connected to a second node connected to the light emitting diode, and a gate electrode connected to a third node; a second transistor connected between the data line and the second node, wherein a gate electrode of the second transistor is connected to the first scan line; and A third transistor is connected between the third node and a third power source, wherein a gate electrode of the third transistor is connected to the second scan line.

16. The display device according to claim 15, wherein The pixel further includes a fourth transistor connected between the first power source and the first node, wherein a gate electrode of the fourth transistor is connected to the emission control line.

17. The display device according to claim 15 or 16, wherein: The pixel further includes a storage capacitor connected between the second node and the third node.

18. The display device according to claim 15, wherein The second transistor and the third transistor are turned on when the sensing reference voltage or the data signal is supplied to the pixel.

19. The display device according to claim 16, wherein: The second transistor and the third transistor are turned on when the sensing reference voltage or the data signal is supplied to the pixel.

20. The display device according to claim 19, wherein The second transistor and the fourth transistor are turned on when the sensing current is supplied to the sensing unit.

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