Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device, the display substrate comprising: gate lines, data lines and a gate driving circuit; the gate lines comprising: a plurality of horizontal gate lines crossing the data lines to define a plurality of sub-pixels, and a plurality of vertical gate lines parallel to the data lines; wherein the number of the vertical gate lines is less than or equal to the number of the horizontal gate lines, and one of the vertical gate lines is connected to a corresponding one of the horizontal gate lines; the display substrate comprises a display area and a peripheral area located outside the display area, the peripheral area comprising a binding side and a binding opposite side opposite to the binding side, wherein the gate driving circuit comprises a first gate driving unit located on the binding side or the binding opposite side, and the vertical gate lines are connected to the first gate driving unit. The display substrate and the display device provided by the present disclosure can further narrow the border of the display product.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) displays offer advantages such as active illumination without the need for a backlight, high contrast, and flexibility, making them highly promising as the next generation of display technology. Gate Driver On Array (GOA) technology integrates the display device's gate driver circuit (IC) onto an array substrate. GOA reduces IC usage, thereby lowering product production costs and power consumption. It also enables narrower bezels for display devices. However, further narrowing the bezels within existing designs remains a pressing issue. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device, which can further narrow the border of a display product.

[0004] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0005] An embodiment of the present disclosure provides a display substrate, comprising: gate lines, data lines, and a gate driving circuit; the gate lines comprise: a plurality of transverse gate lines intersecting the data lines to define a plurality of sub-pixels, and a plurality of longitudinal gate lines parallel to the data lines; wherein the number of the longitudinal gate lines is less than or equal to the number of the transverse gate lines, and one longitudinal gate line is connected to a corresponding one of the transverse gate lines;

[0006] The display substrate includes a display area and a peripheral area located outside the display area, the peripheral area includes a binding side and a binding opposite side opposite to the binding side, wherein the gate drive circuit includes a first gate drive unit located on the binding side or the binding opposite side, and the longitudinal gate line is connected to the first gate drive unit.

[0007] Exemplarily, the number of the longitudinal grid lines is the same as the number of the transverse grid lines, and one longitudinal grid line is connected to a corresponding one transverse grid line.

[0008] Exemplarily, the number of the longitudinal gate lines is less than the number of the transverse gate lines, and the gate driving circuit further includes at least one second gate driving unit, wherein at least part of the transverse gate lines not connected to the longitudinal gate lines are connected to the second gate driving unit.

[0009] Exemplarily, the display substrate further includes: a driving chip disposed on the binding side, and the gate driving circuit is connected to the driving chip via a gate driving signal line.

[0010] Exemplarily, the gate driving signal lines are arranged in the peripheral area around the display area.

[0011] Exemplarily, on the opposite side of the binding, the peripheral area includes a gate drive circuit area and a bending area located between the display area and the gate drive circuit area, and the first gate drive unit is arranged in the gate drive circuit area; the longitudinal gate line is connected to the first gate drive unit through the routing on the bending area.

[0012] Exemplarily, the bending region is bent from the display surface to the non-display surface of the display substrate, so as to fold the gate driving circuit region to the non-display surface side of the display substrate.

[0013] Exemplarily, the display substrate includes an encapsulation layer, and the encapsulation layer does not cover and encapsulate the bending area and the gate driving circuit area.

[0014] Exemplarily, the display substrate further includes a power line, one end of which is connected to the driver chip, and the other end of which extends along the peripheral area and is connected to the driver chip, and the power line surrounds the side of the gate drive signal line away from the display area.

[0015] Exemplarily, the display substrate includes an encapsulation layer, and the encapsulation layer covers and encapsulates the gate driving circuit area.

[0016] Exemplarily, the display substrate further includes a power line, one end of the power line is connected to the driving chip, and the other end of the power line extends along the peripheral area and is connected to the driving chip;

[0017] The power line is located on a side of the bending area close to the display area, and is located on a side of the second gate driving signal line away from the display area.

[0018] Exemplarily, the transverse gate lines and the longitudinal gate lines are arranged in different layers, and an insulating layer is provided between the longitudinal gate lines and the transverse gate lines, and the longitudinal gate lines are connected to the corresponding transverse gate lines through via holes in the insulating layer.

[0019] The embodiments of the present disclosure further provide a display device, comprising the display substrate provided by the embodiments of the present disclosure.

[0020] The beneficial effects brought about by the embodiments of the present disclosure are as follows:

[0021] The display substrate and display device provided by the embodiments of the present disclosure design at least a portion of the gate drive circuit (GOA) on the binding side of the display substrate (i.e., the lower side of the display substrate) or the binding opposite side (i.e., the upper side of the display substrate). In this way, the gate drive circuit layout space on the left and right side frames of the display substrate can be reduced, thereby reducing the frame width. Moreover, for high-frequency settings, since the GOA circuit size needs to be significantly increased in order to increase the driving frequency, the display substrate provided by the embodiments of the present disclosure designs at least a portion of the GOA circuit on the upper side. Even if the GOA size is significantly increased, it will not cause a significant impact on the frame width, and can be reduced, or even will not affect the frame width. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram showing wiring of a display substrate in the related art;

[0023] Figure 2 A schematic diagram showing the wiring of a display substrate in some embodiments of the present disclosure;

[0024] Figure 3 Schematic diagram showing wiring of a display substrate before bending in a bending region in some other embodiments of the present disclosure;

[0025] Figure 4 Schematic diagram showing wiring of a display substrate after being bent in a bending area in other embodiments of the present disclosure;

[0026] Figure 5 Schematic diagram showing wiring of a display substrate after being bent in a bending area in some other embodiments of the present disclosure;

[0027] Figure 6 Schematic diagram showing the wiring of the display substrate after being bent in the bending area in some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0030] Before describing in detail the display substrate provided by the embodiments of the present disclosure, it is necessary to describe the related technologies as follows:

[0031] In the related art, full screen can provide the ultimate visual experience, so the demand for extremely narrow borders in the market is gradually increasing. The gate drive circuit (GOA circuit) is transferred from IC integration to the AMOLED display panel, so that the AMOLED display panel has a narrower border. The gate drive circuit is usually formed by cascading multiple GOA units, each GOA unit corresponds to a row of pixel areas, and the row of pixel areas includes multiple sub-pixel areas, each sub-pixel area is formed with a thin film transistor, and the gates of the multiple thin film transistors in the row of pixel areas are connected, and the output end of the GOA unit can be connected to the gate of the thin film transistor close to the GOA unit among the multiple thin film transistors, and the GOA unit can control the opening and closing of the multiple thin film transistors in a row of pixel areas by the potential of the drive signal it outputs.

[0032] Take AMOLED display substrate as an example. Figure 1 As shown, the display substrate includes a display area AA and a peripheral area. The peripheral area includes a binding area and a binding opposite side opposite to the binding area. The binding area is located at the lower side of the display screen, and the binding opposite side is the upper side of the display screen. The gate lines are arranged horizontally, and the gate drive circuit (GOA) 2 is arranged on the left and right sides of the display area and is connected to the gate lines.

[0033] The peripheral area also includes peripheral wiring, such as power lines, including VSS line (low-voltage signal line) 3, VDD line, Vint line (initial voltage line) 4, etc. Due to the limitations of the low-cost gate drive circuit GOA and VSS line overlap, the width of VSS line 3 needs to be large enough to prevent the bezel from being compressed. In addition, the higher the PPI (Pixels Per Inch) product, the larger the GOA wiring space required, resulting in an increase in the bezel.

[0034] In order to solve the problem of the limitation of further narrowing the frame, the embodiments of the present disclosure provide a display substrate and a display device, which can achieve the purpose of further narrowing the frame.

[0035] Figure 2 Shown are schematic structural diagrams of some embodiments of the display substrate provided by the present disclosure; Figure 3 and Figure 4 Shown are structural schematic diagrams of other embodiments of the display substrate provided by the present disclosure.

[0036] like Figures 2 to 4 As shown, the display substrate provided by the embodiment of the present disclosure includes a base substrate 100, on which gate lines 200, data lines 300 and a gate driving circuit are arranged; wherein the gate lines 200 include: a plurality of horizontal gate lines 210 that cross the data lines 300 to define a plurality of sub-pixels, and a plurality of vertical gate lines 220 that are parallel to the data lines 300; the number of the vertical gate lines 220 is less than or equal to the number of the horizontal gate lines 210, and one of the vertical gate lines 220 is connected to a corresponding horizontal gate line 210 that crosses it; the display substrate includes a display area AA and a peripheral area B located outside the display area AA, the peripheral area B includes a binding side and a binding opposite side opposite to the binding side, wherein the gate driving circuit includes a first gate driving unit 410 (i.e., a first GOA unit) located on the binding side or the binding opposite side, and the vertical gate lines 220 are connected to the first gate driving unit 410.

[0037] It should be noted that, here, the longitudinal gate lines are parallel to the data lines, which means that the extension directions of the longitudinal gate lines and the data lines are roughly the same. The specific routing directions of the longitudinal gate lines and the data lines cover a relatively reasonable range and are not limited to the situation where they are completely consistent.

[0038] For ease of explanation, the following embodiments are described in more detail by taking the case where the binding area is located at the lower side of the display screen, the opposite side of the binding is the upper side of the display screen, and the two opposite sides between the upper side and the lower side are the left side and the right side.

[0039] In the above solution, the GOA wiring is rearranged and at least a portion of the GOA is moved to the upper side or the lower side of the display substrate to achieve the purpose of reducing the frame.

[0040] Specifically, by designing at least a portion of the gate drive circuit (GOA circuit) on the binding side of the display substrate (i.e., the lower side of the display substrate) or the binding opposite side (i.e., the upper side of the display substrate), the gate drive circuit layout space on the left and right side frames of the display substrate can be reduced, thereby reducing the frame width; and, for high-frequency settings, since the GOA circuit size needs to be significantly increased in order to increase the driving frequency, the display substrate provided by the embodiment of the present disclosure, by designing at least a portion of the GOA circuit on the upper side, even if the GOA size is significantly increased, it will not cause a large impact on the frame width, and can be reduced, or even will not affect the frame width.

[0041] In the display substrate provided by the present disclosure, a longitudinal gate line 220 is additionally provided, and at least a portion of the transverse gate lines 210 is connected to the longitudinal gate line 220, and is connected to a first gate driving unit located on the opposite side of the binding of the display substrate. In order to avoid interference between the longitudinal gate line 220 and other signal lines, the longitudinal gate line 220 can be provided on a different layer from the transverse gate line 210. In the actual display substrate manufacturing process, a mask process (i.e., a patterning process) can be added to form the longitudinal gate line 220 separately.

[0042] Exemplarily, an insulating layer is provided between the longitudinal gate lines 220 and the transverse gate lines 210 , and the longitudinal gate lines 220 are connected to the corresponding transverse gate lines 210 through via holes in the insulating layer.

[0043] It should be noted that if Figure 2 and Figure 4 As shown, the number of longitudinal grid lines 220 and the arrangement period of the longitudinal grid lines 220 (ie, every few rows of transverse grid lines 210 are connected to longitudinal grid lines 220 ) can be designed according to actual needs and are not limited here.

[0044] It should also be noted that, in the embodiment of the present disclosure, a portion of the GOA circuit may be arranged on the upper side of the display substrate, and the other portion may be arranged on at least one side of the left side and the right side. At this time, the driving timing of the GOA circuits located on the left and right sides and the GOA circuit located on the upper side should be coordinated according to the row number of the horizontal gate line 210 connected to the vertical gate line 220, etc., and the driving IC needs to write the Data signal (data line signal) and the corresponding EM / Gate (gate scan signal line) to open normally to ensure normal writing.

[0045] The display substrate provided by the embodiment of the present disclosure is described below in more detail.

[0046] like Figure 3 As shown, in some embodiments of the present disclosure, the number of the longitudinal gate lines 220 is the same as the number of the transverse gate lines 210, and one of the longitudinal gate lines 220 is connected to a corresponding one of the transverse gate lines 210; the display substrate also includes: a driving chip (driving IC) 500 arranged on the binding side, and the gate driving circuit and the driving chip 500 are connected via a gate driving signal line (i.e., GOA signal line) 600, and the gate driving signal line 600 is arranged in the peripheral area B around the display area AA.

[0047] In the above solution, the GOA circuit is only provided on the upper side of the display substrate, that is, the GOA circuit is completely moved to the upper side of the display substrate. In this way, there are only GOA signal lines 600 on the left and right sides, but no GOA circuit, thereby achieving the purpose of reducing the width of the left and right side borders.

[0048] In the above embodiment, in terms of driving the gate line 200, the longitudinal gate line 220 and the transverse gate line 210 are connected through vias, and the driving timing of the first gate driving unit 410 on the upper side and the transverse gate lines 210 of each row need to be coordinated well, and the Data signal is written through the driving chip 500 and the corresponding EM / Gate (gate scanning signal line) is opened normally to ensure normal writing.

[0049] In addition, in the embodiment of the present disclosure, in order to further reduce the width of the upper side frame, as shown in FIG. Figure 3 and Figure 4 As shown, on the opposite side of the binding, the peripheral area B includes a gate drive circuit area B1 and a bending area B2 located between the display area AA and the gate drive circuit area B1, and the first gate drive unit is arranged in the gate drive circuit area; the longitudinal gate line 220 is connected to the first gate drive unit 410 through the routing on the bending area B2; the bending area B2 is bent from the display surface to the non-display surface of the display substrate to fold the gate drive circuit area B1 to the non-display surface side of the display substrate.

[0050] With the above solution, the GOA circuit is only arranged on the upper side of the display substrate. That is to say, the GOA circuit is completely moved to the upper side of the display substrate. In this way, there are only GOA signal lines on the left and right sides, without the GOA circuit, so as to achieve the purpose of reducing the widths of the left and right borders. At the same time, a routing layout of the bending area B2 (Bending area) is added to the upper side of the display substrate, so that the GOA circuit can be folded to the non-display surface side of the display substrate without occupying the border space of the display substrate, further reducing the border. And for high-frequency settings, since the size of the GOA circuit needs to be greatly increased to increase the driving frequency, therefore, in the display substrate provided by the embodiments of the present disclosure, by designing at least a part of the GOA circuit on the upper side, even if the size of the GOA is greatly increased, it will not affect the border width.

[0051] In addition, in this exemplary embodiment, since the gate driving circuit area B1 and the bending area B2 will be folded to the non-display side of the display substrate, the display substrate includes a packaging layer 800, and the packaging layer 800 does not cover and package the bending area B2 and the gate driving circuit area B1.

[0052] In this exemplary embodiment, as Figure 3 and Figure 4 shown, the display substrate further includes a power supply line 700. In some embodiments, the packaging substrate of the packaging layer 800 can be multiplexed by the VSS line 700. One end of the power supply line 700 is connected to the driving chip 500, and the other end extends along the peripheral area B and is connected to the driving chip 500, and the power supply line 700 surrounds the side of the gate driving signal line 600 away from the display area AA.

[0053] As shown in the figure, in some embodiments, the power supply line 700 can include a low-voltage signal VSS line 700, a VDD line, etc. Among them, the VSS line can be routed in a "冂" shape in the peripheral area B of the display substrate.

[0054] In addition, in some embodiments, the gate driving circuit can be a bidirectional gate driving circuit, including a bidirectional scanning Gate (gate) / Reset (reset signal) GOA circuit and a bidirectional scanning Emission (gate scanning) GOA circuit. <0000​​​​​​

[0057] Table 1

[0058]

[0059] In Table 1 above, AA-Vint refers to the distance between the display area AA and the initial voltage Vint line, Vint-GOA refers to the distance between the initial voltage Vint line and the GOA circuit; GOA-VSS refers to the distance between the GOA circuit and the low voltage signal VSS line 700; VSS-panel edge refers to the distance between the VSS line 700 of the peripheral area B and the edge of the display substrate; Vint-GOA signal line refers to the distance between the initial voltage Vint line and the GOA circuit signal line; GOA signalline-VSS refers to the distance between the GOA circuit signal line and the low voltage signal VSS line 700.

[0060] As can be seen from Table 1 above, the GOA, Vint, and VSS lines are rearranged, and the GOA is completely moved to the upper side of the display substrate. Only the scanning signal lines of the GOA circuit are on the left and right sides. In addition, a bending area B2 (Bending area) is added to the upper side of the display substrate. This allows the GOA circuit to be folded to the back of the panel after the display substrate is completed, without occupying panel space, thereby achieving the purpose of reducing the frame.

[0061] Taking the data in Table 1 as a reference, under the condition of the same circuit width, by moving part of the GOA to the upper side of the display substrate, the border width can be further reduced from 2.5mm to 1.7mm.

[0062] Figure 2 Shown are structural schematic diagrams of other embodiments of the present disclosure.

[0063] like Figure 2 As shown, in other exemplary embodiments, the number of the longitudinal gate lines 220 is less than the number of the transverse gate lines 210, and the gate driving circuit further includes at least one second gate driving unit 420, wherein at least a portion of the transverse gate lines 210 not connected to the longitudinal gate lines 220 is connected to the second gate driving unit 420. That is, in this exemplary embodiment, the gate driving circuit is respectively provided on at least one of the left and right sides and the upper side of the display substrate.

[0064] In this exemplary embodiment, Figure 2 As shown, the display substrate further includes: a driving chip 500 arranged on the binding side, the gate driving circuit and the driving chip 500 are connected via a gate driving signal line 600, and the gate driving signal line 600 is arranged in the peripheral area B around the display area AA.

[0065] In addition, in the present exemplary embodiment, as Figure 2 shown, the display substrate further includes a power supply line 700, for example, a low-voltage signal VSS line, a VDD line, etc. One end of the power supply line 700 is connected to the driving chip 500, and the other end extends along the peripheral area B and is connected to the driving chip 500, and the power supply line 700 surrounds the side of the gate driving signal line 600 away from the display area AA.

[0066] As Figure 2 shown, in some embodiments, the power supply line 700 includes a low-voltage signal VSS line, and the low-voltage signal VSS line 700 has a "冂" - shaped routing in the peripheral area B of the display substrate.

[0067] In addition, in some embodiments, the gate driving circuit may be a bidirectional gate driving circuit, including a bidirectional scanning Gate(栅极) / Reset(复位信号)GOA circuit and a bidirectional scanning Emission(栅极扫描)GOA circuit.

[0068] In addition, in some embodiments, the VDD lines in the display area AA include longitudinal VDD lines and transverse VDD lines, and the longitudinal VDD lines and the transverse VDD lines are arranged crosswise.

[0069] In addition, as Figure 2 shown, in the present exemplary embodiment, the display substrate includes a packaging layer 800, and the packaging layer 800 covers and packages the gate driving circuit area B1.

[0070] It should be noted that, in the present exemplary embodiment, the first gate driving unit 410 on the upper side of the display substrate is covered and packaged by the packaging layer 800. In other embodiments, it may also be that the peripheral area B on the upper side of the display substrate includes a gate driving circuit area and a bending area B2 located between the gate driving circuit area and the display area AA, and the first gate driving unit is disposed in the gate driving circuit area; the longitudinal gate line 220 is connected to the first gate driving unit 410 through the routing on the bending area B2; the bending area B2 bends from the display surface of the display substrate to the non-display surface to fold the gate driving circuit area to the non-display surface side of the display substrate.

[0071] In this way, GOA circuits are arranged on the upper side and left and right sides of the display substrate to achieve the purpose of reducing the width of the left and right side bezels. At the same time, a bending area B2 (Bending area) wiring layout is added to the upper side of the display substrate, so that the GOA circuit can be folded to the non-display side of the display substrate without occupying the bezel space of the display substrate, thereby further reducing the bezel. In addition, for high-frequency settings, since the size of the GOA circuit needs to be significantly increased in order to increase the driving frequency, the display substrate provided by the embodiment of the present disclosure, by designing at least a portion of the GOA circuit on the upper side, will not affect the bezel width even if the GOA size is significantly increased.

[0072] The following table 2 shows a comparison of the border wiring layout space of the display substrate in this exemplary embodiment and the display substrate in the related art.

[0073] Table 2

[0074] Item AA-Vint Vint-GOA GOA-VSS VSS-panel edge Summary Border Design size in related technologies (μm) 100 1000 1000 400 2500 Item AA-Vint Vint-GOA GOA-VSS VSS-Panel edge This example shows the design size of the substrate (μm) 100 600 1000 400 2100

[0075] In Table 2 above, AA-Vint refers to the distance between the display area AA and the initial voltage Vint line, Vint-GOA refers to the distance between the initial voltage Vint line and the GOA circuit; GOA-VSS refers to the distance between the GOA circuit and the low voltage signal VSS line 700; VSS-panel edge refers to the distance between the VSS line 700 of the peripheral area B and the edge of the display substrate.

[0076] As can be seen from Table 2 above, taking the data in Table 2 as a reference, under the condition of the same circuit width, by moving part of the GOA to the upper side of the display substrate, the border width can be further reduced from 2.5mm to 2.1mm.

[0077] In addition, if Figure 5 As shown, in some exemplary embodiments of the present disclosure, the longitudinal gate line 200 and the corresponding transverse gate line connected thereto are connected through a via, and the via connection is the electrical connection position between the longitudinal gate line and the transverse gate line. The extension length of the longitudinal gate line 220 can be extended from the electrical connection position as the starting point to the first gate driving unit 410.

[0078] In other embodiments, Figure 6 As shown, the longitudinal gate line 220 can also be disconnected near the electrical connection position and divided into two parts, namely, a first part 221 connected to the first gate driving unit 410, and a second part 222 disconnected from the first part 221, wherein the second part 222 can be used as a virtual line (dummy); alternatively, the second part 222 can also be connected to the VDD signal to improve the uniformity of the VDD signal.

[0079] In addition, it should be noted that the display substrate includes a source-drain metal layer, and the pattern of the source-drain metal layer includes the source, drain and data line of the thin film transistor, etc., wherein the longitudinal gate line 220 can be formed by patterning the source-drain metal layer, or the longitudinal gate line 220 can also be formed by other conductive film layers, such as a light-shielding metal layer on the display substrate.

[0080] It should be noted that the display substrate provided in the embodiment of the present disclosure may be an AMOLED display substrate, but is not limited to an AMOLED substrate. For example, it may also be an AMQLED substrate, etc.

[0081] In addition, the present disclosure also provides a display device including the display substrate provided in the present disclosure. The display device can be various display products including mobile phones, tablets, monitors, televisions, etc.

[0082] There are a few points to note:

[0083] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0084] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0085] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0086] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A gate line, a data line and a gate driving circuit; wherein the gate line comprises: a plurality of transverse gate lines crossing the data line to define a plurality of sub-pixels, and a plurality of longitudinal gate lines parallel to the data line; wherein the number of the longitudinal gate lines is less than or equal to the number of the transverse gate lines, and one of the longitudinal gate lines is connected to a corresponding one of the transverse gate lines; The display substrate includes a display area and a peripheral area located outside the display area, the peripheral area includes a binding side and a binding opposite side opposite to the binding side, wherein the gate driving circuit includes a first gate driving unit located on the binding side or the binding opposite side, and the longitudinal gate line is connected to the first gate driving unit; wherein, The longitudinal gate lines and the corresponding transverse gate lines are connected via vias, and the via connection is the electrical connection position between the longitudinal gate lines and the transverse gate lines. At least one of the longitudinal gate lines is disconnected near the electrical connection position and is divided into a first part and a second part, the first part is connected to the first gate driving unit, and the second part is disconnected from the first part. The second part serves as a virtual line or the second part is connected to a VDD signal.

2. The display substrate according to claim 1, characterized in that: The number of the longitudinal grid lines is the same as the number of the transverse grid lines, and one of the longitudinal grid lines is connected to a corresponding one of the transverse grid lines.

3. The display substrate according to claim 1, characterized in that: The number of the longitudinal gate lines is less than the number of the transverse gate lines, and the gate driving circuit further includes at least one second gate driving unit, wherein at least part of the transverse gate lines not connected to the longitudinal gate lines are connected to the second gate driving unit.

4. The display substrate according to claim 2 or 3, characterized in that: The display substrate further includes: a driving chip disposed on the binding side, and the gate driving circuit is connected to the driving chip via a gate driving signal line.

5. The display substrate according to claim 4, characterized in that: The gate driving signal lines are arranged in the peripheral area surrounding the display area.

6. The display substrate according to claim 2 or 3, characterized in that: On the opposite side of the binding, the peripheral area includes a gate drive circuit area and a bending area located between the display area and the gate drive circuit area, and the first gate drive unit is arranged in the gate drive circuit area; the longitudinal gate line is connected to the first gate drive unit through the routing on the bending area.

7. The display substrate according to claim 6, characterized in that: The bending region is bent from the display surface of the display substrate to the non-display surface, so as to fold the gate driving circuit region to the non-display surface side of the display substrate.

8. The display substrate according to claim 6, characterized in that: The display substrate includes a packaging layer, and the packaging layer does not cover and package the bending area and the gate driving circuit area.

9. The display substrate according to claim 4, characterized in that: The display substrate further includes a power line, one end of which is connected to the driving chip, and the other end of which extends along the peripheral area and is connected to the driving chip, and the power line is located on a side of the gate driving signal line away from the display area.

10. The display substrate according to claim 6, characterized in that: The display substrate comprises a packaging layer, and the packaging layer covers and packages the gate driving circuit area.

11. The display substrate according to claim 10, characterized in that: The display substrate further comprises: a driving chip disposed on the binding side, and the gate driving circuit is connected to the driving chip via a gate driving signal line; The display substrate further comprises a power line, one end of which is connected to the driving chip, and the other end of which extends along the peripheral area and is connected to the driving chip; The power line is located on a side of the bending area close to the display area, and is located on a side of the gate driving signal line away from the display area.

12. The display substrate according to claim 1, characterized in that: The transverse gate lines and the longitudinal gate lines are arranged in different layers, and an insulating layer is arranged between the longitudinal gate lines and the transverse gate lines. The longitudinal gate lines are connected to the corresponding transverse gate lines through via holes in the insulating layer.

13. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 12.

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