Relay protection device locking signal logic circuit and control method thereof

Abstract

The present application relates to a relay protection device locking signal logic circuit and a control method thereof. The relay protection device locking signal logic circuit includes: a state detection module, which is used to connect the board of the device; the state detection module is used to detect the current operating state of the board, and output a passive locking signal when the current operating state is detected to be a power-on state; a hardware enable control module, one end of which is connected to the state detection module and the other end is used to connect the board; the hardware enable control module is used to output a locking control signal when receiving a passive locking signal or receiving an active locking signal output by the board; the locking control signal is used to instruct the device to perform a locking action; the active locking signal is output when the device determines that there is an abnormality in the device after the board detects it. The present application realizes the active locking function of the relay protection device under normal operation and the passive locking function under abnormal conditions.

Description

Technical Field

[0001] The present application relates to the technical field of power system protection, and in particular to a relay protection device locking signal logic circuit and a control method thereof. Background Art

[0002] With the development of modern electronic technology, relay protection with microprocessor function has been widely used in my country's power automation industry. As the protection function becomes more and more powerful, the types of boards increase, the software program structure becomes more and more complex, and the instruction code becomes longer and longer, the probability of abnormal faults of electrical quantities on site increases exponentially.

[0003] During the implementation process, the inventors found that the conventional technology has at least the following problems:

[0004] Traditional relay protection devices are unable to complete the locking action in a timely manner and have problems with applicability and poor real-time performance. Summary of the invention

[0005] Based on this, it is necessary to provide a relay protection device locking signal logic circuit and a control method thereof to address the above technical problems.

[0006] In order to achieve the above-mentioned object, on the one hand, an embodiment of the present application provides a relay protection device locking signal logic circuit, including:

[0007] A state detection module, which is used to connect to a board of a relay protection device; the state detection module is used to detect the current operating state of the board, and output a passive locking signal when it is detected that the current operating state is a power-on state;

[0008] A hardware enabling control module, one end of which is connected to the status detection module, and the other end of which is used to connect to the board;

[0009] Among them, the hardware enable control module is used to output a locking control signal when it receives a passive locking signal or an active locking signal output by the board; the locking control signal is used to instruct the relay protection device to perform a locking action; the active locking signal is output by the relay protection device when the board detects that there is currently an abnormality in the device.

[0010] In one embodiment, the state detection module includes a monostable trigger circuit; the hardware enable control module includes a latching logic circuit;

[0011] The input end of the monostable trigger circuit is used to access the power detection signal of the board; when the power detection signal is at a low level, the output end of the monostable trigger circuit outputs a passive locking signal;

[0012] One input end of the locking logic circuit is connected to the output end of the monostable trigger circuit, the other input end is used to connect to the board card, and the output end is used to connect to the differential locking bus.

[0013] In one embodiment, the monostable trigger circuit includes a monostable trigger chip, a first resistor, a second resistor and a first capacitor;

[0014] Among them, the first pin and the second pin of the monostable trigger chip are both used to connect to the board, the third pin is connected to one end of the first resistor, the fourth pin is connected to one end of the first capacitor, and the fifth pin is connected to one end of the second resistor; the other end of the first resistor is used to connect to the power supply; the other end of the first capacitor is connected to one end of the first resistor; the other end of the second resistor is used to ground;

[0015] The latching logic circuit includes a two-input AND gate logic chip and a third resistor;

[0016] Among them, the first pin of the two-input AND gate logic chip is connected to the fifth pin, the second pin is used to connect to the board, the second pin is also connected to one end of the third resistor, the third pin is used to connect to the differential locking bus; the other end of the third resistor is used for grounding.

[0017] In one embodiment, it further includes a blocking signal conversion module connected to the hardware enable control module; the blocking signal conversion module is used to connect to the board;

[0018] The locking signal conversion module is used to convert the received locking control signal into a differential bus signal and output it;

[0019] The locking signal conversion module is used to convert the drive bus signal into a single-ended locking signal and output it when receiving the drive bus signal; the single-ended locking signal is used to instruct the board to obtain the locking state of the relay protection device; the drive bus signal is output by the board that drives the differential locking bus in the relay protection device.

[0020] In one of the embodiments, the locking signal conversion module includes a locking signal conversion circuit;

[0021] An input end of the locking signal conversion circuit is used to access the locking control signal; an output end of the locking signal conversion circuit is used to output the differential bus signal to the differential locking bus, and another output end of the locking signal conversion circuit is used to connect the board.

[0022] In one embodiment, the locking signal conversion circuit includes a CAN transceiver chip;

[0023] The first pin of the CAN transceiver chip is used to access the locking control signal, the second pin and the third pin are both used to connect the differential locking bus, and the fourth pin is used to connect the board.

[0024] A control method for a relay protection device locking signal logic circuit is applied to a hardware enabling control module in the above relay protection device locking signal logic circuit, and the method comprises the following steps:

[0025] When receiving a passive blocking signal or an active blocking signal, a blocking control signal is output; the blocking control signal is used to instruct the relay protection device to perform a blocking action;

[0026] Among them, the passive locking signal is output when the board card determines that the current operating state is the power-on state through detection by the status detection module; the active locking signal is output when the relay protection device determines that there is currently an abnormality in the device through detection by the board card.

[0027] A relay protection device comprises a board card and a relay protection device locking signal logic circuit connected to the board card.

[0028] In one embodiment, there are multiple boards.

[0029] A computer-readable storage medium stores a computer program, which implements the steps of the above method when executed by a processor.

[0030] One of the above technical solutions has the following advantages and beneficial effects:

[0031] The present application detects the operating state of the relay protection device board through a state detection module, and outputs a passive locking signal when the operating state is detected to be a power-on state, and outputs an active locking signal when the board detects that the relay protection device is abnormal, and then uses the hardware enabling control module to instruct the relay protection device to perform a locking action according to the received passive locking signal or active locking signal; the present application uses the hardware enabling control module to instruct the relay protection device to perform locking according to the signal output by the state detection module or the board, which solves the problem that the traditional relay protection device cannot complete the locking action in time, and realizes the active locking function of the relay protection device under normal operation and the passive locking function under abnormal conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A module structure diagram of a relay protection device locking signal logic circuit in one embodiment;

[0034] Figure 2 A schematic diagram of the structure of a blocking signal logic circuit of a relay protection device in one embodiment;

[0035] Figure 3 A schematic diagram of a specific structure of a blocking signal logic circuit of a relay protection device in an embodiment;

[0036] Figure 4 It is a module structure diagram of a blocking signal logic circuit of a relay protection device in another embodiment;

[0037] Figure 5 It is a structural schematic diagram of a blocking signal logic circuit of a relay protection device in another embodiment;

[0038] Figure 6 A schematic diagram of the specific structure of a blocking signal logic circuit of a relay protection device in another embodiment;

[0039] Figure 7 The figure is a flow chart of a method for controlling a locking signal logic circuit of a relay protection device in one embodiment. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0044] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0045] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0046] A common method to solve the abnormal fault of electrical quantity on site of relay protection device is to design a lockout signal during circuit design. The basic principle is: when the CPU (Central Processing Unit, referred to as CPU) determines that the device is abnormal or collects abnormal fault electrical quantity, it outputs a lockout signal, drives the lockout relay, and turns off the device operation light to ensure that the device will not malfunction, etc. However, this single-ended signal design method can often only be driven by one CPU, which is not applicable to complex multi-CPU board architecture protection devices or has low real-time performance.

[0047] At the same time, common solutions are generally only effective when the CPU is operating normally. Under the influence of the strong electromagnetic environment at the power site, phenomena such as device loss of control, program "runaway", and various functional modules "freezing" often occur. When the CPU program is stuck in a certain state, it is impossible to give a locking signal in time.

[0048] The relay protection device locking signal logic circuit provided in the present application can promptly complete the active locking action when the on-site electrical quantity of the relay protection device fails abnormally while the protection device is operating normally, and can also promptly complete the passive locking action when the protection device is abnormal.

[0049] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] In one embodiment, Figure 1 As shown, a relay protection device locking signal logic circuit is provided, and the relay protection device locking signal logic circuit is applied to a relay protection device as an example for explanation, and may include:

[0051] The state detection module 110 is used to connect the board of the relay protection device; the state detection module 110 is used to detect the current operating state of the board, and output a passive locking signal when it is detected that the current operating state is a power-on state;

[0052] A hardware enabling control module 120, one end of which is connected to the status detection module 110, and the other end of which is used to connect to a board;

[0053] Among them, the hardware enable control module 120 is used to output a locking control signal when it receives a passive locking signal or an active locking signal output by a board card; the locking control signal is used to instruct the relay protection device to perform a locking action; the active locking signal is output by the relay protection device when the board card detects that there is currently an abnormality in the device.

[0054] Specifically, Figure 1 As shown, the state detection module 110 can detect the operating state of the board, which can refer to the CPU in the relay protection device. In some examples, the operating state of the board in the present application can include the state that the board is currently powered on, the board is operating abnormally, and the board is operating normally;

[0055] In the present application, the state detection module 110 can detect the operating state of the board power supply. When the operating state is detected to be the power-on state, a passive locking signal is output. In a specific example, the passive locking signal can also be output when the state detection module 110 detects the operating state of the board after the board power supply is powered on and is abnormally operated.

[0056] It should be noted that the state detection module 110 in the present application can determine the current operating state of the above-mentioned board by detecting the received pulse signal and / or level signal; in some embodiments, the state detection module 110 can be implemented using a corresponding chip or circuit structure. In some examples, the active locking signal can be output when the board detects an abnormality in the relay protection device when the board is operating normally. When the hardware enable control module 120 receives the above-mentioned passive locking signal or active locking signal, it outputs a locking control signal, which can be used to instruct the relay protection device to lock.

[0057] In the present application, the hardware enabling control module 120 may perform a logic AND operation on the acquired signals and output the result of the logic AND operation. In some embodiments, the hardware enabling control module 120 may be implemented using a corresponding chip or circuit structure.

[0058] As described above, the present application instructs the relay protection device to perform locking according to the signal output by the status detection module 110 or the board through the hardware enabling control module 120, thereby realizing the active locking function under normal operation of the relay protection device and the passive locking function under abnormal conditions. Based on the present application, it is possible to ensure that the device is in a locked state during uncertain conditions such as the device power-on process and the board CPU software program loading process, effectively avoiding the occurrence of misoperation of the protection device.

[0059] In one embodiment, the state detection module 110 may include a monostable trigger circuit; the hardware enable control module 120 may include a latching logic circuit;

[0060] The input end of the monostable trigger circuit is used to access the power detection signal of the board; when the power detection signal is at a low level, the output end of the monostable trigger circuit outputs a passive locking signal;

[0061] One input end of the locking logic circuit is connected to the output end of the monostable trigger circuit, the other input end is used to connect to the board card, and the output end is used to connect to the differential locking bus.

[0062] Specifically, if Figure 2As shown, one input end of the monostable trigger circuit can be used to access the power detection signal of the board. Further, the power detection signal can be the power detection signal PWROK of the board. When the power detection signal PWROK is at a low level, the monostable trigger circuit outputs a passive blocking signal. In some examples, the other input end of the monostable trigger circuit can be used to access the IO_STALL of the board. The IO_STALL pin can output a pulse signal of a certain period to the monostable trigger circuit to detect whether the CPU program running in the board is running normally. When the CPU program is in abnormal operation, the abnormal operation of the program can be that the CPU program runs away or the CPU program runs to death, driving the monostable trigger circuit to output a passive blocking signal. In some examples, the other input end of the blocking logic circuit can be used to connect to the IO_BS_TX of the board.

[0063] In one embodiment, the monostable trigger circuit may include a monostable trigger chip U1, a first resistor R1, a second resistor R2 and a first capacitor C1;

[0064] Among them, the first pin and the second pin of the monostable trigger chip U1 are both used to connect to the board, the third pin is connected to one end of the first resistor R1, the fourth pin is connected to one end of the first capacitor C1, and the fifth pin is connected to one end of the second resistor R2; the other end of the first resistor R1 is used to connect to the power supply; the other end of the first capacitor C1 is connected to one end of the first resistor R1; the other end of the second resistor R2 is used to be grounded;

[0065] The latching logic circuit may include a two-input AND gate logic chip U2 and a third resistor R3;

[0066] Among them, the first pin of the two-input AND gate logic chip U2 is connected to the fifth pin of the monostable trigger chip U1, the second pin is used to connect to the board, the second pin is also connected to one end of the third resistor R3, and the third pin is used to connect to the differential locking bus; the other end of the third resistor R3 is used for grounding.

[0067] Specifically, in some examples, the monostable trigger chip U1 can be implemented using the domestic logic chip AiP74HC123SA.TB. Taking the domestic logic chip AiP74HC123SA.TB applied to the monostable trigger circuit as an example, the first pin of the monostable trigger chip U1 is 1RD, the second pin is 1A, the third pin is 1RC, the fourth pin is 1C, and the fifth pin is 1Q; in a specific example, the sixth pin of the monostable trigger chip U1 is 1B;

[0068] Among them, the 1RD pin and the 1A pin can be used to connect the board, the 1RC pin is connected to one end of R1, the 1C pin is connected to one end of C1, the 1Q pin is connected to one end of R2, and the 1B pin is connected to one end of R4; the other end of R1 is used to connect to the power supply; the other end of C1 is connected to one end of R1; the other end of R2 is used for grounding; the other end of R4 is used to connect to the power supply;

[0069] Specifically, the 1RD pin can be a low level or rising edge trigger pin, which can be used to access the power detection signal PWROK of the board. When the power supply is abnormal, PWROK will become a low level; the 1A pin can be used to connect the IO_STALL of the board, where the IO_STALL pin needs to output a pulse signal of a certain period to the monostable trigger chip U1 to detect whether the CPU program is running normally; the 1Q pin can be a low level output pin, that is, it outputs a low level valid signal; the 1B pin can be a rising edge trigger input pin; R1 can be an external time resistor, and C1 can be an external time capacitor. According to the resistance value of R1 and the capacitance value of C1, the time sensitivity for detecting whether the CPU program is normal can be flexibly set. In some examples, the period t of the pulse signal provided by the IO_STALL pin of the board can be calculated by the following formula:

[0070] t=0.45×R1×C1

[0071] Among them, the unit of t is nanosecond, the unit of R1 is kiloohm, and the unit of C1 is picofarad.

[0072] Take the two-input AND gate logic chip U2 used in the latching logic circuit as an example. The first pin of the two-input AND gate logic chip U2 is A, the second pin is B, and the third pin is F; among them, the A pin is connected to the 1Q pin of the monostable trigger chip U1 to access the low-level output signal, the B pin is used to connect to the board, the B pin is also connected to one end of R3, and the F pin is used to connect the differential latching bus; the other end of R3 is used for grounding. In some examples, the B pin can be used to connect to the IO_BS_TX of the board.

[0073] In order to further illustrate the solution of the present application, a specific example is given below. Figure 3As shown, when the device is initially powered on, the power detection signal PWROK is at a low level, driving the 1Q pin of the monostable trigger chip U1 to output a low level. Since U2 is an AND gate logic chip, the output pin F of U2 is also at a low level, making the differential signal end at a dominant level, and the differential locking bus signal is valid, thereby driving the relay protection device to lock; in a specific example, after the board power is powered on, the power detection signal PWROK outputs a high level. At this time, the locking state decision is transferred to the board. Only when all the CPU software programs running in the board are loaded and run normally, and according to the time period determined by the external time resistor and time capacitor of the monostable trigger, the IO_STALL pin of the board stably outputs a pulse signal, can it be ensured that the device is not locked; in some examples, the board can also drive the B pin of U2 through its own IO_BS_TX pin, thereby actively locking.

[0074] The above-mentioned relay protection device blocking signal logic circuit detects the running status of the board power supply and the CPU program through a monostable trigger circuit. When one of the two is abnormal, a passive blocking signal is output. The passive blocking signal and the active blocking signal output by the board are further logically ANDed through the blocking logic circuit, and the active blocking signal has both active blocking and passive blocking functions. It ensures that the device is in a blocking state in uncertain states such as the device power-on process and the CPU software program loading process, effectively avoiding the occurrence of false operation of the protection device.

[0075] In one embodiment, Figure 4 As shown, a relay protection device locking signal logic circuit is provided, and the relay protection device locking signal logic circuit is applied to a relay protection device as an example for explanation, and may include:

[0076] The state detection module 210 is used to connect the board of the relay protection device; the state detection module 210 is used to detect the current operating state of the board, and output a passive locking signal when it is detected that the current operating state is a power-on state;

[0077] A hardware enabling control module 220, one end of which is connected to the state detection module 210, and the other end of which is used to connect to a board;

[0078] It also includes a locking signal conversion module 230 connected to the hardware enable control module 220; the locking signal conversion module 230 is used to connect the board;

[0079] The hardware enabling control module 220 is used to output a locking control signal when receiving a passive locking signal or an active locking signal output by a board; the locking control signal is used to instruct the relay protection device to perform a locking action; the active locking signal is output when the relay protection device determines that there is an abnormality in the device after the board detection; the locking signal conversion module 230 is used to convert the received locking control signal into a differential bus signal and output it;

[0080] The locking signal conversion module 230 is used to convert the driving bus signal into a single-ended locking signal and output it when receiving the driving bus signal; the single-ended locking signal is used to instruct the board to obtain the locking state of the relay protection device; the driving bus signal is output by the board that drives the differential locking bus in the relay protection device.

[0081] Specifically, the related functions of the state detection module 210 and the hardware enabling control module 220 can be implemented in the manner of the state detection module 110 and the hardware enabling control module 120 mentioned above, and will not be described in detail here.

[0082] like Figure 4 As shown, the lockout signal conversion module 230 can be used to convert the lockout control signal output by the hardware enable control module 220 into a differential bus signal and output it; the lockout signal conversion module 230 can also be used to convert the drive bus signal into a single-ended lockout signal and output it when receiving a drive bus signal; wherein, taking the lockout signal conversion module 230 applied to a relay protection device as an example, the single-ended lockout signal is used to instruct the board to obtain the lockout state of the relay protection device; the drive bus signal can be the output of the board that drives the differential lockout bus in the relay protection device.

[0083] In the above-mentioned relay protection device locking signal logic circuit, the locking control signal is converted into a differential bus signal and output through the locking signal conversion module 230, which improves the signal's anti-interference ability and makes the device safer and more reliable. The locking control signal is designed in a bus form to facilitate the simultaneous use of multiple boards; and when the locking signal conversion module 230 receives a drive bus signal, the drive bus signal is converted into a single-ended locking signal and output, so that the board can collect the single-ended locking signal and output the corresponding control commands in time, such as sending messages to the monitoring host and closing the action output.

[0084] In one embodiment, the lockout signal conversion module 230 may include a lockout signal conversion circuit;

[0085] An input end of the locking signal conversion circuit is used to access the locking control signal; an output end of the locking signal conversion circuit is used to output the differential bus signal to the differential locking bus, and another output end of the locking signal conversion circuit is used to connect the board.

[0086] In order to further illustrate the solution of the present application, a specific example is given below. Figure 5 As shown, the other output end of the locking signal conversion circuit can be used to connect to the IO_BS_RX of the board.

[0087] In one embodiment, the locking signal conversion circuit includes a CAN transceiver chip U3;

[0088] The first pin of the CAN transceiver chip U3 is used to access the locking control signal, the second pin and the third pin are both used to connect the differential locking bus, and the fourth pin is used to connect the board.

[0089] Specifically, in some embodiments, the CAN transceiver chip U3 can be implemented using a domestic CAN chip SIT65HVD234DR. Taking the application of the domestic CAN chip SIT65HVD234DR in the locking signal conversion circuit as an example, the first pin of the CAN transceiver chip U3 is D, the second pin is H, the third pin is L, and the fourth pin is R; wherein the D pin is used to access the locking control signal, the H pin and the L pin are both used to connect the differential locking bus, and the R pin is used to connect the board;

[0090] In order to further illustrate the solution of the present application, a specific example is given below. Figure 6 As shown, the D pin can be a single-ended transmission signal pin; the R pin can be a single-ended reception signal pin, which can be used to connect the IO_BS_RX pin of the board; the H pin and the L pin are differential signal pins. After the D pin is connected to the locking control signal, it obtains a low level, which further makes the differential signal end (H pin and L pin) at a dominant level, and the differential locking bus signal is valid, so that the device performs a locking action. When other boards drive the differential locking bus, the board can read the low level state of the R pin of U3 through the IO_BS_RX pin, obtain the locking state of the device at the first time, and make corresponding logical processing in a timely and effective manner.

[0091] In the above-mentioned relay protection device locking signal logic circuit, the signal conversion function of the locking signal conversion circuit is used to realize the flexible driving of the differential locking bus by the multi-board architecture protection device, and to facilitate the above-mentioned board to obtain the locking status of the device and make corresponding logical processing in a timely and effective manner.

[0092] In one embodiment, Figure 7 As shown, a control method for a relay protection device locking signal logic circuit is provided. The method is applied to a hardware enabling control module in the above relay protection device locking signal logic circuit as an example for explanation. The method may include the following steps:

[0093] Step 702: when a passive locking signal or an active locking signal is received, a locking control signal is output; the locking control signal is used to instruct the relay protection device to perform a locking action;

[0094] Among them, the passive locking signal is output when the board card determines that the current operating state is the power-on state through detection by the status detection module; the active locking signal is output when the relay protection device determines that there is currently an abnormality in the device through detection by the board card.

[0095] The control method of the above-mentioned relay protection device locking signal logic circuit, through the hardware enabling control module, instructs the relay protection device to perform the locking action according to the signal received from the status detection module or the board, thereby realizing the active locking function of the relay protection device under normal operation and the passive locking function under abnormal conditions.

[0096] It should be understood that although Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0097] In one embodiment, a relay protection device is provided, including a board card, and the above-mentioned relay protection device locking signal logic circuit connected to the board card.

[0098] In one embodiment, there are multiple boards.

[0099] Specifically, all boards can be connected to the differential locking bus. Furthermore, any board connected to the differential locking bus can both drive the locking action and read the state of the differential locking bus.

[0100] In the present application, when other boards drive the differential locking bus, the board mentioned above can directly obtain the locking state of the device through the locking signal conversion module at the first time, and make corresponding logical processing in a timely and effective manner.

[0101] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the control method of the locking signal logic circuit of the relay protection device are implemented.

[0102] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0103] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0104] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A relay protection device locking signal logic circuit, characterized in that: include: A status detection module, wherein the status detection module is used to connect to a board of a relay protection device; The state detection module is used to detect the current running state of the board, and outputs a passive locking signal when it is detected that the current running state is a power-on state; the state detection module includes a monostable trigger circuit; the input end of the monostable trigger circuit is used to access the power detection signal of the board; when the power detection signal is at a low level, the output end of the monostable trigger circuit outputs the passive locking signal; the other input end of the monostable trigger circuit is used to access the IO_STALL pin of the board, and the IO_STALL pin is used to output a pulse signal of a certain period to the monostable trigger circuit to detect whether the CPU program running in the board is running normally; A hardware enabling control module, one end of which is connected to the state detection module, and the other end of which is used to connect to the board; Among them, the hardware enable control module is used to output a locking control signal when it receives the passive locking signal or receives the active locking signal output by the board; the locking control signal is used to instruct the relay protection device to perform a locking action; the active locking signal is output by the relay protection device when the board detects and determines that there is currently an abnormality in the device.

2. The relay protection device locking signal logic circuit according to claim 1, characterized in that: The hardware enable control module includes a locking logic circuit; One input end of the locking logic circuit is connected to the output end of the monostable trigger circuit, the other input end is used to connect to the board card, and the output end is used to connect to the differential locking bus.

3. The relay protection device locking signal logic circuit according to claim 2, characterized in that: The monostable trigger circuit comprises a monostable trigger chip, a first resistor, a second resistor and a first capacitor; The first pin and the second pin of the monostable trigger chip are both used to connect to the board, the third pin is connected to one end of the first resistor, the fourth pin is connected to one end of the first capacitor, and the fifth pin is connected to one end of the second resistor; the other end of the first resistor is used to connect to a power supply; the other end of the first capacitor is connected to one end of the first resistor; and the other end of the second resistor is grounded; The latching logic circuit includes a two-input AND gate logic chip and a third resistor; Among them, the first pin of the two-input AND gate logic chip is connected to the fifth pin, the second pin is used to connect to the board, the second pin is also connected to one end of the third resistor, and the third pin is used to connect to the differential locking bus; the other end of the third resistor is used for grounding.

4. The relay protection device locking signal logic circuit according to any one of claims 1 to 3, characterized in that: It also includes a locking signal conversion module connected to the hardware enable control module; the locking signal conversion module is used to connect to the board; Wherein, the locking signal conversion module is used to convert the received locking control signal into a differential bus signal and output it; The locking signal conversion module is used to convert the drive bus signal into a single-ended locking signal and output it when receiving the drive bus signal; the single-ended locking signal is used to instruct the board to obtain the locking state of the relay protection device; the drive bus signal is output by the board that drives the differential locking bus in the relay protection device.

5. The relay protection device locking signal logic circuit according to claim 4, characterized in that: The locking signal conversion module includes a locking signal conversion circuit; The input end of the locking signal conversion circuit is used to access the locking control signal; an output end of the locking signal conversion circuit is used to output the differential bus signal to the differential locking bus, and the other output end of the locking signal conversion circuit is used to connect to the board.

6. The relay protection device blocking signal logic circuit according to claim 5, characterized in that: The locking signal conversion circuit includes a CAN transceiver chip; The first pin of the CAN transceiver chip is used to access the locking control signal, the second pin and the third pin are both used to connect to the differential locking bus, and the fourth pin is used to connect to the board.

7. A control method for a relay protection device locking signal logic circuit, characterized in that: The method is applied to a hardware enabling control module in a blocking signal logic circuit of a relay protection device according to any one of claims 1 to 6, and the method comprises the following steps: When receiving the passive locking signal or the active locking signal, outputting the locking control signal; the locking control signal is used to instruct the relay protection device to perform a locking action; Among them, the passive locking signal is output by the board when the state detection module determines that the current operating state is the power-on state; the active locking signal is output by the relay protection device when the board detects that there is currently an abnormality in the device.

8. A relay protection device, characterized in that: It comprises a board card, and a relay protection device locking signal logic circuit according to any one of claims 1 to 6 connected to the board card.

9. The relay protection device according to claim 8, characterized in that: The number of the boards is multiple.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method described in claim 7 are implemented.

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