Memory circuit arrangement for accurate and secure reading

Abstract

Embodiments of the present disclosure relate to memory circuit arrangements for accurate and secure reads. The present disclosure relates to the arrangement of user data memory cells and test memory cells in a configurable memory array that can perform differential and single-ended read operations during memory startup and normal memory usage, respectively. The different arrangement of user data memory cells and test memory cells in the memory array results in an improvement in the effectiveness of the memory array in terms of area optimization, memory read accuracy, and encryption for data security.

Description

TECHNICAL FIELD

[0001] During a boot operation of a non-volatile memory (NVM), trim and configuration bits are provided to components of a system on a chip (SOC), including a reference current block that provides a stable current to components of the SOC. BACKGROUND

[0002] The NVM can be read with differential reads or single-ended reads. To perform a differential read, where each byte is stored in two physical cells called a direct cell and a complementary cell. The same byte is stored as a logical 1 in the direct cell and as a logical 0 in the complementary cell, and vice versa.

[0003] When a read operation is performed on a cell, the current from the direct cell and its complementary cell is compared using a sense amplifier. The output of the sense amplifier is either high or low. In some cases, a high sense amplifier output will indicate that an erased cell has been read, and a low sense amplifier output will indicate that a programmed cell has been read. In other cases, a high sense amplifier output will indicate that a programmed cell has been read, and a low sense amplifier output will indicate that an erased cell has been read.

[0004] During a boot operation, differential reads eliminate the dependency on the availability of a reference current from a bandgap or current reference block. There is an NVM array that includes cells for differential reads and cells for single-ended reads. SUMMARY

[0005] A primary memory array includes a plurality of configurable rows that each have a plurality of memory cells. The memory cells have two types, including user memory cells and test memory cells. The user memory cells include information or data to be stored in the memory. The test memory cells are configuration or trim bits to be used at boot up or in a boot operation. The test memory cells have two types, including test data memory cells and complementary test data memory cells.

[0006] The configurable rows of the present disclosure can be configured as user memory cells or test memory cells. Each memory cell can be configured as a test memory cell or a user memory cell. For example, a single row can include user memory cells and test memory cells. In a first configuration, a first cell of the row can be used as a user memory cell. In a second configuration, the first cell of the row can be used as a test memory cell.

[0007] The primary memory array includes a plurality of columns of memory cells. The primary memory array includes a plurality of word lines such that each configurable row is coupled to a word line. The primary memory array also has a plurality of bit lines such that a bit line is coupled to each column. A column multiplexer is coupled to the plurality of bit lines. The column multiplexer includes a first plurality of transistors, where each transistor is coupled to one of the plurality of bit lines. There are at least two rows of the first plurality of transistors. In some embodiments, each row of the first plurality of transistors includes two groups of transistors.

[0008] The column multiplexer also has a plurality of group select transistors, where each group select transistor is coupled to one of the two groups of transistors of the first plurality of transistors. The column multiplexer also has two types of mode select transistors. One type of mode select transistor (first mode select transistor) is coupled to an inverter and the other type includes a plurality of second mode select transistors. Each of the second mode select transistors is coupled to one of the group select transistor group. A sense amplifier is coupled to the column multiplexer, which includes an operational amplifier and two current to voltage converters coupled to the operational amplifier. The mode select transistors are coupled to the current to voltage converters. A reference current transistor switch is coupled to the first mode select transistor through the inverter. The source of the reference current transistor switch is coupled to a reference memory cell array, which can be used to provide a reference current to the primary memory array for a single ended read operation.

[0009] During a boot operation, NVM read operations are not reliable in the absence of a stable reference current from a bandgap or current reference block. At the same time, the bandgap or current reference block cannot provide a stable current to the NVM primary array as reliable trim and configuration bits cannot be obtained from the NVM. Therefore, these trim and configuration bits are stored in test memory cells to be read in a differential manner during the boot operation.

[0010] In one embodiment, the reference current can also be generated using a reference memory cell array instead of a bandgap or reference current generator. The reference memory cell array includes one or more memory cells that are formed in the same process as the memory cells of the primary memory array. Therefore, the response to process and temperature variations of the reference memory cell array is similar to the primary memory cell array, which results in better accuracy of the single ended read operation. The accuracy of the reference current obtained from the reference memory cell array is adjustable by selecting a plurality of memory cells to generate the reference current. The reference current is generated based on an average of all selected memory cells in the reference current array. By selecting a larger number of memory cells to generate the reference current, the accuracy of the reference current is improved, which is an average of all selected cells.

[0011] The primary memory array can have a plurality of memory cells arranged as two or more rows of words, such that the cells in each row are test memory cells and user memory cells. The test memory cells are of two types: data memory cells and their complements, referred to as complementary data memory cells. The data in a data memory cell is also stored in its complementary data memory cell for differential read operations. In this disclosure, each row can contain data memory cells, associated complementary data memory cells, and user memory cells, such that the row can have a single-ended read portion and a differential read portion. In one arrangement, a first set of user memory cells is spaced apart from a second set of user memory cells of a single row by the data and complementary data memory cells of the same row. Alternatively, each row can also be configured such that the data memory cells and complementary data memory cells are spaced apart from each other by user memory cells. In this embodiment, each row can be configured in various orientations of user data memory cells, data memory cells, and complementary data cells to provide flexibility of usage. This can be adjusted when the user stores data based on parameters of usage of the memory array. This allows for optimal usage of the area of the primary memory array.

[0012] In another embodiment, the primary memory array can have memory cells arranged as two or more consecutive rows of words, where the placement of the memory cells in one row is the same as the placement of the memory cells in another row. During usage, instead of obtaining a current from a single memory cell to be read, an average current is taken by selecting the same cells from two or more consecutive rows. The average current of two or more identical memory cells allows for a more accurate reading of the memory cell compared to reading a single cell.

[0013] In another embodiment where differential reading is implemented, more than one row of memory cells of the memory array can be configured such that data memory cells are in one row and associated complementary data memory cells are in another row. The rows can be physically adjacent to each other, or the rows can be separated by other rows of the memory array. This arrangement allows for a more secure read operation by providing immunity to data hacking. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a block diagram of components of a system on a chip;

[0015] Figure 2 is an array of memory cells and circuit components for differential and single-ended reading;

[0016] Figure 3 and 4A is a column decoder according to an embodiment of the present application;

[0017] Figure 4Bis Figure 4A truth table for a column decoder of

[0018] Figure 5 and 6 is Figure 2 an array of memory cells of

[0019] Figure 7 is a word line including a plurality of memory cells having single-ended and differential read cells;

[0020] Figure 8 is a plurality of consecutive word lines each having a plurality of memory cells and circuit components to generate more reliable read information;

[0021] Figure 9 is a plurality of consecutive word lines each having a plurality of memory cells and circuit components for data encryption and data security related applications in alternative embodiments of the present disclosure; and

[0022] Figure 10 is an enhanced view of a reference current generator of Figure 2 DETAILED DESCRIPTION

[0023] Figure 1 is a block diagram of components of a system on a chip (SOC) 100 including a non-volatile memory (NVM) array 102 coupled to a data bus 108. The NVM array 102 includes a user memory section 112, a boot code section 114, and a trim data section 116. The user memory section 112 stores data associated with user usage of the memory. The boot code section 114 includes data associated with the startup of the memory array. The trim data section 116 includes calibration information that can be used during the startup of the memory array along with the boot code section 114 data.

[0024] The NVM array 102 is coupled to a system random access memory (RAM) 118 through the bus 108. The system RAM 118 is used in conjunction with the NVM array 102 during operation of the SOC 100. The user memory 112 is non-volatile memory from which data is copied onto the system RAM 118 (which is volatile memory) at the time of startup of the SCO 100. Data is copied from the user memory 112 into the system RAM 118 to enable high frequency communication with the microcontroller 106. When the SOC 100 is turned off, the data from the system RAM 118 is erased. In contrast, the data in the user memory 112 is retained even after the SOC 100 is turned off.

[0025] ​An input / output (I / O) controller 126 is coupled to the bus 108 for controlling and monitoring data coming into and going out of the SOC 100. A microcontroller 106 is also on the SOC 100 and is coupled to the bus 108. Additional digital logic can be included in the SOC 100 as glue logic 120. A digital-to-analog converter and analog-to-digital converter (ADC DAC) block 122 of the SOC 100 receives trim bits from the trim data block 116 of the NVM array 102 for calibration. An oscillator block 124, coupled to the NVM array 102 with electrical connections 110, is used to generate a time clock that receives configuration bits from the boot code block 114 of the NVM array 102. A bandgap current reference block 104 is coupled to the NVM array 102 that provides a reference current to the user memory 112 of the NVM array 102 after the SOC 100 is started up.

[0026] During a boot or start-up operation of the SOC 100, the NVM array 102 read operations are not reliable in the absence of a stable reference current from the bandgap current reference block 104. At the same time, the bandgap current reference block 104 is unable to provide a stable reference current to the NVM array 102 because reliable trim and configuration bits cannot be obtained from the NVM array 102. In this regard, these trim and configuration bits are stored in a test or start-up parameter memory unit to be read in a differential manner during the boot operation.

[0027] Figure 2 is an array 200 of memory cells and circuit components for differential and single-ended reads. The memory array 200 includes a primary memory cell array 201 coupled to a bit line or column multiplexer 220 that is coupled to a sense amplifier 232. The primary memory cell array 201 includes a plurality of memory sectors 203 that each include a plurality of memory cell rows 202. Each of the plurality of memory cell rows 202 includes a plurality of memory cells 206. In this embodiment, each of the plurality of memory sectors 203 has two memory cell rows, namely, a first memory cell row 244 and a second memory cell row 246. In other embodiments, each memory sector 203 can have more than two memory cell rows.

[0028] Each of the plurality of memory cell rows 202 includes an even number of memory cells of the plurality of memory cells 206. The even number of memory cells 206 are divided into two groups, namely, a first group 205 and a second group 207. The first group 205 and the second group 207 are coupled to the column multiplexer 220, the operation of which is described in more detail below.

[0029] Multiple memory cell rows 202 can be configured as multiple user memory cell rows 212 (see sector) <0> and sectors <1> ) or multiple test memory cell rows 214 (see sector) <n>). The memory cells 206 of the user memory cell row 212 can be configured as data storage elements to store data for all activities except for SOC boot operations. The memory cells 206 of the test memory cell row 214 can be configured as test memory cells where data is stored for the purpose of SOC boot operations that are configured for differential reads that do not rely on a reference current. The test memory cells have two types, data storage cells 216 (labeled DO through D15) and complementary data storage cells 218 (labeled CO through C15). The primary memory cell array 201 also includes a plurality of word lines 208 such that each word line of the plurality of word lines 208 is coupled to each row of the plurality of memory cell rows 202. The primary memory cell array 201 also includes a plurality of bit lines 210. In embodiments where each sector 203 has two rows 202, a first bit line 209 is coupled to the first row 244 and a second bit line 211 is coupled to the second row 246 (see sector <0>). The first bit line 209 is coupled to each first row 244 of each sector 203 and the second bit line 211 is coupled to each second row 246 of each sector 203.

[0030] The plurality of memory cell columns 204 are coupled to a column multiplexer 220. Each column will include one memory cell from each row of a sector. Bit lines are coupled to every other row of the column. The columns 204 will be discussed below with respect to operation of the memory array.

[0031] The column multiplexer 220 includes a first plurality of rows of bit line select transistors 222 where each transistor of the first plurality of bit line select transistors 222 is coupled to a unique bit line of the plurality of bit lines 210. Each row of the first plurality of bit line select transistors 222 includes a first group 219 and a second group 221 of transistors. The first group of memory cells 205 of each row is coupled to the first group 219 of the first plurality of bit line select transistors 222. The second group of memory cells 207 of each row is coupled to the second group 221 of the first plurality of bit line select transistors 222. The plurality of rows of bit line select transistors 222 are arranged as a first row of bit line select transistors 248 and a second row of bit line select transistors 250. The transistors in the first row of bit line select transistors 248 are coupled to the transistors of the second memory cell row 246 of the memory sector 203 through the second bit line 211. The transistors in the second row of bit line select transistors 250 are coupled to the transistors of the first memory cell row 244 of the memory sector 203 through the first bit line 209. The column multiplexer 220 also includes a plurality of group select transistors including a first group 224 and a second group 225 where each transistor of the plurality of group select transistors 224 is coupled to a group 219 of the plurality of bit line select transistors 222 and each transistor of the plurality of group select transistors 225 is coupled to a group 221 of the plurality of bit line select transistors 222.

[0032] The array of primary memory cells 201 can be read in a differential read mode or a single-ended read mode. The column multiplexer 220 includes a plurality of mode selection transistors 226 that facilitate the differential and single-ended read modes. In the differential read mode, two memory cells 206 are used to store a data bit, i.e., one memory cell 206 in the first group 205 and another memory cell 206 in the second group 207. In the single-ended read mode, each of the memory cells 206 is used for one data bit. Each of the plurality of mode selection transistors 226 is coupled to a group of the plurality of group selection transistors 224 and 225. For example, the plurality of transistors Y0<0> through Y0<7> of the first group 219 of the first row bit line selection transistors 248 are coupled to the transistor YM<1> in the first group of group selection transistors 224. The transistor YM<1> is coupled to YN<0> of the first type of mode selection transistor 228 and YN<1> of the second type of mode selection transistor 230. The plurality of transistors Y0<0> through Y0<7> of the first group 219 of the second row bit line selection transistors 250 are coupled to the transistor YM<0> in the first group of group selection transistors 224. The transistor YM<0> is coupled to YN<0> of the first type of mode selection transistor 228 and YN<1> of the second type of mode selection transistor 230. Similar arrangements apply to the second group 221 as can be seen in Figure 2 .

[0033] The two types of model selection transistors 226 include the first type of mode selection transistor 228 (YN<0>) and the second type of mode selection transistor 230 (YN<1> and YN<2>), where each of the mode selection transistors 226 has a gate terminal, a source terminal, and a drain terminal. The column multiplexer 220 is coupled to a sense amplifier 232 through the mode selection transistors 226. The sense amplifier includes a first current to voltage converter 241 and a second current to voltage converter 242, which are both coupled to an operational amplifier 234. A reference current transistor switch 238 is coupled to the second current to voltage converter 242 and a reference current generator with memory cell array 240. This can be considered a replica offset generator that tracks the current of the memory cell through temperature, process, voltage, etc.

[0034] The gate terminal of the first type of mode selection transistor 228 is coupled through an inverter 236 to the gate terminal of a reference current transistor switch 238. The source terminal of the first type of mode selection transistor 228 is coupled to the input of a second current to voltage converter 242. The source terminals of the second type of mode selection transistor 230 of the plurality of mode selection transistors 226 are coupled together and to the input of a first current to voltage converter 241. The output of the first current to voltage converter 241 is coupled to the input of the positive terminal of an operational amplifier 234. The output of the second current to voltage converter 242 is coupled to the input of the negative terminal of the operational amplifier 234.

[0035] Figure 3 A column decoder 300 is included for selecting one or more mode selection transistors YN<0>, YN<1>, and YN<2> from the plurality of mode selection transistors 226. The column decoder 300 includes a plurality of level shifters 302, a plurality of inputs 312 coupled to the level shifters 302, and an inverter 310. A first level shifter 304 of the plurality of level shifters 302 and the inverter 310 receive a differential enable signal 314. A second level shifter 306 of the plurality of level shifters 302 receives an input signal 316, which is the output of the inverter 310. The output signal 316 of the inverter 310 is the inverted differential enable signal 314. A third input signal 318 is the input to a level shifter 308 of the plurality of level shifters 302.

[0036] The plurality of level shifters 302 raise or lower the voltage level of the plurality of inputs 312 for the plurality of level shifters 302. A plurality of output signals 320 are output from the plurality of level shifters 302. A first output signal 322 of the plurality of outputs 320 is output from the level shifter 304, a second output signal 324 of the plurality of output signals 320 is output from the level shifter 306, and a third output signal 326 of the plurality of output signals 320 is output from the level shifter 308. The output signal 322 is coupled to the gate of the first type of mode selection transistor 228. The outputs 324 and 326 are connected to the gates of the two mode selection transistors 231, 233 of the second type 230.

[0037] As explained above, Figure 2 The memory array 200 in Figure 3 can be read in either a differential read mode or a single-ended read mode. For a differential read of the memory array, the differential enable signal 314 is held high, and for a single-ended read of the memory array, the differential enable signal 314 is held low. When the differential enable signal 314 is high, then the mode select transistor switch 231 is open, and the mode select transistor switches 228 and 233 are on. When the differential enable signal 314 is low, then the mode select transistor switch 228 is open, and the mode select transistor switches 231 and 233 are on.

[0038] Figure 4 includes another column decoder 400 for selecting one or more group select transistors YM<0> and YM<1> from a plurality of group select transistors 223, for example. The column decoder 400 includes a plurality of inverters 401 coupled to a plurality of address bits 404. There are a plurality of outputs 423 of the plurality of inverters 401. There are a plurality of AND gates 407 coupled to a plurality of level shifters 412. There is an exclusive OR (X-OR) gate 417 coupled to one of the plurality of AND gates 407. There are a plurality of level shifter outputs 418. The address bits 404 also include a first address bit 405 coupled to a first inverter 402 and a second address bit 406 coupled to a second inverter 403. The plurality of AND gates 407 also include AND gates 408, 409, 410, and 411. The plurality of level shifters 412 also include level shifters 413, 414, 415, and 416. Level shifter output 419 is an output from level shifter 413, level shifter output 420 is an output from level shifter 414, level shifter output 421 is an output from level shifter 415, and level shifter output 422 is an output from level shifter 416.

[0039] The outputs of the inverters 402 and 403 are coupled to inputs of the AND gate 408, the output of which is coupled to an input of the level shifter 413. The input of the inverter 402 coupled to the address bit 405 and the output 425 of the inverter 403 are coupled to inputs of the AND gate 409, the output of which is coupled to an input of the level shifter 414. An input 427 of the AND gate 410 is coupled to the output 424 of the inverter 402. Another input 428 of the AND gate 410 is coupled to an output 429 of the X-OR gate 417. An input 430 of the AND gate 411 is coupled to the input of the inverter 402 coupled to the address bit 405. Another input 431 of the AND gate 411 is coupled to the output 429 of the X-OR gate 417. An input 432 of the X-OR gate 417 is coupled to the input 435 of the inverter 403 coupled to the address bit 406. An input 426 of the X-OR gate 417 is coupled to the differential enable signal 314.

[0040] Level shifter output 419 is coupled to the gate of transistor 251 of the first group 224 of the plurality of group select transistors 223. Level shifter output 420 is coupled to the gate of transistor 252 of the first group 224 of the plurality of group select transistors 223. Level shifter output 421 is coupled to the gate of transistor 254 of the second group 225 of the plurality of group select transistors 223. Level shifter output 422 is coupled to the gate of transistor 255 of the second group 225 of the group select transistors 223.

[0041] As explained above, the memory array 200 can be read in either differential read mode or single-ended read mode. As an example configuration, for differential reads of the memory array, the differential enable signal 314 remains high, and for single-ended reads of the memory array, the differential enable signal 314 remains low.

[0042] This is indicated by logic 1 when group selection transistors 251, 252, 254, and 255 are on. This is indicated by logic 0 when group selection transistors 251, 252, 254, and 255 are off. Figure 4A The truth table of the circuit is in Figure 4B In the middle, the Figure 4B The logic states of group selection transistors 251, 252, 254, and 255 are captured. The truth table provides the different logic states of the group selection transistors for different logic values ​​of enable signal 314 and address bits 405 and 406.

[0043] Figure 5 An array 500 comprising memory cells and circuit components, which can operate in single-ended or differential read operations. Figure 2 Representation of the memory array. Figure 5 The diagram illustrates a differential read operation of memory array 500. The differential read operation is performed during startup or boot operations, before the bandgap reference current has stabilized and is used. Differential read operations can also be used in other memory operations. Figure 6 In this process, a reference current generator with a memory cell array 240 is used during single-ended data reading, which is stored in the memory array.

[0044] Memory array 500 includes a plurality of user memory sectors 512 and one or more test memory sectors 514. Test memory sectors 514 are configured for differential read operations, while user memory sectors 512 are configured for single-ended read operations. Test memory sectors 514 include test data memory cells 501 and complementary test data memory cells 503. In this configuration, each test data memory cell has a corresponding complementary test data memory cell in the same row. The data stored in the complementary test data memory cell is the complement or inverse of the data stored in the corresponding test data memory cell. To read test data memory cell 502, memory array 500 receives instructions from a plurality of column decoders, such as column decoders 300 and 400 of Figures 3 and 4. Figure 3

[0045] The instructions initiate the following steps in the memory array for performing a differential read operation. Test data memory cell 502 (D1) is selected, and the corresponding complementary test data memory cell 504 (C1) is also selected. First bit line select transistor 510 of first group 219 of bit line select transistors is turned on. Second bit line select transistor 513 of second group 221 of bit line select transistors is turned on. Second group select transistor 252 from first group 224 of group select transistors is turned on. Second group select transistor 255 from second group 225 of group select transistors is turned on. First type of mode select transistor 228 is turned on, and second transistor 233 of the second type of mode select transistors is turned on. First transistor 231 of the second type of mode select transistors is turned off. The instructions can be repeated for reading any of the test data memory cells 501.

[0046] This step allows first bit line 506 of the plurality of second bit lines 211 to discharge when test memory cell 502 is read. Simultaneously, complementary test memory cell 504 (C1) is read, which causes current on second bit line 508 of the plurality of second bit lines 211 to discharge. First bit line 506 discharges through transistors 510, 252, and 228. The discharged current is converted to a voltage by second current-to-voltage converter 242. Second bit line 508 discharges through transistors 513, 255, and 233. The discharged current is converted to a voltage by first current-to-voltage converter 241.

[0047] ​The outputs of the two current-to-voltage converters 241 and 242 are inputs to a comparator or operational amplifier (op-amp) 234. The operational amplifier 234 compares the two voltage outputs from the current-to-voltage converters 241 and 242 and gives a logic high or logic low output. According to one logic, if the erased test memory cell 502 is read, the output of the operational amplifier 234 is a logic high (logic 1) and if the programmed test memory cell 502 is read, the output of the operational amplifier 234 is a logic low (0). If a different logic is used, if the erased test memory cell 502 is read, the output of the operational amplifier 234 can be a logic low (logic 0) and if the programmed test memory cell 502 is read, the output of the operational amplifier 234 is a logic high (1).

[0048] The first type of mode selection transistor 228 is turned on due to the high voltage on the gate of the transistor 228. The high voltage on the gate of the transistor 228 is also the input to the inverter 236. The inverter 236 converts the high input voltage to a low output voltage which turns off the reference current transistor switch 238, isolating the reference current generator with the memory cell array 240 from the memory array 500.

[0049] Figure 6 representing a single-ended read operation in the memory array 600 Figure 2 The memory array 600 is a memory array. The memory array includes a plurality of user memory sectors 612 and one or more test memory sectors 614.

[0050] The test memory sectors 614 are configured to perform differential read operations while the user memory sectors 612 are configured to perform single-ended read operations. The user memory sectors 612 include user data memory cells in which user storage data of the memory array 600 is stored for normal data storage operations of the memory array 600. The data stored in the user memory array 600 is used for operations other than memory initialization operations.

[0051] The memory array 600 includes a reference current generator with a memory cell array 240 to stabilize the bandgap reference current during a read in a single-ended read operation. To initiate a single-ended read, the memory array 600 decodes a plurality of columns from a plurality of column decoders (such as the column decoder 220) to select a column of memory cells in the memory array 600. Figure 3 The column decoders in Figures 1-4 receive an instruction to read a user memory cell 602. In response to the instruction, the user memory cell 602 is selected. A first bit line select transistor 610 of a first set 219 of bit line select transistors is turned on. A first set select transistor 251 from a first set 224 of set select transistors is turned on. A second set select transistor 252 from the first set 224 of set select transistors is turned off. Second set select transistors 254 and 255 from a second set 225 of set select transistors are turned off. A first type of mode select transistor 228 is turned off. A second transistor 233 of a second type of mode select transistor 230 is turned off, and a first transistor 231 of the second type of mode select transistor 230 is turned on.

[0052] In response, when the test memory cell 602 is read, a first bit line 606 of the plurality of first bit lines 209 is discharged. The first bit line 606 is discharged through the transistors 610, 251, and 231. The discharged current is converted to a voltage by a first current to voltage converter 241. The first type of mode select transistor 228 is turned off due to a low voltage on the gate of the transistor 228. The low voltage on the gate of the transistor 228 is the input of the inverter 236. The inverter 236 converts the low input voltage to a high output voltage, which turns on the reference current transistor switch 238, allowing the reference current generator with the memory cell array 240 to provide a current to the input of a second current to voltage converter 242. The second current to voltage converter 242 converts the input current to a voltage.

[0053] The outputs of the two current to voltage converters 241 and 242 are inputs to an operational amplifier (op-amp) 234. The op-amp 234 compares the two voltage outputs from the current to voltage converters 241 and 242 and gives a logic high (logic 1) or a logic low (logic 0) output. According to one logic, if the erased test memory cell 602 is read, the output of the op-amp 234 is logic high, and if the programmed test memory cell 602 is read, the output of the op-amp 234 is logic low. If a different logic is used, if the erased test memory cell 602 is read, the output of the op-amp 234 can be logic low, and if the programmed test memory cell 602 is read, the output of the op-amp 234 is logic high.

[0054] Figure 10 is Figure 2 and 6 one of the plurality of possible embodiments of the reference current generator memory 240. The reference current generator with the memory cell array 240 is in the sense amplifier 232 and is configured to provide a current to the input of the second current to voltage converter 242 when the first bit line 606 is discharged. Figure 2 to provide a more stable reference current during single-ended reads of the memory array. The memory array 240 includes a secondary memory cell array 1002 coupled through a column multiplexer 1004 to the source of a source follower transistor 1006. The drain of the source follower transistor 1006 is coupled to a P-MOS (P-channel metal-oxide-semiconductor) current mirror 1008, which in turn is coupled to an N-MOS (N-channel metal-oxide-semiconductor) current mirror 1010.

[0055] Instead of the bandgap reference current generation block 104, a reference current generator with a memory cell array 240 can be used in conventional memory to provide a more stable reference current. For single-ended memory read operations, the current generator with the memory cell array 240 is structured so that a more accurate reference current is provided to the memory array 600 than the bandgap reference current generator block 104.

[0056] To provide more accurate current generation by the reference current generator with the memory cell array 240, the secondary memory cell array 1002 is fabricated using the same process as used to fabricate the cells of the primary memory cell array 201. This ensures that the memory cells of the memory array 1002 respond to process, temperature, and other operational variations the same or substantially similar to the memory cells of the primary memory cell array 201. The column multiplexer 1004 of the memory array 240 can have the same architecture as the column multiplexer 220 of the single-ended read memory array 600. This minimizes the time variation between the times used to read the memory cells of the arrays 201 and 1002.

[0057] To generate a stable reference current, the memory cells of the secondary memory cell array 1002 are read and averaged together. The secondary memory cell array 1002 includes an even number of memory cells. Half of the memory cells are program cells (i.e., logical 1) and half of the memory cells are erase cells (i.e., logical 0). All of the cells or an even subset of the cells of the secondary memory cell array 1002 are selected for reading during a configuration phase. In this example, two cells 1012, 1014 are selected for reading. Alternatively, when a more accurate reference current is preferred and an even subset of the cells are selected for reading, all of the cells are selected.

[0058] The reference current generation memory is configured to average the current produced by the selected cells for reading to output an average current for the array 1002 that is representative of the individual memory cell to be compared to the cells read from the primary memory cell array. The greater the number of cells selected for reading, the more accurate the reference current from the memory 240 to the memory array 200 will be.

[0059] To provide more accurate reference current to the memory array 600, when a Vgs or Vread voltage is applied to the gates of the cells 1012 and 1014, the secondary memory cell array 1002 of the memory 240 preselects the first memory cell 1012 and the second memory cell 1014. Of the memory cells 1012 and 1014, one cell is an erased memory cell and the other is a programmed memory cell. Upon receiving the bias voltage Vds, the source follower transistor 1006 is turned on. This allows the single bit line 1016 to discharge or otherwise resolve current through the first P-MOS transistor 1007 of the P-MOS current mirror 1008 and the source follower transistor 1006. The current mirror 1008 allows an average current corresponding to both memory cells 1012 and 1014 to flow through the second P-MOS transistor of the P-MOS current mirror 1008. This current then passes through the N-MOS current mirror 1010. The current available on the drain of the N-MOS transistor 1013 of the N-MOS current mirror 1010 is the reference current needed for a single-ended read operation of the memory array 600.

[0060] Figure 7 The configurable row 700 including the memory cells 702 is such that any memory cell of the row 700 can be configured to operate in either a single-ended or differential read mode. Instead of the user memory sector row 512 or the test memory sector row 514, the configurable memory row 700 can be used in the memory array 500 to provide flexibility to the memory user. With the arrangement of the configurable row 700, the memory user is not forced to use the memory row in either only a differential read mode or only a single-ended read mode. With the memory array 500 rows, each row is established as either a single-ended read row or a differential read row and is not adjusted during use. Thus, some of the memory cells of these rows can not be used by the memory during operation, which can not be the most efficient use of the memory area. In contrast, the configurable row 700 can be used as a single-ended read row, a differential read row, or a combination of single-ended and differential read rows. This provides for flexible use of a memory array formed of multiple of these configurable rows 700 such that each row can be configured to the read type that is most beneficial for the overall memory function.

[0061] The configurable row 700 arrangement provides area efficiency and provides access to more memory cells that otherwise can not be accessible in a memory array having dedicated single-ended read rows and dedicated differential read rows. With dedicated differential read rows, if some cells are not used for boot or boot strap operations, those cells remain unused and inaccessible for the life of the memory. In contrast, in the configurable row 700, any cells that are not used for boot or boot strap operations for differential read will remain accessible and available for user data, read using single-ended read. Thus, more memory cells in the memory array can be used, maximizing available memory. In one particular embodiment of the configurable memory row 700, there are sixteen memory cells 702. The first four memory cells make up a first word of the configurable memory row 700, and the last four memory cells make up a second word of the configurable memory row 700. Eight memory cells are configured as differential read memory cells, and the remaining eight memory cells are configured as single-ended read memory cells. The eight differential read memory cells are equally divided into test data memory cells Dl, D2, D3, D4 and complementary test data memory cells Cl, C2, C3, C4, which are placed in the center of the row in this embodiment. In other embodiments, the differential read test data memory cells can be separated from the complementary test data memory cells by single-ended memory cells. Figure 7

[0062] In Figure 7 In this embodiment, there are four single-ended read cells 704 on a first side of the differential read cell 706. There are four single-ended read cells 708 on a second side of the differential read cell 706. Different configurations of single-ended read cells and differential read cells are contemplated, such that in a configurable memory cell row, the row includes a first plurality of single-ended read cells separated from a second plurality of single-ended read cells by a plurality of differential read cells, such that in the first word and the second word of the configurable memory row 700, test data memory cells and complementary test data memory cells are never placed in the same word. The number of the plurality of differential read cells is equal to the number of the first plurality of single-ended read cells and the second plurality of single-ended read cells. For example, in this embodiment, there are 8 differential read cells, and there are 8 single-ended read cells in total.

[0063] In alternative embodiments, the configurable row 700 can include ten or twelve cells configured for differential read and six or four cells configured for single-ended read, respectively.

[0064] The differential read cell can be a front cell of the row, and the single-ended read cells can be end cells of the row, such that the differential read cell is not between the plurality of single-ended read cells in the single-ended read cells.​

[0065] In an example method using a memory array comprising a plurality of configurable rows 700, a first row comprises a plurality of first memory cells and a second row comprises a second plurality of memory cells. The first row is configured to have single-ended and differential read cells in a first arrangement. The second row is configured to have single-ended and differential read cells in a second arrangement, which is different from the first arrangement. For example, the first arrangement can be Figure 7 the arrangement in FIG. 1 1 1, where there are single-ended read cells on both sides of the differential read cells. The second arrangement can have single-ended read cells first, followed by differential read cells. The number of single-ended read cells in the first row can be different from the number of single-ended read cells in the second row.

[0066] In another configuration, the first row is configured to have single-ended and differential read cells in a first arrangement, and the second row has only single-ended read cells or differential read cells in a second arrangement. In the second arrangement, the differential read cells can be arranged with all test data memory cells first, followed by complementary test data memory cells, as long as the test data memory cells and the complementary test data memory cells are not placed in the same word in the first word and the second word of the configurable memory row 700.

[0067] In yet another embodiment, the configurable rows of memory can have a first configuration for a first period of use and a second configuration for a second period of use, respectively, so that a user or manufacturer, such as through an update, can reuse each row, which is most beneficial to the current use cases of memory arrays and memory.

[0068] Figure 8 is part of a memory array 800 comprising a plurality of configurable memory rows 700. In this embodiment, there are two rows 806, 808 in this part of the memory array, however, there can be any number of rows selected by the application or user accessing the memory. The data in each of the rows 806, 808 of this part is the same. This same data in the rows provides for more accurate reading of the memory cells, as the data can be averaged during differential reading or single-ended reading. These rows can be integrated with the circuit structures of the figures of the present disclosure, such as Figure 5 and 6 . Specifically, Figure 3 and the column decoders, sense amplifiers, and reference generator memory 240 of FIGS. 1 1 1, 1 12, and other circuitry will be integrated with these rows to perform the read operations described herein.

[0069] In this section, two rows 806, 808 are configured to have a test data cell 802 in the first word of the row and a complementary test data cell 803 in the second word of the row. Other cells can be additional differential read cells or single-ended read cells as established by the current use case of the memory.

[0070] To read the same row, corresponding bit lines of the plurality of bit lines 209 or 211 are discharged through the same memory cells 802 and 804. These bit lines carry current that is the average current of the two memory cells 802 and 804. The greater the number of the same memory cells from the same data row, the more accurate the read because there will be more cells to average. This averaging minimizes the effects of temperature and process variations, manufacturing differences, and other variations that can affect the accuracy of the data in the memory cells. Similarly, in another embodiment, in the case of single-ended reads, two identical memory cells along the same bit line in two memory rows 806 and 808 can be read by discharging the corresponding bit lines.

[0071] Figure 9 is a portion of a memory array 900 that illustrates another embodiment of a memory array of the present disclosure that can use two or more configurable memory rows 700. In this configuration, test data memory cells are in one row and corresponding complementary test data memory cells are in another row based on encryption logic. This encryption logic is used in conjunction with column decoder logic that is used to select memory cells for reads. When used in these memory arrays, the encryption logic results in memory that is difficult to crack, providing more secure memory.

[0072] This encryption is implemented in this portion of the memory array 900 where a test data memory cell 902 is in a first memory row 910 and a corresponding complementary test data memory cell 904 is in a second memory row 912. The test data memory cell 902 is in a second cell of a first word of the first row 910 and the complementary test data memory cell 904 is in a second cell of a second word of the second row 912. For a differential read of the test data memory cell 902, the first and second rows are accessed using encryption logic and column decoder logic. Likewise, a test data memory cell 906 is in a third cell of a second word of the first memory row 910 and a corresponding complementary test data memory cell 908 is in a third cell of a first word of the second memory row 912. Generally, test data memory cells and complementary test data memory cells cannot be in the same word.

[0073] In the present disclosure, read accuracy is achieved by averaging current from multiple memory cells that have the same data placed along a common bit line in single ended and differential read operations. Another technique to improve read accuracy during normal memory operations is shown where reference current is obtained from a reference memory array of memory cells that is composed using the same memory cells as the primary memory array, referred to above as a configurable memory array. By placing test data memory cells in one memory row in the same or misaligned word positions, and complementary test data memory cells in another row, encryption for data security is ensured.

[0074] The present disclosure relates to an apparatus comprising a configurable memory array comprising a plurality of rows of memory cells, at least one row of memory cells comprising a plurality of user data memory cells, a plurality of test data memory cells, and a plurality of complementary test data memory cells. The row comprises at least a first word and a second word, the plurality of test data memory cells in the first word and the plurality of complementary test data memory cells in the second word. A first group of the plurality of user data memory cells is in the first word and a second group of the plurality of user data memory cells is in the second word. The first group of the plurality of user data memory cells is separated from the second group of the plurality of user data memory cells by the plurality of test data memory cells and the plurality of complementary test data memory cells.

[0075] The plurality of test data memory cells and the plurality of complementary test data memory cells in the row are separated by the plurality of user data memory cells. The plurality of user data memory cells are configured to be read with a single ended read operation and the plurality of test data memory cells and the plurality of complementary test data memory cells are configured to be read with a differential read operation. Each row of the plurality of rows comprises a first word and a second word, the configurable memory array comprising a column multiplexer coupled to the first word and the second word of each row, a sense amplifier coupled to the column multiplexer. The sense amplifier comprises a reference current memory cell array. The reference current memory cell array is configured to provide a reference current in the sense amplifier in a single ended read operation.

[0076] The present disclosure relates to an apparatus including a configurable memory array having a first row of memory cells including a plurality of test data memory cells and a second row of memory cells including a plurality of complementary test data memory cells corresponding to the plurality of test data memory cells of the first row. The first row includes a first word and a second word, and the second row includes the first word and the second word. A first test data memory cell is in the first word of the first row and a first complementary test data memory cell is in the second word of the second row. A second test data memory cell is in the second word of the first row and a second complementary test data memory cell is in the first word of the second row.

[0077] The plurality of test data memory cells in the first word of the first row correspond to the plurality of complementary test data memory cells in the second word of the second row. The plurality of test data memory cells in the second word of the first row correspond to the plurality of complementary test data memory cells in the first word of the second row.

[0078] The present disclosure relates to a method including reading a primary memory array by averaging current from two or more memory cells along a first bit line. The reading includes selecting memory rows of the primary memory array, each row storing a same data value in respective memory cells of each row, and enabling a first plurality of transistors corresponding to the first bit line in a column multiplexer and a sense amplifier according to column decoder logic. Each of the selected memory rows is adjacent to each other in the primary memory array. The method further includes performing a single-ended read operation using the first bit line, where the reading includes generating a reference current in the sense amplifier from a reference current generator memory cell array having memory cells with same temperature and process variations as the primary memory array, discharging the first bit line, converting current from the discharged first bit line to a first voltage, converting current from the reference current to a second voltage, and comparing the first voltage to the second voltage.

[0079] The generating includes a plurality of memory cells read from a reference current generator memory cell array having memory cells with same temperature and process variations as the primary memory array. Reading the plurality of memory cells from the reference current generator memory cell array includes sending a read signal to a first row and a second row of the reference current generator memory cell array and discharging a bit line of the reference current generator memory cell array with a column multiplexer associated with the memory cells of the first row and the second row of the reference current generator memory cell array.

[0080] The method also includes performing a differential read operation, the read including averaging current from two or more memory cells along a second bit line, the second bit line corresponding to a complementary test data memory cell, and the first bit line corresponding to a test data memory cell. The read includes enabling a second plurality of transistors corresponding to the second bit line in a column multiplexer and a sense amplifier according to column decoder logic.

[0081] The disclosure relates to an apparatus including a primary memory array having a plurality of bit lines, a plurality of rows of memory cells, a column multiplexer coupled to the plurality of bit lines, and a sense amplifier coupled to the column multiplexer. The sense amplifier includes a reference current generator memory cell array. The reference current generator memory cell array includes a plurality of rows of reference current memory cells, a column multiplexer, and a current mirror. The column multiplexer is coupled between the current mirror and the plurality of rows of reference current memory cells.

[0082] The sense amplifier also includes a first current to voltage converter, a second current to voltage converter, the reference current generator memory cell array is coupled to the second current to voltage converter. The column multiplexer of the primary memory array includes a plurality of bit line select transistors, a plurality of group select transistors coupled to the plurality of bit line select transistors, and a plurality of mode select transistors coupled to the plurality of group select transistors and the sense amplifier, a first mode select transistor of the plurality of mode select transistors is coupled to the reference current generator memory cell array.

[0083] The disclosure relates to a method including forming a primary memory cell array including a plurality of rows of memory cells and a reference current generator memory cell array including a plurality of rows of memory cells in a semiconductor substrate, forming a first column multiplexer and a sense amplifier in the substrate, coupling the first column multiplexer to bit lines of the primary memory cell array, coupling the sense amplifier to the first column multiplexer and the reference current generator memory cell array. The method also includes forming a first current to voltage converter and a second current to voltage converter in the sense amplifier, forming a comparator in the sense amplifier, coupling the first current to voltage converter and the second current to voltage converter to the comparator, coupling the reference current generator memory cell array to the second current to voltage converter.

[0084] The method includes coupling the first column multiplexer to the first current to voltage converter and the second current to voltage converter of the sense amplifier. The method also includes forming the primary memory cell array simultaneously, and forming the reference current generator memory cell array. The method also includes forming a second column multiplexer, coupling the second column multiplexer to the plurality of rows of reference current generator memory cell array, forming a current mirror, and coupling the current mirror to the second column multiplexer.

[0085] The present disclosure relates to an apparatus including a primary memory array having: a first configurable row having a first plurality of memory cells including a first plurality of test data cells and a first plurality of complementary test data cells in a first configuration and having a first data set; and a second configurable row having a second plurality of memory cells including a second plurality of test data cells and a second plurality of complementary test data cells in the first configuration and having the first data set. The primary memory array in operation averages corresponding data from the first plurality of test data cells from the first configurable row and from the second plurality of test data cells from the second configurable row. The primary memory array includes a third configurable row having a third plurality of memory cells including a third plurality of test data cells and a third plurality of complementary test data cells in the first configuration and having the first data set and in operation, the primary memory array averages corresponding data from the first plurality of test data cells from the first configurable row, from the second plurality of test data cells from the second configurable row, and from the third plurality of test data cells from the third configurable row.

[0086] The first configurable row and the second configurable row store the first data set in a first operational time period, and in a second operational time period, the first configurable row has a second data set in the first plurality of memory cells in a second configuration, and the second configurable row has the second data set in the second plurality of memory cells in the second configuration. The first configurable row and the second configurable row store the first data set in a first operational time period, and in a second operational time period, the first configurable row has a second data set in the first plurality of memory cells, and the second configurable row has a third data set in the second plurality of memory cells, the second data set and the third data set being different.

[0087] The present disclosure relates to an apparatus including a substrate, a primary memory array in the substrate, the primary memory array including: a plurality of rows of memory cells, a first column multiplexer coupled to the plurality of rows of memory cells, a sense amplifier coupled to the first column multiplexer, the sense amplifier including: a reference current generator memory array in the substrate. The first column multiplexer includes: a plurality of row select transistors; a plurality of group select transistors coupled to the plurality of row select transistors; a plurality of mode select transistors coupled to the plurality of group select transistors and the sense amplifier. The first column multiplexer includes a column decoder including: a first level shifter coupled between an enable signal and a first mode select transistor of the plurality of mode select transistors; a second level shifter coupled between an inversion of the enable signal and a second mode select transistor of the plurality of mode select transistors; and a third level shifter coupled to a third mode select transistor of the plurality of mode select transistors.

[0088] The first column multiplexer includes a column decoder including: a plurality of inverters; a plurality of address bits coupled to the plurality of inverters; a plurality of level shifters coupled to the plurality of address bits and the plurality of inverters. The column decoder includes a plurality of AND gates coupled to the plurality of level shifters and an XOR gate coupled to one of the plurality of AND gates. The plurality of address bits includes a first address bit coupled to a first inverter of the plurality of inverters and a second address bit coupled to a second inverter of the plurality of inverters.

[0089] Example 1. An apparatus comprising:

[0090] A configurable memory array comprising:

[0091] A plurality of rows of memory cells, at least one row of the memory cells including a plurality of user data memory cells, a plurality of test data memory cells, and a plurality of complementary test data memory cells.

[0092] Example 2. The apparatus of example 1, wherein the row includes at least a first word and a second word, the plurality of test data memory cells are in the first word, and the plurality of complementary test data memory cells are in the second word.

[0093] Example 3. The apparatus of example 2, wherein a first group of the plurality of user data memory cells are in the first word and a second group of the plurality of user data memory cells are in the second word.

[0094] Example 4. The apparatus of example 3, wherein the first group of the plurality of user data memory cells are separated from the second group of the plurality of user data memory cells by the plurality of test data memory cells and the plurality of complementary test data memory cells.

[0095] Example 5. The apparatus of example 1, wherein the plurality of test data memory cells and the plurality of complementary test data memory cells in the row are separated by the plurality of user data memory cells.

[0096] Example 6. The apparatus of example 1, wherein the plurality of user data memory cells are configured to be read with a single-ended read operation and the plurality of test data memory cells and the plurality of complementary test data memory cells are configured to be read with a differential read operation.

[0097] Example 7. The apparatus of example 1, wherein each row of the plurality of rows includes a first word and a second word, the configurable memory array comprising:

[0098] A column multiplexer coupled to the first word and the second word of each row; and

[0099] a sense amplifier coupled to the column multiplexer, the sense amplifier including:

[0100] a reference current memory cell array.

[0101] Example 8. The device of example 7, wherein the reference current memory cell array is configured to provide a reference current in the sense amplifier in a single-ended read operation.

[0102] Example 9. A device comprising:

[0103] a configurable memory array including:

[0104] a first row of memory cells including a plurality of test data memory cells, and a second row of memory cells including a plurality of complementary test data memory cells corresponding to the plurality of test data memory cells of the first row.

[0105] Example 10. The device of example 9, wherein the first row includes a first word and a second word, and the second row includes a first word and a second word.

[0106] Example 11. The device of example 10, wherein a first test data memory cell is in the first word of the first row and a first complementary test data memory cell is in the second word of the second row.

[0107] Example 12. The device of example 11, wherein a second test data memory cell is in the second word of the first row and a second complementary test data memory cell is in the first word of the second row.

[0108] Example 13. The device of example 10, wherein the plurality of test data memory cells in the first word of the first row correspond to the plurality of complementary test data memory cells in the second word of the second row.

[0109] Example 14. The device of example 13, wherein the plurality of test data memory cells in the second word of the first row correspond to the plurality of complementary test data memory cells in the first word of the second row.

[0110] Example 15. A method comprising:

[0111] reading a primary memory array by averaging current from two or more memory cells along a first bit line, the reading including:

[0112] selecting memory rows of the primary memory array, each row storing a same data value in respective memory cells of each row; and

[0113] According to column decoder logic, a first plurality of transistors corresponding to the first bit line are enabled in a column multiplexer and a sense amplifier.

[0114] Example 16. The method of example 15, wherein each of the selected memory rows are adjacent to each other in the primary memory array.

[0115] Example 17. The method of example 15, further comprising performing a single-ended read operation using the first bit line, wherein the read comprises:

[0116] generating a reference current in a reference current generator memory cell array in the sense amplifier;

[0117] discharging the first bit line;

[0118] converting current from the discharged first bit line to a first voltage;

[0119] converting current from the reference current to a second voltage; and

[0120] comparing the first voltage to the second voltage.

[0121] Example 18. The method of example 17, wherein the generating comprises reading a plurality of memory cells from the reference current generator memory cell array, the memory cells of the reference current generator memory cell array having the same temperature and process variation as the primary memory array.

[0122] Example 19. The method of example 18, wherein reading the plurality of memory cells from the reference current generator memory cell array comprises:

[0123] sending a read signal to a first row and a second row of a reference current generator memory cell array; and

[0124] discharging bit lines of the reference current generator memory cell array with a column multiplexer, the column multiplexer associated with the memory cells of the first row and the second row of the reference current generator memory cell array.

[0125] Example 20. The method of example 15, further comprising performing a differential read operation, the read comprising averaging current from two or more memory cells along a second bit line, the second bit line corresponding to a complementary test data memory cell and the first bit line corresponding to a test data memory cell.

[0126] Example 21. The method of example 20, wherein the reading includes enabling, according to the column decoder logic, a second plurality of transistors corresponding to the second bit line in the column multiplexer and the sense amplifier.

[0127] Example 22. An apparatus comprising:

[0128] a primary memory array comprising:

[0129] a plurality of bit lines;

[0130] a plurality of rows of memory cells; and

[0131] a column multiplexer coupled to the plurality of bit lines; and

[0132] a sense amplifier coupled to the column multiplexer, the sense amplifier comprising:

[0133] a reference current generator memory cell array.

[0134] Example 23. The apparatus of example 22, wherein the reference current generator memory cell array comprises:

[0135] a plurality of rows of reference current memory cells;

[0136] a column multiplexer; and

[0137] a current mirror.

[0138] Example 24. The apparatus of example 23, wherein the column multiplexer is coupled between the current mirror and the plurality of rows of reference current memory cells.

[0139] Example 25. The apparatus of example 23, wherein the sense amplifier further comprises:

[0140] a first current to voltage converter; and

[0141] a second current to voltage converter, the reference current generator memory cell array coupled to the second current to voltage converter.

[0142] Example 26. The apparatus of example 25, wherein the column multiplexer of the primary memory array comprises:

[0143] a plurality of bit line select transistors;

[0144] a plurality of group select transistors coupled to the plurality of bit line select transistors;

[0145] a plurality of mode select transistors coupled to the plurality of group select transistors and the sense amplifier, a first mode select transistor of the plurality of mode select transistors coupled to the reference current generator memory cell array.

[0146] Example 27. A method comprising:

[0147] forming, in a semiconductor substrate, a primary memory cell array comprising a plurality of rows of memory cells and a reference current generator memory cell array comprising a plurality of rows of memory cells;

[0148] forming, in the substrate, a first column multiplexer and a sense amplifier;

[0149] coupling the first column multiplexer to a bit line of the primary memory cell array;

[0150] coupling a sense amplifier to the first column multiplexer and the reference current generator memory cell array.

[0151] Example 28. The method of example 27, further comprising:

[0152] forming, in the sense amplifier, a first current to voltage converter and a second current to voltage converter;

[0153] forming, in the sense amplifier, a comparator;

[0154] coupling the first current to voltage converter and the second current to voltage converter to the comparator;

[0155] coupling the reference current generator memory cell array to the second current to voltage converter.

[0156] Example 29. The method of example 28, further comprising:

[0157] coupling a first column multiplexer to the first current to voltage converter and the second current to voltage converter of the sense amplifier.

[0158] Example 30. The method of example 27, further comprising: forming the primary memory cell array concurrently with forming the reference current generator memory cell array.

[0159] Example 31. The method of example 27, further comprising:

[0160] forming a second column multiplexer;

[0161] coupling the second column multiplexer to a plurality of rows of the reference current generator memory cell array;

[0162] forming a current mirror;

[0163] coupling the current mirror to the second column multiplexer.

[0164] Example 32. An apparatus comprising:

[0165] a primary memory array comprising:

[0166] a first configurable row having a first plurality of memory cells including a first plurality of test data cells and a first plurality of complementary test data cells in a first configuration and having a first data set; and

[0167] a second configurable row having a second plurality of memory cells including a second plurality of test data cells and a second plurality of complementary test data cells in the first configuration and having the first data set.

[0168] Example 33. The apparatus of example 32, wherein the primary memory array in operation averages corresponding data from the first plurality of test data cells from the first configurable row and the second plurality of test data cells from the second configurable row.

[0169] Example 34. The apparatus of example 32, wherein the primary memory array comprises a third configurable row having a third plurality of memory cells including a third plurality of test data cells and a third plurality of complementary test data cells in the first configuration and having the first data set and in operation, the primary memory array in operation averages corresponding data from the first plurality of test data cells from the first configurable row, the second plurality of test data cells from the second configurable row, and the third plurality of test data cells from the third configurable row.

[0170] Example 35. The apparatus of example 32, wherein the first configurable row and the second configurable row store the first data set in a first operational time period, and in a second operational time period, the first configurable row has a second data set in the first plurality of memory cells in a second configuration, and the second configurable row has the second data set in the second plurality of memory cells in the second configuration.

[0171] Example 36. The apparatus of example 35, wherein the first configurable row and the second configurable row store the first set of data in a first operational time period, and in a second operational time period, the first configurable row has a second set of data in the first plurality of memory cells and the second configurable row has a third set of data in the second plurality of memory cells, the second set of data and the third set of data being different.

[0172] Example 37. An apparatus comprising:

[0173] a substrate; and

[0174] a primary memory array in the substrate, the primary memory array comprising:

[0175] a plurality of rows of memory cells;

[0176] a first column multiplexer coupled to the plurality of rows of memory cells; and

[0177] a sense amplifier coupled to the first column multiplexer, the sense amplifier comprising:

[0178] a reference current generator memory array in the substrate.

[0179] Example 38. The apparatus of example 37, wherein the first column multiplexer comprises:

[0180] a plurality of row select transistors;

[0181] a plurality of group select transistors coupled to the plurality of row select transistors;

[0182] a plurality of mode select transistors coupled to the plurality of group select transistors and the sense amplifier.

[0183] Example 39. The apparatus of example 38, wherein the first column multiplexer comprises a column decoder, the column decoder comprising:

[0184] a first level shifter coupled between an enable signal and a first mode select transistor of the plurality of mode select transistors;

[0185] a second level shifter coupled between an inverse of the enable signal and a second mode select transistor of the plurality of mode select transistors; and

[0186] a third level shifter coupled to a third mode select transistor of the plurality of mode select transistors.

[0187] Example 40. The apparatus of example 38, wherein the first column multiplexer comprises a column decoder, the column decoder comprising:

[0188] a plurality of inverters;

[0189] a plurality of address bits coupled to the plurality of inverters;

[0190] a plurality of level shifters coupled to the plurality of address bits and the plurality of inverters.

[0191] Example 41. The apparatus of example 40, wherein the column decoder includes a plurality of AND gates coupled to the plurality of level shifters and an XOR gate coupled to one of the plurality of AND gates.

[0192] Example 42. The apparatus of example 41, wherein the plurality of address bits includes a first address bit coupled to a first inverter of the plurality of inverters and a second address bit coupled to a second inverter of the plurality of inverters.

[0193] The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification are hereby incorporated by reference in their entirety. Various aspects of the embodiments can be modified if necessary to employ the concepts of the various patents, applications, and publications to provide yet further embodiments.

[0194] These and other changes can be made to the embodiments in light of the above- detailed description. In general, the terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited to the disclosure.< / n>

Claims

1. An apparatus comprising: Primary memory array, including: Multiple bit lines; Multi-line memory units; and Column multiplexers are coupled to the plurality of bit lines; and A sensing amplifier, coupled to the column multiplexer, the sensing amplifier comprising: Comparator; A first current-to-voltage converter and a second current-to-voltage converter are respectively coupled to the two inputs of the comparator; and A reference current generator memory cell array is coupled to the second current-to-voltage converter to provide current to the input of the second current-to-voltage converter.

2. The device according to claim 1, wherein the reference current generator memory cell array comprises: Multi-line reference current memory cell; Column multiplexer; as well as Current mirror.

3. The device of claim 2, wherein the column multiplexer is coupled between the current mirror and the multi-row reference current memory cell.

4. The device of claim 1, wherein the column multiplexer of the primary memory array comprises: Multiple bit line select transistors; Multiple group selection transistors are coupled to the multiple bit line selection transistors; Multiple mode selection transistors are coupled to the multiple group selection transistors and the sense amplifier, and a first mode selection transistor of the multiple mode selection transistors is coupled to the reference current generator memory cell array.

5. A method comprising: A primary memory cell array comprising multiple rows of memory cells and a reference current generator memory cell array comprising multiple rows of memory cells are formed in a semiconductor substrate. A first column of multiplexers and a sensing amplifier are formed in the substrate; The first column multiplexer is coupled to the bit line of the primary memory cell array; The sensing amplifier is coupled to the first column multiplexer and the reference current generator memory cell array; A first current-to-voltage converter and a second current-to-voltage converter are formed in the sensing amplifier; A comparator is formed in the sensing amplifier; The first current-to-voltage converter and the second current-to-voltage converter are respectively coupled to the two inputs of the comparator; The reference current generator memory cell array is coupled to the second current-to-voltage converter to provide current to the input of the second current-to-voltage converter.

6. The method according to claim 5, further comprising: The first column multiplexer is coupled to the first current-to-voltage converter and the second current-to-voltage converter of the sensing amplifier.

7. The method according to claim 5, further comprising: Simultaneously, the primary memory cell array is formed, and the reference current generator memory cell array is also formed.

8. The method according to claim 5, further comprising: Form a second column multiplexer; The second column multiplexer is coupled to the multi-row reference current generator memory cell array; Forming a current mirror; The current mirror is coupled to the second column multiplexer.

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