Read-write conversion circuit and memory

Abstract

The embodiment of the present invention provides a read-write conversion circuit and a memory, wherein the read-write conversion circuit comprises: a read-write conversion module, which performs read-write operations in response to a read-write control signal, so that data is transmitted between the local data line and the local complementary data line and the global data line, and during the read-write operation, the data signal phases of the local data line and the local complementary data line are opposite; and a control module, which outputs a variable read-write control signal in response to a read-write speed configuration signal, so as to control the speed of the read-write operation of the read-write conversion module to be variable. The speed of the read-write operation of the read-write conversion circuit in the embodiment of the present invention can be varied, which is beneficial to improving the performance of the memory.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a read-write conversion circuit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] DRAM can be divided into double data rate (DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and low power double data rate (LPDDR) dynamic random access memory. As DRAM is applied in more and more fields, such as DRAM is increasingly used in the mobile field, users have higher and higher requirements for DRAM power consumption indicators.

[0004] However, current DRAM performance still needs to be improved. Summary of the invention

[0005] The technical problem solved by the embodiments of the present invention is to provide a read-write conversion circuit and a memory, so that the speed of the read-write operation of the read-write conversion circuit can be variable to improve the performance of the memory.

[0006] To solve the above problems, an embodiment of the present invention provides a read-write conversion circuit, characterized in that it includes: a read-write conversion module, which responds to a read-write control signal to perform read-write operations; and a control module, which responds to a read-write speed configuration signal to output a variable read-write control signal to control the speed of the read-write operation of the read-write conversion module.

[0007] In addition, it also includes: a speed configuration module, which is connected to the control module and is used to output the read-write speed configuration signal to the control module.

[0008] In addition, the read-write control signal includes a read control signal and a write control signal, and the read-write conversion module responds to the read control signal to perform a read operation, and responds to the write control signal to perform a write operation; the speed configuration module includes: a read speed configuration unit, which is used to output the read speed configuration signal in the read-write speed configuration signal to the control module, so that the control module outputs the variable read control signal in response to the read speed configuration signal to control the speed of the read operation to be variable; a write speed configuration unit, which is used to output the write speed configuration signal in the read-write speed configuration signal to the control module, so that the control module outputs the variable write control signal in response to the read speed configuration signal to control the speed of the write operation to be variable.

[0009] In addition, it also includes: a local data line, a local complementary data line and a global data line; during the read and write operations, data is transmitted between the local data line and the local complementary data line and the global data line, and the data signals of the local data line and the local complementary data line are in opposite phases.

[0010] In addition, the read-write conversion module includes: a local read-write unit, which responds to the local read-write control signal in the read-write control signal to perform local read-write operations; the control module includes: a local control unit, which responds to the local read-write speed configuration signal in the read-write speed configuration signal to output the variable local read-write control signal to control the speed of the local read-write operation of the local read-write unit to be variable.

[0011] In addition, the read-write conversion circuit further includes: a local speed configuration module, connected to the local control unit, and configured to output the local read-write speed configuration signal to the local control unit.

[0012] In addition, the read-write conversion circuit further includes: a sensitive amplifier, which is connected to the local read-write unit via the local data line and the local complementary data line and is used to sense the bit line voltage.

[0013] In addition, the same local read / write unit is connected to a plurality of the sense amplifiers via the local data line and the local complementary data line.

[0014] In addition, the write data path includes: from the local read-write unit via the local data line and the local complementary data line to the sensitive amplifier, and then via the sensitive amplifier to the bit line; the read data path includes: from the bit line via the sensitive amplifier to the local data line and the local complementary data line, and then via the local data line and the local complementary data line to the local read-write unit.

[0015] In addition, the read-write conversion module includes: a global read-write unit, which responds to the global read-write control signal in the read-write control signal to perform global read-write operations; the control module includes: a global control unit, which responds to the global read-write speed configuration signal in the read-write speed configuration signal to output the variable global read-write control signal to control the speed of the global read-write operation of the global read-write unit.

[0016] In addition, the read-write conversion circuit further includes: a global speed configuration module, connected to the global control unit, and configured to output the global read-write speed configuration signal to the global control unit.

[0017] In addition, the local read / write unit includes: a local amplifier connected between the local data line and the local complementary data line, and used to amplify the data of the local data line and the data of the local complementary data line.

[0018] In addition, the local amplifier includes: a first inverter, an input end of the first inverter is electrically connected to the local data line, and an output end of the first inverter is electrically connected to the local complementary data line; a second inverter, an input end of the second inverter is electrically connected to the output end of the first inverter and the local complementary data line, and an output end of the second inverter is electrically connected to the input end of the first inverter and the local data line.

[0019] In addition, the first inverter includes: a first PMOS tube and a first NMOS tube, the gate of the first PMOS tube and the gate of the first NMOS tube are connected and serve as the input end of the first inverter, the source of the first PMOS tube is connected to the working power supply, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and serve as the output end of the first inverter; the second inverter includes: a zeroth PMOS tube and a zeroth NMOS tube, the gate of the zeroth PMOS tube is connected to the gate of the zeroth NMOS tube and serve as the input end of the second inverter, the source of the zeroth PMOS tube is connected to the working power supply, the drain of the zeroth PMOS tube is connected to the drain of the zeroth NMOS tube and serve as the output end of the second inverter.

[0020] In addition, the local read-write unit includes a local read conversion circuit, which is used to transfer the data of the local data line and the local complementary data line to the global data line in response to the local read control signal in the local read-write control signal; the local read conversion circuit includes: a third NMOS tube and a fourth NMOS tube; the drain of the third NMOS tube is connected to the global data line, the gate of the third NMOS tube is connected to the local complementary data line, and the source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the fourth NMOS tube receives the local read signal in the local read control signal, and the source is grounded.

[0021] In addition, the read-write conversion circuit also includes: a global complementary data line, and during the read operation, the data signal phase of the global complementary data line is opposite to that of the global data line; the local read conversion circuit also includes: an eighth NMOS tube and a ninth NMOS tube; the drain of the eighth NMOS tube is connected to the global complementary data line, the gate of the eighth NMOS tube is connected to the local data line, and the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; the gate of the ninth NMOS tube receives the local read signal, and the source is grounded.

[0022] In addition, the local read-write unit includes: a local write conversion circuit, which is used to transfer the data of the global data line to the local data line and the local complementary data line in response to the local write control signal in the local read-write control signal; the local write conversion circuit includes: a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; the drain of the fifth NMOS tube is connected to the local complementary data line, the gate of the fifth NMOS tube is connected to the source of the seventh NMOS tube, and the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; the gate of the sixth NMOS tube receives the local write signal in the local write control signal, and the source is grounded; the drain of the seventh NMOS tube is connected to the local data line, and the gate receives the local write signal.

[0023] In addition, the read-write conversion circuit also includes: a global complementary data line, and during the read-write operation, the data signal phase of the global complementary data line is opposite to that of the global data line; the local write conversion circuit also includes: a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube; the drain of the tenth NMOS tube is connected to the local data line, the gate of the tenth NMOS tube is connected to the source of the twelfth NMOS tube and to the global complementary data line, and the source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the eleventh NMOS tube receives the local write signal, and the source is grounded; the drain of the twelfth NMOS tube is connected to the local complementary data line, and the gate receives the local write signal.

[0024] In addition, the local read / write unit further includes: a precharge circuit, which is connected between the local data line and the local complementary data line and is used to respond to a precharge control signal to precharge the local data line and the local complementary data line.

[0025] In addition, the pre-charging circuit includes: a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube and the gate of the fifth PMOS tube receive a pre-charging control signal; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the working power supply, the drain of the third PMOS tube is electrically connected to the local data line; the drain of the fourth PMOS tube is electrically connected to the local complementary data line; the fifth PMOS tube is electrically connected to the local data line and the local complementary data line in response to the pre-charging control signal.

[0026] Correspondingly, an embodiment of the present invention further provides a memory, comprising the above-mentioned read-write conversion circuit.

[0027] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0028] The embodiment of the present invention provides a read-write conversion circuit with superior structural performance, including a read-write conversion module that performs read-write operations in response to a read-write control signal, and a control module that outputs a variable read-write control signal in response to a read-write speed configuration signal, so as to control the speed of the read-write operation of the read-write conversion module to be variable. Since the read-write control signal output by the control module is variable, the speed of the read-write operation performed by the read-write conversion module receiving the variable read-write control is also variable, so that the speed of the read-write operation of the read-write conversion circuit can be configured. Compared with the fixed speed of the read-write operation of the read-write conversion circuit, the read-write conversion circuit provided by the embodiment of the present invention can adjust the speed of the read-write operation according to actual needs, so that the read-write conversion circuit can be more widely used, such as not only being applicable to the scene of low-speed read-write operation, but also being applicable to the scene of high-speed read-write operation; in addition, the read-write conversion circuit provided by the embodiment of the present invention can be adjusted to a low-speed read-write operation when a high-speed read-write operation is not required, thereby avoiding the problem of high power consumption caused by the high-speed read-write operation. Therefore, the performance of the read-write conversion circuit provided by the embodiment of the present invention is improved.

[0029] In addition, the read-write conversion module includes a local read-write unit, and the control module includes a local control unit, which responds to the local read-write speed configuration signal in the read-write speed configuration signal to output a variable local read-write control signal to control the speed of the local read-write operation of the local read-write unit to be variable. In this way, the speed of the local read-write operation of the read-write conversion circuit provided by the embodiment of the present invention is configurable.

[0030] In addition, the read-write conversion module includes a global read-write unit, and the control module includes: a local control unit, responsive to the global read-write speed configuration signal in the read-write speed configuration signal, to output a variable global read-write control signal to control the speed of the global read-write operation of the global read-write unit to be variable. In this way, the speed of the global read-write operation of the read-write conversion circuit provided by the embodiment of the present invention is configurable.

[0031] In addition, the local read / write unit includes: a local amplifier connected between the local data line and the local complementary data line, and used to amplify the data of the local data line and the data of the local complementary data line. The local amplifier is conducive to accelerating the distinction between the local data line and the local complementary data line, which is not only conducive to improving the speed of local read / write operations, but also conducive to reducing the driving requirements of the local data line and the local complementary data line for the sensitive amplifier, thereby reducing the design difficulty of the sensitive amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0033] Figure 1 A read-write conversion circuit provided by an embodiment of the present invention;

[0034] Figure 2 A read-write conversion circuit provided by another embodiment of the present invention;

[0035] Figure 3 Another read-write conversion circuit provided by another embodiment of the present invention;

[0036] Figure 4 A timing diagram of read / write control signals corresponding to high-speed write operations and low-speed write operations in a write operation performed by a read / write conversion circuit provided by another embodiment of the present invention;

[0037] Figure 5 A timing diagram of read / write control signals corresponding to high-speed read operations and low-speed read operations in a read / write conversion circuit provided by another embodiment of the present invention;

[0038] Figure 6 A schematic diagram of a circuit structure of a local read-write unit in a read-write conversion circuit provided by another embodiment of the present invention;

[0039] Figure 7 A schematic diagram of another circuit structure of a local read-write unit in a read-write conversion circuit provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0040] As can be seen from the background technology, the performance of DRAM in the prior art still needs to be improved.

[0041] The inventor of the present invention has found that in the prior art, for the same DRAM, the speed of its read and write operations (including the read speed and the write speed) is fixed. Since the speed of the read and write operations of the DRAM is fixed, it is difficult to meet the demand for the DRAM to have a high read and write speed in a certain period; if the DRAM is designed to have a fixed high read and write speed, then for the situation where the DRAM has a low read and write speed in a certain period to meet the demand, the high read and write speed will bring about the problem of high DRAM power consumption. In other words, the current problem is that the speed of the read and write operations of the memory is fixed and the power consumption is high.

[0042] To solve the above problem, the present invention provides a read-write conversion circuit, including a read-write conversion module and a control module, wherein the control module responds to a read-write speed configuration signal to output a variable read-write control signal, thereby controlling the read-write operation speed of the read-write conversion module to be variable. In this way, the embodiment of the present invention can configure the speed of the read-write operation, so as to adjust the speed of the read-write operation of the read-write conversion circuit to meet the expectations, and avoid unnecessary power consumption of the read-write conversion circuit, thereby improving the performance of the read-write conversion circuit.

[0043] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0044] Figure 1 A read-write conversion circuit is provided in one embodiment of the present invention.

[0045] refer to Figure 1 In this embodiment, the read-write conversion circuit includes: a read-write conversion module 101, which responds to a read-write control signal to perform a read-write operation; a control module 102, which responds to a read-write speed configuration signal to output a variable read-write control signal to control the read-write operation speed of the read-write conversion module 101.

[0046] The read-write conversion circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0047] In this embodiment, the read-write conversion circuit also includes: a local data line Ldat, a local complementary data line Ldat#, and a global data line Gdat. During the read-write operation, data is transmitted between the local data line Ldat and the local complementary data line Ldat# and the global data line Gdat#, and the data signals of the local data line Ldat and the local complementary data line Ldat# have opposite phases.

[0048] In this embodiment, the data read or the data signal written by the read-write conversion circuit are in pairs, and each pair of data signals includes two data. During the read-write operation, one of the two data is a high-level signal and the other is a low-level signal. Therefore, the read-write conversion circuit includes at least one pair of local data lines Ldat and local complementary data lines Ldat#. Specifically, during the read operation of the read-write conversion circuit, the data is transmitted to the global data line Gdat via the local data line Ldat and the local complementary data line Ldat#; during the write operation of the read-write conversion circuit, the data is transmitted to the local data line Ldat and the local complementary data line Ldat# via the global data line Gdat.

[0049] The local data line Ldat is also called a local data line, the local complementary data line Ldat# is also called a complementary local data line; and the global data line Gdat is also called a global data line.

[0050] In this embodiment, the global data line Gdat of the read-write conversion circuit is in single-ended transmission mode, that is, the read-write conversion circuit is not provided with a global complementary data line whose phase is complementary to the data signal of the global data line Gdat.

[0051] It should be noted that in other embodiments, the global data line of the read-write conversion circuit can also be a two-port transmission mode, that is, the read-write conversion circuit also includes a global complementary data line, and during the read and write operation, the data signal phase of the global complementary data line is opposite to that of the global data line.

[0052] Specifically, the read-write conversion circuit is applied to a memory, and the memory includes a column selection module 100, a local data line Ldat is connected to a bit line BL through the column selection module 100, and a local complementary data line Ldat# is connected to a complementary bit line BL# through the column selection module 100. A storage unit for a read operation or a write operation is selected through the column selection module 100, and accordingly, a signal is transmitted between the bit line BL connected to the selected storage unit and the local data line Ldat, and a signal is transmitted between the complementary bit line BL# connected to the selected storage unit and the local complementary data line Ldat#.

[0053] During a read operation, the read-write conversion module 101 transfers data from the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat; during a write operation, the read-write conversion module 101 transfers data from the global data line Gdat to the local data line Ldat and the local complementary data line Ldat#.

[0054] The read / write control signals include: column selection signals, local read / write control signals and global read / write control signals. The local read / write control signals are used to control the read / write conversion module 101 to perform local read / write operations, and the global read / write control signals are used to control the read / write conversion module 101 to perform global read / write operations.

[0055] The rate of the read / write control signal affects the speed of the read / write operation of the read / write conversion circuit. For example, the faster the rate of the read / write control signal, the faster the corresponding read / write operation; the slower the rate of the read / write control signal, the slower the corresponding read / write operation.

[0056] The read / write control signal is provided by the control module 102, and the read / write control signal output by the control module 102 is variable, specifically, the rate of the read / write control signal is variable. The read / write speed configuration signal is related to the expected speed of the read / write operation. When the speed of the read / write operation is not the expected speed, the read / write control signal output by the control module 102 changes, that is, the rate of the read / write control signal changes, so that the speed of the read / write operation performed by the read / write conversion module 101 in response to the changed read / write control signal changes, thereby ensuring that the read / write speed of the read / write operation is the expected speed.

[0057] For example, when the speed of the read-write operation performed by the read-write conversion module 101 in response to the first read-write control signal is lower than the expected speed, the control module 102 responds to the read-write speed configuration signal to output the second read-write control signal to increase the read-write operation speed of the read-write conversion module 101 to the expected speed; when the speed of the read-write operation performed by the read-write conversion module 101 in response to the third read-write control signal is higher than the expected speed, the control module 102 responds to the read-write speed configuration signal to output the fourth read-write control signal to reduce the read-write operation speed of the read-write conversion module 101 to the expected speed.

[0058] Since the speed of the read and write operations of the read and write conversion module 101 is variable, the speed of the read and write operations of the read and write conversion module 101 can be adjusted according to actual performance requirements, such as increasing the speed of data transmission in the read and write operations or reducing the speed of data transmission in the read and write operations. While meeting different read and write performance requirements, unnecessary power consumption can be reduced.

[0059] In this embodiment, the read-write conversion circuit may further include: a speed configuration module 103, connected to the control module 102, for outputting a read-write speed configuration signal to the control module 102. In this way, integrating the speed configuration module 103 in the read-write conversion circuit is conducive to reducing the transmission path of the read-write speed configuration signal to the control module 102, and further improving the response speed of the control module 102, so that the control module 102 can output the adjusted read-write control signal more timely, thereby achieving the purpose of changing the speed of the read-write operation of the read-write conversion module 101 more quickly.

[0060] The read / write control signal includes a read control signal and a write control signal. The read / write conversion module 101 performs a read operation in response to the read control signal and performs a write operation in response to the write control signal. In this embodiment, the control module 102 outputs a variable read control signal in response to the read / write speed configuration signal to control the speed of the read operation of the read / write conversion module 101 to be variable; the control module 102 also outputs a variable write control signal in response to the read / write speed configuration signal to control the speed of the write operation of the read / write conversion module 101 to be variable.

[0061] Correspondingly, the read-write speed configuration signal includes a read speed configuration signal and a write speed configuration signal; the speed configuration module 103 includes: a read speed configuration unit 113, which is used to output the read speed configuration signal in the read-write speed configuration signal to the control module 102, so that the control module 102 outputs a variable read control signal in response to the read speed configuration signal to control the speed of the read operation to be variable; a write speed configuration unit 123, which is used to output the write speed configuration signal in the read-write speed configuration signal to the control module 102, so that the control module outputs a variable write control signal in response to the read speed configuration signal to control the speed of the write operation to be variable.

[0062] It should be noted that the speed configuration module may also include a local speed configuration module and a global speed configuration module. The local speed configuration module is used to output a local read / write speed configuration signal to the control module to control the speed of the local read / write operation of the read / write conversion module to be variable; the global speed configuration module is used to output a global read / write speed configuration signal to the control module to control the speed of the global read / write operation of the read / write conversion module to be variable.

[0063] It should also be noted that, in other embodiments, the speed configuration module may also be provided by other circuits besides the read-write conversion circuit.

[0064] The read-write conversion circuit provided in this embodiment has a control module 101 that outputs a variable read-write control signal, so that the speed of the read-write operation of the read-write conversion module 101 is variable, thereby making the application scenarios of the read-write conversion circuit wider, such as being able to perform both high-speed read-write operations and low-speed read-write operations, and avoiding the problem of high power consumption caused by being in a high-speed read-write operation state for a long time.

[0065] Another embodiment of the present invention further provides a read-write conversion circuit, which is substantially the same as the read-write conversion circuit provided in the previous embodiment, except that: the read-write conversion module and the control module are described in more detail in this embodiment. The read-write conversion circuit provided in this embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same or corresponding to the previous embodiment can refer to the detailed description of the previous embodiment.

[0066] Figure 2 A read-write conversion circuit is provided according to another embodiment of the present invention.

[0067] refer to Figure 2 The read-write conversion circuit includes: a local data line Ldat, a local complementary data line Ldat#, a global data line Gdat and a global complementary data line Gdat#; a read-write conversion module 201 and a control module 202. The read-write conversion module 201 responds to a read-write control signal to perform a read-write operation so that data is transmitted between the local data line Ldat and the local complementary data line Ldat# and the global data line Gdat and the global complementary data line Gdat#. During the read-write operation, the data signals of the local data line Ldat and the local complementary data line Ldat# are in opposite phases, and the data signals of the global data line Gdat and the global complementary data line Gdat# are in opposite phases.

[0068] It should be noted that, in other embodiments, the read-write conversion circuit may not be provided with a global complementary data line.

[0069] In this embodiment, the read-write conversion module 201 includes: a local read-write unit 211, which performs local read-write operations in response to a local read-write control signal in the read-write control signal, wherein the local read-write control signal includes a local read signal Rd and a local amplification enable signal.

[0070] Accordingly, the control module 202 includes: a local control unit 212, which responds to the local read / write speed configuration signal in the read / write speed configuration signal to output a variable local read / write control signal to control the speed of the local read / write operation of the local read / write unit 211 to be variable.

[0071] In this way, the speed of the local read and write operations in the read-write conversion circuit is variable. Specifically, the speed of the local read operation in the local read-write operation is variable, and the speed of the local write operation in the local read-write operation is variable. For example, the local read operation can be reduced from high-speed reading to low-speed reading, or increased from low-speed reading to high-speed reading; the local write operation can be reduced from high-speed writing to low-speed writing, or increased from low-speed writing to high-speed writing. Since the speed of the local read and write operation is variable, the speed of the local read and write operation can be adjusted according to actual needs, thereby ensuring that the read-write conversion circuit has the advantage of low power consumption while meeting the data transmission speed requirements.

[0072] In this embodiment, the read-write conversion circuit may further include: a local speed configuration module 213 connected to the local control unit 212, used to output a local read-write speed configuration signal to the local control unit 212, so that the local read-write control signal output by the local control unit 212 is adjustable.

[0073] It should be noted that, in other embodiments, an external circuit may also provide a local read / write speed configuration signal to the local control unit, that is, the read / write conversion circuit does not require a local speed configuration module.

[0074] The read-write conversion circuit may further include: a sensitive amplifier 214, which is connected to the local read-write unit 211 via the local data line Ldat and the local complementary data line Ldat#, and is used to sense the voltages of the bit line BL and the complementary bit line BL#.

[0075] The bit line BL is connected to the local data line Ldat via the sense amplifier 214 , and the complementary bit line BL# is connected to the local complementary data line Ldat# via the sense amplifier 214 .

[0076] In this embodiment, the sense amplifier 214 receives a column selection signal CSL. The sense amplifier 214 includes two NMOS transistors (not shown), and the gates of the NMOS transistors receive the column selection signal CSL. One NMOS transistor connects the bit line BL and the local data line Ldat in response to the column selection signal CSL, and the other NMOS transistor connects the complementary bit line BL# and the local complementary data line Ldat# in response to the column selection signal CSL.

[0077] It is understandable that in other embodiments, the sensitive amplifier may include any number of transistors, such as multiple NMOS transistors and / or multiple PMOS transistors. Any device that can realize the sensitive amplification function may be used as the sensitive amplifier.

[0078] The bit line BL is connected to a storage transistor (not shown), the gate of the storage transistor is connected to a word line WL, one end of the storage transistor is connected to the bit line BL, and the other end is connected to a voltage Vplate via a capacitor (not shown). The complementary bit line BL# is connected to a control transistor (not shown), one end of the control transistor is connected to the complementary bit line BL#, and the other end is connected to a voltage Vplate.

[0079] In addition, the same local read / write unit 211 can be connected to multiple sense amplifiers 214 via the local data line Ldat and the local complementary data line Ldat#. Figure 2 Only one sense amplifier 214 is shown.

[0080] In this embodiment, the read-write conversion circuit is applied to the memory, and the write data path includes: from the local read-write unit 211 through the local data line Ldat and the local complementary data line Ldat# to the sensitive amplifier, and then through the sensitive amplifier 214 to the bit line BL and the complementary bit line BL#; the read data path includes: from the bit line through the sensitive amplifier 214 to the local data line Ldat and the local complementary data line Ldat#, and then through the local data line Ldat and the local complementary data line Ldat# to the local read-write unit 211.

[0081] In this embodiment, the read-write conversion module 201 further includes: a global read-write unit 221, which responds to the global read-write control signal in the read-write control signal to perform a global read-write operation.

[0082] The control module 202 includes: a global control unit 222, which responds to the global read-write speed configuration signal in the read-write speed configuration signal to output a variable global read-write control signal to control the speed of the global read-write operation of the global read-write unit 221 to be variable. In this way, the speed of the global read-write operation in the read-write conversion circuit is variable. Specifically, the speed of the global read operation in the global read-write operation is variable, and the speed of the global write operation in the global read-write operation is variable.

[0083] That is to say, in this embodiment, not only the speed of local read and write operations is variable, but also the speed of global read and write operations is variable.

[0084] It should be noted that, in other embodiments, the control module may include only one of the local control unit or the global control unit. Accordingly, only the speed of the local read and write operation is variable or only the speed of the global read and write operation is variable.

[0085] Correspondingly, the read-write conversion circuit may further include: a global speed configuration module 223 connected to the global control unit 222 and configured to output a global read-write speed configuration signal to the global control unit 222 .

[0086] The local speed configuration module 213 and the global speed configuration module 223 may be integrated into the same speed configuration module 203 , which is used to output local read / write speed configuration signals to the local control unit 212 and also to output global read / write speed configuration signals to the global control unit 222 .

[0087] It is understandable that in other embodiments, an external circuit may provide a global read / write speed configuration signal to the global control unit, that is, the read / write conversion circuit does not require a global speed configuration module.

[0088] Figure 3 Another read-write conversion circuit is provided in another embodiment. Figure 3As shown, in another example, the read-write conversion circuit may further include: a read speed configuration unit 243, which is used to output a read speed configuration signal in the read-write speed configuration signal to the local control unit 212 and the global control unit 222, so that the local control unit 212 outputs a variable local read control signal in response to the read speed configuration signal to control the speed of the local read operation to be variable, and the global control unit 222 outputs a variable global read control signal in response to the read speed configuration signal to control the speed of the global read operation to be variable; a write speed configuration unit 253, which is used to output a write speed configuration signal in the read-write speed configuration signal to the local control unit 212 and the global control unit 222, so that the local control unit 212 outputs a variable local write control signal in response to the write speed configuration signal to control the speed of the local write operation to be variable, and the global control unit 222 outputs a variable global write control signal in response to the write speed configuration signal to control the speed of the global write operation to be variable. The read speed configuration unit 243 and the write speed configuration unit 253 may be integrated in the same speed configuration module 203, and the description of the speed configuration module 203 may refer to the aforementioned embodiment.

[0089] For the read-write conversion circuit with a global read-write unit 221, the write data path includes: via the global read-write unit 221 to the global data line Gdat and the global complementary data line Gdat#, and then transmitted to the local read-write unit 211 via the global data line Gdat and the global complementary data line Gdat#; from the local read-write unit 211 via the local data line Ldat and the local complementary data line Ldat# to the sensitive amplifier 214, and then via the sensitive amplifier 214 to the bit line BL and the complementary bit line BL#.

[0090] For the read-write conversion circuit with a global read-write unit 221, the read data path includes: from the bit line BL and the complementary bit line BL# via the sensitive amplifier 214 to the local data line Ldat and the local complementary data line Ldat#, and then via the local data line Ldat and the local complementary data line Ldat# to the local read-write unit 211; then via the local read-write unit 211 to the global data line Gdat and the global complementary data line Gdat#; via the global data line Gdat and the global complementary data line Gdat# to the global read-write unit 221.

[0091] In this embodiment, the local read / write unit 211 includes a local read conversion circuit 2111, which is used to transmit the data of the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary data line Gdat# in response to the local read control signal in the local read / write control signal.

[0092] The control module 202 outputs a local read control signal, and the control module 202 outputs a variable local read control signal in response to the read / write speed configuration signal to adjust the read speed of the local read conversion circuit 2111, thereby making the speed of the local read operation of the read / write conversion module 201 variable.

[0093] The local read / write unit 211 further includes: a local write conversion circuit 2112 for transmitting data of the global data line Gdat and the global complementary data line Gdat# to the local data line Ldat and the local complementary data line Ldat# in response to a local write control signal in the local read / write control signal.

[0094] The control module 202 outputs a local write control signal, and the control module 202 outputs a variable local write control signal in response to the read / write speed configuration signal to adjust the write speed of the local write conversion circuit 2112, thereby making the speed of the local write operation of the read / write conversion module 201 variable.

[0095] The local read / write unit 211 further includes: a local amplifier 2113 connected between the local data line Ldat and the local complementary data line Ldat#, and used to amplify the data of the local data line Ldat and the data of the local complementary data line Ldat#.

[0096] The control module 202 outputs a variable local read control signal or a local write control signal, so that the amplification speed of the local amplifier 2113 is variable, thereby also being able to change the speed of the local read operation and the local write operation of the read-write conversion module 201 to a certain extent.

[0097] The local amplifier 2113 constitutes a circuit for amplifying the signal of the local data line Ldat and the signal of the local complementary data line Ldat#, which helps to accelerate the differentiation of the local data line Ldat and the local complementary data line Ldat#, thereby increasing the speed of data signal transmission and improving the data reading and writing speed. In addition, since the data signals of the local data line Ldat and the local complementary data line Ldat# are amplified, the driving capability requirements of the local data line Ldat and the local complementary data line Ldat# for the sensitive amplifier in the memory are reduced. Therefore, even if the area of ​​the sensitive amplifier is gradually reduced, the sensitive amplifier still has sufficient driving capability for the local data line Ldat and the local complementary data line Ldat#, so as to ensure that the read-write conversion circuit has good electrical performance while meeting the development trend of device miniaturization, thereby improving the storage performance of the memory including the read-write conversion circuit.

[0098] The global read / write unit 221 includes a sense amplifier 2211, a precharge unit 2212 and a write driver unit 2213. The sense amplifier 2211 can amplify data signals of the global data line Gdat and the global complementary data line Gdat#, and the precharge unit 2212 can precharge the global data line Gdat and the global complementary data line Gdat#.

[0099] The control module 202 outputs a variable global read control signal, thereby adjusting the speed of the global read operation or the speed of the global write operation of the global read-write unit 221, such as adjusting the amplification speed of the sensitive amplifier 2211, the pre-charging speed of the pre-charging unit 2212, and the driving speed of the write driver unit 2213, so as to achieve the purpose of changing the speed of the global read-write operation of the read-write conversion module 201.

[0100] In this embodiment, the read-write conversion circuit may also include: a precharge circuit (not shown), which is connected between the local data line Ldat and the local complementary data line Ldat#, and is used to respond to a precharge control signal to precharge the local data line Ldat and the local complementary data line Ldat#.

[0101] Figure 4 A timing diagram of the read-write control signals corresponding to the high-speed write operation and the low-speed write operation in the write operation performed by the read-write conversion circuit provided in this embodiment; Figure 5 A timing diagram of read / write control signals corresponding to high-speed read operations and low-speed read operations in a read operation performed by the read / write conversion circuit provided in this embodiment; Figure 4 and Figure 5 Also shown are bit line / complementary bit line signals (BL / BL#), global data line / global complementary data line signals (Gdat / Gdat#), and local data line / local complementary data line signals (Ldat / Ldat#). It can be understood that high speed and low speed are relative.

[0102] refer to Figure 4 When performing a write operation, the read / write control signal includes: a global write control signal, a column select signal CSL, a local write signal Wr, and a local amplification enable. It can be understood that when performing a low-speed write operation, the level of the local amplification enable can be 0, so the timing diagram corresponding to the low-speed write operation does not illustrate the local amplification enable.

[0103] Depend on Figure 4It is not difficult to find that when the high-speed write operation changes to the low-speed write operation, the rate of the read-write control signal slows down, the data transmission rate of the global data line Gdat and the global complementary data line Gdat# slows down, and the data transmission rate of the local data line Ldat and the local complementary data line Ldat# slows down. When the low-speed write operation changes to the high-speed write operation, the rate of the read-write control signal speeds up, the data transmission rate of the global data line Gdat and the global complementary data line Gdat# speeds up, and the data transmission rate of the local data line Ldat and the local complementary data line Ldat# speeds up.

[0104] also, Figure 4 Only the timing diagram of each read-write control signal within a single clock cycle is shown. From the perspective of the entire clock cycle, a low-speed write operation becomes a high-speed write operation, and the rate of the write control signal in the corresponding read-write control signal becomes faster; a high-speed write operation becomes a low-speed write operation, and the rate of the write control signal in the corresponding read-write control signal becomes slower.

[0105] refer to Figure 5 , when entering the read operation, the read / write control signals include: column selection signal CSL, local read signal Rd, global amplifier enable, global precharge signal, and local amplifier enable. It can be understood that when performing a low-speed read operation, the level of the local amplifier enable can be 0, so the timing diagram of the local amplifier enable corresponding to the low-speed read operation is not shown. Figure 5 It is not difficult to find that when the high-speed read operation changes to the low-speed read operation, the rate of the read-write control signal becomes slower, the data transmission rate of the local data line Ldat and the local complementary data line Ldat# becomes slower, and the data transmission rate of the global data line Gdat and the global complementary data line Gdat# becomes slower; when the low-speed read operation changes to the high-speed read operation, the rate of the read-write control signal becomes faster, the data transmission rate of the local data line Ldat and the local complementary data line Ldat# becomes faster, and the data transmission rate of the global data line Gdat and the global complementary data line Gdat# becomes faster.

[0106] Figure 5 Only the timing diagram of each read-write control signal within a single clock cycle is shown. From the perspective of the entire clock cycle, the low-speed read operation becomes a high-speed read operation, and the rate of the read control signal in the corresponding read-write control signal becomes faster; the high-speed read operation becomes a low-speed write operation, and the rate of the read control signal in the corresponding read-write control signal becomes slower.

[0107] It should be noted that Figure 4 and Figure 5 Only several common read / write control signals that affect the read / write operation speed are shown. In actual circuits, depending on different circuit designs, there may be other read / write control signals that affect the read / write operation speed.

[0108] The circuit structure of the local read-write unit in the read-write conversion channel provided by this embodiment will be specifically described below with reference to the accompanying drawings.

[0109] Figure 6 A schematic diagram of a circuit structure of a local read-write unit in the read-write conversion circuit provided in this embodiment; Figure 7 Another circuit structure diagram of the local read-write unit in the read-write conversion circuit provided in this embodiment.

[0110] refer to Figure 6 The global data line Gdat is in single transmission mode, that is, the read-write conversion circuit does not include a global complementary data line. The local read-write unit 211 includes a local read conversion circuit 2111, which is used to respond to the local read control signal in the local read-write control signal to transmit the data of the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat.

[0111] In this embodiment, the local read conversion circuit 2111 includes: a third NMOS transistor MN3 and a fourth NMOS transistor MN4; the drain of the third NMOS transistor MN3 is connected to the global data line Gdat, the gate of the third NMOS transistor MN3 is connected to the local complementary data line Ldat#, and the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4 receives the local read signal Rd in the local read control signal, and the source is grounded.

[0112] It is understandable that the local read conversion circuit 2111 may also be other suitable modified circuits, for example, the gate of the fourth NMOS tube is connected to the local complementary data line, and the gate of the third NMOS tube receives the local read signal.

[0113] In another example, Figure 7 As shown, the global data line Gdat can also be a dual transmission mode, that is, the read-write conversion circuit includes the global data line Gdat and the global complementary data line Gdat#, and during the read operation, the data signal phases of the global complementary data line Gdat and the global data line Gdat# are opposite. Accordingly, the local read conversion circuit 2111 includes, in addition to the third NMOS tube MN3 and the fourth NMOS tube MN4 mentioned above, an eighth NMOS tube MN8 and a ninth NMOS tube MN9; the drain of the eighth NMOS tube MN8 is connected to the global complementary data line Gdat#, the gate of the eighth NMOS tube MN8 is connected to the local data line Ldat, and the source of the eighth NMOS tube MN8 is connected to the drain of the ninth NMOS tube MN9; the gate of the ninth NMOS tube MN9 receives the local read signal Rd, and the source is grounded.

[0114] The local read / write unit 211 includes: a local write conversion circuit 2112, which is used to transmit the data of the global data line Gdat to the local data line Ldat and the local complementary data line Ldat# in response to the local write control signal in the local read / write control signal.

[0115] In this embodiment, the local write conversion circuit 2112 includes: a fifth NMOS tube MN5, a sixth NMOS tube MN6 and a seventh NMOS tube MN7; the drain of the fifth NMOS tube MN5 is connected to the local complementary data line Ldat#, the gate of the fifth NMOS tube MN5 is connected to the source of the seventh NMOS tube MN7, and the source of the fifth NMOS tube MN5 is connected to the drain of the sixth NMOS tube MN6; the gate of the sixth NMOS tube MN6 receives the local write signal Wr in the local write control signal, and the source is grounded; the drain of the seventh NMOS tube MN7 is connected to the local data line Ldat, and the gate receives the local write signal Wr.

[0116] In another example, Figure 7 As shown, the read-write conversion circuit 211 also includes: a global complementary data line Gdat#, and during the read operation, the data signal phase of the global complementary data line Gdat# is opposite to that of the global data line Gdat; the local write conversion circuit 2112 includes, in addition to the fifth NMOS tube MN5, the sixth NMOS tube MN6 and the seventh NMOS tube MN7 mentioned above, the tenth NMOS tube MN10, the eleventh NMOS tube MN11 and the twelfth NMOS tube MN12; the drain of the tenth NMOS tube MN10 is connected to the local data line Ldat, the gate of the tenth NMOS tube MN10 is connected to the source of the twelfth NMOS tube MN12 and to the global complementary data line Gdat#, the source of the tenth NMOS tube MN10 is connected to the drain of the eleventh NMOS tube MN11; the gate of the eleventh NMOS tube MN11 receives the local write signal Wr, and the source is grounded; the drain of the twelfth NMOS tube MN12 is connected to the local complementary data line Ldat#, and the gate receives the local write signal Wr.

[0117] The local amplifier includes 2113: a first inverter, an input end of the first inverter is electrically connected to the local data line, and an output end of the first inverter is electrically connected to the local complementary data line; a second inverter, an input end of the second inverter is electrically connected to the output end of the first inverter and the local complementary data line, and an output end of the second inverter is electrically connected to the input end of the first inverter and the local data line.

[0118] Specifically, the first inverter includes: a first PMOS tube MP1 and a first NMOS tube MN1, the gate of the first PMOS tube MP1 and the gate of the first NMOS tube MN1 are electrically connected and serve as the input end in1 of the first inverter, the source of the first PMOS tube MP1 is connected to the working power supply VDD, and the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1 and serves as the output end out1 of the first inverter.

[0119] The second inverter includes: a zeroth PMOS tube MP0 and a zeroth NMOS tube MN0, the gate of the zeroth PMOS tube MP0 is connected to the gate of the zeroth NMOS tube MN0 and serves as the input end in2 of the second inverter, the source of the zeroth PMOS tube MP0 is connected to the working power supply VDD, and the drain of the zeroth PMOS tube MP0 is connected to the drain of the zeroth NMOS tube MN0 and serves as the output end out2 of the second inverter.

[0120] The first PMOS transistor MP1 , the first NMOS transistor MN1 , the zeroth PMOS transistor MP0 , and the zeroth NMOS transistor MN0 constitute a local amplifier 2113 .

[0121] In addition, the local amplifier 2113 further includes: an enabling NMOS transistor mn, the first inverter and the second inverter are also connected to the drain of the enabling NMOS transistor mn, and the drain of the enabling NMOS transistor mn is grounded, and the gate receives the local enabling signal En. Specifically, the source of the first NMOS transistor MN1 and the source of the zeroth NMOS transistor MN0 are connected to the drain of the sixth NMOS transistor MN6.

[0122] Due to the setting of the local amplifier 2113, the transmission speed of data from the bit line BL to the local data line Ldat is improved, the transmission speed of data from the complementary bit line BL# to the local complementary data line Ldat# is improved, and the driving requirement of the memory for the sensitive amplifier is reduced. Specifically, taking the data of the bit line BL as a high level and the data of the complementary bit line BL# as a low level as an example, since the first input terminal in1 of the first inverter is connected to the second output terminal out2 of the second inverter, and the first output terminal out1 of the first inverter is connected to the second input terminal in2 of the second inverter, during the transmission of the bit line BL and the complementary bit line BL# to the local data line Ldat and the local complementary data line Ldat#, the setting of the local amplifier including 2113 will make the local complementary data line Ldat# with a lower voltage pull down to "0" more quickly, or make the local data line Ldat with a higher voltage pull up to "1" more quickly. Therefore, the speed at which the local data line Ldat is pulled up is increased, and the speed at which the local complementary data line Ldat# is pulled down is also increased, so that the driving requirements of the local data line Ldat and the local complementary data line Ldat# on the sensitive amplifier are reduced.

[0123] At the same time, since the local data line Ldat and the local complementary data line Ldat# can reach a high level or a low level more quickly, the local data line Ldat and the local complementary data line Ldat# can be transmitted to the global data line Gdat and the global complementary data line Gdat# earlier. In this way, when reading out data, the speed at which data is transmitted from the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary data line Gdat# is improved.

[0124] Correspondingly, during the writing period, the local amplifier including 2113 can also amplify the local data line Ldat and the local complementary data line Ldat#, thereby increasing the speed at which data is transmitted from the global data line Gdat and the global complementary data line Gdat# to the local data line Ldat and the local complementary data line Ldat#.

[0125] In this embodiment, the pre-charging circuit includes: a third PMOS tube MP3, a fourth PMOS tube MP4 and a fifth PMOS tube MP5; the gate of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5 receive the pre-charging control signal Eq; the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are connected to the working power supply VDD, the drain of the third PMOS tube MP3 is electrically connected to the local data line Ldat; the drain of the fourth PMOS tube MP4 is electrically connected to the local complementary data line Ldat#; the fifth PMOS tube MN5 is electrically connected to the local data line Ldat and the local complementary data line Ldat# in response to the pre-charging control signal Eq. The control module 202 outputs a read-write control signal in response to the read-write speed configuration signal to change the data reading rate of the local read conversion circuit 2111 or the data writing rate of the local write conversion circuit 2112, etc., so as to adjust the speed of the read-write operation of the read-write conversion circuit.

[0126] The read-write conversion circuit provided in this embodiment can adjust both the speed of local read-write operations and the speed of global read-write operations, thereby further improving the convenience of adjusting the read-write operation speed of the read-write conversion circuit.

[0127] Accordingly, an embodiment of the present invention provides a memory including the above-mentioned read-write conversion circuit.

[0128] The memory may be DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, etc. As can be seen from the above analysis, the memory provided in this embodiment has the advantage of variable data transmission speed and low demand for the driving capability of the sensitive amplifier, which is conducive to meeting the development trend of device miniaturization.

[0129] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A read-write conversion circuit, characterized in that: include: A read-write conversion module, responding to a read-write control signal to perform a read-write operation; A control module, responsive to a read / write speed configuration signal, to output a variable read / write control signal, so as to control the read / write operation speed of the read / write conversion module to be variable; A local data line, a local complementary data line and a global data line; during the read and write operations, data is transmitted between the local data line and the local complementary data line and the global data line, and the data signal phases of the local data line and the local complementary data line are opposite; Wherein, the read-write conversion module includes: a local read-write unit, responding to a local read-write control signal in the read-write control signal to perform a local read-write operation; The local read / write unit includes a local read conversion circuit, which is used to transmit the data of the local data line and the local complementary data line to the global data line in response to the local read control signal in the local read / write control signal; the local read conversion circuit includes: a third NMOS tube and a fourth NMOS tube; the drain of the third NMOS tube is connected to the global data line, the gate of the third NMOS tube is connected to the local complementary data line, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the fourth NMOS tube receives the local read signal in the local read control signal, and the source is grounded.

2. A read-write conversion circuit, characterized in that: include: A read-write conversion module, responding to a read-write control signal to perform a read-write operation; A control module, responsive to a read / write speed configuration signal, to output a variable read / write control signal, so as to control the read / write operation speed of the read / write conversion module to be variable; A local data line, a local complementary data line and a global data line; during the read and write operations, data is transmitted between the local data line and the local complementary data line and the global data line, and the data signal phases of the local data line and the local complementary data line are opposite; Wherein, the read-write conversion module includes: a local read-write unit, responding to a local read-write control signal in the read-write control signal to perform a local read-write operation; The local read / write unit includes: a local write conversion circuit, which is used to transmit the data of the global data line to the local data line and the local complementary data line in response to the local write control signal in the local read / write control signal; the local write conversion circuit includes: a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; the drain of the fifth NMOS tube is connected to the local complementary data line, the gate of the fifth NMOS tube is connected to the source of the seventh NMOS tube, the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; the gate of the sixth NMOS tube receives the local write signal in the local write control signal, and the source is grounded; the drain of the seventh NMOS tube is connected to the local data line, and the gate receives the local write signal.

3. The read-write conversion circuit according to claim 1 or 2, characterized in that: Also includes: The speed configuration module is connected to the control module and is used to output the read / write speed configuration signal to the control module.

4. The read-write conversion circuit according to claim 3, characterized in that: The read-write control signal includes a read control signal and a write control signal, and the read-write conversion module responds to the read control signal to perform a read operation, and responds to the write control signal to perform a write operation; The speed configuration module includes: a read speed configuration unit, which is used to output a read speed configuration signal in the read / write speed configuration signal to the control module, so that the control module outputs the variable read control signal in response to the read speed configuration signal, so as to control the speed of the read operation to be variable; The write speed configuration unit is used to output a write speed configuration signal in the read / write speed configuration signal to the control module, so that the control module outputs a variable write control signal in response to the read speed configuration signal to control the speed of the write operation to be variable.

5. The read-write conversion circuit according to claim 1 or 2, characterized in that: The control module includes: a local control unit, which responds to the local read-write speed configuration signal in the read-write speed configuration signal to output the variable local read-write control signal to control the speed of the local read-write operation of the local read-write unit to be variable.

6. The read-write conversion circuit according to claim 5, characterized in that: The read-write conversion circuit further includes: a local speed configuration module connected to the local control unit and configured to output the local read-write speed configuration signal to the local control unit.

7. The read-write conversion circuit according to claim 5, characterized in that: The read-write conversion circuit further includes: a sensitive amplifier, which is connected to the local read-write unit via the local data line and the local complementary data line and is used to sense a bit line voltage.

8. The read-write conversion circuit according to claim 7, characterized in that: The same local read / write unit is connected to a plurality of the sense amplifiers via the local data line and the local complementary data line.

9. The read-write conversion circuit according to claim 7, characterized in that: The write data path includes: from the local read-write unit through the local data line and the local complementary data line to the sensitive amplifier, and then through the sensitive amplifier to the bit line; the read data path includes: from the bit line through the sensitive amplifier to the local data line and the local complementary data line, and then through the local data line and the local complementary data line to the local read-write unit.

10. The read-write conversion circuit according to claim 1 or 2, characterized in that: The read-write conversion module includes: a global read-write unit, which responds to the global read-write control signal in the read-write control signal to perform global read-write operations; the control module includes: a global control unit, which responds to the global read-write speed configuration signal in the read-write speed configuration signal to output the variable global read-write control signal to control the speed of the global read-write operation of the global read-write unit to be variable.

11. The read-write conversion circuit according to claim 10, characterized in that: The read-write conversion circuit further includes: a global speed configuration module connected to the global control unit and configured to output the global read-write speed configuration signal to the global control unit.

12. The read-write conversion circuit according to claim 5, characterized in that: The local read / write unit includes: a local amplifier connected between the local data line and the local complementary data line, and used for amplifying data of the local data line and data of the local complementary data line.

13. The read-write conversion circuit according to claim 12, characterized in that: The local amplifier includes: a first inverter, an input end of the first inverter is electrically connected to the local data line, and an output end of the first inverter is electrically connected to the local complementary data line; a second inverter, an input end of the second inverter is electrically connected to the output end of the first inverter and the local complementary data line, and an output end of the second inverter is electrically connected to the input end of the first inverter and the local data line.

14. The read-write conversion circuit according to claim 13, characterized in that: The first inverter includes: a first PMOS tube and a first NMOS tube, the gate of the first PMOS tube and the gate of the first NMOS tube are connected and serve as the input end of the first inverter, the source of the first PMOS tube is connected to the working power supply, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and serve as the output end of the first inverter; the second inverter includes: a zeroth PMOS tube and a zeroth NMOS tube, the gate of the zeroth PMOS tube is connected to the gate of the zeroth NMOS tube and serve as the input end of the second inverter, the source of the zeroth PMOS tube is connected to the working power supply, the drain of the zeroth PMOS tube is connected to the drain of the zeroth NMOS tube and serve as the output end of the second inverter.

15. The read-write conversion circuit according to claim 1, characterized in that: The read-write conversion circuit also includes: a global complementary data line, and during a read operation, the data signal phase of the global complementary data line is opposite to that of the global data line; the local read conversion circuit also includes: an eighth NMOS tube and a ninth NMOS tube; the drain of the eighth NMOS tube is connected to the global complementary data line, the gate of the eighth NMOS tube is connected to the local data line, and the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; the gate of the ninth NMOS tube receives the local read signal, and the source is grounded.

16. The read-write conversion circuit according to claim 2, characterized in that: The read-write conversion circuit also includes: a global complementary data line, and during the read-write operation, the data signal phase of the global complementary data line is opposite to that of the global data line; the local write conversion circuit also includes: a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube; the drain of the tenth NMOS tube is connected to the local data line, the gate of the tenth NMOS tube is connected to the source of the twelfth NMOS tube and to the global complementary data line, and the source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the eleventh NMOS tube receives the local write signal, and the source is grounded; the drain of the twelfth NMOS tube is connected to the local complementary data line, and the gate receives the local write signal.

17. The read-write conversion circuit according to claim 1 or 2, characterized in that: The local read / write unit further includes: a precharge circuit, which is connected between the local data line and the local complementary data line and is used to respond to a precharge control signal to precharge the local data line and the local complementary data line.

18. A memory, characterized in that: include: A read-write conversion circuit as described in any one of claims 1 to 17.

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