SerDes control method, device and storage medium

Abstract

The present invention provides a SerDes control method, device and storage medium, belonging to the field of communication. The method comprises: obtaining the rate change moment of the SerDes; when it is determined that the working moment of the SerDes reaches the rate change moment, controlling the rate of the SerDes to switch between a first preset rate and a second preset rate. The technical solution of the present invention controls the rate of the SerDes to switch between a high rate and a low rate, thereby reducing the power consumption of the SerDes while ensuring the normal operation of the SerDes, thereby reducing the power consumption of devices such as FPGA or FPSC, reducing the heat dissipation pressure of the communication system, and ensuring the normal operation of the communication system.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a SerDes control method, device and storage medium. Background Art

[0002] At present, with the widespread use of multi-antenna technology in the fourth generation of mobile information systems 4G and the fifth generation of mobile information systems 5G, in order to quickly deliver communication systems, many important functions of the communication system are implemented through field programmable gate arrays (Field Programmable Gate Array, FPGA) or field programmable system chips (Field Programmable System Chip, FPSC), and a large number of high-speed serial interfaces (SERializerDESerializer, SerDes) are embedded in FPGA or FPSC, so the power consumption of FPGA or FPSC is related to the power consumption of SerDes. With the iteration of communication systems, the scale of FPGA or FPSC used in communication systems is getting larger and larger. Therefore, the power consumption of communication systems is also getting larger and larger, which will generate more heat, bringing serious heat dissipation problems to the communication system. In the case of poor heat dissipation, devices such as FPGA will be in a high temperature state, affecting the normal use of devices such as FPGA or FPSC, and then affecting the function of the communication system. Summary of the invention

[0003] The main purpose of the present invention is to provide a SerDes control method, device and storage medium, aiming to reduce the power consumption of devices such as FPGA or FPSC and reduce the heat dissipation pressure of the communication system.

[0004] In a first aspect, the present invention provides a SerDes control method, comprising:

[0005] Obtaining the rate change moment of the SerDes;

[0006] When it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, and the first preset rate is greater than the second preset rate.

[0007] In a second aspect, the present invention further provides a SerDes control device, comprising a processor, a memory, a program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the program is executed by the processor, the steps of any one of the SerDes control methods provided in the specification of the present invention are implemented.

[0008] In a third aspect, the present invention further provides a storage medium for computer-readable storage, characterized in that the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of any SerDes control method provided in the specification of the present invention.

[0009] The present invention provides a SerDes control method, device and storage medium. The present invention obtains the rate change moment of the SerDes, and when the working moment of the SerDes reaches the rate change moment, controls the rate of the SerDes to switch between a first preset rate and a second preset rate, that is, controls the rate of the SerDes to switch between a high rate and a low rate, thereby reducing the power consumption of the SerDes while ensuring the normal operation of the SerDes, thereby reducing the power consumption of devices such as FPGA or FPSC, reducing the heat dissipation pressure of the communication system, and ensuring the normal operation of the communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flow chart of a SerDes control method provided by an embodiment of the present invention;

[0011] Figure 2 yes Figure 1 A schematic diagram of the sub-step flow chart of the SerDes control method in FIG.

[0012] Figure 3 yes Figure 2 A schematic diagram of the sub-step flow chart of the SerDes control method in FIG.

[0013] Figure 4 It is a schematic block diagram of the structure of a SerDes control device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0016] It should be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0017] The embodiment of the present invention provides a SerDes control method, device and storage medium. The SerDes control method can be applied to a device, chip and communication system equipped with SerDes, and the chip includes a Field Programmable Gate Array (FPGA) and a Field Programmable System Chip (FPSC).

[0018] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] See also Figure 1 , Figure 1 It is a flow chart of a SerDes control method provided by an embodiment of the present invention.

[0020] like Figure 1 As shown, the SerDes control method includes steps S101 to S102.

[0021] Step S101: Obtain the rate change moment of the SerDes.

[0022] The rate change moment includes a first moment when the rate of the SerDes is reduced from a first preset rate to a second preset rate and a second moment when the rate of the SerDes is increased from a second preset rate to the first preset rate, the first preset rate is greater than the second preset rate, the first preset rate and the second preset rate are determined according to the protocol adopted by the SerDes, and the present invention does not specifically limit this. For example, if the protocol adopted by the SerDes is the Common Public Radio Interface (CPRI) protocol, the first preset rate is 24330.24 Mbit / s and the second preset rate is 614.4 Mbit / s.

[0023] In one embodiment, if Figure 2 As shown, step S101 includes the following steps:

[0024] S1011, obtaining the low-speed time period of the SerDes.

[0025] The low-speed period is determined according to the transmission conditions of the SerDes, for example, in time division duplex (TimeDivision In a TDD (Transmitter Duplex, TDD) communication system, the 5ms frame format is DDDDDDSUU. There are 7 downlink slots (D slots), 1 special slot (S downlink uplink conversion slot) and 2 uplink slots (U slots) in a 5ms period. When it is confirmed that data is transmitted in only one direction, the SerDes can be decelerated so that the rate of the SerDes is at a low speed, thereby reducing the power consumption of the SerDes. Through the 5ms frame format DDDDDDSUU, it can be determined that the length of the low-speed time period of the SerDes in the downlink (receiving) direction is 7 D slots + S slots, a total of 4ms, and the length of the low-speed time period of the SerDes in the uplink (sending) direction is 2 U slots + S slots, a total of 1.5ms, that is, when data is transmitted in the downlink direction, the SerDes is decelerated in the uplink direction, and when data is transmitted in the uplink direction, the SerDes is decelerated in the downlink direction. For another example, the SerDes in a certain communication system transmits data in the first 5ms of each 10ms cycle and does not transmit data in the last 5ms. Therefore, the low-speed time period of the SerDes is the last 5ms of each 10ms cycle, that is, the SerDes is slowed down in both the receiving and sending directions in the last 5ms of each 10ms cycle, so that the rate of the SerDes is at a low speed, thereby reducing the power consumption of the SerDes.

[0026] S1012. Determine the first moment and the second moment according to the low-speed time period.

[0027] The first moment is the moment when the rate of the SerDes is reduced from the first preset rate to the second preset rate, and the second moment is the moment when the rate of the SerDes is restored from the second preset rate to the first preset rate.

[0028] In one embodiment, if Figure 3 As shown, step S1012 includes the following steps:

[0029] S1012a, obtaining a start time and an end time of the low-speed time period, and using the start time as the first time;

[0030] S1012b, obtaining the time required for the rate of the SerDes to recover from the second preset rate to the first preset rate;

[0031] S1012c. Determine the second time according to the end time and the duration.

[0032] Among them, the time required for the SerDes rate to decrease from the first preset rate to the second preset rate is recorded as the first time period, and the time required for the SerDes rate to recover from the second preset rate to the first preset rate is recorded as the second time period. The sum of the first time period and the second time period is less than the length of the low-speed time period. The SerDes rate is always the second preset rate between the start time + the first time period and the end time - the second time period, and the second time is the end time - the second time period.

[0033] For example, the time required for the SerDes rate to be reduced from the first preset rate to the second preset rate is 0.5ms, and the time required for the SerDes rate to be restored from the second preset rate to the first preset rate is 0.5ms. The low-speed time period of SerDes is the last 5ms of each 10ms cycle, recorded as t1-t2, with a time length of 5ms, a start time of t1, and an end time of t2. The time length of the low-speed time period of 5ms is greater than the difference between the first time length of 0.5ms and the second time length of 0.5ms. Therefore, the starting time t1 is taken as the first time, that is, the time when the rate of SerDes is reduced from the first preset rate to the second preset rate, and the ending time t2-0.5ms is taken as the second time, that is, the time when the rate of SerDes is increased from the second preset rate to the first preset rate. It can be known that the rate of SerDes is always the second preset rate between t1+0.5ms and t2-0.5ms, that is, SerDes is in a low-speed state between t1+0.5ms and t2-0.5ms (4ms in total).

[0034] For another example, the low-speed time period of SerDes is the uplink direction within 5ms, recorded as t1~t2, and the time length of the low-speed time period is 1.5ms, the starting time is t1, and the end time is t2. The time length of the low-speed time period 1.5ms is greater than the sum of the first time length 0.5ms and the second time length 0.5ms. Therefore, the starting time t1 is taken as the first time, that is, the time when the rate of SerDes is reduced from the first preset rate to the second preset rate, and the end time t2-0.5ms is taken as the second time, that is, the time when the rate of SerDes is increased from the second preset rate to the first preset rate. It can be known that the rate of SerDes is always the second preset rate between t1+0.5ms-t2-0.5ms, that is, SerDes is in a low-speed state between t1+0.5ms~t2-0.5ms (a total of 0.5ms).

[0035] For another example, the low-speed time period of SerDes is the downlink direction within 5ms, recorded as t1~t2, and the time length of the low-speed time period is 4ms, the starting time is t1, and the end time is t2. The time length of the low-speed time period 4ms is greater than the sum of the first time length 0.5ms and the second time length 0.5ms. Therefore, the starting time t1 is taken as the first time, that is, the time when the rate of SerDes is reduced from the first preset rate to the second preset rate, and the end time t2-0.5ms is taken as the second time, that is, the time when the rate of SerDes is increased from the second preset rate to the first preset rate. It can be known that the rate of SerDes is always the second preset rate between t1+0.5ms-t2-0.5ms, that is, SerDes is in a low-speed state between t1+0.5ms~t2-0.5ms (a total of 3ms).

[0036] In one embodiment, the time required for the SerDes rate to be reduced from the first preset rate to the second preset rate, i.e., the first time, and the time required for the SerDes rate to be restored from the second preset rate to the first preset rate, i.e., the second time, are obtained by testing. For example, the SerDes rate is controlled to be reduced from the first preset rate to the second preset rate, and the start time of the rate reduction and the completion time of the reduction to the second preset rate are recorded. The first time is determined according to the start time of the rate reduction and the completion time of the reduction to the second preset rate; similarly, the SerDes rate is controlled to be restored from the second preset rate to the first preset rate, and the start time of the rate recovery and the completion time of the recovery to the first preset rate are recorded. The second time is determined according to the start time of the rate recovery and the completion time of the recovery to the first preset rate. Among them, the first time and the second time can be tested multiple times in the above manner, and finally the largest first time and second time are taken.

[0037] Step S102: When it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, wherein the first preset rate is greater than the second preset rate.

[0038] After obtaining the rate change moment of SerDes, when it is determined that the working moment of SerDes reaches the rate change moment, the rate of SerDes is controlled to switch between the first preset rate and the second preset rate, that is, under normal circumstances, SerDes works at the first preset rate, and when it is determined that the working moment of SerDes reaches the first moment, the rate of SerDes is controlled to be reduced from the first preset rate to the second preset rate and maintained for a period of time. After the rate of SerDes is reduced from the first preset rate to the second preset rate, when it is determined that the working moment of SerDes reaches the second moment, the rate of SerDes is controlled to be restored from the second preset rate to the first preset rate. Among them, assuming that the low-speed time period is t1~t2, the first time length required for the SerDes rate to be reduced from the first preset rate to the second preset rate is T1, and the second time length required for the SerDes rate to be restored from the second preset rate to the first preset rate is T2. Then, between t1+T1~t2-T2, the SerDes rate maintains the second preset rate, that is, between t1+T1~t2-T2, the SerDes works at a low rate.

[0039] In one embodiment, when it is determined that the working moment of SerDes has not reached the rate change moment, the rate of SerDes is controlled to remain at a first preset rate or a second preset rate, that is, when the rate of SerDes is the first preset rate, the rate of SerDes is controlled to remain unchanged at the first preset rate, and when the rate of SerDes is the second preset rate, the rate of SerDes is controlled to remain unchanged at the second preset rate.

[0040] In one embodiment, when it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the sending direction of the SerDes is controlled to switch between the first preset rate and the second preset rate; and / or the rate of the receiving direction of the SerDes is controlled to switch between the first preset rate and the second preset rate. For example, in a scenario where the sending direction of the SerDes transmits data and the receiving direction of the SerDes does not transmit data, when it is determined that the working moment of the SerDes reaches the first moment, the rate of the receiving direction of the SerDes is controlled to be reduced from the first preset rate to the second preset rate, and when it is determined that the working moment of the SerDes reaches the second moment, the rate of the receiving direction of the SerDes is controlled to be restored from the second preset rate to the second preset rate.

[0041] For another example, in a scenario where the receiving direction of the SerDes transmits data, but the sending direction of the SerDes does not transmit data, when it is determined that the working moment of the SerDes reaches the first moment, the rate of the sending direction of the SerDes is controlled to be reduced from the first preset rate to the second preset rate, and when it is determined that the working moment of the SerDes reaches the second moment, the rate of the sending direction of the SerDes is controlled to be restored from the second preset rate to the second preset rate. For another example, in a scenario where the SerDes transmits data in the first 5ms of each 10ms cycle, but does not transmit data in the next 5ms, when it is determined that the working moment of the SerDes reaches the first moment, the rates of the sending and receiving directions of the SerDes are controlled to be reduced from the first preset rate to the second preset rate at the same time, and when it is determined that the working moment of the SerDes reaches the second moment, the rates of the sending and receiving directions of the SerDes are controlled to be restored from the second preset rate to the second preset rate at the same time.

[0042] The SerDes control method provided by the embodiment of the present invention obtains the rate change moment of the SerDes, and when the working moment of the SerDes reaches the rate change moment, controls the rate of the SerDes to switch between a first preset rate and a second preset rate, that is, controls the rate of the SerDes to switch between a high rate and a low rate. This can reduce the power consumption of the SerDes while ensuring the normal operation of the SerDes, thereby reducing the power consumption of devices such as FPGA or FPSC, reducing the heat dissipation pressure of the communication system, and ensuring the normal operation of the communication system.

[0043] See also Figure 4 , Figure 4 It is a schematic block diagram of the structure of a SerDes control device provided by an embodiment of the present invention.

[0044] like Figure 4 As shown, the SerDes control device 200 includes a processor 201 and a memory 202, and the processor 201 and the memory 202 are connected via a bus 203, which is, for example, an I2C (Inter-integrated Circuit) bus. The SerDes control device 200 can be applied to a field programmable gate array (Field Programmable Gate Array, FPGA) and a field programmable system chip (Field Programmable System Chip, FPSC), etc.

[0045] Specifically, the processor 201 is used to provide computing and control capabilities to support the operation of the entire SerDes control device. The processor 201 can be a central processing unit (CPU), and the processor 201 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0046] Specifically, the memory 202 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk.

[0047] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a partial structure related to the solution of the present invention, and does not constitute a limitation on the SerDes control device to which the solution of the present invention is applied. The specific server may include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0048] The processor is used to run a program stored in the memory, and implement any one of the SerDes control methods provided by the embodiments of the present invention when executing the program.

[0049] In one embodiment, the processor is used to run a program stored in the memory, and implements the following steps when executing the program:

[0050] Obtaining the rate change moment of the SerDes;

[0051] When it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, and the first preset rate is greater than the second preset rate.

[0052] In one embodiment, the rate change moment includes a first moment when the rate of the SerDes decreases from a first preset rate to a second preset rate and a second moment when the rate of the SerDes increases from the second preset rate to the first preset rate.

[0053] In one implementation, when obtaining the rate change moment of the SerDes, the processor is used to implement:

[0054] Obtaining a low-speed time period of the SerDes;

[0055] The first time and the second time are determined according to the low speed time period.

[0056] In one embodiment, when determining the first moment and the second moment according to the low-speed time period, the processor is used to implement:

[0057] Obtaining a start time and an end time of the low-speed time period, and using the start time as the first time;

[0058] Obtaining the time required for the rate of the SerDes to recover from the second preset rate to the first preset rate;

[0059] The second time is determined according to the end time and the duration.

[0060] In one embodiment, the sum of a first duration required for the SerDes rate to decrease from a first preset rate to a second preset rate and a second duration required for the SerDes rate to recover from the second preset rate to the first preset rate is less than the length of the low-speed time period.

[0061] In one embodiment, when the processor controls the rate of the SerDes to switch between the first preset rate and the second preset rate when determining that the working moment of the SerDes reaches the rate change moment, it is configured to implement:

[0062] When it is determined that the working time of the SerDes reaches the first time, controlling the rate of the SerDes to decrease from the first preset rate to the second preset rate;

[0063] When it is determined that the working time of the SerDes reaches the second time, the rate of the SerDes is controlled to be restored from the second preset rate to the first preset rate.

[0064] In one embodiment, the first preset rate and the second preset rate are determined according to a protocol adopted by the SerDes.

[0065] In one embodiment, when the processor controls the rate of the SerDes to switch between the first preset rate and the second preset rate, it is used to implement:

[0066] Controlling the rate of the sending direction of the SerDes to switch between a first preset rate and a second preset rate; and / or

[0067] The rate of the receiving direction of the SerDes is controlled to switch between a first preset rate and a second preset rate.

[0068] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the SerDes control device described above can refer to the corresponding process in the aforementioned SerDes control method embodiment, and will not be repeated here.

[0069] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the following steps:

[0070] Obtaining the rate change moment of the SerDes;

[0071] When it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, and the first preset rate is greater than the second preset rate.

[0072] In one embodiment, the rate change moment includes a first moment when the rate of the SerDes decreases from a first preset rate to a second preset rate and a second moment when the rate of the SerDes increases from the second preset rate to the first preset rate.

[0073] In one implementation, when obtaining the rate change moment of the SerDes, the processor is used to implement:

[0074] Obtaining a low-speed time period of the SerDes;

[0075] The first time and the second time are determined according to the low speed time period.

[0076] In one embodiment, when determining the first moment and the second moment according to the low-speed time period, the processor is used to implement:

[0077] Obtaining a start time and an end time of the low-speed time period, and using the start time as the first time;

[0078] Obtaining the time required for the rate of the SerDes to recover from the second preset rate to the first preset rate;

[0079] The second time is determined according to the end time and the duration.

[0080] In one embodiment, the sum of a first duration required for the SerDes rate to decrease from a first preset rate to a second preset rate and a second duration required for the SerDes rate to recover from the second preset rate to the first preset rate is less than the length of the low-speed time period.

[0081] In one embodiment, when the processor controls the rate of the SerDes to switch between the first preset rate and the second preset rate when determining that the working moment of the SerDes reaches the rate change moment, it is configured to implement:

[0082] When it is determined that the working time of the SerDes reaches the first time, controlling the rate of the SerDes to decrease from the first preset rate to the second preset rate;

[0083] When it is determined that the working time of the SerDes reaches the second time, the rate of the SerDes is controlled to be restored from the second preset rate to the first preset rate.

[0084] In one embodiment, the first preset rate and the second preset rate are determined according to a protocol adopted by the SerDes.

[0085] In one embodiment, when the processor controls the rate of the SerDes to switch between the first preset rate and the second preset rate, it is used to implement:

[0086] Controlling the rate of the sending direction of the SerDes to switch between a first preset rate and a second preset rate; and / or

[0087] The rate of the receiving direction of the SerDes is controlled to switch between a first preset rate and a second preset rate.

[0088] Wherein, the storage medium may be an internal storage unit of the SerDes control device described in the aforementioned embodiment, such as a hard disk or memory of the SerDes control device. The storage medium may also be an external storage device of the SerDes control device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the SerDes control device. In some embodiments, the storage medium may also be a field programmable gate array (Field Programmable Gate Array, FPGA) and a field programmable system chip (Field Programmable System Chip, FPSC), etc.

[0089] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0090] It should be understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations. It should be noted that, in this article, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "including a..." does not exclude the presence of other identical elements in the process, method, article or system including the element.

[0091] The serial numbers of the embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments. The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A high-speed serial interface SerDes control method, characterized in that: include: Get the low-speed time period of SerDes; Obtaining the start time and the end time of the low-speed time period, and taking the start time as the first time; Obtaining a time duration required for the rate of the SerDes to recover from a second preset rate to a first preset rate, where the first preset rate is greater than the second preset rate; Determine a second time according to the end time and the duration; When it is determined that the working moment of the SerDes reaches the rate change moment, controlling the rate of the SerDes to switch between the first preset rate and the second preset rate; The rate change moment includes a first moment when the rate of the SerDes decreases from a first preset rate to a second preset rate and a second moment when the rate of the SerDes increases from the second preset rate to the first preset rate.

2. The SerDes control method according to claim 1, characterized in that: The sum of a first duration required for the SerDes rate to decrease from the first preset rate to the second preset rate and a second duration required for the SerDes rate to recover from the second preset rate to the first preset rate is less than the length of the low-speed time period.

3. The SerDes control method according to claim 1, characterized in that: When it is determined that the working moment of the SerDes reaches the rate change moment, controlling the rate of the SerDes to switch between the first preset rate and the second preset rate includes: When it is determined that the working time of the SerDes reaches the first time, controlling the rate of the SerDes to decrease from the first preset rate to the second preset rate; When it is determined that the working time of the SerDes reaches the second time, the rate of the SerDes is controlled to be restored from the second preset rate to the first preset rate.

4. The SerDes control method according to any one of claims 1 to 3, characterized in that: The first preset rate and the second preset rate are determined according to a protocol adopted by the SerDes.

5. The SerDes control method according to any one of claims 1 to 3, characterized in that: The controlling the rate of the SerDes to switch between the first preset rate and the second preset rate includes: Controlling the rate of the sending direction of the SerDes to switch between a first preset rate and a second preset rate; and / or The rate of the receiving direction of the SerDes is controlled to switch between a first preset rate and a second preset rate.

6. A SerDes control device, characterized in that: The SerDes control device includes a processor, a memory, a program stored in the memory and executable by the processor, and a data bus for realizing connection communication between the processor and the memory, wherein when the program is executed by the processor, the steps of the SerDes control method according to any one of claims 1 to 5 are realized.

7. A storage medium, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the SerDes control method according to any one of claims 1 to 5.

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