Display device

Abstract

An embodiment of the present application relates to a display device including a display panel having a display area displaying an image and a non-display area adjacent to the display area, and a driving circuit disposed in the non-display area, the driving circuit including a plurality of bumps disposed in a plurality of rows, and a first alignment mark bump disposed at an end of at least one of the plurality of rows, thereby improving durability and reliability of the display device.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and more particularly, to a display device that prevents damage of a display panel generated in a bonding process of a display panel and a driving circuit to improve durability and reliability. BACKGROUND

[0002] A display device such as a television, a monitor, a smart phone, and a desktop, which provides an image to a user, includes a display panel that displays an image. As the display panel, various display panels such as a liquid crystal display panel, an organic light emitting display panel, an electro wetting display panel, and an electrophoretic display panel have been developed.

[0003] Recently, as the technology of a display device is developed, a display device including a flexible display panel is being developed. The display panel includes a plurality of pixels that display an image and a driving chip that drives each pixel. Each pixel is disposed in a display area of the display panel, and the driving chip is disposed in a non-display area of the display panel that surrounds the display area. A bending portion is defined between the driving chip and the display area, and the bending portion is bent so that the driving chip is disposed in a lower portion of the display panel. SUMMARY

[0004] An object of the present application is to provide a display device that improves reliability and durability.

[0005] An object of the present application is to provide a display device that includes a flexible base layer while preventing damage of a display panel that can be generated in a bonding process of a driving circuit and a display panel to improve durability and reliability.

[0006] An embodiment of the present application relates to a display device including a display panel having a display area that displays an image and a non-display area adjacent to the display area, and a driving circuit disposed in the non-display area, the driving circuit including a plurality of bumps disposed in a plurality of rows, and a first alignment mark bump disposed at an end of at least one row of the plurality of rows.

[0007] The plurality of bumps can include a plurality of first bumps disposed in a first row adjacent to the display area among the plurality of rows, and the first alignment mark bump can be disposed in the first row.

[0008] The plurality of first protrusions can include a plurality of 11th protrusions configured on a left side with reference to the first reference protrusion, and a plurality of 12th protrusions configured on a right side with reference to the first reference protrusion, the plurality of 11th protrusions being configured to form an acute angle in a clockwise direction with reference to a reference line defined in a center of the driving circuit in a direction crossing the plurality of row directions of the driving circuit, and the plurality of 12th protrusions being configured to form an acute angle in a counterclockwise direction with reference to the reference line.

[0009] The first alignment mark protrusion can have substantially the same thickness as the plurality of first protrusions.

[0010] The plurality of protrusions can further include a dummy protrusion configured in the first row and between the plurality of first protrusions and the first alignment mark protrusion.

[0011] The plurality of protrusions can further include a plurality of second protrusions configured in a second row spaced apart from the display area, the first row being disposed between the second row and the display area.

[0012] The plurality of first protrusions configured in the first row can be output protrusions outputting driving signals for driving light emitting elements included in the display panel.

[0013] The first row in which the plurality of first protrusions is configured can be defined at one end of the driving circuit, and the plurality of protrusions can include a plurality of input protrusions configured in an input row defined at the other end of the driving circuit opposite to the one end among the plurality of rows.

[0014] The driving circuit can further include a second alignment mark protrusion configured at an end of the input row.

[0015] The display panel can include a plurality of pads corresponding to the plurality of protrusions, and a panel alignment mark protrusion corresponding to the first alignment mark protrusion.

[0016] The first alignment mark protrusion can have a thickness of 7 μm or more and 10 μm or less.

[0017] The driving circuit can further include an alignment check mark protrusion overlapping the first alignment mark protrusion in a column direction, the alignment check mark protrusion having substantially the same thickness as the first alignment mark protrusion.

[0018] The display panel can include a first non-folded area, a folded area, and a second non-folded area defined in sequence, the folded area being folded with reference to a folding axis.

[0019] The driving circuit can further include a driving chip configured with the plurality of bumps and the first alignment mark bump, the first alignment mark bump being configured adjacent to one end of the driving chip.

[0020] The display device according to an embodiment of the present disclosure can further include an anisotropic conductive film disposed between the driving circuit and the display panel.

[0021] The plurality of bumps and the first alignment mark bump can include the same substance.

[0022] The driving circuit can further include a corner bump disposed at a corner of the driving circuit, the corner bump having substantially the same thickness as the first alignment mark bump.

[0023] The driving circuit can define a plurality of long sides extending in a direction parallel to the plurality of row directions and a plurality of short sides extending in a direction crossing the plurality of row directions, and the driving circuit can further include a long side side bump disposed adjacent to at least one of the plurality of long sides.

[0024] The long side side bump can have substantially the same thickness as the first alignment mark bump.

[0025] The driving circuit can further include a bezel bump disposed adjacent to the plurality of long sides and the plurality of short sides, the bezel bump having substantially the same thickness as the first alignment mark bump.

[0026] A display device according to an embodiment of the present disclosure can include a display panel including a display area displaying an image and a non-display area adjacent to the display area, and a driving circuit disposed in the non-display area, the driving circuit including a plurality of first bumps disposed in a first row, a plurality of second bumps disposed in a second row, and an alignment mark bump disposed at an end of at least one of the first row and the second row.

[0027] The plurality of first bumps and the plurality of second bumps can have substantially the same thickness as the alignment mark bump.

[0028] (EFFECT OF INVENTION)

[0029] According to an embodiment of the present disclosure, an alignment mark bump disposed at an end of a driving circuit can be formed to have a thickness corresponding to a thickness of a bump included in the driving circuit, and thus, it is possible to prevent a problem such as a bend from occurring on a display panel in a process of bonding the driving circuit and the display panel, and it is possible to improve durability and reliability of a display device. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 FIG. 1 is a perspective view of a display device according to an embodiment of the present application.

[0031] Figure 2 FIG. 2 is a view showing a folded state of the display device according to an embodiment of the present application.

[0032] Figure 3 FIG. 3 is a perspective view of a display device according to an embodiment of the present application.

[0033] Figure 4 FIG. 4 is a view showing a folded state of the display device according to an embodiment of the present application.

[0034] Figure 5 FIG. 5 is a plan view of a display device according to an embodiment of the present application.

[0035] Figure 6 FIG. 6 is a sectional view of a display panel according to an embodiment of the present application.

[0036] Figure 7 FIG. 7 is a sectional view of a portion of a display device according to an embodiment of the present application.

[0037] Figure 8 FIG. 8 is a plan view showing bump arrangement of a driving circuit according to an embodiment of the present application.

[0038] Figure 9a and Figure 9b FIG. 9 is a sectional view of a portion of a display device according to an embodiment of the present application.

[0039] Figure 10 FIG. 10 is a sectional view of another portion of a display device according to an embodiment of the present application.

[0040] Figure 11 FIG. 11 is a sectional view of still another portion of a display device according to an embodiment of the present application.

[0041] Figure 12 and Figure 13 FIG. 12 is a plan view showing bump arrangement of a driving circuit according to an embodiment of the present application.

[0042] Symbol Explanation:

[0043] DD: display device; DP: display panel; DDV: driving circuit; DDV-BP: bump; ALM1, ALM2: alignment mark bump. DETAILED DESCRIPTION

[0044] Hereinafter, each embodiment of the present application will be described with reference to the accompanying drawings. In the present specification, in the case where a certain constitutional element (or region, layer, portion, etc.) is mentioned to be located on, connected to, or combined with another constitutional element, it means that it can be directly connected / bonded thereto, or a third constitutional element can be further disposed therebetween.

[0045] The same reference numerals are used to designate the same elements. Also, in each drawing, the thickness, ratio, and size of each constitutional element are exaggerated for the sake of effective explanation of technical contents. "And / or" includes all combinations of one or more elements definable in relation thereto.

[0046] The terms of first, second, etc. can be used to explain various constitutional elements, but the constitutional elements described should not be limited to the terms described. The terms described are used only for the purpose of distinguishing one constitutional element from another. For example, a first constitutional element can be named a second constitutional element, and similarly, a second constitutional element can be named a first constitutional element, without departing from the scope of the present application. The singular expression herein includes the plural expression unless explicitly stated to the contrary.

[0047] Also, the terms of "below", "under", "above", "upper", etc. are used for the purpose of explanation of the connection relationship of each constitutional element illustrated. The terms described are relative concepts, and are explained based on the direction of the illustration.

[0048] The terms of "include" or "have" etc. should be understood to mean the existence of the features, numbers, steps, operations, constitutional elements, components, or combinations thereof described in the specification, and not to exclude the existence or additional possibility of one or more other features, numbers, steps, operations, constitutional elements, components, or combinations thereof in advance.

[0049] Hereinafter, a display device to which an embodiment of the present application relates, a display panel included in the display device, and a manufacturing method of the display panel will be described.

[0050] Figure 1 is a perspective view of a display device to which an embodiment of the present application relates. Figure 2 is a view showing Figure 1 is a view showing a folded state of the display device illustrated.

[0051] Referring to Figure 1 , the display device DD to which an embodiment of the present application relates can have a rectangular shape including a plurality of long sides in a first direction DR1 and a plurality of short sides in a second direction DR2 intersecting the first direction DR1. However, it is not limited thereto, and the display device DD can have various shapes such as a circular shape and a polygonal shape. The display device DD can be a flexible display device.

[0052] Hereinafter, the direction that substantially intersects the plane defined by the first direction DR1 and the second direction DR2 will be defined as the third direction DR3. Furthermore, in this specification, "when viewed on a plane" can be defined as the state of observation with reference to the third direction DR3.

[0053] The display device DD may include a folded region FA and multiple non-folded regions NFA1 and NFA2. The non-folded regions NFA1 and NFA2 may include a first non-folded region NFA1 and a second non-folded region NFA2. The folded region FA may be disposed between the first non-folded region NFA1 and the second non-folded region NFA2. The folded region FA, the first non-folded region NFA1, and the second non-folded region NFA2 may be arranged in a first direction DR1.

[0054] An illustrative example shows a folded region FA and two non-folded regions NFA1 and NFA2, but the number of folded regions FA and non-folded regions NFA1 and NFA2 is not limited thereto. For example, the display device DD may include more than two non-folded regions and multiple folded regions disposed between the multiple non-folded regions.

[0055] The upper surface of the display device DD can be defined as the display surface DS, which can have a plane defined by a first direction DR1 and a second direction DR2. Through the display surface DS, the image IM generated by the display device DD can be provided to the user.

[0056] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and may define the border of the display device DD printed with predetermined colors.

[0057] The display device DD can sense external input TC applied from the outside. External input TC can include various forms of input provided from outside the display device DD. External input TC can be provided in various forms as input applied from the outside.

[0058] For example, external input TC, in addition to contact generated by a user's hand or other body part, may also include external input applied near or at a predetermined distance from the display device DD (e.g., hovering). Furthermore, it can take various forms such as force, pressure, and light, and is not limited to any one embodiment. Figure 1 The image shows the user's hand as an example of an external input TC.

[0059] Reference Figure 2The display device DD can be a foldable display device DD that can be folded or defolded. For example, the display device DD can be folded by bending the folding region FA with reference to a folding axis FX parallel to the second direction DR2. The folding axis FX can be defined as a short axis parallel to the short side of the display device DD.

[0060] When the display device DD is folded, the first non-folded region NFA1 and the second non-folded region NFA2 face each other, and the display device DD can be in-folded so that the display surface DS is not exposed to the outside.

[0061] Figure 3 This is a perspective view of a display device according to an embodiment of the present invention. Figure 4 It means Figure 3 The diagram shows the folded state of the display device.

[0062] In addition to folding operations Figure 3 The display device DD-1 shown can essentially have the same as Figure 1 The display device DD shown has the same configuration. Therefore, the folding operation of the display device DD-1 will be described below.

[0063] Reference Figure 3 and Figure 4 The display device DD-1 may include a folded region FA′ and multiple non-folded regions NFA1′ and NFA2′. The non-folded regions NFA1′ and NFA2′ may include a first non-folded region NFA1′ and a second non-folded region NFA2′. The folded region FA′ may be configured between the first non-folded region NFA1′ and the second non-folded region NFA2′. The folded region FA′, the first non-folded region NFA1′, and the second non-folded region NFA2′ may be configured on a second direction DR2.

[0064] The folding region FA′ can be bent with reference to the folding axis FX′ parallel to the first direction DR1, thereby folding the display device DD-1. The folding axis FX′ can be defined as a long axis parallel to the long side of the display device DD-1. Figure 1 The display device DD shown can be folded with its short axis as a reference, unlike this, Figure 3 The display device DD-1 shown can be folded with respect to its long axis. The display device DD-1 can be in-folded so that the display surface DS is not exposed to the outside.

[0065] Hereinafter, the display device DD folded inward with reference to the folding axis FX parallel to the short axis will be exemplarily described. However, it is not limited thereto, and the display device of an embodiment can be folded inward with reference to the folding axis parallel to the long axis or folded outward with reference to the folding axis defined at the lower side of the display device.

[0066] Figure 5 is Figure 1 a plan view of the display device.

[0067] Referring to Figure 5 , the display device DD can include a display panel DP, a scan driver SDV, a data driver DDV, and an emission driver EDV.

[0068] The display panel DP to which an embodiment of the disclosure relates can be a light emitting type display panel, and is not particularly limited. For example, the display panel DP can be an organic light emitting display panel or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting display panel can include an organic light emitting substance. The light emitting layer of the quantum dot light emitting display panel can include quantum dots, quantum rods, or the like. Hereinafter, the display panel DP will be described with reference to an organic light emitting display panel.

[0069] The display panel DP can be a flexible display panel. For example, the display panel DP can include a plurality of electronic elements disposed on a flexible substrate. The display panel DP can be longer in the first direction DR1 than in the second direction DR2. The display panel DP can have a plane defined by the first direction DR1 and the second direction DR2.

[0070] The display panel DP can include a first area AA1, a second area AA2, and a bending area BA disposed between the first area AA1 and the second area AA2. The bending area BA can extend in the second direction DR2, and the first area AA1, the bending area BA, and the second area AA2 can be arranged in the first direction DR1.

[0071] The first area AA1 can have a plurality of long sides extending in the first direction DR1 and opposite to each other in the second direction DR2. The length of the bending area BA and the second area AA2 can be less than the length of the first area AA1 with reference to the second direction DR2.

[0072] The first area AA1 can include a display area DA and a non-display area NDA of a periphery of the display area DA. The non-display area NDA can surround the display area DA. The display area DA can be an area in which an image is displayed, and the non-display area NDA can be an area in which an image is not displayed. The second area AA2 and the bending area BA can be areas in which an image is not displayed.

[0073] The first region AA1 can include, when viewed from the second direction DR2, the first non-folded region NFA1, the second non-folded region NFA2, and a folded region FA between the first non-folded region NFA1 and the second non-folded region NFA2.

[0074] The display panel DP can include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a first power line PL1, a second power line PL2, a connection line CNL, and a plurality of signal pads DP-PD. m and n are natural numbers. Each pixel PX can be disposed in the display region DA and connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm.

[0075] The scan driving portion SDV and the emission driving portion EDV can be disposed in the non-display region NDA. The scan driving portion SDV and the emission driving portion EDV can be disposed in the non-display region NDA adjacent to each long side of the first region AA1. The data driving portion DDV can be disposed in the second region AA2. The data driving portion DDV can be mounted on the second region AA2 in the form of an integrated circuit chip.

[0076] The scan lines SL1 to SLm can extend in the second direction DR2 and be connected to the scan driving portion SDV. The data lines DL1 to DLn can extend in the first direction DR1 and be connected to the data driving portion DDV via the bent region BA. The emission lines EL1 to ELm can extend in the second direction DR2 and be connected to the emission driving portion EDV.

[0077] The first power line PL1 can extend in the first direction DR1 and be disposed in the non-display region NDA. The first power line PL1 can be disposed between the display region DA and the emission driving portion EDV. However, it is not limited thereto, and the first power line PL1 can also be disposed between the display region DA and the scan driving portion SDV.

[0078] The first power line PL1 can extend in the second region AA2 via the bent region BA. The first power line PL1 can extend toward a lower end of the second region AA2 when viewed in plan. The first power line PL1 can receive a first voltage.

[0079] The second power line PL2 can be disposed in the non-display region NDA adjacent to each long side of the first region AA1 and in the non-display region NDA facing the second region AA2 with the display region DA interposed therebetween. The second power line PL2 can be disposed at a position further outward than the scan driving portion SDV and the emission driving portion EDV.

[0080] The second power line PL2 can extend in the second area AA2 via the bent area BA. The second power line PL2 can extend along the first direction DR1 with the data driving part DDV sandwiched therebetween in the second area AA2. The second power line PL2 can extend toward a lower end of the second area AA2 when viewed in plan.

[0081] The second power line PL2 can receive a second voltage having a level lower than the first voltage. For ease of illustration, connection relationships are not shown, but the second power line PL2 can extend in the display area DA to be connected with the respective pixels PX, and the second voltage can be supplied to the respective pixels PX through the second power line PL2.

[0082] The respective connection lines CNL can extend in the second direction DR2 and be arranged in the first direction DR1. The connection lines CNL can be connected with the first power line PL1 and the pixels PX. The first voltage can be applied to the pixels PX through the first power line PL1 and the connection lines CNL connected with each other.

[0083] The first control line CSL1 can be connected with the scan driving part SDV and extend toward the lower end of the second area AA2 via the bent area BA. The second control line CSL2 can be connected with the emission driving part EDV and extend toward the lower end of the second area AA2 via the bent area BA. The data driving part DDV can be disposed between the first control line CSL1 and the second control line CSL2.

[0084] The plurality of signal pads DP-PD can be disposed adjacent to the lower end of the second area AA2 when viewed in plan. The data driving part DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 can be connected with the signal pads DP-PD.

[0085] The data lines DL1-DLn can be connected with the corresponding signal pads DP-PD through the data driving part DDV. For example, the data lines DL1-DLn can be connected with the data driving part DDV, and the data driving part DDV can be connected with the signal pads DP-PD corresponding to the data lines DL1-DLn, respectively.

[0086] The timing controller can control operations of the scan driving part SDV, the data driving part DDV, and the emission driving part EDV. The timing controller can generate scan control signals, data control signals, and emission control signals in response to a control signal received from the outside.

[0087] A scan control signal can be supplied to the scan driving section SDV through a first control line CSL1. An emission control signal can be supplied to the emission driving section EDV through a second control line CSL2. A data control signal can be supplied to the data driving section DDV. The timing controller can receive an image signal from the outside and transform a data format of the image signal into an interface specification suitable for the data driving section DDV to supply to the data driving section DDV.

[0088] The scan driving section SDV can generate a plurality of scan signals in response to the scan control signal. Each scan signal can be applied to each pixel PX through a scan line SL1 to SLm. Each scan signal can be applied to each pixel PX in turn.

[0089] The data driving section DDV can generate a plurality of data voltages corresponding to the image signal in response to the data control signal. Each data voltage can be applied to each pixel PX through a data line DL1 to DLn. The emission driving section EDV can generate a plurality of emission signals in response to the emission control signal. Each emission signal can be applied to each pixel PX through an emission line EL1 to ELm. The data driving section DDV, the scan driving section SDV, and the emission driving section EDV can be referred to as a driving circuit to which an embodiment of the present application relates, and hereinafter, the data driving section DDV is explained as an example in explaining the driving circuit to which an embodiment of the present application relates, and the data driving section DDV is referred to as a driving circuit DDV.

[0090] The pixel PX can receive the supply of the data voltage in response to the scan signal. The pixel PX can emit light of a luminance corresponding to the data voltage in response to the emission signal, thereby displaying an image. An emission time of the pixel PX can be controlled according to the emission signal.

[0091] Each pixel PX can include an organic light emitting element. A first voltage can be applied to an anode of the organic light emitting element, and a second voltage can be applied to a cathode of the organic light emitting element. The organic light emitting element can operate in response to the application of the first voltage and the second voltage.

[0092] The display device DD can further include a circuit substrate PCB electrically connected with the display panel DP. The circuit substrate PCB can be a rigid circuit substrate or a flexible circuit substrate.

[0093] A timing control circuit that controls the operation of the display panel DP can be disposed in the circuit substrate PCB. In addition, an input sensing section ISP (refer to FIG. 1) that senses an input of a user can be disposed in the circuit substrate PCB. Figure 6The timing control circuit and the input sensing circuit can be mounted on the circuit substrate PCB in the form of an integrated chip. In an embodiment of the present application, the timing control circuit and the input sensing circuit can be mounted on the circuit substrate PCB in the form of an integrated chip. The circuit substrate PCB can include a circuit substrate pad PCB-PD electrically connected to the signal pad DP-PD of the display panel DP. Although not shown, the circuit substrate PCB can also include signal lines connecting the circuit substrate pad PCB-PD with the timing control circuit and / or the input sensing circuit. In addition, the circuit substrate pad PCB-PD can be an output pad, and the circuit substrate PCB can also include an input pad.

[0094] Figure 6 is a diagram exemplarily showing a cross section of a display panel to which an embodiment of the present application relates. Exemplarily, in Figure 6 , a cross section of the display panel viewed from the first direction DR1 is shown.

[0095] Referring to Figure 6 , the display panel DP can include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, a thin film encapsulation layer TFE disposed on the display element layer DP-OLED, and an input sensing part ISP disposed on the thin film encapsulation layer TFE. The display element layer DP-OLED can be disposed on the display area DA.

[0096] The base layer BL can include the display area DA and a non-display area NDA of a periphery of the display area DA. The base layer BL can include a flexible substance. The base layer BL can include a flexible plastic substance. For example, the base layer BL can include polyimide (PI). The base layer BL can include polyimide having a low modulus.

[0097] The circuit element layer DP-CL can include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, and the like. The insulating layer, the semiconductor layer, and the conductive layer can be formed on the base layer BL by coating, deposition, and the like. Then, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned by a plurality of photolithography processes, thereby forming the semiconductor pattern, the conductive pattern, and the signal line.

[0098] The circuit element layer DP-CL can include a transistor formed of the semiconductor pattern, the conductive pattern, and the signal line. The display element layer DP-OLED can include a light emitting element connected to the transistor. The pixel PX can include the transistor and the light emitting element.

[0099] The thin film encapsulation layer TFE can be configured on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE can include inorganic layers, organic layers, and inorganic layers which are sequentially stacked. The inorganic layers can include inorganic substances to protect the pixels PX from moisture / oxygen. The organic layers can include organic substances to protect the pixels PX from foreign substances such as dust particles.

[0100] The input sensing part ISP can include a plurality of sensors (not shown) for sensing an external input TC (refer to Figure 1 ). Each of the sensors can capacitively sense the external input TC (refer to Figure 1 ). The external input TC (refer to Figure 1 ) can include various forms of input such as a part of a user's body, light, heat, a pen, or pressure.

[0101] The input sensing part ISP can be directly manufactured on the thin film encapsulation layer TFE when the display panel DP is manufactured. However, it is not limited thereto, and the input sensing part ISP can be manufactured as a panel independent of the display panel DP, and thus attached to the display panel DP through an adhesive layer.

[0102] Figure 7 is a cross-sectional view of a portion of a display apparatus according to an embodiment of the present application. In Figure 7 , a cross-sectional view taken along the I-I' line shown in Figure 5 is shown.

[0103] Referring to Figure 5 and Figure 7 together, a driving circuit DDV according to an embodiment of the present application includes a driving chip DV-BS and a plurality of bumps DDV-BP. The plurality of bumps DDV-BP can be configured in a plurality of rows. The plurality of bumps DDV-BP can include output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, DV-OP5 for driving the display panel DP, and input bumps DV-IP for receiving a control signal and a power source, etc. provided from a circuit substrate PCB. The output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, DV-OP5 are provided in a plurality of rows, and as shown in Figure 7 , a plurality of first bumps DV-OP1, a plurality of second bumps DV-OP2, a plurality of third bumps DV-OP3, a plurality of fourth bumps DV-OP4, and a plurality of fifth bumps DV-OP5 are provided in 5 rows. However, it is not limited thereto, and the output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, DV-OP5 can be arranged in 2 to 4 rows or more than 6 rows. Hereinafter, a detailed description of the plurality of bumps DDV-BP included in the driving circuit DDV will be described later.

[0104] A plurality of pads PD corresponding to the plurality of bumps DDV-BP can be included on the base layer BL of the display panel DP. The plurality of pads PD can include a first pad PD1, a second pad PD2, a third pad PD3, a fourth pad PD4, a fifth pad PD5, and a sixth pad PD6 in correspondence with the plurality of bumps DDV-BP, respectively. The first pad PD1, the second pad PD2, the third pad PD3, the fourth pad PD4, and the fifth pad PD5 can be configured to correspond to the plurality of output bumps DV-OP1, DV-OP2, DV-OP3, DV-OP4, DV-OP5, and the sixth pad PD6 can be configured to correspond to the input bump DV-IP.

[0105] An anisotropic conductive film ACF can be configured between the display panel DP and the driving circuit DDV, and the display panel DP and the driving circuit DDV can be attached to each other by the anisotropic conductive film ACF. The anisotropic conductive film ACF can include an adhesive resin RS and conductive particles CB. In the anisotropic conductive film ACF, the conductive particles CB can be configured between the plurality of bumps DDV-BP and the plurality of pads PD, thereby electrically connecting the plurality of bumps DDV-BP and the plurality of pads PD. The display panel DP and the driving circuit DDV can be electrically connected by a process of applying pressure and heat after the anisotropic conductive film ACF is interposed therebetween. However, it is not limited thereto, and in the display device DD of one embodiment, the anisotropic conductive film ACF can be omitted, and the display panel DP and the driving circuit DDV can be electrically connected by a process of ultrasonic bonding or the like.

[0106] The circuit substrate PCB can be electrically connected to the display panel DP by the anisotropic conductive film ACF. The circuit substrate PCB can include a circuit base layer PCB-BS and a circuit substrate pad PCB-PD configured on the circuit base layer PCB-BS to be electrically connected to the signal pad DP-PD of the display panel DP.

[0107] Hereinafter, a specific arrangement of the plurality of bumps DDV-BP of the driving circuit DDV will be described with reference to Figure 8

[0108] Figure 8 is a plan view illustrating an arrangement of bumps of a driving circuit according to one embodiment of the present application.

[0109] Hereinafter, a specific arrangement of the plurality of bumps DDV-BP of the driving circuit DDV will be described with reference to Figure 7 and Figure 8 ​The multiple bumps DDV-BP may include output bumps and input bumps DV-IP configured on input rows RI. The output bumps include multiple first bumps DV-OP1, multiple second bumps DV-OP2, multiple third bumps DV-OP3, multiple fourth bumps DV-OP4, and multiple fifth bumps DV-OP5 configured on multiple output rows R-1, R-2, R-3, R-4, and R-5. Figure 7 and Figure 8 The example illustrates an output bump consisting of five output rows R-1, R-2, R-3, R-4, and R-5, but it is not limited to this; the output bump can also be arranged in two to four rows, or even six or more rows. The first row R-1 of the multiple output rows R-1, R-2, R-3, R-4, and R-5 can be adjacent to the display area DA in a display device DD suitable for one embodiment. Figure 5 The nearest row. That is, the first row R-1 can be defined adjacent to the first long side DDV-S1 of the long sides DDV-S1 and DDV-S2 of the drive circuit DDV, which is adjacent to the display area DA. The input row RI can be defined adjacent to the second long side DDV-S2, which is away from the display area DA. Although not shown, the drive circuit DDV may also include multiple signal lines connected to multiple output bumps and multiple input bumps respectively. Multiple output bumps and multiple input bumps can be configured along the second direction DR2 respectively, and the multiple output bumps and multiple input bumps can be spaced apart along the first direction DR1. The long sides DDV-S1 and DDV-S2 of the drive circuit DDV can extend along the second direction DR2, and the short sides DDV-S3 and DDV-S4 of the drive circuit DDV can extend along the first direction DR1. Hereinafter, in this specification, the first direction DR1 may be referred to as the column direction, and the second direction DR2 may be referred to as the row direction.

[0110] The plurality of first bumps DV-OP1, the plurality of second bumps DV-OP2, the plurality of third bumps DV-OP3, the plurality of fourth bumps DV-OP4, and the plurality of fifth bumps DV-OP5 can each include n bumps. That is, the number of each bump constituting the plurality of first bumps DV-OP1, the plurality of second bumps DV-OP2, the plurality of third bumps DV-OP3, the plurality of fourth bumps DV-OP4, and the plurality of fifth bumps DV-OP5 can be the same. However, it is not limited to this; depending on the structure of the display device, the number of bumps arranged in each column can be different.

[0111] The centrally-arranged first reference bump among the plurality of first bumps DV-OP1 and the centrally-arranged second reference bump among the plurality of second bumps DV-OP2 can be arranged on a reference line VL defined by the second direction DR2. Also, the centrally-arranged third reference bump among the plurality of third bumps DV-OP3 can also be arranged on the reference line VL. Likewise, the centrally-arranged fourth reference bump among the plurality of fourth bumps DV-OP4 can also be arranged on the reference line VL, and the centrally-arranged fifth reference bump among the plurality of fifth bumps DV-OP5 can also be arranged on the reference line VL.

[0112] The plurality of first bumps DV-OP1 can include a plurality of 11th bumps DV-OP11 arranged approximately on the left side with the first reference bump as a center and a plurality of 12th bumps DV-OP12 arranged approximately on the right side with the first reference bump as a center.

[0113] The plurality of second bumps DV-OP2 can likewise include a plurality of 21st bumps DV-OP21 arranged on the left side opposite to each other with the second reference bump as a center and a plurality of 22nd bumps DV-OP22 arranged on the right side opposite to each other with the second reference bump as a center, as with the plurality of first bumps DV-OP1. Also, the plurality of third bumps DV-OP3 can likewise include a plurality of 31st bumps DV-OP31 arranged on the left side opposite to each other with the third reference bump as a center and a plurality of 32nd bumps DV-OP32 arranged on the right side opposite to each other with the third reference bump as a center. Likewise, the plurality of fourth bumps DV-OP4 can include a plurality of 41st bumps DV-OP41 arranged on the left side opposite to each other with the fourth reference bump as a center and a plurality of 42nd bumps DV-OP42 arranged on the right side opposite to each other with the fourth reference bump as a center, and the plurality of fifth bumps DV-OP5 can include a plurality of 51st bumps DV-OP51 arranged on the left side opposite to each other with the fifth reference bump as a center and a plurality of 52nd bumps DV-OP52 arranged on the right side opposite to each other with the fifth reference bump as a center.

[0114] The plurality of 11th protrusions DV-OP11, the plurality of 21st protrusions DV-OP21, the plurality of 31st protrusions DV-OP31, the plurality of 41st protrusions DV-OP41, and the plurality of 51st protrusions DV-OP51 disposed on the left side of the reference line VL are respectively configured to have a preset inclination with reference to the reference line VL. The preset inclination can be an inclination having a certain value, i.e., a certain inclination. Specifically, the plurality of 11th protrusions DV-OP11, the plurality of 21st protrusions DV-OP21, the plurality of 31st protrusions DV-OP31, the plurality of 41st protrusions DV-OP41, and the plurality of 51st protrusions DV-OP51 can be configured to form an acute angle in the clockwise direction with respect to the reference line VL, respectively. Symmetrically thereto, the plurality of 12th protrusions DV-OP12, the plurality of 22nd protrusions DV-OP22, the plurality of 32nd protrusions DV-OP32, the plurality of 42nd protrusions DV-OP42, and the plurality of 52nd protrusions DV-OP52 disposed on the right side of the reference line VL can be configured to form an acute angle in the counterclockwise direction with respect to the reference line VL, respectively.

[0115] When the number of the plurality of first protrusions DV-OP1 and the number of the plurality of second protrusions DV-OP2 are the same, the inclination of the protrusion configured as the nth among the plurality of first protrusions DV-OP1 and the inclination of the protrusion configured as the nth among the plurality of second protrusions DV-OP2 can be the same. Likewise, when the number of the plurality of first protrusions DV-OP1, the number of the plurality of third protrusions DV-OP3, the number of the plurality of fourth protrusions DV-OP4, and the number of the plurality of fifth protrusions DV-OP5 are the same, respectively, the inclination of the protrusion configured as the nth among the plurality of first protrusions DV-OP1, the inclination of the protrusion configured as the nth among the plurality of third protrusions DV-OP3, the inclination of the protrusion configured as the nth among the plurality of fourth protrusions DV-OP4, and the inclination of the protrusion configured as the nth among the plurality of fifth protrusions DV-OP5 can be the same, respectively.

[0116] The pitch between the plurality of first protrusions DV-OP1 can be smaller than the pitch between the plurality of second protrusions DV-OP2. The pitch between the plurality of second protrusions DV-OP2 can be smaller than the pitch between the plurality of third protrusions DV-OP3. The pitch between the plurality of third protrusions DV-OP3 can be smaller than the pitch between the plurality of fourth protrusions DV-OP4. The pitch between the plurality of fourth protrusions DV-OP4 can be smaller than the pitch between the plurality of fifth protrusions DV-OP5. That is, the more the plurality of first protrusions DV-OP1 are toward the plurality of fifth protrusions DV-OP5, the larger the arrangement interval between the protrusions can be.

[0117] When the protrusion farthest from the reference line VL is referred to as an outermost protrusion, the distance from the reference line VL to the first outermost protrusion of the first row R-1 can be shorter than the distance from the reference line VL to the second outermost protrusion of the second row R-2. In addition, the distance from the reference line VL to the second outermost protrusion of the second row R-2 can be shorter than the distance from the reference line VL to the third outermost protrusion of the third row R-3. Likewise, the distance from the reference line VL to the third outermost protrusion of the third row R-3 can be shorter than the distance from the reference line VL to the fourth outermost protrusion of the fourth row R-4, and the distance from the reference line VL to the fourth outermost protrusion of the fourth row R-4 can be shorter than the distance from the reference line VL to the fifth outermost protrusion of the fifth row R-5. In other words, the farther the first outermost protrusion is toward the fifth outermost protrusion, the farther it is arranged from the reference line VL. The separation distance from each short side DDV-S3, DDV-S4 of the drive circuit DDV to the first outermost protrusion can be longer than the separation distance from each short side DDV-S3, DDV-S4 of the drive circuit DDV to the second outermost protrusion through the fifth outermost protrusion, respectively.

[0118] The input protrusions DV-IP arranged in the input row R-I can also include, like the output protrusions DV-OP1, DV-OP2, DV-OP3, DV-OP4, DV-OP5, a reference input protrusion arranged on the reference line VL and a plurality of first input protrusions DV-IP1 arranged on the left side and a plurality of second input protrusions DV-IP2 arranged on the right side with the reference input protrusion as a center.

[0119] The drive circuit DDV further includes alignment mark protrusions ALM1, ALM2 arranged at the end of at least one of the plurality of rows R-1, R-2, R-3, R-4, R-5, R-I. In one embodiment, the alignment mark protrusions ALM1, ALM2 can include a first alignment mark protrusion ALM1 arranged at the end of the first row R-1 and a second alignment mark protrusion ALM2 arranged at the end of the input row R-I. In one embodiment, the second alignment mark protrusion ALM2 can also be omitted.

[0120] The alignment mark protrusions ALM1, ALM2 can be used as a recognition mark for grasping the position of the drive circuit DDV or for aligning the drive circuit DDV and the display panel DP in a process of joining the drive circuit DDV and the display panel DP. Figure 8 The alignment mark protrusions ALM1, ALM2 are exemplified as having a cross shape in the above embodiment, but are not limited thereto, and can be formed in various shapes as long as they are used for alignment of the respective components.

[0121] The alignment mark bumps ALM1, ALM2 can protrude substantially the same thickness as the plurality of bumps DDV-BP. On the other hand, in the present specification, "substantially the same" means not only a case where each of the thicknesses is exactly the same value, but also a case where it is the same within a range including a difference that can occur due to an error in a process, even if the same design is used. The thickness of the plurality of bumps DDV-BP can be about 7 μm or more and about 10 μm or less. The thickness of the alignment mark bumps ALM1, ALM2 can be about 7 μm or more and about 10 μm or less.

[0122] The alignment mark bumps ALM1, ALM2 can include the same substance as the plurality of bumps DDV-BP. The alignment mark bumps ALM1, ALM2 can include the same conductive metal as the plurality of bumps DDV-BP. In one embodiment, the plurality of bumps DDV-BP and the alignment mark bumps ALM1, ALM2 can be formed by the same process. That is, the plurality of bumps DDV-BP and the alignment mark bumps ALM1, ALM2 can be formed in the same process by a one-time patterning process after deposition of a metal on the drive chip DV-BS.

[0123] The alignment mark bumps ALM1, ALM2 can be disposed at the outermost profile of at least one of the plurality of rows R-1, R-2, R-3, R-4, R-5, R-I in which the plurality of bumps DDV-BP are disposed. That is, the alignment mark bumps ALM1, ALM2 can be disposed at both ends of at least one of the plurality of rows R-1, R-2, R-3, R-4, R-5, R-I, and can be disposed adjacent to both of the short sides DDV-S3, DDV-S4 of the drive circuit DDV. With the alignment mark bumps ALM1, ALM2 disposed at both ends of each row, a function for aligning the drive circuit DDV can be performed.

[0124] The drive circuit DDV can further include an alignment check mark bump ALI overlapping the alignment mark bumps ALM1, ALM2 in the column direction. Hereinafter, in the present specification, the alignment check mark bump ALI in the column direction can be applied as an identification mark for grasping the position of the drive circuit DDV or for grasping whether the alignment of the drive circuit DDV is appropriate in a process of checking the alignment of the drive circuit DDV. A plurality of alignment check mark bumps ALI can be provided. At least one of the plurality of alignment check mark bumps ALI can also be disposed side by side with at least one of the plurality of rows R-1, R-2, R-3, R-4, R-5, R-I in which the plurality of bumps DDV-BP are disposed. For example, a pair of the plurality of alignment check mark bumps ALI can be disposed side by side in the fifth row R-5.

[0125] The alignment inspection mark bump ALI can protrude substantially the same thickness as the alignment mark bumps ALM1, ALM2. The alignment inspection mark bump ALI can include the same substance as the alignment mark bumps ALM1, ALM2, and can be formed by the same process.

[0126] The plurality of bumps DDV-BP included in the driving circuit DDV can further include dummy bumps DMB configured in at least one of the plurality of rows R-1, R-2, R-3, R-4, R-5, R-I. The dummy bumps DMB can be configured between the outermost profile bumps and the two short sides DDV-S3, DDV-S4 of the driving circuit DDV in at least one of the plurality of rows R-1, R-2, R-3, R-4, R-5, R-I. In an embodiment, the dummy bumps DMB can be respectively configured in the first row R-1, the second row R-2, the third row R-3, and the fourth row R-4. The dummy bump DMB configured in the first row R-1 can be configured between the first outermost profile bump and the first alignment mark bump ALM1.

[0127] As the distance from the short sides DDV-S3, DDV-S4 of the driving circuit DDV to the outermost profile bumps of the respective rows R-1, R-2, R-3, R-4, R-5, R-I is different, the dummy bumps DMB can be configured to compensate for the difference. As the dummy bumps DMB are configured, the distance from the short sides DDV-S3, DDV-S4 of the driving circuit DDV to the outermost profile bumps or the dummy bumps DMB configured at the outermost profile can be substantially the same in the first row R-1 to the fifth row R-5.

[0128] The dummy bumps DMB can protrude substantially the same thickness as the alignment mark bumps ALM1, ALM2. The dummy bumps DMB can include the same substance as the alignment mark bumps ALM1, ALM2, and can be formed by the same process.

[0129] The dummy bumps DMB can be bumps that do not output a separate signal. However, the dummy bumps DMB can also be bumps that output output signals output by the plurality of bumps configured on the respective rows in which the dummy bumps DMB are configured, without being limited thereto.

[0130] An embodiment of the present disclosure relates to a display device DD that can include alignment mark bumps ALM1, ALM2, thereby preventing problems such as the base layer BL of the display panel DP being bent or cracks being generated in the display panel DP due to pressure generated in the process of crimping the driving circuit DDV to the display panel DP. Hereinafter, a more detailed description will be given with reference to Figure 9a to Figure 11 a cross-sectional view.

[0131] Figure 9a and Figure 9bis a cross-sectional view of a portion of a display device to which an embodiment of the present invention relates. Figure 10 is a cross-sectional view of another portion of a display device to which an embodiment of the present invention relates. Figure 11 is a cross-sectional view of still another portion of a display device to which an embodiment of the present invention relates. Figure 9a and Figure 9b in which a cross-sectional view of the display panel and the driving circuit is shown taken along the II-II' intercept line of Figure 8 in which a cross-sectional view of the display panel and the driving circuit is shown taken along the III-III' intercept line of Figure 10 in which a cross-sectional view of the display panel and the driving circuit is shown taken along the IV-IV' intercept line of Figure 8 in which a cross-sectional view of the display panel and the driving circuit is shown taken along the IV-IV' intercept line of Figure 11 Figure 8 With reference to ,

[0132] , Figure 5 and Figure 8 , in a display device DD to which an embodiment relates, the display panel DP and the driving circuit DDV can be joined by an anisotropic conductive film ACF, and pads PD of the display panel DP can be configured to correspond to a plurality of bumps DDV-BP configured in the driving circuit DDV. As shown in Figure 9a and Figure 9b , a first pad PD12 can be configured to correspond to a first bump DV-OP12 configured in a first row R-1 among the plurality of bumps DDV-BP. The first bump DV-OP12 can be an output bump for driving the display panel DP, and the first pad PD12 can be an input pad that receives a signal from the driving circuit DDV. Although not shown, the display panel DP can include a plurality of first pads PD12 corresponding to a plurality of first bumps DB-OP12 configured in the first row R-1. Figure 9a Figure 9b A thickness of the first bump DV-OP12 configured in the first row R-1 and a thickness of the dummy bump DMB can be substantially the same. A thickness of the first bump DV-OP12 configured in the first row R-1 and a thickness of the first alignment mark bump ALM1 can be substantially the same. The first bump DV-OP12, the dummy bump DMB, and the first alignment mark bump ALM1 can include the same substance, and can be formed by the same process.

[0133] The display panel DP can further include an additional pad APD corresponding to the dummy bump DMB of the driving circuit DDV. As shown in and

[0134] , the first pad PD12 can be configured to correspond to the first bump DV-OP12 configured in the first row R-1 among the plurality of bumps DDV-BP. The first pad PD12 can be an input pad that receives a signal from the driving circuit DDV, and the first bump DV-OP12 can be an output bump for driving the display panel DP. Although not shown, the display panel DP can include a plurality of first pads PD12 corresponding to a plurality of first bumps DB-OP12 configured in the first row R-1. Figure 9a Figure 9b , the first pad PD12 can be configured to correspond to the first bump DV-OP12 configured in the first row R-1 among the plurality of bumps DDV-BP. The first pad PD12 can be an input pad that receives a signal from the driving circuit DDV, and the first bump DV-OP12 can be an output bump for driving the display panel DP. Although not shown, the display panel DP can include a plurality of first pads PD12 corresponding to a plurality of first bumps DB-OP12 configured in the first row R-1.As shown, the display panel DP can include a plurality of additional pads APD corresponding to the plurality of dummy bumps DMB disposed in the first row R-1 of the driving circuit DDV. In an embodiment, a first dummy bump DMB1, a second dummy bump DMB2, a third dummy bump DMB3, and a fourth dummy bump DMB4 can be disposed in the first row R-1 of the driving circuit DDV, and corresponding to this, the display panel DP can include a first additional pad APD1, a second additional pad APD2, a third additional pad APD3, and a fourth additional pad APD4.

[0135] The additional pads APD can include the same substance as the first pads PD12, and can be formed with the same thickness. The additional pads APD can be formed through the same process as the first pads PD12. In an embodiment, the additional pads APD disposed in the display panel DP can also be omitted. That is, the display panel DP can also not be provided with pads corresponding to the dummy bumps DMB.

[0136] The display panel DP can further include panel alignment mark bumps corresponding to the alignment mark bumps ALM1, ALM2 disposed in the driving circuit DDV. As shown, Figure 9a As shown, the display panel DP can include a first panel alignment mark bump DP-ALM1 corresponding to the first alignment mark bump ALM1 disposed in the first row R-1 of the driving circuit DDV. The first panel alignment mark bump DP-ALM1 can be used as an identification mark for grasping the position of the display panel DP in a process of bonding the driving circuit DDV and the display panel DP or for aligning the display panel DP and the driving circuit DDV by aligning with the first alignment mark bump ALM1. The first panel alignment mark bump DP-ALM1 can be formed with the same thickness as the first pads PD12 and the additional pads APD. The first panel alignment mark bump DP-ALM1 can include the same substance as the first pads PD12 and the additional pads APD, and can be formed through the same process.

[0137] Alternatively, as shown, Figure 9b The first panel alignment mark bump DP-ALM1 can be omitted, and pads corresponding to the first alignment mark bump ALM1 can not be provided. In this case, the display panel DP can also include a panel alignment mark (not shown) that does not have a separate height difference.

[0138] Referring to Figure 5 , Figure 8 and Figure 10The thickness of the fifth bump DV-OP52 provided in the fifth row R-5 of the drive circuit DDV and the thickness of the alignment inspection mark bump ALI can be substantially the same. The fifth bump DV-OP52 and the alignment inspection mark bump ALI can include the same substance and can be formed by the same process.

[0139] The display panel DP can further include a fifth pad PD52 provided corresponding to the fifth bump DV-OP52 provided in the fifth row R-5 of the drive circuit DDV. The display panel DP can further include a panel alignment inspection mark bump DP-ALI provided corresponding to the alignment inspection mark bump ALI provided side by side with the fifth row R-5 of the drive circuit DDV. The panel alignment inspection mark bump DP-ALI can have substantially the same thickness as the fifth pad PD52. The panel alignment inspection mark bump DP-ALI can be formed by the same process as the fifth pad PD52. In an embodiment, the panel alignment inspection mark bump DP-ALI can be omitted and the display panel DP can include a panel alignment inspection mark (not shown) without a separate height difference.

[0140] Referring to Figure 5 , Figure 8 and Figure 11 , the thickness of the input bump DV-IP2 provided in the input row R-I of the drive circuit DDV and the thickness of the second alignment mark bump ALM2 can be substantially the same. The input bump DV-IP2 and the second alignment mark bump ALM2 can include the same substance and can be formed by the same process.

[0141] The display panel DP can further include a sixth pad PD62 provided corresponding to the input bump DV-IP2 provided in the input row R-I of the drive circuit DDV. The sixth pad PD62 can be an output pad for transferring a signal or the like provided by the circuit substrate PCB to the drive circuit DDV. The display panel DP can further include a second panel alignment inspection mark bump DP-ALM2 provided corresponding to the second alignment mark bump ALM2 provided side by side with the input row R-I of the drive circuit DDV. The second panel alignment inspection mark bump DP-ALM2 can have substantially the same thickness as the sixth pad PD62. The second panel alignment inspection mark bump DP-ALM2 can be formed by the same process as the sixth pad PD62. In an embodiment, the second panel alignment inspection mark bump DP-ALM2 can be omitted and the display panel DP can include a panel alignment inspection mark (not shown) without a separate height difference.

[0142] An embodiment of the present application relates to a display device including alignment mark bumps disposed adjacent to the short sides of a driving circuit, so that a problem of the display panel being bent or cracked due to pressure generated in the process of joining the display panel and the driving circuit can be prevented. More specifically, in the case of a display panel including a flexible base layer, the display panel is easily bent or cracks are easily generated in the process of crimping the display panel and the driving circuit, but in the present application, for the alignment marks disposed at the end of the driving circuit, the alignment marks protrude at substantially the same thickness as output bumps and input bumps, etc., so that pressure applied to the display panel can be uniformly applied, thereby preventing bending of the display panel and generation of cracks.

[0143] On the other hand, as for the problem of the separation distance between the outermost profile bumps of each row in which a plurality of bumps are arranged and the end of the driving circuit becoming uneven due to the arrangement of the plurality of bumps disposed in the driving circuit, although dummy bumps can be formed in each row in which a plurality of bumps are arranged to compensate for the separation distance, thereby preventing the generation of the above-described problems, in the present application, for the alignment marks disposed closer to the end of the driving circuit than the dummy bumps, the alignment mark bumps are formed by the same process as the plurality of bumps when the alignment marks are formed, so that the generation of problems such as bending in the display panel overlapping the outermost portion of the driving circuit can be prevented.

[0144] Figure 12 and Figure 13 is a plan view showing the arrangement of bumps of a driving circuit according to another embodiment of the present application. Hereinafter, when the driving circuit DDV-1, DDV-2 according to an embodiment is explained with reference to Figure 12 and Figure 13 , the same reference numerals are assigned to the same components as those explained above and detailed explanation is omitted.

[0145] With reference to Figure 12 , the driving circuit DDV-1 according to an embodiment further includes at least one corner bump CB disposed at a corner portion of the driving circuit DDV-1. The corner bump CB can be disposed adjacent to a place where the corner of the driving circuit DDV-1, i.e., the long sides DDV-S1, DDV-S2 and the short sides DDV-S3, DDV-S4 meet. In Figure 12 , a case in which corner bumps CB are disposed at all four corners of the driving circuit DDV-1 is exemplified, but at least one of the four corner bumps CB can be omitted.

[0146] The corner bump CB can have substantially the same thickness as the first alignment mark bump ALM1. The corner bump CB can include substantially the same material as the first alignment mark bump ALM1 and can be formed by the same process. However, the corner bump CB can have a smaller thickness than the first alignment mark bump ALM1, but is not limited thereto.

[0147] The driving circuit DDV-1 according to an embodiment can further include a plurality of long side bumps LSB disposed adjacent to any one of the long sides DDV-S1 and DDV-S2 of the driving circuit DDV-1. In an embodiment, the plurality of long side bumps LSB can be disposed adjacent to the first long side DDV-S1 of the driving circuit DDV-1 adjacent to the display area DA. However, the plurality of long side bumps LSB can be disposed adjacent to the second long side DDV-S2 of the driving circuit DDV-1, but is not limited thereto. Although not illustrated, the plurality of long side bumps LSB can be arranged not to overlap with a portion in which a plurality of signal lines are disposed, where the plurality of signal lines are connected to the first to fifth bumps DV-OP1 to DV-OP5, the input bump DV-IP, and the like.

[0148] The plurality of long side bumps LSB can have substantially the same thickness as the first alignment mark bump ALM1. The plurality of long side bumps LSB can include substantially the same material as the first alignment mark bump ALM1 and can be formed by the same process. However, the plurality of long side bumps LSB can have a smaller thickness than the first alignment mark bump ALM1, but is not limited thereto.

[0149] Referring to Figure 13 The driving circuit DDV-2 according to an embodiment can further include a plurality of bezel bumps BDB disposed along the bezel of the driving circuit DDV-2. The plurality of bezel bumps BDB can be disposed adjacent to the long sides DDV-S1 and DDV-S2 and the short sides DDV-S3 and DDV-S4 of the driving circuit DDV-2, respectively. Although not illustrated, the plurality of bezel bumps BDB can be arranged not to overlap with a portion in which a plurality of signal lines are disposed, where the plurality of signal lines are connected to the first to fifth bumps DV-OP1 to DV-OP5, the input bump DV-IP, and the like.

[0150] The plurality of bezel bumps BDB can have substantially the same thickness as the first alignment mark bump ALM1. The plurality of bezel bumps BDB can include substantially the same material as the first alignment mark bump ALM1 and can be formed by the same process. However, the plurality of bezel bumps BDB can have a smaller thickness than the first alignment mark bump ALM1, but is not limited thereto.

[0151] As the driving circuit DDV-1, DDV-2 according to an embodiment further includes additional bumps disposed at the outermost portion of the driving circuit DDV-1, DDV-2, i.e., at least one corner bump CB disposed at the corner portion of the driving circuit DDV-1, a plurality of long side bumps LSB disposed adjacent to any one of the long sides DDV-S1, DDV-S2 of the driving circuit DDV-1, and a plurality of bezel bumps BDB disposed along the bezel of the driving circuit DDV-2, etc., it is possible to prevent the base layer BL portion of the display panel DP overlapping the outermost portion of the driving circuit DDV-1, DDV-2 from being bent or cracked, etc., due to the pressure generated in the process of crimping the driving circuit DDV-1, DDV-2 to the display panel DP.

[0152] The above description has been made with reference to preferred embodiments of the present application, but those skilled in the art or those skilled in the art with ordinary technical knowledge should be able to understand that the present application can be modified or changed in various ways without departing from the scope of the technical idea and technical field of the present application as recited in the claims. Therefore, the technical scope of the present application is not limited to the contents recited in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device comprising: a display panel including a display region in which an image is displayed and a non-display region adjacent to the display region; and a driver circuit disposed in the non-display region, the driver circuit including a driver chip, a plurality of bumps disposed in the driver chip and disposed in a plurality of rows, and a first alignment mark bump disposed at an end of at least one of the plurality of rows, the first alignment mark bump having a same thickness as at least one of the plurality of bumps. 2.The display device of claim 1, wherein the plurality of bumps include a plurality of first bumps disposed in a first row adjacent to the display region among the plurality of rows, and the first alignment mark bump is disposed in the first row. 3.The display device of claim 2, wherein the plurality of first bumps include a plurality of 11th bumps disposed on a left side with reference to a first reference bump and a plurality of 12th bumps disposed on a right side with reference to the first reference bump, the plurality of 11th bumps are disposed to form an acute angle in a clockwise direction with reference to a reference line defined in a center of the driver circuit in a direction crossing the plurality of row directions of the driver circuit, and the plurality of 12th bumps are disposed to form an acute angle in a counterclockwise direction with reference to the reference line. 4.The display device of claim 2, wherein the plurality of bumps further include a dummy bump disposed in the first row and disposed between the plurality of first bumps and the first alignment mark bump. 5.The display device of claim 2, wherein the plurality of first bumps disposed in the first row are output bumps outputting a driving signal for driving a light emitting element included in the display panel. 6.The display device of claim 2, wherein the first row in which the plurality of first bumps are disposed is defined at one end of the driver circuit, the plurality of bumps include a plurality of input bumps disposed in an input row defined at the other end of the driver circuit opposite to the one end among the plurality of rows. 7.The display device of claim 6, wherein the driver circuit further includes a second alignment mark bump disposed at an end of the input row. 8.The display device of claim 1, wherein the display panel includes: a plurality of pads corresponding to the plurality of bumps; and a panel alignment mark bump corresponding to the first alignment mark bump. 9.The display device of claim 1, wherein a thickness of the first alignment mark bump is 7 μm or more and 10 μm or less. 10.The display device of claim 1, wherein the driver circuit further includes an alignment check mark bump overlapping the first alignment mark bump in a column direction, a thickness of the alignment check mark bump is the same as a thickness of the first alignment mark bump. 11.The display device of claim 1, wherein the display panel includes a first non-folded region, a folded region, and a second non-folded region defined in sequence, the folded region is folded with reference to a folding axis. ​ 12. The display device according to claim 1, wherein the first alignment mark bump is disposed adjacent to one end of the driver chip.

13. The display device according to claim 1, further comprising: an anisotropic conductive film disposed between the driver circuit and the display panel.

14. The display device according to claim 1, wherein the plurality of bumps and the first alignment mark bump include the same substance.

15. The display device according to claim 1, wherein the driver circuit further includes: a corner bump disposed at a corner of the driver circuit, the corner bump has the same thickness as the first alignment mark bump.

16. The display device according to claim 1, wherein the driver circuit defines a plurality of long sides extending in a direction parallel to a direction of the plurality of rows and a plurality of short sides extending in a direction intersecting the direction of the plurality of rows, the driver circuit further includes: a long side side bump disposed adjacent to at least one of the plurality of long sides, the long side side bump has the same thickness as the first alignment mark bump.

17. The display device according to claim 16, wherein the driver circuit further includes: a frame bump disposed adjacent to the plurality of long sides and the plurality of short sides, the frame bump has the same thickness as the first alignment mark bump.

18. A display device comprising: a display panel including a display region that displays an image and a non-display region adjacent to the display region; and a driver circuit disposed in the non-display region, the driver circuit includes: a driver chip; a plurality of first bumps disposed in the driver chip and disposed in a first row; a plurality of second bumps disposed in the driver chip and disposed in a second row; and an alignment mark bump disposed at an end of at least one of the first row and the second row; the alignment mark bump has the same thickness as at least one of the plurality of first bumps.

19. The display device according to claim 18, wherein the plurality of first bumps and the plurality of second bumps have the same thickness as the alignment mark bump. ​

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