Semiconductor device and decoding method

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a decoding method. The present invention is to reduce detection of an error edge caused by variation in a case where a sampling frequency is not greater than a data transmission frequency. A semiconductor device includes a data reception circuit configured to receive first data at a first time and receive second data at a second time, and an edge identification circuit configured to set a range and detect an edge contained in the range. The edge identification circuit includes a measurement circuit configured to measure a first period taken from reception of the first data to reception of the second data, and configured to determine the range in which an edge contained in data received by the data reception circuit is detected based on the first period.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2020-096553 including the specification, drawings and abstract is incorporated herein by reference in its entirety. BACKGROUND

[0003] The present application relates to a semiconductor device, and can be applied to a semiconductor device including a decoding circuit using, for example, Manchester coding.

[0004] When some or more differences occur between a transmission reference clock and a reception reference clock, a communication system can have a problem in which normal data cannot be received, and the like.

[0005] As one method for preventing this problem, a high-speed data sampling is exemplified. This is a method in which a plurality of sampling timings are set in one time slot, and data is determined from the results of the sampling timings. A time slot is a time taken for transmission of one bit of data.

[0006] Also, Manchester coding is adopted as a method for preventing a problem in which normal data cannot be received when some or more differences occur between a transmission reference clock and a reception reference clock due to a difference in frequency or phase therebetween. For example, in Manchester coding, a potential is set to be definitely changed in one time slot, so that when the potential changes from a high potential to a low potential, a logic value becomes "1"; and when the potential changes from a low potential to a high potential in one time slot (to generate an intermediate edge), the logic value becomes "0".

[0007] The disclosed technology is listed below.

[0008] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2011-61525 SUMMARY

[0009] At the time of data transmission, data is delayed by noise such as jitter, which is a fluctuation in a signal waveform in a time axis direction. The amount of delay is not constant, but varies. When a sampling frequency is not greater than a frequency of data transmission, an error edge can be detected due to this variation. If clock synchronization can be performed between a transmission side and a reception side, or if a sufficiently large sampling frequency can be set, the problem as described above does not occur. However, it is generally difficult to perform synchronization due to a limitation in circuit design.

[0010] According to an aspect of the present application, a semiconductor device includes a data reception circuit configured to receive first data at a first time and second data at a second time, and an edge recognition circuit configured to set a range and detect an edge within the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and configured to determine the range for detecting an edge contained in data received by the data reception circuit based on the first period.

[0011] According to the semiconductor device, when a sampling frequency is not greater than a frequency of data transmission, detection of an erroneous edge due to variation can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a graph showing a propagation delay model of a signal to be a target of the present application.

[0013] Figure 2 is a graph showing Figure 1 in the signal propagation delay model shown in

[0014] Figure 3 is a graph showing a timing example in a case where jitter equal to or greater than 1 / 8 of a data period occurs.

[0015] Figure 4A is a timing chart in a case where no change in a data detection range occurs.

[0016] Figure 4B is a timing chart in a case of delay correction that corrects a data detection range.

[0017] Figure 4C is a timing chart in a case of advance correction that corrects a data detection range.

[0018] Figure 5 is a timing chart for explaining the delay correction and the advance correction.

[0019] Figure 6 is a block diagram showing a configuration of a communication system according to a first working example.

[0020] Figure 7 is a block diagram showing Figure 6 a configuration of a decoder shown in

[0021] Figure 8 is a timing chart showing Figure 7 operation waveforms of the decoder shown in

[0022] Figure 9 is a timing chart showing Figure 7The flowchart shown illustrates the hardware processing in the case where the decoder detects a falling edge.

[0023] Figure 10 This is a timing diagram showing the operating waveforms of the decoder according to the second working example.

[0024] Figure 11 This is a flowchart illustrating the hardware processing in the case where the decoder detects a falling edge according to the second working example.

[0025] Figure 12 This is a block diagram showing the configuration of the decoder according to the third working example.

[0026] Figure 13 This is a circuit diagram showing a three-input majority decision circuit.

[0027] Figure 14 It shows Figure 12 The diagram shows the configuration of the flip-flop for shifting, the flip-flop for data sampling, the noise filter, and the edge detection circuit.

[0028] Figure 15 It shows Figure 12 A block diagram of a portion of the configuration of the edge recognition circuit shown.

[0029] Figure 16 It shows Figure 12 A block diagram of a portion of the configuration of the edge recognition circuit shown.

[0030] Figure 17 yes Figure 12 The block diagram of the clock generation circuit shown is shown.

[0031] Figure 18 This is a timing diagram showing the operation of the decoder according to the third working example.

[0032] Figure 19 This is a timing diagram showing the operation of the decoder according to the third working example.

[0033] Figure 20 This is a timing diagram showing the operation of the decoder according to the third working example.

[0034] Figure 21 This is a timing diagram showing the operation of the decoder according to the third working example.

[0035] Figure 22 This is a timing diagram showing the operation of the decoder according to the third working example.

[0036] Figure 23 This is a timing diagram showing the operation of the decoder according to the third working example.

[0037] Figure 24 is a timing chart showing the operation of a decoder according to the third working example.

[0038] Figure 25 is a block diagram showing a part of the configuration of an edge recognition circuit according to the fourth working example.

[0039] Figure 26 is a block diagram showing a part of the configuration of an edge recognition circuit according to the fourth working example.

[0040] Figure 27 is a table showing the truth table of the correction circuit shown in Figure 26

[0041] Figure 28 is a timing chart showing the operation of a decoder according to the fourth working example. DETAILED DESCRIPTION

[0042] Embodiments and working examples are described below with reference to the accompanying drawings. In the following description, like reference numerals are attached to like elements throughout the description, and repetitive description thereof will be omitted.

[0043] First, reference is made to Figure 1 and Figure 2 to explain jitter. Figure 1 is a graph showing a signal propagation delay model to be the target of the present application. Figure 2 is a graph showing the propagation delay of the signal propagation delay model shown in Figure 1

[0044] As shown in Figure 1 , a transmitter semiconductor device (T_LSI) 100 and a receiver semiconductor device (R_LSI) 200 are mounted on a printed circuit board (PCB) 10. The semiconductor device 100 and the semiconductor device 200 are connected to each other by a wiring 20 formed in the printed board 10. In this case, a signal is transmitted from the semiconductor device 100 to the semiconductor device 200 through the wiring 20.

[0045] Considering a clock (CLK) on the transmitter side as a starting point, the following delays are generated until the clock reaches a flip-flop (F / F) 201 serving as an input logic circuit on the receiver side.

[0046] Clock jitter (CLK): tTCD

[0047] Internal propagation delay of the semiconductor device 100: tTID

[0048] Delay of the output buffer 102 of the semiconductor device 100: tTBD ​​

[0049] Delay of the wiring 20 of the PCB 10: tBWD

[0050] Delay of the input buffer 202 of the semiconductor device 200: tRBD

[0051] Internal propagation delay of the semiconductor device 200: tRID

[0052] In this case, "tBWD" includes delays due to each package of the semiconductor device 100 and the semiconductor device 200. Each of the delays varies depending on conditions such as variations in temperature, voltage, manufacturing noise, or environmental noise. As shown in FIG. 2, the delay (tDE) in the case of the minimum value of the sum (tD) of these delays and the delay (tDL) in the case of the maximum value of the sum (tD) are different from each other. The difference between the delay (tDE) and the delay (tDL) is the jitter of the input signal. Figure 2

[0053] Next, reference will be made to Figure 1 and Figure 3 The effect of the jitter in the Manchester coding studied by the inventor will be explained. Figure 3 is a diagram showing a timing example in the case where the jitter equal to or greater than 1 / 8 of a data period occurs. The case where the Manchester coding is received at a communication speed of 100 Mbps (bits / sec) will be explained below.

[0054] When the clock with the fastest frequency generated in the semiconductor device 200 is 400 MHz, even if the rising edge and the falling edge of the clock are used, only 8 samplings are performed within one data period. Therefore, the sampling is 1.25 ns (nanoseconds), which is more rough than the precision of the specification 100 Mbps.

[0055] Meanwhile, in the case where the LVDS (Low Voltage Differential Signal) interface is used for the terminal into which the Manchester coding signal is input, the signal is input as a differential input from the outside of the semiconductor device 200 to the input buffer 202. Therefore, when the number of currents is reduced in order to reduce the power consumption, the jitter of the input buffer 202 increases. Also, when the CMOS (Complementary Metal Oxide Semiconductor) process with low leakage current is used in order to reduce the power consumption and the cost, the number of currents of the power supply is also reduced. Therefore, in this case, the influence of the noise is easy, and there is large jitter in the internal propagation of the semiconductor device 200. Also, there is jitter in the clock source such as the PLL (Phase Locked Loop) circuit which supplies the clock. In addition to them, there is jitter in the wiring 20 outside the semiconductor device 200 and the circuit of the transmitter semiconductor device 100, and therefore, the total jitter value often exceeds ±1.25 ns.

[0056] ​For example, when the sampling accuracy of a Manchester code signal having a period of 10 ns is 1.25 ns, and the induced jitter exceeds ±1.25 ns, the middle edge and the boundary edge can be sampled at the same position. The boundary edge is an edge generated at the boundary of the data / clock period (at the data boundary) at the time of encoding, and the middle edge is an edge generated at the middle of the data / clock period (at the data middle). Therefore, the difference between the middle edge and the boundary edge cannot be identified, and decoding cannot be performed correctly. For example, as shown in FIG. 6, when jitter of ±1.5 ns is induced and the edge is sampled at the "A" point, the edge cannot be identified as an edge generated due to the delay of the middle edge ME (illustrated using a dotted line) or an edge generated by the advance of the boundary edge BE (illustrated using a dashed line) due to the jitter. Figure 3

[0057] As described above, the data transmission is delayed due to noise such as jitter. The amount of the delay is not constant but varies. When the sampling frequency is not greater than the frequency of the data transmission, an erroneous edge due to the variation can be detected.

[0058] If the clock is synchronized between the transmission side and the reception side or if a sufficiently large sampling frequency is set by using a PLL dedicated to transmission / reception, the problem described above does not occur. However, in some cases, it is difficult to perform synchronization due to the limitation of the circuit design. Also, in the case of using a PLL dedicated to transmission / reception, the cost disadvantage is very large, and only the period (preamble period) for performing oscillation to lock the PLL is also necessary.

[0059] Next, the embodiments of the present application are explained below. The shift value between the adjacent periods due to jitter varies depending on whether the delay of the previous period is large or small. For example, in the case of jitter of 2 ns, when the sum of the delays of the previous periods (tD) is the average value, the delay direction and the advance direction of the next period can vary by 1 ns (±1 ns). In this case, the state in which the sum (tD) is the average value means the middle state between the earliest delay (tDE) and the latest delay (tDL).

[0060] Meanwhile, when the sum of the delays of the previous periods (tD) is 0.5 ns less than the average value (when the signal is transmitted early), the advance amount of the next period can be -0.5 ns, and the delay amount of the next period can be +1.5 ns. When the sum of the delays of the previous periods (tD) is the minimum (the earliest case (tDE)), the next period cannot be earlier, and the delay amount can be at most +2 ns.

[0061] ​On the other hand, when the sum of the delays of the previous cycles (tD) is greater than the average (when the signal is sent later), it can be said that it is contrary to the case where it is less than the average. That is, when the number of delays of the previous cycles is small, the shift of the next cycle is large in the delay direction and small in the advance direction. In contrast, when the number of delays of the previous cycles is large, the shift of the next cycle is large in the advance direction and small in the delay direction.

[0062] In the embodiment, in order to receive the Manchester coded signal containing the jitter, the data detection range is corrected based on the middle edge that must be generated in the Manchester coded signal. In this case, the correction that sets the end of the data detection range earlier than the normal detection end is called "advance correction". Also, the correction that sets the start of the data detection range later than the normal detection start is called "delay correction".

[0063] By correcting the data detection range of the next cycle, it can be predicted whether the delay of the previous cycle is large or small. In the case of the advance correction that corrects the data detection range of the next cycle, it can be determined that the delay of the previous cycle is at least not the latest delay, and it can be determined that the next cycle is later than the previous cycle. In the case of the delay correction that corrects the data detection range of the next cycle, it can be determined that the delay of the previous cycle is at least not the latest delay, and it can be determined that the next cycle is earlier than the previous cycle.

[0064] The embodiment utilizes these features, stores the correction result of the data detection range of the previous cycle in advance, and then corrects the data detection range (W) of the next cycle based on the correction result.

[0065] The correction of the data detection range will be explained with reference to Figure 4A to Figure 4C . Figure 4A is a timing chart in the case where there is no change in the data detection range. Figure 4B is a timing chart in the case of the delay correction for correcting the data detection range. Figure 4C is a timing chart in the case of the advance correction for correcting the data detection range.

[0066] As shown in Figure 4A , in the case where there is no correction of the data detection range (W), the edge at the sampling point "SP" illustrated by the thick arrow cannot be recognized as the middle edge ME or the boundary edge BE.

[0067] Therefore, as shown in Figure 4BAs shown in FIG. 8, in a case where the edge detection of the previous cycle is advanced corrected (AC), the delay correction is performed in the next cycle. That is, in the edge detection of the next cycle, the center of the data detection range (W) is delayed, or the range of the data detection range (W) on the advanced side is shortened. In this way, the edge at the sampling point "SP" illustrated using the thick arrow can be determined as the boundary edge BE.

[0068] Therefore, as Figure 4C As shown in FIG. 9, in a case where the edge detection of the previous cycle is delay corrected (DC), the advance correction is performed in the next cycle. That is, in the edge detection of the next cycle, the center of the data detection range (W) is advanced, or the range of the data detection range (W) on the delay side is shortened. In this way, the edge at the sampling point "SP" illustrated using the thick arrow can be determined as the intermediate edge ME.

[0069] Next, an embodiment of a different point of view from the above-described point of view is explained. In order to set the data detection range, the receiver semiconductor device according to the present embodiment measures, for example, the time taken to receive two consecutive data, and sets the data detection range based on the measured time. If the time interval between data reception is short, the next incoming data can arrive after a time interval longer than the time interval of the normal data reception interval elapses. Therefore, the delay correction for setting the start of the data detection range later than the normal detection start is performed. If the time interval between data reception is long, the next incoming data can arrive after a time interval shorter than the time interval of the normal data reception interval elapses. Therefore, the advance correction for setting the end of the data detection range earlier than the normal detection end is performed.

[0070] Reference is made to Figure 5 Specific examples of the delay correction and the advance correction are explained. Figure 5 is a timing chart for explaining the delay correction and the advance correction. Figure 5 The assumption of FIG. 8 is that data reception is performed with a cycle of 8 ns and shifted by about ±2 ns due to jitter in some cases.

[0071] First, a case where there is no delay correction and no advance correction (case "A") is explained. Due to jitter, the second intermediate edge ME2 is shifted by about ±2 ns. Considering the jitter, the data detection range of the third intermediate edge ME3 needs to be set within the range of 4 ns to 12 ns with reference to the shifted second intermediate edge ME2.

[0072] Next, the processing of the delay correction in the case of a short data interval (case "B") will be explained. In a communication with a period of 8 ns, when the data interval between the first middle edge ME1 and the second middle edge ME2 is 6 ns, the following reasons mainly occur.

[0073] B1: DATA2 is 2 ns ahead.

[0074] B2: DATA1 is 2 ns delayed.

[0075] In case B1, the third middle edge ME3 of DATA3 can be in the range of 8 ns to 12 ns with reference to the second middle edge ME2 of DATA2. In case B2, the third middle edge ME3 of DATA3 can be in the range of 6 ns to 10 ns with reference to the second middle edge ME2 of DATA2. Therefore, in order to support both possibilities, the range of 6 ns to 12 ns can be set as the edge detection range. Since the delay correction for setting the start of the data detection range to be delayed by 2 ns, this data detection range can be narrower than the range of 4 ns to 12 ns in case A, and thus, error detection can be prevented.

[0076] Next, the processing of the delay correction in the case of a short data interval (case "B") will be explained. In a communication with a period of 8 ns, when the data interval between the first middle edge ME1 and the second middle edge ME2 is 6 ns, the following reasons mainly occur.

[0077] C1: DATA1 is 2 ns ahead.

[0078] C2: DATA2 is 2 ns delayed.

[0079] In case C1, DATA3 can be in the range of 6 ns to 10 ns with reference to the second middle edge ME2 of DATA2. In case C2, DATA3 can be in the range of 4 ns to 8 ns with reference to the second middle edge ME2 of DATA2. Therefore, in order to support both possibilities, the range of 4 ns to 10 ns can be set as the edge detection range. Since the advance correction for setting the end of the data detection range to be advanced by 2 ns, this data detection range can be narrower than the range of 4 ns to 12 ns in case A, and thus, error detection can be prevented.

[0080] In this embodiment, the receiver measures the time taken to receive two successive data. The data detection range is set based on the time interval between data reception. If the time interval between data reception is short, the next incoming data can arrive after a time interval longer than the time interval of the normal data reception interval. Therefore, the start of the data detection range is set later than the normal detection start. If the time interval between data reception is long, the next incoming data can arrive after a time interval shorter than the time interval of the normal data reception interval. Therefore, the end of the data detection range can be set earlier than the normal detection end.

[0081] According to the embodiment, the clock and data can be correctly recovered even when the jitter including the sampling accuracy (timer accuracy) is equal to or greater than ±1 / 8 cycle. In this way, even when the jitter is equal to or greater than ±1 / 8 cycle, data can be correctly received by a circuit having low power and low cost without using a PLL dedicated to transmission / reception. In the present embodiment, the reception of a Manchester code signal is exemplified. However, the present embodiment is also applicable to, for example, communication in which a clock and data signal are superimposed (such as 8b / 10b coding, RLL (Run Length Limited) coding, and WFM) and asynchronous communication using, for example, an asynchronous signal.

[0082] Some typical working examples of the embodiment are explained below. In the following explanation of the working examples, the same symbol as that of the embodiment described above is used to annotate a part of the configuration and function similar to that described above. For the explanation of the part, the explanation of the embodiment can be appropriately utilized within a range not technically contradictory. A part of the embodiment described above and a part or all of the working examples can be appropriately combined and utilized within a range not technically contradictory.

[0083] (First working example)

[0084] Figure 6 is a block diagram showing the configuration of a communication system according to the first working example.

[0085] In the communication system 1 according to the first working example, communication between the semiconductor device 100 and the semiconductor device 200 is performed in Manchester coding. The semiconductor device 100 is also called a master device, and is constituted by, for example, an MCU (Micro Controller Unit). The semiconductor device 200 is also called a slave device, and is connected to, for example, a sensor or a control device. The communication is controlled by respective communication modules 110 and 210 of the semiconductor devices 100 and 200. The communication modules 110 and 210 include transmission circuits 120 and 220 and reception circuits 140 and 240, respectively. The transmission circuits 120 and 220 include encoders 130 and 230 for Manchester coding, and the reception circuits 140 and 240 include decoders 150 and 250 for Manchester coding, respectively. The encoders 130 and 230 for Manchester coding are connected to the decoders 150 and 250 for Manchester coding through communication lines 21 and 22, respectively. Since a clock and data are reproduced from a signal of Manchester coding, each of the decoders 150 and 250 for Manchester coding is called a CDR (Clock Data Recovery).

[0086] Asynchronous serial communication is performed between the transmission circuit 120 and the reception circuit 240, and between the transmission circuit 220 and the reception circuit 140. In the asynchronous serial communication, character information of a single character is transmitted before being sandwiched by a "start bit" meaning start and a "stop bit" meaning end. Also, a "parity bit" is added before the stop bit, for checking whether data has been correctly transmitted. Note that the above explanation has been made in an example of ensuring full-duplex communication of the signal line for each direction of data flow. However, half-duplex communication using one signal line, the communication direction of which is switched, can be applied.

[0087] Note that a set signal or a control signal for a sensor or a control device is transmitted from the semiconductor device 100 to the semiconductor device 200. Data, state information, or error information of the sensor or the control device is transmitted from the semiconductor device 200 to the semiconductor device 200.

[0088] The semiconductor device 100 includes, in addition to the communication module 110, a CPU 160, a timer 170, and another control circuit (CNTR) 180. The communication module 110 performs communication in response to data and control from these circuits. The semiconductor device 200 includes a control circuit (CNTR) 260 that controls a sensor or a control device not illustrated, and the communication module 210 performs communication in response to data and control from the control circuit 260. The semiconductor device 200 can be constituted by an MCU.

[0089] Next, reference will be made to Figure 7 Decoders 150 and 250 for Manchester coding will be explained. Figure 7 is a block diagram showing the configuration of the decoder shown in Figure 6 Although the decoder 150 will be explained below, the decoder 250 has a similar configuration to that of the decoder 150 and operates in a similar manner thereto.

[0090] The decoder 150 includes a data receiving circuit having a synchronization circuit (SYNC) 151, a noise filter (FLTR) 152 and an edge detection circuit (EDC) 153, and a clock generation circuit (CG) 157. The decoder 150 also includes an edge recognition circuit having an edge determination circuit (EJC) 154, an edge history circuit (EHC) 155, and a counter (CNTR) 156.

[0091] A serial input signal (SI) of Manchester coding is passed through the synchronization circuit 151 and the noise filter 152, and is input to the edge detection circuit 153. In this case, the synchronization circuit 151 is constituted by, for example, a multi-level flip-flop (F / F) circuit, for avoiding the occurrence of metastability. The noise filter 152 is constituted by, for example, a three-input majority decision circuit.

[0092] The clock signal (CLK) is a clock generated in the semiconductor device 100, and is obtained by dividing a clock generated in a PLL or the like. However, division is not always necessary, and the clock can not be divided. For the clock signal (CLK), either the rising edge or the falling edge can be used, or both the rising edge and the falling edge can be used. Alternatively, a two-phase clock signal (CLK) can be used, the phases of which are 180 degrees out of phase with each other. In this case, the number of clock signals (CLK) is two.

[0093] The edge determination circuit 154 generates reception data (R_DATA) based on the edge detected by the edge detection circuit 153. The edge history circuit 155 is a storage circuit for storing phase shift (delay) information (LDI) of a previous cycle based on reception edge information (REI) that is an output of the edge determination circuit 154. The counter 156 is initialized based on the reception edge information (REI), and counts the clock signal (CLK).

[0094] The clock generation circuit 157 generates a reception clock (R_CLK) based on the reception edge information (REI).

[0095] Reference will be made to Figure 8 A method of detecting an intermediate edge will be explained. Figure 8 is a block diagram showing the configuration of the decoder shown in Figure 7The timing chart of the operation waveform of the illustrated decoder. When the input period of the Manchester code is 10 ns (100 Mbps), the operation is implemented in a jitter of less than ±1.875 ns (i.e., "sampling period" x 3 / 2). Hereinafter, a system in which the sampling period is 1.25 ns and the jitter is ±1.5 ns will be explained.

[0096] The transmission reference signal (T_REF) corresponds to the transmission clock (CLK) used as the start point of Figure 1 The reception input signal (R_IN) corresponds to the Manchester-coded input in Figure 3 The reception input signal (R_IN) corresponds to the input signal of the flip-flop 201 used as the input first-stage logic in Figure 1 The reception input signal (R_IN) is the serial input signal (SI) of the synchronization circuit 151 or the input signal of the edge detection circuit 153 in Figure 7 The reception input signal (R_IN) is the serial input signal (SI) of the synchronization circuit 151 or the input signal of the edge detection circuit 153 in

[0097] The input signal (S_IN) is a signal obtained after sampling the reception input signal (R_IN), and corresponds to the Manchester-coded input in Figure 3 The input signal (S_IN) is the output signal of the synchronization circuit 151, the noise filter 152 or the F / F circuit within the edge detection circuit 153 in Figure 7 The input signal (S_IN) is the output signal of the synchronization circuit 151, the noise filter 152 or the F / F circuit within the edge detection circuit 153 in

[0098] In this case, Figure 8 (a) to (c) of the input signal (S_IN) of the Manchester code decoder 100 show the signal waveforms in the following cases.

[0099] (a) Small delay (from the average value -1.875 ns to -0.625 ns)

[0100] (b) Medium delay (within ±0.625 ns from the average value)

[0101] (c) Large delay (from the average value +0.625 ns to +1.875 ns)

[0102] And, the cases (a) to (c) depend on the jitter, and thus can change for each edge. For example, even when the first intermediate edge ME1 is in the case (a), the second boundary edge BE2 is not limited to the case (a), but can be in any one of the cases (a) to (c). And, when the first intermediate edge ME1 is in the case (b) or (c), the second boundary edge BE2 can likewise be in any one of the cases (a) to (c).

[0103] Figure 8The solid arrow in the middle indicates sampling of the middle edge, and the dashed arrow indicates sampling of the boundary edge. In order to extract the clock and data from the Manchester encoded signal, it is necessary to identify the difference between the middle edge and the boundary edge.

[0104] When the edge determination circuit 154 detects an edge, the value of the counter (CNTR) 156 is cleared to "0", and is incremented by 1 in each sampling period. However, Figure 8 The case where the value is continuously incremented (the case where the second middle edge ME2 is not detected) is shown for ease of understanding.

[0105] The detection method of the second middle edge ME2, which is an example of a detection target middle edge, will be explained.

[0106] First, the delay information (LDI) stored in the edge history circuit 155 will be explained. The value of the delay information (LDI) stored in the edge history circuit 155 is composed of three values of "0", "1", and "2".

[0107] The case where the delay information (LDI) is "0" is an unknown delay case, and indicates that the input signal (R_IN) is in Figure 8 the case (a), (b), or (c). The data detection range of the second middle edge ME2 is set so that the counter value of the counter 156 is 6 to 10. The case where the delay information (LDI) is "0" is called "edge history 0", and is expressed as "EH=0".

[0108] The case where the delay information (LDI) is "1" is a small delay case or a medium delay case, and indicates that the input signal (R_IN) is in Figure 8 the case (a) or (b). The data detection range of the second middle edge ME2 is set so that the counter value is 7 to 10. The case where the delay information (LDI) is "1" is called "edge history 1", and is expressed as "EH=1".

[0109] The case where the delay information (LDI) is "2" is a medium delay case or a large delay case, and indicates that the input signal (R_IN) is in Figure 8 the case (b) or (c). The data detection range of the second middle edge ME2 is set so that the counter value is 6 to 9. The case where the delay information (LDI) is "2" is called "edge history 2", and is expressed as "EH=2".

[0110] The detection operation and update of the edge history of the second middle edge ME2, which is the middle edge of the next period of each edge history of the first middle edge ME1, which is the middle edge of the previous period, will be explained.

[0111] Operation in edge history 1 (EH = 1):

[0112] The second intermediate edge ME2 occurs when the counter value of the counter 156 is any one of 7 to 10, in the case (EH = 1) where the first intermediate edge ME1 is in the case (a) or (b). Although edges can occur when the counter value is 3 to 6 or 11 to 14, these edges are negligible since they are boundary edges (the second boundary edge BE2 or the third boundary edge BE3). The edge determination circuit 154 detects the edge in the range of 7 to 10 of the counter value.

[0113] The edge determination circuit 154 outputs the reception data (R_DATA) as "1" when the edge changes from high (H) to low (L), or outputs the reception data (R_DATA) as "0" when the edge changes from low (L) to high (H), and outputs the reception clock (R CLK). Hereinafter, the change from high (H) to low (L) is referred to as "H→L", and the change from low (L) to high (H) is referred to as "L→H".

[0114] When the counter value at the time of edge detection is 7 or 8, the second intermediate edge ME2 is in the case (a) or (b) (EH = 1), the edge determination circuit 154 stores the value "1" into the edge history circuit 155, and updates the edge history. When the counter value at the time of edge detection is 9 or 10, the second intermediate edge ME2 is in the case (b) or (c) (EH = 2), the edge determination circuit 154 stores the value "2" into the edge history circuit 155, and updates the edge history.

[0115] Operation in edge history 2 (EH = 2):

[0116] The second intermediate edge ME2 occurs when the counter value of the counter 156 is any one of 6 to 9, in the case (EH = 2) where the first intermediate edge ME1 is in the case (b) or (c). Although edges can occur when the counter value is 2 to 5 or 10 to 13, these edges are negligible since they are boundary edges (the second boundary edge BE2 or the third boundary edge BE3). The edge determination circuit 154 detects the edge in the range of 6 to 9 of the counter value.

[0117] The edge determination circuit 154 outputs the reception data (R_DATA) as "1" when the change of the edge is "H→L", and outputs the reception data (R_DATA) as "0" when the change of the edge is "L→H", and outputs the reception clock (R CLK).

[0118] When the counter value at the time of edge detection is 6 or 7, the second intermediate edge ME2 is in case (a) or (b) (EH = 1), and the edge determination circuit 154 stores the value "1" into the edge history circuit 155, and updates the edge history. When the counter value at the time of edge detection is 8 or 9, the second intermediate edge ME2 is in case (b) or (c) (EH = 2), the edge determination circuit 154 stores the value "2" into the edge history circuit 155, and updates the edge history.

[0119] Edge history operation 0 (EH = 0):

[0120] In the case of the edge in the first period, when it is assumed that the start bit is "1", the change of the intermediate edge is necessarily "H→L". Therefore, when "H→L" is shifted, the counter value in the first period is cleared to "0", "1" is output as the reception data (R_DATA), and the reception clock (R CLK) is output. In the first period, it is not possible to determine which of the cases (a) to (c) the intermediate edge is in, so "EH = 0" is set.

[0121] In the case of "EH = 0" including the first period, the acceptable counter values of the second intermediate edge ME2 are 6 to 10. If only a single edge is detected in the range of 6 to 10 of the counter values, the edge determination circuit 154 calculates the edge history based on the counter value at the time of edge detection as follows.

[0122] When the counter value is 6 or 7, the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "1" into the edge history circuit 155, and updates the edge history.

[0123] When the counter value is 8, the edge determination circuit 154 determines that the second intermediate edge ME2 is the same as the delay of the first intermediate edge ME1, stores the value "0" into the edge history circuit 155, and updates the edge history.

[0124] When the counter value is 9 or 10, the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b) or (c), stores the value "2" into the edge history circuit 155, and updates the edge history.

[0125] In the case of "EH=0", two edges are rarely detected at the counter values 6 and 10. In the case of "EH=0", it is not possible to determine which of the edges is the middle edge or which of the edges is the boundary edge, and therefore, the edge determination circuit 154 generates a decoding error. When a decoding error is generated, the reception circuit 140 stops reception hereafter until the next frame is received, and the frame or the bits obtained after the error is generated are discarded completely. When reception of the entire frame or the partial bits is discarded, the reception buffer (BFFR) 141 in the reception circuit 140 retains the previous value. Furthermore, even in the cases other than "EH=0", two or more edges can be detected because of error operations due to noise or the like. Even in these cases, the edge determination circuit 154 generates a decoding error similarly to the description above.

[0126] Reference Figure 9 The edge detection operation of the decoder 150 is explained. Figure 9 is a flowchart showing a hardware process performed when Figure 7 is a flowchart showing a hardware process performed when

[0127] (Step S0)

[0128] The edge detection circuit 153 detects an edge that changes to "H→L".

[0129] (Step S1)

[0130] The edge determination circuit 154 outputs "1" as the input signal (R_DATA), and outputs the reception edge information (REI) to the edge history circuit 155, the counter 156, and the clock generation circuit 157. The clock generation circuit 156 generates and outputs the reception clock (R_CLK) based on the reception edge information (REI). The counter 156 clears the counter value to "0" based on the reception edge information (REI). The edge history circuit 155 stores the edge history "0" based on the reception edge information (REI).

[0131] (Step S2)

[0132] The edge determination circuit 154 sets the detection range based on the edge history. In this process, the lower limit of the detection range is "WL", and the upper limit of the detection range is "WH".

[0133] (Step S3)

[0134] The counter value of the counter 156 is incremented by the clock signal (CLK).

[0135] (Step S4)

[0136] The edge determination circuit 154 determines whether the counter value of the counter 156 is equal to or greater than the lower limit (WL) of the detection range.

[0137] (Step S5)

[0138] The edge determination circuit 154 determines whether the counter value of the counter 156 is equal to or less than the upper limit (WH) of the detection range.

[0139] (Step S6)

[0140] The edge determination circuit 154 determines whether an edge has been detected based on the output of the edge detection circuit 153.

[0141] (Step S7)

[0142] The edge determination circuit 154 determines whether the detected edge is a first detected edge.

[0143] (Step S8)

[0144] The edge determination circuit 154 sets the counter value of the counter 156 at the time of edge detection as the first edge position.

[0145] (Step S9)

[0146] The edge determination circuit 154 outputs the input signal (R_DATA) and outputs the reception edge information (REI) to the edge history circuit 155, the counter 156, and the clock generation circuit 157. The clock generation circuit 156 generates and outputs the reception clock (R_CLK) based on the reception edge information (REI). The edge history circuit 155 updates the edge history based on the reception edge information (REI).

[0147] (Step S10)

[0148] In step S5, if the counter value is greater than the upper limit of the detection range, the counter 156 clears the counter value to "0".

[0149] (Step 11)

[0150] In step S7, if the detected edge is a second detected edge, the edge determination circuit 154 outputs a decoding error.

[0151] According to the first working example, when the counter value used to identify an intermediate edge is changed based on the previous edge history, decoding is implemented within a sampling period of 1 / 8 of a period of Manchester encoded data and with a jitter of less than ±(1 / 8 x 2 / 3) of a period of Manchester encoded data.

[0152] (Second Working Example)

[0153] ReferenceFigure 10 A detection method of the second intermediate edge (ME2) according to the second working example is explained. Figure 10 is a timing chart showing an operation waveform of the decoder according to the second working example.

[0154] The decoder according to the second embodiment is identical in configuration to the decoder 150 and the decoder 250 according to the first working example. However, the operation of the edge determination circuit 154 and the edge history circuit 155 is different. When the input period of the Manchester encoded signal is 10 ns (100 Mbps), the operation is implemented with a jitter of less than ±2.5 ns (i.e., the sampling period x 2). The following explanation will be made in a system in which the jitter is ±1.5 ns.

[0155] In the second working example, (a) to (d) of the input signal (S_IN) show signal waveforms in the following cases.

[0156] (a) Small delay (from the average value -2.5 ns to -1.25 ns)

[0157] (b) Slightly small delay (from the average value -1.25 ns to 0 ns)

[0158] (c) Slightly large delay (from the average value 0 ns to +1.25 ns)

[0159] (d) Large delay (from the average value 1.25 ns to +2.5 ns)

[0160] And, the cases (a) to (d) depend on the jitter, and thus can change for each edge. For example, even when the first intermediate edge ME1 is in the case (a), the second intermediate edge ME2 is not limited to the case (a), but can be in any one of the cases (a) to (d). And, the same is true for the second intermediate edge ME2 in the cases (b) to (d).

[0161] Figure 10 The solid arrow in indicates the sampling of the intermediate edge, and the dashed arrow indicates the sampling of the boundary edge. In order to extract the clock and the data from the Manchester encoded signal, it is necessary to recognize the difference between the intermediate edge and the boundary edge.

[0162] When the edge determination circuit 154 detects the edge, the value of the counter 156 is cleared to "0", and is incremented by 1 in each sampling period. However, Figure 10 shows a case in which the value is continuously incremented (a case in which the second intermediate edge ME2 is not detected) for the convenience of understanding.

[0163] The detection method of the second intermediate edge ME2 as a detection target is explained. The value of the delay information (LDI) stored in the edge history circuit 155 is constituted of ten values from "0" to "9".

[0164] The case where the delay information (LDI) is "0" is an unknown delay case, and indicates that the input signal (R_IN) is in the Figure 10 case (a), (b), (c) or (d). The data detection range of the second intermediate edge ME2 is set so that the counter value of the counter 156 is 5 to 11. The case where the delay information (LDI) is "0" is called "edge history 0", and is expressed as "EH=0".

[0165] The case where the delay information (LDI) is "1" is a small delay case, and indicates that the input signal (R_IN) is in the Figure 10 case (a). The data detection range of the second intermediate edge ME2 is set so that the counter value is 8 to 11. The case where the delay information (LDI) is "1" is called "edge history 1", and is expressed as "EH=1".

[0166] The case where the delay information (LDI) is "2" is a slightly small delay case, and indicates that the input signal (R_IN) is in the Figure 10 case (b). The data detection range of the second intermediate edge ME2 is set so that the counter value is 7 to 10. The case where the delay information (LDI) is "2" is called "edge history 2", and is expressed as "EH=2".

[0167] The case where the delay information (LDI) is "3" is a slightly large delay case, and indicates that the input signal (R_IN) is in the Figure 10 case (c). The data detection range of the second intermediate edge ME2 is set so that the counter value is 6 to 9. The case where the delay information (LDI) is "3" is called "edge history 3", and is expressed as "EH=3".

[0168] The case where the delay information (LDI) is "4" is a large delay case, and indicates that the input signal (R_IN) is in the Figure 10 case (d). The data detection range of the second intermediate edge ME2 is set so that the counter value is 5 to 8. The case where the delay information (LDI) is "4" is called "edge history 4", and is expressed as "EH=4".

[0169] The case where the delay information (LDI) is "5" is a non-large delay case, and indicates that the input signal (R_IN) is in the Figure 10Case (a), (b) or (c). The data detection range of the second middle edge ME2 is set so that the counter value is 6 to 11. The case where the delay information (LDI) is "5" is referred to as "edge history 5", and is expressed as "EH=5".

[0170] The case where the delay information (LDI) is "6" is a non-small delay case, and indicates that the input signal (R_IN) is in Figure 10 Case (b), (c) or (d). The data detection range of the second middle edge ME2 is set so that the counter value is 5 to 10. The case where the delay information (LDI) is "6" is referred to as "edge history 6", and is expressed as "EH=6".

[0171] The case where the delay information (LDI) is "7" is a small delay case, and indicates that the input signal (R_IN) is in Figure 10 Case (a) or (b). The data detection range of the second middle edge ME2 is set so that the counter value is 7 to 11. The case where the delay information (LDI) is "7" is referred to as "edge history 7", and is expressed as "EH=7".

[0172] The case where the delay information (LDI) is "8" is a large delay case, and indicates that the input signal (R_IN) is in Figure 10 Case (c) or (d). The data detection range of the second middle edge ME2 is set so that the counter value is 5 to 9. The case where the delay information (LDI) is "8" is referred to as "edge history 8", and is expressed as "EH=8".

[0173] The case where the delay information (LDI) is "9" is a non-small delay case, and indicates that the input signal (R_IN) is in Figure 10 Case (b) or (c). The data detection range of the second middle edge ME2 is set so that the counter value is 6 to 10. The case where the delay information (LDI) is "9" is referred to as "edge history 9", and is expressed as "EH=9".

[0174] The detection operation and update of the edge history of the second middle edge ME2, which is the middle edge of the next cycle of each edge history of the first middle edge ME1, which is the middle edge of the previous cycle, are explained.

[0175] Operation in the edge history 1 (EH=1):

[0176] The second middle edge ME2 occurs when the counter value of the counter 156 is any one of 8 to 11 in the case (a) of the first middle edge ME1 (EH = 1). Although edges can occur when the counter value is 4 to 7 or 12 to 15, these edges are ignored because they are boundary edges (the second boundary edge BE2 or the third boundary edge BE3). The edge determination circuit 154 detects the edge in the range of 8 to 11 of the counter value.

[0177] The edge determination circuit 154 outputs the reception data (R_DATA) as "1" when the change of the edge is "H→L", or as "0" when the change of the edge is "L→H", and outputs the reception clock (R CLK).

[0178] The edge determination circuit 154 determines the delay state of the second middle edge ME2 based on the counter value at the time of the edge detection, stores the delay information into the edge history circuit 155, and uses the delay information for determining the third middle edge ME3 of the next cycle.

[0179] In the case of "counter value = 8", the edge determination circuit 154 determines that the second middle edge ME2 is in the case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0180] In the case of "counter value = 9", the edge determination circuit 154 determines that the second middle edge ME2 is in the case (b), stores the value "2" into the edge history circuit 155, and updates the edge history (EH = 2).

[0181] In the case of "counter value = 10", the edge determination circuit 154 determines that the second middle edge ME2 is in the case (c), stores the value "3" into the edge history circuit 155, and updates the edge history (EH = 3).

[0182] In the case of "counter value = 11", the edge determination circuit 154 determines that the second middle edge ME2 is in the case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0183] Operation in the edge history 2 (EH = 2):

[0184] In the case where the first middle edge ME1 is in case (b) (EH = 2), the second middle edge ME2 occurs when the counter value of the counter 156 is any one of 7 to 10. The edge determination circuit 154 determines the edge detected within the counter value range of 7 to 10 as the second middle edge ME2, and outputs the received data (R_DATA) and the received clock (R CLK) based on the change in the data at that time.

[0185] The edge determination circuit 154 determines the delay state of the second middle edge ME2 based on the counter value at the time of the edge detection, stores the delay information into the edge history circuit 155, and uses the delay information for determining the third middle edge ME3 of the next cycle.

[0186] In the case of "counter value = 7", the edge determination circuit 154 determines that the second middle edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0187] In the case of "counter value = 8", the edge determination circuit 154 determines that the second middle edge ME2 is in case (b), stores the value "2" into the edge history circuit 155, and updates the edge history (EH = 2).

[0188] In the case of "counter value = 9", the edge determination circuit 154 determines that the second middle edge ME2 is in case (c), stores the value "3" into the edge history circuit 155, and updates the edge history (EH = 3).

[0189] In the case of "counter value = 10", the edge determination circuit 154 determines that the second middle edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0190] Operation in the edge history 3 (EH = 3):

[0191] In the case where the first middle edge ME1 is in case (c) (edge history 3 (EH = 3)), the second middle edge ME2 occurs when the counter value of the counter 156 is any one of 6 to 9. The edge determination circuit 154 determines the edge detected within the counter value range of 6 to 9 as the second middle edge ME2, and outputs the received data (R_DATA) and the received clock (R CLK) based on the change in the data at that time.

[0192] The edge determination circuit 154 determines the delay state of the second middle edge ME2 based on the counter value at the time of the edge detection, stores the delay information into the edge history circuit 155, and uses the delay information for determining the third middle edge ME3 of the next cycle.

[0193] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0194] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b), stores the value "2" into the edge history circuit 155, and updates the edge history (EH = 2).

[0195] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c), stores the value "3" into the edge history circuit 155, and updates the edge history (EH = 3).

[0196] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0197] Operation in the edge history 4 (EH = 4):

[0198] In the case where the first intermediate edge ME1 is in case (d) (EH = 4), the second intermediate edge ME2 occurs when the counter value of the counter 156 is any one of 5 to 8. The edge determination circuit 154 determines the edge detected in the range of the counter value 5 to 8 as the second intermediate edge ME2, and outputs the reception data (R_DATA) and the reception clock (R CLK) based on the change of the data at that time.

[0199] The edge determination circuit 154 determines the delay state of the second intermediate edge ME2 based on the counter value at the time of the edge detection, stores the delay information into the edge history circuit 155, and uses the delay information for determining the third intermediate edge ME3 of the next cycle.

[0200] In the case of "counter value = 5", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0201] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b), stores the value "2" into the edge history circuit 155, and updates the edge history (EH = 2).

[0202] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c), stores the value "3" into the edge history circuit 155, and updates the edge history (EH = 3).

[0203] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0204] Operation in the edge history 0 (EH = 0):

[0205] Similar to the first working example, the edge case of the first cycle is "EH = 0". Also, in any one of cases (a) to (d), the case where the intermediate edge (the first intermediate edge ME1) of the previous cycle is unknown is also "EH = 0".

[0206] In the case of (EH = 0), the acceptable counter values of the second intermediate edge ME2 are 5 to 11. When only a single edge is detected within the range of the counter values 5 to 11, the edge determination circuit 154 outputs the received data (R_DATA) and the received clock (R_CLK) based on the change in the data at that time. Then, the edge determination circuit 154 calculates the next edge history based on the counter value at the time of the edge detection as follows.

[0207] In the case of "counter value = 5", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0208] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "7" into the edge history circuit 155, and updates the edge history (EH = 7).

[0209] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), (b), or (c), stores the value "5" into the edge history circuit 155, and updates the edge history (EH = 5).

[0210] In the case of "counter value = 8", the edge determination circuit 154 cannot determine that the second intermediate edge ME2 is in any one of cases (a) to (d), stores the value "0" into the edge history circuit 155, and updates the edge history (EH = 0).

[0211] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b), (c) or (d), stores the value "6" into the edge history circuit 155, and updates the edge history (EH = 6).

[0212] In the case of "counter value = 10", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c) or (d), stores the value "8" into the edge history circuit 155, and updates the edge history (EH = 8).

[0213] In the case of "counter value = 11", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0214] Operation in the edge history 5 (EH = 5):

[0215] In the case where the first intermediate edge ME1 is determined to be in case (a), (b) or (c) (EH = 5), the acceptable counter values of the counter 156 of the second intermediate edge ME2 are 6 to 11. When only one edge is detected in the counter value, the edge determination circuit 154 outputs the received data (R_DATA) and the received clock (R CLK) based on the change of the data at that time.

[0216] The edge determination circuit 154 calculates the next edge history as follows based on the counter value at the time of edge detection.

[0217] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0218] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "7" into the edge history circuit 155, and updates the edge history (EH = 7).

[0219] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), (b) or (c), stores the value "5" into the edge history circuit 155, and updates the edge history (EH = 5).

[0220] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b), (c) or (d), stores the value "6" into the edge history circuit 155, and updates the edge history (EH = 6).

[0221] In the case of "counter value = 10", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c) or (d), stores the value "8" into the edge history circuit 155, and updates the edge history (EH = 8).

[0222] In the case of "counter value = 11", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0223] Operation in the edge history 6 (EH = 6):

[0224] In the case where the first intermediate edge ME1 is determined to be in case (b), (c), or (d), the acceptable counter value of the counter 156 of the second intermediate edge ME2 is 5 to 10. When only a single edge is detected in the counter value, the edge determination circuit 154 outputs the received data (R_DATA) and the received clock (R_CLK) based on the change in the data at that time.

[0225] The edge determination circuit 154 calculates the next edge history as follows based on the counter value at the time of edge detection.

[0226] In the case of "counter value = 5", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0227] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "7" into the edge history circuit 155, and updates the edge history (EH = 7).

[0228] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), (b), or (c), stores the value "5" into the edge history circuit 155, and updates the edge history (EH = 5).

[0229] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b), (c), or (d), stores the value "6" into the edge history circuit 155, and updates the edge history (EH = 6).

[0230] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c) or (d), stores the value "8" into the edge history circuit 155, and updates the edge history (EH = 8).

[0231] In the case of "counter value = 10", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0232] Operation in the edge history 7 (EH = 7):

[0233] In the case (EH = 7) where the first intermediate edge ME1 is determined to be case (a) or (b), the acceptable counter values of the counter 156 of the second intermediate edge ME2 are 7 to 11. In the case where only a single edge is detected in the counter value, the edge determination circuit 154 outputs the received data (R_DATA) and the received clock (R CLK) based on the change in the data at that time.

[0234] The edge determination circuit 154 calculates the next edge history based on the counter value at the time of edge detection as follows.

[0235] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0236] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "7" into the edge history circuit 155, and updates the edge history (EH = 7).

[0237] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b) or (c), stores the value "9" into the edge history circuit 155, and updates the edge history (EH = 9).

[0238] In the case of "counter value = 10", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c) or (d), stores the value "8" into the edge history circuit 155, and updates the edge history (EH = 8).

[0239] In the case of "counter value = 11", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0240] Operation in the edge history 8 (EH = 8):

[0241] In the case where the first intermediate edge ME1 is determined as case (c) or (d) (EH = 8), the acceptable counter value of the counter 156 of the second intermediate edge ME2 is 5 to 9. When only a single edge is detected in the counter value, the edge determination circuit 154 outputs the received data (R_DATA) and the received clock (R CLK) based on the change in the data at that time.

[0242] The edge determination circuit 154 calculates the next edge history as follows based on the counter value at the time of edge detection.

[0243] In the case of "counter value = 5", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0244] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "7" into the edge history circuit 155, and updates the edge history (EH = 7).

[0245] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b) or (c), stores the value "9" into the edge history circuit 155, and updates the edge history (EH = 9).

[0246] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c) or (d), stores the value "8" into the edge history circuit 155, and updates the edge history (EH = 8).

[0247] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0248] Operation in edge history 9 (EH = 9):

[0249] In the case where the first intermediate edge ME1 is determined as case (b) or (c) (EH = 9), the acceptable counter value of the counter 156 of the second intermediate edge ME2 is 6 to 10. When only a single edge is detected in the counter value, the edge determination circuit 154 outputs the received data (R_DATA) and the received clock (R CLK) based on the change in the data at that time.

[0250] The edge determination circuit 154 calculates the next edge history as follows based on the counter value at the time of edge detection.

[0251] In the case of "counter value = 6", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a), stores the value "1" into the edge history circuit 155, and updates the edge history (EH = 1).

[0252] In the case of "counter value = 7", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (a) or (b), stores the value "7" into the edge history circuit 155, and updates the edge history (EH = 7).

[0253] In the case of "counter value = 8", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (b) or (c), stores the value "9" into the edge history circuit 155, and updates the edge history (EH = 9).

[0254] In the case of "counter value = 9", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (c) or (d), stores the value "8" into the edge history circuit 155, and updates the edge history (EH = 8).

[0255] In the case of "counter value = 10", the edge determination circuit 154 determines that the second intermediate edge ME2 is in case (d), stores the value "4" into the edge history circuit 155, and updates the edge history (EH = 4).

[0256] In the case of "EH = 0" or "EH = 5 to 9", the edge can be detected twice. In this case, which edge is the intermediate edge can be determined by combining the edge history of the intermediate edge of the previous cycle and the two counter values at which the edge of the next cycle is detected, as described below. In this process, the received data (R_DATA) and the received clock (R_CLK) at the determined intermediate edge are output based on the change in the data at that time, and the next edge history is calculated.

[0257] In the case of "EH = 0" and in the case where one of the two counter values is 8, the edge at the counter value 8 is determined to be the intermediate edge.

[0258] In the case of "EH = 5" and in the case where one of the two counter values is 8 or 9, the edge determination circuit 154 determines that the edge at the counter value of 8 or 9 is the intermediate edge.

[0259] In the case of "EH = 6" and in the case where one of the two counter values is 7 or 8, the edge determination circuit 154 determines that the edge at the counter value of 7 or 8 is the intermediate edge.

[0260] In the case of "EH = 7" and in the case of one of the two counter values being 8, 9, or 10, the edge determination circuit 154 determines the edge of which the counter value is 8, 9, or 10 as the middle edge.

[0261] In the case of "EH = 8" and in the case of one of the two counter values being 6, 7, or 8, the edge determination circuit 154 determines the edge of which the counter value is 6, 7, or 8 as the middle edge.

[0262] In the case of "EH = 9" and in the case of one of the two counter values being 7, 8, or 9, the edge determination circuit 154 determines the edge of which the counter value is 7, 8, or 9 as the middle edge.

[0263] In the case of "EH = 0" or in the case of "EH = 5 to 9", even by the determination described above, which one is the middle edge cannot be often determined. In this case, the edge determination circuit 154 processes a decoding error. When a decoding error is generated, the reception circuit 140 stops the subsequent reception until the next frame is received, and the frame is completely discarded or the bits obtained after the error occurs are discarded. When the entire frame or the reception of the partial bits is discarded, the reception buffer 141 in the reception circuit 140 retains the previous value, and does not perform the update.

[0264] Regardless of the edge history, there can be a case where two or more edges are detected due to the influence of noise or other factors. Even in this case, which one of the middle edge, the boundary edge, and the pseudo edge caused by noise is the target edge cannot be determined, and therefore, the edge determination circuit 154 generates a decoding error. When a decoding error is generated, the reception circuit 140 stops the subsequent reception until the next frame is received, and the frame is completely discarded or the bits obtained after the error occurs are discarded. When the entire frame or the reception of the partial bits is discarded, the reception buffer 141 in the reception circuit 140 retains the previous value, and does not perform the update.

[0265] Reference Figure 6 The edge detection operation of the decoder 150 according to the second embodiment is explained. Figure 11 is a flowchart showing a hardware process performed when the decoder according to the second working example detects a falling edge.

[0266] The operations in steps S0 to S6 according to the second working example are the same as those of the first working example.

[0267] (Step S12)

[0268] The edge determination circuit 154 determines how many edges have been received before the detected edge.

[0269] (Step S13)

[0270] If the detected edge is the first edge, the edge determination circuit 154 sets the counter value of the counter 156 to the first edge position (T1).

[0271] (Step S14)

[0272] If the detected edge is the second edge, the edge determination circuit 154 sets the counter value of the counter 156 to the second edge position (T2).

[0273] (Step S15)

[0274] In step S5, if the counter value is greater than the upper limit of the detection range, the edge determination circuit 154 performs the following based on the edge history and T1 and T2. The edge determination circuit 154 checks the decoding error. Also, the edge determination circuit 154 outputs the input signal (R_DATA), and outputs the reception edge information (REI) to the edge history circuit 155, the counter 156, and the clock generation circuit 157. The clock generation circuit 156 generates and outputs the reception clock (R_CLK) based on the reception edge information (REI). The edge history circuit 155 updates the edge history based on the reception edge information (REI).

[0275] (Steps S16 and S17)

[0276] In step S16, the edge determination circuit 154 determines whether or not there is a decoding error. In step S17, if no decoding error is detected in step S16, the counter 156 clears the counter value to "0".

[0277] (Step 18)

[0278] If the edge detected in step S12 is the third edge and if an error has been determined in step S16, the edge determination circuit 154 outputs the decoding error.

[0279] According to the second working example, when the counter value for identifying the intermediate edge changes through the previous edge history, decoding is implemented in a sampling period that is 1 / 8 of the period of the Manchester coded data and with a jitter of up to ±(1 / 8 x 2) of the period of the Manchester coded data. The jitter range of the second working example is 4 / 3 times the jitter range of the first working example.

[0280] (Third Working Example)

[0281] Figure 12 is a block diagram illustrating a configuration of a decoder according to the third working example. Figure 13 is a circuit diagram illustrating a three-input majority decision circuit. Figure 14 is a circuit diagram illustratingFigure 12 a block diagram of a configuration of the edge recognition circuit shown in Figure 15 is a block diagram showing Figure 12 a block diagram of a part of the configuration of the edge recognition circuit shown in Figure 16 is a block diagram showing Figure 12 a block diagram of a part of the configuration of the edge recognition circuit shown in Figure 17 is Figure 12 a block diagram of the clock generation circuit shown in

[0282] Like the first working example, the decoder 150 according to the third working example includes a synchronization circuit (SYNC) 151, a noise filter (FLTR) 152, an edge detection circuit (EDC) 153, and a clock generation circuit (CG) 157. The decoder 150 according to the third working example further includes an edge recognition circuit 158, in place of the edge determination circuit (EJC) 154, the edge history circuit (EHC) 155, and the counter (CNTR) 156 according to the first working example.

[0283] As shown in Figure 12 the synchronization circuit (SYNC) 151 is composed of a shift flip-flop (S_F / F) 151a and a data sampling flip-flop (D_F / F) 151b. A 400 MHz two-phase clock (clkup_p and clkup_n), a Manchester encoded signal (mc_si), and a 100 MHz clock (clk1) are input to the synchronization circuit (SYNC) 151. The clock (clk1) is a clock extracted from the Manchester encoded signal (mc_si). Sampling using the 400 MHz two-phase clock (clkup_p and clkup_n) is sampling using an 800 MHz clock.

[0284] As shown in Figure 14 the shift flip-flop 151a is composed of flip-flops connected in series, and sequentially receives the Manchester encoded signal (mc_si) while using the two-phase clock (clkup_p and clkup_n). In this process, the shift flip-flop 151a is composed of, for example, 18 flip-flops. The data received into the flip-flops 151a is referred to as "sin[*]". The data sampling flip-flop (D_F / F) 151b is composed of flip-flops, the number of which is the same as the number of the shift flip-flop 151a. The data sampling flip-flop 151b samples in parallel the data that has been received into the flip-flops 151a in the rising timing of the clock (clk1). The data that has been received into the data sampling flip-flop 151b is referred to as "data1[*]".

[0285] As shown in Figure 13As shown in FIG. 15, the noise filter 152 is composed of a three-input majority decision circuit. This circuit is a circuit that outputs "1" if two or more pieces of data are "1". The noise filter 152 is composed of, for example, 16 three-input majority decision circuits.

[0286] The edge detection circuit 153 extracts data having different adjacent bit values from the data1 [*] signal that has passed through the noise filter 152. A signal indicating that data has been detected to change from "0" to "1" is "edge_r [*]", and a signal indicating that data has been detected to change from "1" to "0" is "edge_f [*]". The term "edge_r [*]" is also referred to as "edge_r [n:0]", and the term "edge_f [*]" is also referred to as "edge_f [n:0]". In this case, "n" is a natural number. For example, assume that "n = 14".

[0287] The edge recognition circuit 158 includes a shift circuit (SHFTR) 1581 and a shift circuit 1582, a window cut-off circuit 1583 and a window cut-off circuit 1584, and an edge history circuit (EDGHS) 1585.

[0288] The shift circuit 1581 and the shift circuit 1582 output a signal "edges_r [n:0]" and a signal "edges_f [n:0]" obtained by shifting the respective signals "edge_r [n:0]" and "edge_f [n:0]" by a shift amount (sft [i:0]). The shift amount (sft [i:0]) is generated by a shift amount generation circuit 1587 described later. If the value of the shift amount (sft [i:0]) is positive, the shift circuit 1581 and the shift circuit 1582 shift the respective signals "edge_r [n:0]" and "edge_f [n:0]" to the right (toward the lower-order bit). If the value of the shift amount (sft [i:0]) is negative, the shift circuit 1581 and the shift circuit 1582 shift the respective signals "edge_r [n:0]" and "edge_f [n:0]" to the left (toward the higher-order bit).

[0289] Although the following explanation is made on the window cut-off circuit 1583, the operation of the window cut-off circuit 1584 is similar to that of the window cut-off circuit 1583. The window cut-off circuit 1583 extracts 5 bits from "edges_r[n:0]" and sets "edgec_r[4:0]", i.e., a range in which a middle edge is detected (middle edge detection range). The middle edge detection range is controlled by "sft[i:0]". For example, after a middle edge is detected, any bit of "edgec_r[4:0]" becomes "1". The edge history circuit 1585 records "edgec_r" indicating a position of a previous cycle in which a middle edge has been detected (middle edge position). The window cut-off circuit 1583 corrects the middle edge detection range (edgec_r[4:0]) based on the middle edge position of the previous cycle (edgec_r) recorded in the edge history circuit 1585.

[0290] More specifically, if the middle edge position of the previous cycle (edgec_r) is in a high-order bit of the middle edge detection range (edgec_r[4:0]), the window cut-off circuit 1583 masks the highest-order bit (bit [4]). In this process, the high-order bit is bit [3] or bit [4]. That is, bits [3:0] of the middle edge detection range (edgec_r[4:0]) are set to the edge detection range. If the middle edge position of the previous cycle (edgec_r) is in a low-order bit thereof (bit [0] or bit [1]), the window cut-off circuit 1583 masks the lowest-order bit (bit [0]) of the middle edge detection range (edgec_r[4:0]). That is, bits [4:1] of the middle edge detection range (edgec_r[4:0]) are set to the edge detection range. If the middle edge position of the previous cycle (edgec_r) is another bit (bit [2]), the bit to be masked is unchanged, in other words, the bit to be masked is set to the same as the masked bit of the previous cycle.

[0291] As Figure 15As shown in FIG. 8, the edge recognition circuit 158 further includes a data detection circuit 1586. If any bit of "edgec_r[4:0]" is 1, this means that an edge from "0" to "1" exists in the middle edge detection range, and therefore the data detection circuit 1586 sets the "data_1" signal to "1". If any bit of "edgec_f[4:0]" is 1, this means that an edge from "1" to "0" exists in the middle edge detection range, and therefore the data detection circuit 1586 sets the "data_0" signal to "1". However, if both "edgec_r[4:0]" and "edgec_f[4:0]" contain "1", a skew cannot be recognized, and therefore the data detection circuit 1586 sets the "CDR_error" signal to "1". If all bits of "edgec_r[4:0]" and "edgec_f[4:0]" are "0", the data detection circuit 1586 determines that there is no middle edge, in other words, determines that this is not the frame (end of frame), and sets the "passive" signal to "1".

[0292] As shown in FIG. 8, the edge recognition circuit 158 further includes a data detection circuit 1586. If any bit of "edgec_r[4:0]" is 1, this means that an edge from "0" to "1" exists in the middle edge detection range, and therefore the data detection circuit 1586 sets the "data_1" signal to "1". If any bit of "edgec_f[4:0]" is 1, this means that an edge from "1" to "0" exists in the middle edge detection range, and therefore the data detection circuit 1586 sets the "data_0" signal to "1". However, if both "edgec_r[4:0]" and "edgec_f[4:0]" contain "1", a skew cannot be recognized, and therefore the data detection circuit 1586 sets the "CDR_error" signal to "1". If all bits of "edgec_r[4:0]" and "edgec_f[4:0]" are "0", the data detection circuit 1586 determines that there is no middle edge, in other words, determines that this is not the frame (end of frame), and sets the "passive" signal to "1". Figure 16 As shown in FIG. 8, the edge recognition circuit 158 further includes a shift amount generation circuit 1587 and a clock control circuit 1588.

[0293] The shift amount generation circuit 1587 includes a flip-flop 1587a that stores a "sft[*]" value indicating a shift amount. If the first falling edge in the frame is detected, "edgef_f[4:0]" contains "1". This is set as an initial value, and the bit value having "1" in "edgef_f[4:0]" is input to the flip-flop 1587a. That is, the initial sft[*] value corresponds to the phase difference between the clock superimposed on the Manchester encoded signal (mc_si) at the start of the frame and the clock (clk1) having the same frequency as that generated in the decoder 150 at the start of the frame.

[0294] Then, in the case where the 800 MHz clock (clkup_p / clkup_n) is shifted by one cycle due to jitter, the increment / decrement circuit (Inc / Dec) 1587b corrects the sft[*] value to "value + 1" or "value - 1". In this process, shifting by one cycle corresponds to the case where "edgec_r[3]", "edgec_f[3]", "edgec_r[1]", or "edgec_f[1]" is "1". If "edgec_r[3]" or "edgec_f[3]" is "1", the sft[*] value is incremented by "1" (to "value + 1"). If "edgec_r[1]" or "edgec_f[1]" is "1", the sft[*] value is decremented by "1" (to "value - 1").

[0295] Further, in the case where the 800MHz clock (clkup_p / clkup_n) is shifted by two cycles, the adder 1587c sets the sft[*] value within one cycle to "value+2" or "value-2". Further, in the case where the 800MHz clock (clkup_p / clkup_n) is shifted by two cycles, the clock period of the control clock (clk1) is controlled as described later. In this process, the shift by two cycles corresponds to a case where "edgec_r[4]", "edgec_f[4]", "edgec_r[0]", or "edgec_f[0]" is "1". If "edgec_r[4]" or "edgec_f[4]" is "1", the sft[*] value is incremented by "2" (to become "value+2"). If "edgec_r[0]" or "edgec_f[0]" is "1", the sft[*] value is decremented by "2" (to become "value-2").

[0296] The clock control circuit 1588 generates a signal (cdiv) for controlling the division ratio of the clock generation circuit 157. The "divide by four" is normally set to a division ratio of the frequency of the clock (clkup_p) (400MHz) to the baud rate (100MHz). In the case of "divide by four", the cdiv value becomes "3". In the intermediate edge detection, in the case where the 800MHz clock (clkup_p / clkup_n) is shifted by two cycles, the clock control circuit 1588 sets the cdiv value of only one cycle of the clock (clk1) to "value+1" or "value-1". If "edgec_r[0]" or "edgec_f[0]" is "1", the clock control circuit 1588 sets the cdiv value to "4". If "edgec_r[4]" or "edgec_f[4]" is "1", the clock control circuit 1588 sets the cdiv value to "2".

[0297] Note that the clock control circuit 1588 includes a two-bit register UBRS[l:0]. In the register UBRS[l:0], a "divide-by-four" (8 cycles), a "divide-by-five" (10 cycles), and a "divide-by-six" (12 cycles) can be set as a division ratio. In the case of "divide-by-five", the cdiv value normally becomes "4". If "edgec_r[0]" or "edgec_f[0]" is "1", the cdiv value normally becomes "5". If "edgec_r[4]" or "edgec_f[4]" is "1", the cdiv value normally becomes "3". In the case of "divide-by-six", the cdiv value normally becomes "5". If "edgec_r[0]" or "edgec_f[0]" is "1", the cdiv value normally becomes "6". If "edgec_r[4]" or "edgec_f[4]" is "1", the cdiv value normally becomes "4".

[0298] The clock generation circuit 157 generates a clock (clk1) by dividing the frequency of the clock (clkup_p) by the cdiv value. The process is explained in detail below. The clock generation circuit 157 includes a counter 1571, a comparator 1572 for comparing the output of the counter 1571 with the cdiv value, and a flip-flop 1573 for storing the comparison result. The counter 1571 counts the counter value from "0" to the cdiv value for each clock (clkup_p) by using an increment circuit 1571b. The comparator 1572 compares the output (counter value) of the flip-flop 1571a of the counter 1571 with the cdiv value, and outputs "0" if the counter value is smaller than the cdiv value. If the counter value is equal to the cdiv value, the comparator 1572 outputs "1". If the enable signal (EN) as the output of the flip-flop 1573 is "0", the counter 1571 counts the counter value. If the enable signal (EN) is "1", the counter 1571 clears the counter value to "0". The enable signal (EN) becomes "1" for every "cdiv's value + 1". If the enable signal (EN) is "1", the clock gating circuit (ICG) 1574 outputs the clock (clkup_p). In this process, the output is the value obtained by adjusting one pulse based on the clock (clkup_p) to the number of pulses corresponding to the cdiv value as the clock (clk1). By changing the cdiv value, the number of samples per cycle of the clock (clk1) can be changed.

[0299] The counter 1571 counts a counter value from "0" to a cdiv value, and the clock generation circuit 157 can change the period of the clock (clk1) by changing the cdiv value. Note that the counter 1571 can count a counter value from a set value other than "0" to the cdiv value to change the period of the clock (clk1).

[0300] Reference Figure 18 to Figure 24 The operation of the decoder according to the third working example is explained. Figure 18 to Figure 24 Each of the figures illustrates a timing chart of the operation of the decoder according to the third working example.

[0301] First, the symbols of Figure 18 to Figure 24 The term "edgebit" indicates which bit of "edgec_r" or "edgec_f" is "1". That is, if "edgec_r[0]" or "edgec_f[0]" contains "1", the "edgebit" becomes "-2". If "edgec_r[1]" or "edgec_f[1]" contains "1", the "edgebit" becomes "-1". If "edgec_r[2]" or "edgec_f[2]" contains "1", the "edgebit" becomes "0". If "edgec_r[3]" or "edgec_f[3]" contains "1", the "edgebit" becomes "+1". If "edgec_r[4]" or "edgec_f[4]" contains "1", the "edgebit" becomes "+2". If the "passive" value is "1", the "edgebit" becomes "0".

[0302] The term "data2_pre" indicates which of "dadta_0", "data_1", "passive", or "CDR_error" has been set in the data detection circuit 1586 shown in Figure 15 The term "data2" indicates the final data value. Also, the vertical solid line of each figure indicates the bit boundary of the Manchester encoded signal (mc_si), and the vertical dotted line of the figure indicates the bit midpoint of the Manchester encoded signal (mc_si).

[0303] The vertical arrow indicates the rising edge of the clock (clk1) as the load timing from "sin[*]" to "data_1". Note that the waveform of the clock (clk1) is illustrated as having a duty cycle close to 50%. However, in Figure 17In the waveform of the clock (clk1) generated in the clock generation circuit 157 shown in the middle, the rising edge is located at the position in the figure so that the clock has the pulse width of the clock (clkup_p), and the position of the falling edge is different from the position in the figure.

[0304] Figure 18 A waveform (steady state) having noise but the jitter is within 1 / 8 of the bit period is shown in the case where the middle edge of the start bit is contained in the "H" period of the clock (clkup_n).

[0305] When sampled in the period T2, the first edge of the Manchester encoded signal (mc_si) is detected, and the following data is generated. In this process, the rightmost is the bit [0]. "data1" is data having a length of 18 bits, and FLTR is data having a length of 16 bits. Each of "edge_f", "edge_r", "edges_f", and "edges_r" is data having a length of 15 bits.

[0306] data1 = 11_11111111_11111000

[0307] FLTR = 11111111_11111100

[0308] edge_f = -0000000_00000010

[0309] edge_r = -0000000_00000000

[0310] edges_f = -0000000_00000010

[0311] edges_r = -0000000_00000000

[0312] At the first sampling, the flip-flop 1587a is cleared to "0" by an input signal of an unillustrated clear terminal to the flip-flop 1587a. Therefore, since the sft value is "0", "edge_f = edges_f" is established. At this time, the bit of the edge detected is "edges_f[1]", and therefore, "edgebit" becomes "2", that is, the detected bit of "edge_f". Therefore, in the flip-flop 1587a, "2" is set as the initial sft value. The sft value of the next period T3 becomes "2". "data2_pre" of the period T2 corresponds to the edge detection after "no source" of the period T1, and therefore, becomes "no source".

[0313] In the period after the period T3, the shift circuit 1581 and the shift circuit 1582 generate "edges_f" and "edges_r" by shifting "edge_f" and "edge_r" by the sft value, respectively. If the sft value is positive, the shift circuit 1581 and the shift circuit 1582 shift them to the right (shift to the low-order bit side); and if the sft value is negative, shift them to the left (shift to the high-order bit side). The shift amount generation circuit 1587 generates the sft value of the next period by adding the "edgebit" value of the previous period to the sft value of the previous period. In this process, the intermediate edge detection range (edgec_r[4:0] and edgec_f[4:0]) corresponds to edges_r[9:5] and edges_f[9:5], respectively.

[0314] For example, in the period T3, the following data is generated. In this data, "X" indicates meaningless data.

[0315] data1 = 11_11111000_01111000

[0316] FLTR = 11111100_00111100

[0317] edge_f = -0000010_00000010

[0318] edge_r = -0000000_00100000

[0319] edges_f = -XX00000_10000000

[0320] edges_r = -XX00000_00001000

[0321] edgec_f[4:0] = 00100

[0322] edgec_r[4:0] = 00000

[0323] In the period T3, "edges_f[7]" which is the intermediate position of "edges_f[9:5]" shifted two bits to the right from "edge_f" is "1". That is, since the edgec_f[2] value is "1", the "edgebit" value becomes "0", and the intermediate edge detection range is not corrected in the next period T4. Also, the sft value of the next period T4 does not change and remains "2". Since "1" is detected in "edges_f", the data_1 value becomes "1", the data2_pre value becomes "1", and the data2 value in the next period T4 becomes "1".

[0324] After the period T3, the sft value is the same as "2", and the period after the period T4 proceeds in a similar manner. When the jitter is within 1 / 8 of a period, "edgec_r[2]" or "edgec_f[2]", which is the middle bit of "edges_r" or "edges_f", must be changed to "1".

[0325] In the operation of the period T7, an "H" noise having a width equal to or smaller than 1 / 8 of a period is superimposed on the Manchester code signal (mc_si). Also, in the operation of the period T8, an "L" noise having a width equal to or smaller than 1 / 8 of a period is superimposed on the Manchester code signal (mc_si). Although the noise is loaded into "data1", the noise of 1 bit is removed by the noise filter (FLTR), and then the data thereafter is processed normally.

[0326] The waveform in the case where the "H" period of the clock (clkup_p) contains the middle edge of the start bit is the same as that of Figure 18 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as that of Figure 18 is performed. Like Figure 18 , the operations performed in the period T7 and the period T8 with the noise are also the same as those performed without the noise by the noise filter FLTR.

[0327] Figure 19 The waveform is shown in the case where the "H" period of the clock (clkup_n) contains the middle edge of the start bit, with the jitter leading by 1 / 8 of a bit period. The left arrow of the Manchester code signal (mc_si) indicates that the edge leads by 1 / 8 of a period, and its right arrow indicates that the edge returns to the original edge. The operations up to the period T4 are the same as those of Figure 18 . The period T5 is first affected by the jitter.

[0328] In the period T5, the following data is generated.

[0329] data1 = 00_00001111_10000111

[0330] FLTR = 00000111_11000011

[0331] edge_f = -0000000_00100000

[0332] edge_r = -0000100_00000010

[0333] edges_f = -xx0000_00001000

[0334] edges_r = -xx0001_00000000

[0335] edgec_f[4:0] = 00000

[0336] edgec_r[4:0] = 01000

[0337] In the period T5, "1" is detected at "edges_r[8]" which is one bit left from the middle position of "edges_r[9:5]". That is, since "edgec_r[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period T6 is changed from "2" to "3". Since "edgec_r[3]" is "1", the window cut-off circuit 1583 masks the highest order bit (bit [4]) in the next period T6. That is, bits [3:0] of the middle edge detection range ("edgec_r[4:0]", "edgec_f[4:0]") are set to the edge detection range.

[0338] Therefore, in the period T6, the following data is generated. In this data, the term "M" in each of "edgec_f" and "edgec_r" indicates a masked bit.

[0339] data1 = 11_10000111_11110000

[0340] FLTR = 10000011_11111000

[0341] edge_f = -1000000_00000100

[0342] edge_r = -0000010_00000000

[0343] edges_f = -xxx1000_00000000

[0344] edges_r = -xxx0000_01000000

[0345] edgec_f[4:0] = M0000

[0346] edgec_r[4:0] = M0010

[0347] In the period T6, "1" is detected at "edges_r[6]" which is shifted one bit to the right from the middle position of "edges_r[9:5]". That is, since "edgec_r[1]" is "1", the "edgebit" value becomes "-1", and the sft value of the next period T7 returns from "3" to "2". Since "edgec_r[1]" is "1", the window cut-off circuit 1583 masks the lowest order bit (bit [0]) in the next period T7. That is, bits [4:1] of the middle edge detection range ("edgec_r[4:0]", "edgec_f[4:0]") are set to the edge detection range.

[0348] Therefore, in the period T7, the following data is generated.

[0349] data1 = 11_11110000_00001111

[0350] FLTR = 11111000_00000111

[0351] edge_f = -0000100_00000000

[0352] edge_r = -0000000_00000100

[0353] edges_f = -xx00001_00000000

[0354] edges_r = -xx00000_00000001

[0355] edgec_f[4:0] = 0100M

[0356] edgec_r[4:0] = 0000M

[0357] In the period T7, "1" is detected at "edges_f[8]" which is shifted one bit to the left from the middle position of "edges_f[9:5]". That is, since "edgec_f[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period T8 changes from "2" to "3" again.

[0358] Therefore, in the period T8, the following data is generated.

[0359] data1 = 00_00001111_11111000

[0360] FLTR = 00000111_11111100

[0361] edge_f = -0000000_00000010

[0362] edge_r = -0000100_00000000

[0363] edges_f = -xxx0000_00000000

[0364] edges_r = -xxx0000_10000000

[0365] edgec_f[4:0] = M0000

[0366] edgec_r[4:0] = M0010

[0367] In period T8, the middle edge is sampled at the same phase as in period T7. However, a "1" is detected at "edges_r[7]", which is the middle bit of "edges_r[9:5]". That is, since "edgec_r[2]" is "1", the "edgebit" value becomes "0", and the sft value of the next period T9 is unchanged and is "3".

[0368] Therefore, in period T9, the following data is generated.

[0369] data1 = 11_01111000_00000111

[0370] FLTR = 11111100_00000011

[0371] edge_f = -0000010_00000000

[0372] edge_r = -0000000_00000010

[0373] edges_f = -xxx0000_10000000

[0374] edges_r = -xxx0000_00000000

[0375] edgec_f[4:0] = 0010M

[0376] edgec_r[4:0] = 0000M

[0377] In the period T9, "1" is detected at "edges_f[6]" which is shifted one bit to the right from the middle position of "edges_f[9:5]". That is, since "edgec_f[1]" is "1", the "edgebit" value becomes "-1", and the sft value of the next period returns from "3" to "2" again.

[0378] The waveform in the case where the "H" period of the clock (clkup_p) contains the middle edge of the start bit is the same as that of Figure 19 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as that of Figure 19 is performed.

[0379] Figure 20 A waveform in the case where the "H" period of the clock (clkup_n) contains the middle edge of the start bit is shown. The right arrow of the Manchester code signal (mc_si) indicates that the edge is delayed by 1 / 8 of a period, and the left arrow thereof indicates that the edge returns to the original edge. The operations up to the period T4 are the same as those of Figure 18 . The period T5 is first affected by the jitter.

[0380] In the period T5, the following data is generated.

[0381] data1 = 00_00000011_10000111

[0382] FLTR = 00000001_11000011

[0383] edge_f = -0000000_00100000

[0384] edge_r = -0000001_00000001

[0385] edges_f = -xx0000_00001000

[0386] edges_r = -xx0000_01000000

[0387] edgec_f[4:0] = 00000

[0388] edgec_r[4:0] = 00010

[0389] In cycle T5, "1" is detected at "edges_r[6]" which is shifted one bit to the right from the middle position of "edges_r[9:5]". That is, since "edgec_r[1]" is "1", the "edgebit" value becomes "-1", and the sft value of the next cycle T6 changes from "2" to "1".

[0390] Therefore, in cycle T6, the following data is generated.

[0391] data1 = 11_10000111_11111100

[0392] FLTR = 10000011_11111110

[0393] edge_f = -1000000_00000001

[0394] edge_r = -0000010_00000000

[0395] edges_f = -×××1000_00000000

[0396] edges_r = -×××0001_00000000

[0397] edgec_f[4:0] = 0000M

[0398] edgec_r[4:0] = 1000M

[0399] In cycle T6, "1" is detected at "dges_r[8]" which is shifted one bit to the left from the middle position of "edges_r[9:5]". That is, since "edgec_r[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next cycle T7 returns from "1" to "2".

[0400] Therefore, in cycle T7, the following data is generated.

[0401] data1 = 11_11111100_00000011

[0402] FLTR = 11111110_00000001

[0403] edge_f = -1000001_00000000

[0404] edge_r = -0000000_00000001

[0405] edges_f = -×××0000_01000000

[0406] edges_r=-×××0000_00000000

[0407] edgec_f[4:0]=M0001

[0408] edgec_r[4:0]=M0000

[0409] In period T7, a "1" is detected at "edges_f[6]", which is shifted one bit to the right from the middle position of "edges_f[9:5]". That is, since "edgec_f[1]" is "1", the value of "edgebit" becomes "-1", and the sft value of the next period T8 changes from "2" to "1" again.

[0410] Therefore, the following data is generated in period T8.

[0411] data1 = 00_00000011_11111000

[0412] FLTR = 00000001_11111100

[0413] edge_f = -0000000_00000010

[0414] edge_r = -0000001_00000000

[0415] edges_f = -×000000_00000000

[0416] edges_r = -×000000_10000000

[0417] edgec_f[4:0]=0000M

[0418] edgec_r[4:0]=0010M

[0419] In period T8, the middle edge is sampled with the same phase as in period T7. However, a "1" is detected at "edges_r[7]", which is the middle bit of "edges_r[9:5]". That is, since "edgec_r[2]" is "1", the value of "edgebit" becomes "0", and the sft value of the next period T9 remains unchanged and is still "1".

[0420] Therefore, the following data is generated in period T9.

[0421] data1 = 11_01111000_00000111

[0422] FLTR = 11111100_00000011

[0423] edge_f = -0000010_00000000

[0424] edge_r = -0000000_00000010

[0425] edges_f = -x000001_00000000

[0426] edges_r = -x000000_00000000

[0427] edgec_f[4:0] = 1000M

[0428] edgec_r[4:0] = 0000M

[0429] In the period T9, "1" is detected at "edges_f[8]" which is one bit left from the middle position of "edges_f[9:5]". That is, since "edgec_f[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period returns from "1" to "2" again.

[0430] The waveform in the case where the middle edge of the start bit is contained in the "H" period of the clock (clkup_p) is the same as that of Figure 20 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as that of Figure 20 is performed.

[0431] Figure 21 The waveform in the case where the middle edge of the start bit is contained in the "H" period of the clock (clkup_n) is shown, in which the jitter leads by 1 / 4 of a bit period. The left arrow of the Manchester code signal (mc_si) indicates that the edge leads by 1 / 4, and the right arrow thereof indicates that the edge returns to the original edge. The operation until the period T4 is the same as that of Figure 18 . The period T5 is first affected by the jitter.

[0432] In the period T5, the following data is generated.

[0433] data1 = 00_00011111_10000111

[0434] FLTR = 00001111_11000011

[0435] edge_f = -0000000_00100000

[0436] edge_r = -0001000_00000010

[0437] edges_f = -xx0000_00001000

[0438] edges_r = -xx00010_00000000

[0439] edgec_f[4:0] = 00000

[0440] edgec_r[4:0] = 10000

[0441] In the period T5, "1" is detected at "edges_r[9]" which is shifted two bits to the left from the middle position of "edges_r[9:5]". That is, since "edgec_r[4]" is "1", the "edgebit" value becomes "+2", and the sft value of the next period T6 is temporarily changed from "2" to "4". Also, by adding "-1" to "3", the cdiv value is temporarily changed to "2", and the range is reduced to three periods of the clock (clkup_p) in the next period T6.

[0442] Therefore, in the period T6, the following data is generated.

[0443] data1 = 11_10000111_11100000

[0444] FLTR = 10000011_11110000

[0445] edge_f = -1000000_00001000

[0446] edge_r = -0000010_00000000

[0447] edges_f = -xxxxx100_00000000

[0448] edges_r = -xxxxx000_00100000

[0449] edgec_f[4:0] = M0000

[0450] edgec_r[4:0] = M0001

[0451] In the cycle T6, "1" is detected at "edges_r[5]" which is shifted two bits to the right from the middle position of "edges_r[9:5]". That is, since "edgec_r[0]" is "1", the "edgebit" value becomes "-2", and the sft value of the next cycle T7 is temporarily changed from "2" which is the original value to "0". Also, by adding "+1" to "3", the cdiv value is temporarily changed to "4", and the range of the next cycle T7 is increased to five cycles of the clock (clkup_p).

[0452] Therefore, in the cycle T7, the following data is generated.

[0453] data1 = 11_11111000_00000111

[0454] FLTR = 11111100_00000011

[0455] edge_f = -0000010_00000000

[0456] edge_r = -0000010_00000010

[0457] edges_f = -0000010_00000000

[0458] edges_r = -0000000_00000000

[0459] edgec_f[4:0] = 1000M

[0460] edgec_r[4:0] = 0000M

[0461] In the cycle T7, "1" is detected at "edges_f[9]" which is shifted two bits to the left from the middle position of "edges_f[9:5]". That is, since "edgec_f[4]" is "1", the "edgebit" value becomes "+2", and the sft value of the next cycle T8 is temporarily changed from "2" to "4". Also, by adding "-1" to "3", the cdiv value is temporarily changed to "2", and the range of the next cycle T8 is decreased to three cycles of the clock (clkup_p).

[0462] Therefore, in the cycle T8, the following data is generated.

[0463] data1 = 00_00011111_11111000

[0464] FLTR = 00001111_11111100

[0465] edge_f = -0000000_00100010

[0466] edge_r = -0001000_00000000

[0467] edges_f = -xxx0000_00000000

[0468] edges_r = -xxx0000_10000000

[0469] edgec_f[4:0] = M0000

[0470] edgec_r[4:0] = M0100

[0471] In the period T8, the middle edge is sampled at the same phase as the phase of the period T7. A "1" is detected at "edges_r[7]" which is the middle bit of "edges_r[9:5]". That is, since "edgec_r[2]" is "1", the "edgebit" value becomes "0", and the sft value of the next period T9 returns to "2" which is the original value. Also, the cdiv value becomes "3", and the range of the next period T9 returns to four periods of the clock (clkup_p).

[0472] Therefore, in the period T9, the following data is generated.

[0473] data1 = 11_11111110_00011110

[0474] FLTR = 11111111_00001111

[0475] edge_f = -0000000_10000000

[0476] edge_r = -0000000_00001000

[0477] edges_f = -xx00000_00100000

[0478] edges_r = -xx00000_00000010

[0479] edgec_f[4:0] = M0001

[0480] edgec_r[4:0] = M0000

[0481] In the cycle T9, "1" is detected at "edges_f[5]" which is shifted right by two bits from the middle position of "edges_f[9:5]". That is, since "edgec_f[0]" is "1", the "edgebit" value becomes "-2", and the sft value in the next cycle T10 is temporarily changed from "2" which is the original value to "0". Also, by adding "+1" to "3", the cdiv value is temporarily changed to "4", and the range of the next cycle T10 is increased to five cycles of the clock (clkup_p).

[0482] Therefore, in the cycle T10, the following data is generated.

[0483] data1 = 10_00011110_00000001

[0484] FLTR = 10001111_00000000

[0485] edge_f = -1000000_10000000

[0486] edge_r = -0001000_00000000

[0487] edges_f = -0000000_10000000

[0488] edges_r = -0001000_00000000

[0489] edgec_f[4:0] = 0010M

[0490] edgec_r[4:0] = 0000M

[0491] In the cycle T10, "1" is detected at "edges_f[7]" which is the middle bit of "edges_f[9:5]". That is, since "edgec_f[2]" is "1", the "edgebit" value becomes "0", and the sft value in the next cycle T11 returns to "2" which is the original value. Also, the cdiv value becomes "3", and the range of the next cycle T11 returns to four cycles of the clock (clkup_p).

[0492] where the "H" period of the clock (clkup_p) contains the middle edge of the start bit is the same as the waveform of Figure 21 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as in the cycle T9 is performed.Figure 21 The operation in the period T4 is the same as that of the operation.

[0493] Figure 22 A waveform in which the middle edge containing the start bit is delayed by 1 / 4 of a bit period at the "H" period of the clock (clkup_n) is shown. The right arrow of the Manchester encoded signal (mc_si) indicates that the edge is delayed by 1 / 4 of a period, and its left arrow indicates that the edge returns to the original edge. The operation until the period T4 is the same as that of the operation. Figure 18 The operation in the period T5 is the same as that of the operation.

[0494] In the period T5, the following data is generated.

[0495] data1 = 00_00000001_10000111

[0496] FLTR = 00000000_11000011

[0497] edge_f = -0000000_00100000

[0498] edge_r = -0001000_10000000

[0499] edges_f = -xx0000_00001000

[0500] edges_r = -xx0000_00100000

[0501] edgec_f[4:0] = 00000

[0502] edgec_r[4:0] = 00001

[0503] In the period T5, "1" is detected at "edges_r[5]" which is shifted right by two bits from the middle position of "edges_r[9:5]". That is, since "edgec_r[0]" is "1", the "edgebit" value becomes "-2", and the sft value of the next period T6 is temporarily changed from "2" to "0". Also, by adding "+1" to "3", the cdiv value temporarily becomes "4", and the range of the next period T6 is increased to five periods of the clock (clkup_p).

[0504] Therefore, in the period T6, the following data is generated.

[0505] data1 = 11_10000111_11111110

[0506] FLTR = 10000011_11111111 ​

[0507] edge_f = -1000000_00000000

[0508] edge_r = -0000010_00000000

[0509] edges_f = -1000000_00000000

[0510] edges_r = -0000010_00000000

[0511] edgec_f[4:0] = 0000M

[0512] edgec_r[4:0] = 1000M

[0513] In the period T6, "1" is detected at "edges_r[9]" which is shifted two bits to the right from the middle position of "edges_r[9:5]". That is, since "edgec_r[4]" is "1", the "edgebit" value becomes "+2", and the sft value of the next period T7 is temporarily changed from "2" to "4". Also, by adding "-1" to "3", the cdiv value is temporarily changed to "2", and the range is reduced to three periods of the clock (clkup_p) in the next period T7.

[0514] Therefore, in the period T7, the following data is generated.

[0515] data1 = 11_11111000_00000111

[0516] FLTR = 11111100_00000011

[0517] edge_f = -0000010_00000000

[0518] edge_r = -0000000_00000010

[0519] edges_f = -××××000_00100000

[0520] edges_r = -××××000_00000000

[0521] edgec_f[4:0] = M0001

[0522] edgec_r[4:0] = M0000

[0523] In the period T7, "1" is detected at "edges_f[5]" which is shifted two bits to the right from the middle position of "edges_f[9:5]". That is, since "edgec_f[0]" is "1", the "edgebit" value becomes "-2", and the sft value of the next period T8 is temporarily changed from "2" which is the original value to "0". Also, by adding "+1" to "3", the cdiv value is temporarily changed to "4", and the range of the next period T8 is increased to five periods of the clock (clkup_p).

[0524] Therefore, in the period T8, the following data is generated.

[0525] data1 = 10_00000001_11111000

[0526] FLTR = 00000000_11111100

[0527] edge_f = -0000000_00000010

[0528] edge_r = -0000000_10000000

[0529] edges_f = -0000000_00000010

[0530] edges_r = -0000000_10000000

[0531] edgec_f[4:0] = 0000M

[0532] edgec_r[4:0] = 0010M

[0533] In the period T8, the middle edge is sampled at the same phase as that of the period T7. "1" is detected at "edges_r[7]" which is the middle bit of "edges_r[9:5]". That is, since "edgec_r[2]" is "1", the "edgebit" value becomes "0", and the sft value of the next period T9 returns to "2" which is the original value. Also, the cdiv value becomes "3", and the range of the next period T9 returns to four periods of the clock (clkup_p).

[0534] Therefore, in the period T9, the following data is generated.

[0535] data1 = 11_11100001_11100000

[0536] FLTR = 11110000_11110000

[0537] edge_f = -0001000_00000000

[0538] edge_r = -0000000_10000000

[0539] edges_f = -xx00010_00000000

[0540] edges_r = -xx00000_00100000

[0541] edgec_f[4:0] = 10000

[0542] edgec_r[4:0] = 00001

[0543] In the period T9, "1" is detected at "edges_f[9]" which is shifted two bits to the left from the middle position of "edges_f[9:5]". That is, since "edgec_f[4]" is "1", the "edgebit" value becomes "+2", and the sft value of the next period T10 is temporarily changed from "2" to "4". Also, by adding "-1" to "3", the cdiv value is temporarily changed to "2", and the range is reduced to three periods of the clock (clkup_p) in the next period T10.

[0544] Therefore, in the period T10, the following data is generated.

[0545] data1 = 11_11100000_00011110

[0546] FLTR = 11110000_00001111

[0547] edge_f = -0001000_00000000

[0548] edge_r = -0000000_00001000

[0549] edges_f = -xxx000_10000000

[0550] edges_r = -xxx000_00000000

[0551] edgec_f[4:0] = M0100

[0552] edgec_r[4:0] = M0000

[0553] In the period T10, "1" is detected at "edges_f[7]" which is the middle bit of "edges_f[9:5]". That is, since "edgec_f[2]" is "1", the "edgebit" value becomes "0", and the sft value of the next period T11 returns to "2" which is the original value. Also, the cdiv value becomes "4", and the range of the next period T11 returns to four periods of the clock (clkup_p).

[0554] The waveform in the case where the "H" period of the clock (clkup_p) contains the middle edge of the start bit is the same as that of Figure 22 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as that of Figure 22 is performed.

[0555] Figure 23 The waveform is shown in which the jitter leads the bit period by 1 / 4 but changes by 1 / 8 during two periods in the case where the "H" period of the clock (clkup_n) contains the middle edge of the start bit. The left arrow of the Manchester coded signal (mc_si) indicates that the edge leads by 1 / 8 or 1 / 4 due to the jitter, and its right arrow indicates that the edge returns to the original edge by 1 / 8 or 1 / 4. The operation until the period T4 is the same as that of Figure 18 . The period T5 is first affected by the jitter.

[0556] In the period T5, the following data is generated.

[0557] data1 = 00_00001111_10011111

[0558] FLTR = 00000111_11001111

[0559] edge_f = -0000000_00100000

[0560] edge_r = -0000100_00001000

[0561] edges_f = -xx0000_00001000

[0562] edges_r = -xx0001_00000010

[0563] edgec_f[4:0] = 00000

[0564] edgec_r[4:0] = 01000

[0565] In the period T5, "1" is detected at "edges_r[8]" which is shifted one bit to the left from the middle position of "edges_r[9:5]". That is, since "edgec_r[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period T6 is changed from "2" to "3".

[0566] Therefore, in the period T6, the following data is generated.

[0567] data1 = 11_10011111_11111000

[0568] FLTR = 11001111_11111100

[0569] edge_f = -0100000_00000010

[0570] edge_r = -0001000_00000000

[0571] edges_f = -xx×0100_00000000

[0572] edges_r = -xx×0001_00000000

[0573] edgec_f[4:0] = M0000

[0574] edgec_r[4:0] = M1000

[0575] In the period T6, the determination is made with a second time 1 / 4 cycle of jitter. "1" is detected at "edges_r[8]" which is shifted one bit to the left from the middle position of "edges_r[9:5]". That is, since "edgec_r[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period T7 is changed from "3" to "4".

[0576] Therefore, in the period T7, the following data is generated.

[0577] data1 = 11_11111000_00011111

[0578] FLTR = 11111100_00001111

[0579] edge_f = -0000010_00000000

[0580] edge_r = -0000000_00001000

[0581] edges_f = -xxx0000_00100000

[0582] edges_r = -xxx0000_00000000

[0583] edgec_f [4:0] = M0001

[0584] edgec_r [4:0] = M0000

[0585] In the period T7, the determination is made with one return to the first 1 / 8 period. The "1" is detected at "edges_f [5]" which is shifted two bits to the right from the middle position of "edges_f [9:5]". That is, since "edgec_f [0]" is "1", the "edgebit" value becomes "-2", and the sft value of the next period T8 is temporarily changed from "4" to "2". Also, by adding "+1" to "3", the cdiv value temporarily becomes "4", and the range of the next period T8 is increased to five periods of the clock (clkup_p).

[0586] Therefore, in the period T8, the following data is generated.

[0587] data1 = 00_00001111_11110000

[0588] FLTR = 00000111_11111000

[0589] edge_f = -0000000_00000100

[0590] edge_r = -0000100_00000000

[0591] edges_f = -xx0000_00000001

[0592] edges_r = -xx0001_00000000

[0593] edgec_f [4:0] = 0000M

[0594] edgec_r [4:0] = 0100M

[0595] In cycle T8, the determination is made with the second 1 / 8 cycle returned. A "1" is detected at "edges_r[8]" which is shifted one bit to the left from the middle position of "edges_r[9:5]". That is, since "edgec_r[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next cycle T9 is changed from "4" which is the original value to "5". Also, the cdiv value becomes "3", and the range of the next cycle T9 returns to four cycles of the clock (clkup_p).

[0596] Therefore, in cycle T9, the following data is generated.

[0597] data1 = 11_11000001_11100000

[0598] FLTR = 11100000_11110000

[0599] edge_f = -0010000_00001000

[0600] edge_r = -0000000_10000000

[0601] edges_f = -×××××00_10000000

[0602] edges_r = -×××××00_00000100

[0603] edgec_f[4:0] = M0100

[0604] edgec_r[4:0] = M0000

[0605] In cycle T9, a "1" is detected at "edges_f[7]" which is the middle position of "edges_f[9:5]". That is, since "edgec_f[2]" is "1", the "edgebit" value becomes "0", and the sft value of the next cycle T10 is not changed and remains "5". The cdiv value is not changed and remains "3", the cycle T10 is not changed, and remains to correspond to four cycles of the clock (clkup_p).

[0606] Therefore, in cycle T10, the following data is generated.

[0607] data1 = 11_11100000_00011110

[0608] FLTR = 11110000_00001111

[0609] edge_f = -0001000_00000000

[0610] edge_r = -0000000_00001000

[0611] edges_f = -xxxxx00_01000000

[0612] edges_r = -xxxxx00_00000000

[0613] edgec_f[4:0] = M0010

[0614] edgec_r[4:0] = M0000

[0615] In the period T10, "1" is detected at "edges_f[6]" which is one bit right of the middle position of "edges_f[9:5]". That is, since "edgec_f[1]" is "1", the "edgebit" value becomes "-1", and the sft value of the next period T11 is changed from "5" to "4".

[0616] The waveform in the case where the "H" period of the clock (clkup_p) contains the middle edge of the start bit is the same as that of Figure 23 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as that of Figure 23 is performed.

[0617] Figure 24 The waveform is shown in the case where the "H" period of the clock (clkup_n) contains the middle edge of the start bit, the jitter delays the 1 / 4 of the bit period but changes 1 / 8 period during two periods. The right arrow of the Manchester coded signal (mc_si) indicates that the edge is delayed by 1 / 8 or 1 / 4 due to the jitter, and its left arrow indicates that the edge returns 1 / 8 or 1 / 4. The operation until the period T4 is the same as that of Figure 18 . The period T5 is first affected by the jitter.

[0618] In the period T5, the following data is generated.

[0619] data1 = 00_00000011_10000001

[0620] FLTR = 00000001_11000000

[0621] edge_f = -0000000_00100000

[0622] edge_r = -0000001_00000000

[0623] edges_f = -xx00000_00001000

[0624] edges_r = -xx00000_01000000

[0625] edgec_f[4:0] = 00000

[0626] edgec_r[4:0] = 00010

[0627] In the period T5, the determination is made with one return to the first 1 / 4 period. The "1" is detected at "edges_r[6]" which is shifted one bit to the right from the middle position of "edges_r[9:5]". That is, since "edgec_r[1]" is "1", the "edgebit" value becomes "-1", and the sft value of the next period T6 is changed from "2" to "1".

[0628] Therefore, in the period T6, the following data is generated.

[0629] data1 = 11_10000001_11111000

[0630] FLTR = 11000000_11111100

[0631] edge_f = -0100000_00000010

[0632] edge_r = -0000000_10000000

[0633] edges_f = -x010000_00000001

[0634] edges_r = -x000000_01000000

[0635] edgec_f[4:0] = 0000M

[0636] edgec_r[4:0] = 0001M

[0637] In the period T6, determination is made with the edge delayed by a second 1 / 4 period. A "1" is detected at "edges_r[6]" which is shifted one bit to the right from the middle position of "edges_r[9:5]". That is, since "edgec_f[1]" is "1", the "edgebit" value becomes "-1", and the sft value of the next period T7 changes from "1" to "0".

[0638] Therefore, in the period T7, the following data is generated.

[0639] data1 = 11_11111000_00000001

[0640] FLTR = 11111100_00000000

[0641] edge_f = -0000010_00000000

[0642] edge_r = -0000000_00000000

[0643] edges_f = -0000010_00000000

[0644] edges_r = -0000000_00000000

[0645] edgec_f[4:0] = 1000M

[0646] edgec_r[4:0] = 0000M

[0647] In the period T7, determination is made with the return of a 1 / 8 period. A "1" is detected at "edges_f[9]" which is shifted two bits to the left from the middle position of "edges_f[9:5]". That is, since "edgec_f[4]" is "1", the "edgebit" value becomes "+2", and the sft value of the next period T8 temporarily changes from "0" to "2". Also, by adding "-1" and "3", the cdiv value temporarily becomes "2", and the range of the next period T10 is reduced to three periods of the clock (clkup_p).

[0648] Therefore, in the period T8, the following data is generated.

[0649] data1 = 00_00000001_11111100

[0650] FLTR = 00000000_11111110

[0651] edge_f = -0000000_00000001

[0652] edge_r = -0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

[0653] edges_f = -x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[0654] edges_r = -x x 0 0 0 0 0 0 0 0 0 0 0 0 0 1

[0655] edgec_f[4:0] = M 0 0 0 0

[0656] edgec_r[4:0] = M 0 0 0 1

[0657] In the period T8, determination is made with return to the next 1 / 4 period. A "1" is detected at "edges_r[5]" which is shifted two bits to the right from the middle position of "edges_r[9:5]". That is, since "edgec_r[0]" is "1", the "edgebit" value becomes "-2", and the sft value of the next period T9 is temporarily changed from "0" which is the original value to "-2". Also, by adding "+1" to "3", the cdiv value is temporarily changed to "4", and the range of the next period T9 is increased to five periods of the clock (clkup_p).

[0658] Therefore, in the period T9, the following data is generated.

[0659] data1 = 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0

[0660] FLTR = 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1

[0661] edge_f = -0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

[0662] edge_r = -0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0

[0663] edges_f = -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[0664] edges_r = -0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

[0665] edgec_f[4:0] = 0 1 0 0 M

[0666] edgec_r[4:0] = 0 0 0 0 M

[0667] In the period T9, "1" is detected at "edges_f[8]" which is shifted one bit to the left from the middle position of "edges_f[9:5]". That is, since "edgec_f[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period T10 is changed from "0" which is the original value to "1". Also, the cdiv value becomes "3", and the range of the next period T10 returns to four periods of the clock (clkup_p).

[0668] Therefore, in the period T10, the following data is generated.

[0669] data1 = 00_01111000_00000111

[0670] FLTR = 00111100_00000011

[0671] edge_f = -0000010_00000000

[0672] edge_r = -0000000_00000010

[0673] edges_f = -x000001_00000000

[0674] edges_r = -x000000_00000001

[0675] edgec_f[4:0] = M1000

[0676] edgec_r[4:0] = M0000

[0677] In the period T10, "1" is detected at "edges_f[8]" which is shifted one bit to the left from the middle position of "edges_f[9:5]". That is, since "edgec_f[3]" is "1", the "edgebit" value becomes "+1", and the sft value of the next period T11 is changed from "1" to "2".

[0678] where the "H" period of the clock (clkup_p) contains the same waveform as that in the case where the middle edge of the start bit is detected Figure 24 Although the waveforms of the odd bits and the even bits of "sin[*]" have been switched, the order in the sampled "data1" is corrected by the clock (clk1) whose timing is the same as that of the clock (clkup_p). After "data1", the same operation as that of Figure 24 is performed.

[0679] Compared with the first working example and the second working example, the third working example includes only the shift flip-flop 151a as a circuit operating at the high-speed sampling clock, and does not include a calculator for addition, shift, comparison, and the like operating at the high-speed sampling clock. Thus, operation at a frequency and a baud rate higher than those of the first working example and the second working example is realized. In other words, at the same frequency and baud rate, operation can be realized at lower power by inexpensive manufacturing technology without microfabrication.

[0680] (Fourth Working Example)

[0681] Figure 25 is a block diagram showing a part of the configuration of the edge recognition circuit according to the fourth working example. Figure 26 is a block diagram showing a part of the configuration of the edge recognition circuit according to the fourth working example. Figure 27 is Figure 26 a truth table of the correction circuit shown in

[0682] The configuration of the decoder 150 according to the fourth working example is the same as that of the third working example except for the edge recognition circuit 158. Thus, the explanation of the synchronization circuit (SYNC) 151, the noise filter (FLTR) 152, the edge detection circuit (EDC) 153, and the clock generation circuit (CG) 157 is omitted.

[0683] The edge recognition circuit 158 according to the fourth working example includes the shift circuit (SHFTR) 1581 and the shift circuit 1582, and the window cut circuit (WNDW) 1583 and the window cut circuit 1584. The shift circuit 1581 and the shift circuit 1582 are the same in configuration as the shift circuit 1581 and the shift circuit 1582 of the third working example and perform the same operation as the configuration and operation of the shift circuit 1581 and the shift circuit 1582 of the third working example.

[0684] Although the window cut circuit 1583 is explained below, the operation of the window cut circuit 1584 is similar to that of the window cut circuit 1583. The window cut circuit 1583 extracts 7 bits from "edges_r[n:0]" and sets "edgec_r[7:0]", that is, the middle edge detection range. The middle edge detection range according to the fourth working example is wider than that of the third working example. The window cut circuit 1583 corrects the middle edge detection range (edgec_r[6:0]) based on the middle edge position (edgec_r) of the previous cycle.

[0685] More specifically, if the intermediate edge position (edgec_r) of the previous cycle is in the high-order bit of the intermediate edge detection range (edgec_r[6:0]), the window cut-off circuit 1583 masks the high-order bit (bit [5] or bit [6]). In this process, the high-order bit is bit [4], bit [5], or bit [6]. That is, bits [4:0] of the intermediate edge detection range (edgec_r[6:0]) are set to the edge detection range. If the intermediate edge position (edgec_r) of the previous cycle is in the low-order bit of the intermediate edge detection range (edgec_r[6:0]), the window cut-off circuit 1583 masks the low-order bit (bit [0] or bit [1]) of the intermediate edge detection range (edgec_r[6:0]). In this process, the low-order bit is bit [0], bit [1], or bit [2]. That is, bits [6:2] of the intermediate edge detection range (edgec_r[6:0]) are set to the edge detection range. If the intermediate edge position (edgec_r) of the previous cycle is in another bit (bit [3]), the bit to be masked is unchanged, in other words, the bit to be masked is set to be the same as the mask bit of the previous cycle.

[0686] As shown in FIG. 15B, the edge recognition circuit 158 further includes a data detection circuit 1586. The data detection circuit 1586 is identical in configuration to the data detection circuit 1586 according to the third working example, and performs the same operation as the configuration and operation of the data detection circuit 1586 according to the third working example. Figure 25 As shown in FIG. 15B, the edge recognition circuit 158 further includes a data detection circuit 1586. The data detection circuit 1586 is identical in configuration to the data detection circuit 1586 according to the third working example, and performs the same operation as the configuration and operation of the data detection circuit 1586 according to the third working example.

[0687] Figure 26 As shown in FIG. 15B, the edge recognition circuit 158 further includes a shift amount generation circuit 1587 and a clock control circuit 1588.

[0688] The shift amount generation circuit 1587 includes a flip-flop 1587a that stores an initial shift value (i_sft[*]) at the start of a frame, and a flip-flop 1587d that stores a correction shift value (c_sft[*]). When the first falling edge in a frame is detected, "edgef_f[4:0]" contains "1". This is set as the initial value, and the bit value in which "1" is present in "edgef_f[4:0]" is input to the flip-flop 1587a. That is, the initial value of i_sft[*] is the phase difference between the clock superimposed on the Manchester encoded signal (mc_si) at the start of a frame and the clock (clk1) having the same frequency and generated in the decoder 150 at the start of a frame.

[0689] The correction shift value (c_sft[*]) is a correction value at the time of receiving a frame. An adder 1587c calculates an sft[*] value indicating the shift amount by adding the correction shift value (c_sft[*]) to the initial shift value (i_sft[*]) at the start of a frame. ​

[0690] The shift amount generating circuit 1587 further includes a correction circuit 1587e. The correction circuit 1587e has a terminal "D" into which a shift value of the previous cycle (a correction shift value) is input, and terminals "IN(-3, -2, -1, 0, +1, +2, +3)" into which "edgec_r[6:0]" or "edgec_f[6:0]" is input. "edgec_r[6:0]" or "edgec_f[6:0]" is referred to as an edge correction input, and "1" is input to any one of the seven terminals IN. The correction circuit 1587e further has a terminal "Ql" from which a next shift value (a correction shift value) is output, and a terminal "Q2" from which a counter shift value is output. The correction circuit 1587e uses data input to the terminals IN and the terminal D, and outputs data from the terminal Ql and the terminal Q2 in accordance with a truth table shown in Table 1. Figure 20

[0691] That is, in a case where the clock (clkup_p / clkup_n) of 800 MHz is shifted by one cycle due to jitter, if the previous uncorrected data (c_sft[*] = 0), "-1" or "+1" is considered to be input to the terminal IN, and "0" is input to the terminal D. At this time, "-1" or "+1" is output from the terminal Ql. Therefore, the next correction shift value (c_sft[*]) becomes "-1" or "+1". If the data has been corrected (c_sft[*] = -1 or +1), "-1" or "+1" is considered to be input to the terminal IN, and "-1" or "+1" is input to the terminal D. At this time, "0" is output from the terminal Ql. Therefore, the next correction shift value (c_sft[*]) becomes "0" (meaning no correction).

[0692] Similar to the clock control circuit 1588 according to the third working example, the clock control circuit 1588 generates a signal (cdivc) for controlling a division ratio of the clock generating circuit 157. Normally, a division ratio of the frequency (400 MHz) of the clock (clkup_p) to the baud rate (100 MHz) is set. That is, in a case of "division by four", the cdiv value becomes "3". However, the clock control circuit 1588 temporarily increases / decreases the value based on the counter correction value input from the terminal Ql of the correction circuit 1587e.

[0693] ​In this process, if the sign of the edge correction input and the previous correction shift value are the same as each other, this means that the clock (clkl) is shifted by one period of 400 MHz, and therefore the range of the clock (clkl) is temporarily increased / decreased by one period of the clock (clkup_p) of 400 MHz. This control is based on the counter correction value input to the terminal "cor" of the clock control circuit 1588, and the cdiv value is generated by adding the counter correction value to the value determined by the division ratio ("3" in the case of "quadruple division").

[0694] In the case of shifting the clock (clkup_p / clkup_n) by two periods of 800 MHz, only the cdiv value is adjusted, without changing the c_sft[*] value. In the case of shifting the clock (clkup_p / clkup_n) by three periods of 800 MHz, both the cdiv value and the c_sft[*] value are adjusted.

[0695] Note that, similarly to the third working example, the clock control circuit 1588 includes a two-bit register UBRS[l:0]. In the register UBRS[l:0], "quadruple division" (8 periods), "quintuple division" (10 periods), and "sextuple division" (12 periods) can be set as the division ratio. In the case of "quintuple division", the cdiv value is normally changed to "4", and the cdiv value is adjusted by adding the counter correction value. In the case of "sextuple division", the cdiv value is normally changed to "5", and the cdiv value is adjusted by adding the counter correction value.

[0696] Similarly to the third working example, the clock generation circuit 157 generates the clock (clkl) by dividing the frequency of the clock (clkup_p) by the cdiv value.

[0697] Reference Figure 28 The operation of the decoder according to the fourth working example is explained. Figure 28 is a timing chart illustrating the operation of the decoder according to the fourth working example. Figure 18 to Figure 24 Each of the charts in is a timing chart illustrating the operation according to the third working example, and the same operation is also performed in the fourth working example.

[0698] Figure 28 A waveform in the case where the transmission frequency is slightly later than the reception frequency is illustrated. The rightward arrow of the Manchester encoded signal (mc_si) indicates a waveform delayed by the slightly later transmission frequency.

[0699] The first edge is detected at the sampling in the period T2, and the following data is generated in the period T2.

[0700] data1 = 11_11111111_11111000

[0701] FLTR = 11111111_11111100

[0702] edge_f = -0000000_00000010

[0703] edge_r = -0000000_00000000

[0704] At the first sampling time, the value of the flip-flop 1587a is cleared to "0" by an input signal to a not-shown clear terminal of the flip-flop 1587a, and the i_sft value becomes "0". Also, the value of the flip-flop 1587d is cleared to "0" by an input signal to a not-shown clear terminal of the flip-flop 1587d, and the c_sft value becomes "0". Therefore, since the sft value is "0", "edge_f = edges_f" is established. The bit at which the edge is detected at this time is "edges_f[1]", and therefore, the detected bit of "edge_f" becomes "2". Therefore, "2" is set as the initial i_sft value at the flip-flop 1587a. Also, the c_sft value is not changed and is "0". Therefore, the sft value of the next cycle T3 becomes "2". "data2_pre" of the cycle T2 corresponds to the edge detection after "passive" of the cycle Tl, and therefore, becomes "passive".

[0705] In the cycle after the cycle T3, the shift circuit 1581 and the shift circuit 1582 generate "edge_f" and "edge_r" by shifting "edges_f" and "edges_r", respectively, by the sft value. If the sft value is positive, the shift circuit 1581 and the shift circuit 1582 shift them to the right; and if the sft value is negative, shift them to the left. The shift amount generation circuit 1587 generates the sft value of the next cycle by adding the c_sft value of the previous cycle to the i_sft value of the previous cycle. The intermediate edge detection range (edgec_r[6:0] and edgec_f[6:0]) corresponds to edges_r[10:4] and edges_f[10:4].

[0706] For example, in the cycle T3, the following data is generated.

[0707] data1 = 11_11111000_01111000

[0708] FLTR = 11111100_00111100

[0709] edge_f = -0000010_00000010

[0710] edge_r = -0000000_00100000

[0711] edges_f = -xx00000_10000000

[0712] edges_r = -xx00000_00001000

[0713] edgec_f [6:0] = 0001000

[0714] edgec_r [6:0] = 0000000

[0715] In the period T3, "edges_f [7]" which is the middle position of "edges_f [10:4]" is "1". That is, since "edgec_f [3]" is "1" and the c_sft value of the previous period T2 is "0", "c_sft = 0" is established based on the truth table shown in Figure 27 Since "1" is detected in "edges_f", the data_l value becomes "1", the data2_pre value becomes "1", and the data2 value of the next period T4 becomes "1".

[0716] The period T5 is first affected by the delay. In the period T5, the following data is generated.

[0717] data1 = 00_00000011_11000111

[0718] FLTR = 00000011_11000001

[0719] edge_f = -0000000_00100000

[0720] edge_r = -0000001_00000001

[0721] edges_f = -xx00000_00001000

[0722] edges_r = -xx00000_01000000

[0723] edgec_f [6:0] = 0000000

[0724] edgec_r [6:0] = 0000100

[0725] In the period T5, "edges_r [6]" which is shifted one bit to the right from the middle position of "edges_r [10:4]" is "1". That is, "edgec_r [2]" is "1" and the c_sft value of the previous period T4 is "0", and therefore, based on the truth table shown in Figure 27According to the truth table shown in FIG. 16, the c_sft value becomes "-1". Since the i_sft value is "2", the sft value is changed from "2" to "1" in the next period T6. Since "edgec_r[3]" is "1", the window cut-off circuit 1583 masks the lowest order bits (bit[0] and bit[1]) in the next period T6. That is, bit[6:2] of the intermediate edge detection range ("edgec_r[6:0]", "edgec_f[6:0]") is set to the edge detection range.

[0726] Accordingly, in the period T6, the following data is generated.

[0727] data1 = 11_11000101_11111110

[0728] FLTR = 11100001_11111111

[0729] edge_f = -0100000_00000000

[0730] edge_r = -0000001_00000000

[0731] edges_f = -x010000_00000000

[0732] edges_r = -x000000_10000000

[0733] edgec_f[6:0] = 00000MM

[0734] edgec_r[6:0] = 00010MM

[0735] In the period T6, "edges_r[7]" which is the intermediate position of "edges_r[10:4]" is "1". That is, "edgec_r[3]" is "1", the c_sft value of the previous period T5 is "-1", and therefore, based on Figure 27 According to the truth table shown in FIG. 16, the c_sft value becomes "-1". Since the i_sft value is "2", the sft value is changed from "2" to "1" in the next period T6. Since "edgec_r[3]" is "1", the window cut-off circuit 1583 masks the lowest order bits (bit[0] and bit[1]) in the next period T6. That is, bit[6:2] of the intermediate edge detection range ("edgec_r[6:0]", "edgec_f[6:0]") is set to the edge detection range.

[0736] Accordingly, in the period T6, the following data is generated.

[0737] data1 = 01_11111110_00000001

[0738] FLTR = 11111111_00000000

[0739] edge_f = -0000001_00000000

[0740] edge_r = -0000000_00000000

[0741] edges_f = -x010000_10000000

[0742] edges_r = -x000000_00000000

[0743] edgec_f[6:0] = 00010MM

[0744] edgec_r[6:0] = 00000MM

[0745] In cycle T7, "edges_f[7]" which is the middle position of "edges_f[10:4]" is "1". That is, "edgec_f[3]" is "1", the c_sft value of the previous cycle T6 is "-1", and therefore, based on the truth table shown in Table 1, the c_sft value becomes "-1". Since the i_sft value is "2", the sft value of the next cycle T8 does not change and is "1". Figure 27

[0746] Therefore, in cycle T8, the following data is generated.

[0747] data1 = 10_00000001_11111111

[0748] FLTR = 00000000_11111111

[0749] edge_f = -0000000_00000000

[0750] edge_r = -0000000_10000000

[0751] edges_f = -x010000_00000000

[0752] edges_r = -x000000_01000000

[0753] edgec_f[6:0] = 00000MM

[0754] edgec_r[6:0] = 00001MM

[0755] In cycle T8, "edges_r[6]" which is shifted one bit to the right from the middle position of "edges_r[10:4]" is "1". That is, "edgec_r[2]" is "1", the c_sft value of the previous cycle T7 is "-1", and therefore, based on the truth table shown in Table 1, the c_sft value becomes "-1". Since the i_sft value is "2", the sft value of the next cycle T9 does not change and is "1". Figure 27 ​The c_sft value becomes "0" as shown in the truth table. Since the i_sft value is "2", the sft value is changed from "1" to "2" for the next period T9. Further, the c_sft value of the previous period T7 is "-1", and thus, based on the truth table shown in Table 2, the counter correction value becomes "+1". That is, by adding "+1" to "3", the cdiv value becomes "4", the range of the period T8 is increased to five periods of the clock (clkup_p), and the period of the clock (clk1) is temporarily extended. Figure 27 The c_sft value becomes "0" as shown in the truth table. Since the i_sft value is "2", the sft value is changed from "1" to "2" for the next period T9. Further, the c_sft value of the previous period T7 is "-1", and thus, based on the truth table shown in Table 2, the counter correction value becomes "+1". That is, by adding "+1" to "3", the cdiv value becomes "4", the range of the period T8 is increased to five periods of the clock (clkup_p), and the period of the clock (clk1) is temporarily extended.

[0756] In the third working example, if baud rate tolerance (i.e., a difference between a reception frequency and a transmission frequency) occurs, the sft [*] value is continuously increased / decreased, and thus, resources for supporting the continuity are required. The baud rate tolerance occurs in a case where the frequency between the clock superimposed on the Manchester coded signal (mc_si) and the clock (clk1) having the same frequency and generated in the decoder does not match completely. In the fourth working example, the correction value of the shift value is only ±1. Thus, even if the baud rate tolerance occurs between the reception side and the transmission side, it is only necessary to prepare the sft [*] value and the c_sft [*] value in accordance with the number of samples per period, regardless of the frame length. Thus, the fourth working example does not require resources depending on the frame length, and thus, compared to the third working example, it is possible to support the operation by using the least resources.

[0757] In the above, the application of the present application made by the inventor has been specifically described based on the embodiments and working examples. However, it goes without saying that the application of the present application is not limited to the foregoing embodiments and working examples, and various modifications can be made.

[0758] For example, the embodiments and working examples have been explained in a case where the logic value of the Manchester coded signal is "1" when shifted from a high potential to a low potential in one time slot and is "0" when shifted from a low potential to a high potential in one time slot. However, the embodiments and working examples are also applicable to a Manchester coded signal whose logic value is "0" when shifted from a high potential to a low potential in one time slot or whose logic value is "1" when shifted from a low potential to a high potential in one time slot.

Claims

1. A semiconductor device comprising: data receiving circuitry configured to receive data, the data including first data and second data, the first data being received at a first time, the second data being received at a second time; and edge identifying circuitry configured to: measure a first period taken from the reception of the first data to the reception of the second data; determine, based on the measured first period, a data detection range within which an edge contained in the second data received by the data receiving circuitry is to be detected; and detect the edge contained in the determined data detection range, wherein the data received by the data receiving circuitry further includes third data, wherein the edge identifying circuitry is configured to determine, based on the first period and a predetermined interval, a data detection range within which a data detection range of an edge contained in the third data is detected, and wherein the edge identifying circuitry is configured to determine the predetermined interval based on a value of a data period and a value of a jitter of data received by the data receiving circuitry.

2. The semiconductor device according to claim 1, wherein the first data, the second data, and the third data are sequentially received by the data receiving circuitry in this order.

3. The semiconductor device according to claim 2, wherein when the first period is shorter than the predetermined interval, the edge identifying circuitry is configured to set the data detection range to a range from the second time to a third time if the first period is shorter than the predetermined interval, and wherein the third time is later than a time of the first period after the second time.

4. The semiconductor device according to claim 3, wherein the edge identifying circuitry is configured to set a start time of the data detection range to a period from the second time and longer than the first period.

5. The semiconductor device according to claim 2, wherein when the first period is longer than the predetermined interval, the edge identifying circuitry is configured to set the data detection range to a range from the second time to a fourth time if the first period is longer than the predetermined interval, and wherein the fourth time is earlier than a time of the first period after the second time.

6. The semiconductor device according to claim 5, wherein the edge identifying circuitry is configured to set a start time of the data detection range to a period shorter than the first period counted from the second time.

7. The semiconductor device according to claim 2, wherein the edge identifying circuitry is configured to not change the data detection range if the first period is equal to the predetermined interval.

8. The semiconductor device according to claim 1, wherein the data received by the data receiving circuitry is an asynchronous Manchester encoded signal.

9. The semiconductor device according to claim 1, wherein the edge identifying circuitry includes a counter, and wherein the counter is configured to be triggered by an intermediate edge serving as an edge indicating a data value of an edge contained in the data received by the data receiving circuit to measure a time taken for the reception of the first data to the reception of the second data.

10. The semiconductor device according to claim 1, wherein the edge identification circuit is configured to output an error when a plurality of edges are detected within a range in which an edge is detected, if a range of a first edge detection or a previous edge detection is not corrected.

11. The semiconductor device according to claim 10, further comprising: a receiving circuit having a reception buffer, wherein the edge identification circuit decodes and outputs received data, and wherein the receiving circuit is configured to not update the reception buffer by the output data from the edge identification circuit if the error is received.

12. A semiconductor device comprising: a data receiving circuit configured to receive an asynchronous Manchester coded signal; and an edge identification circuit configured to set an edge detection range in which an edge contained in the asynchronous Manchester coded signal received by the data receiving circuit is detected, wherein the edge identification circuit is configured to set a detection range of an edge of a next cycle based on a detection position of an edge of a previous cycle, and wherein the edge identification circuit is configured to change the detection range of the edge of the next cycle by temporarily changing a number of samples per bit when a correction in a delay direction continues at a time of detection of a plurality of consecutive edges, or when a correction in an advance direction continues at the time of the detection of the plurality of consecutive edges.

13. The semiconductor device according to claim 12, wherein the edge identification circuit is configured to change the detection range of the edge of the next cycle by temporarily changing a number of samples per bit when the correction in the delay direction continues for a certain time without the correction in the advance direction at the time of the detection of the plurality of consecutive edges, or when the correction in the advance direction continues for a certain time without the correction in the delay direction at the time of the detection of the plurality of consecutive edges.

14. The semiconductor device according to claim 12, wherein the data receiving circuit comprises: a shift register configured to sample input data at a sampling period; a clock generation circuit having a counter synchronized with a clock used to sample the edge; a data register configured to store the sampled input data of the shift register in parallel based on a clock generated by the clock generation circuit; and an edge detection circuit configured to detect an edge based on an output of the data register, wherein the edge identification circuit comprises: a shifter configured to shift an output of the edge detection circuit; and a window cut-off circuit configured to cut off data within an edge detection range from an output of the shifter, and ​ wherein the edge recognition circuit is configured to set a shift number of the shifter and a cut-off range of the window cut-off circuit based on a detected position of an edge of a previous cycle.

15. The semiconductor device according to claim 14, wherein the edge recognition circuit is configured to temporarily change a number of samples per bit by setting a period of a clock generated by the clock generation circuit based on the detected position of the edge of the previous cycle.

16. A method of processing data, comprising: receiving first data; receiving second data; measuring a time taken from the receiving of the first data to the receiving of the second data; and determining a data detection range in which to detect an edge contained in third data received later based on the measured time, wherein the first data, the second data, and the third data are sequentially received in this order, wherein no change to the data detection range is set, a lead correction is set for setting an end of the data detection range to be earlier, or a lag correction is set for setting a start of the data detection range to be later.

17. The method according to claim 16, wherein if the lead correction is performed on a previous cycle, a data detection range in a lead direction is shortened in a next cycle.

18. The method according to claim 17, wherein if the lag correction is performed on the previous cycle, a data detection range in a lag direction is shortened in the next cycle.

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