A Fractional Frequency Division Ratio Phase-Locked Loop

Abstract

The present invention discloses a fractional frequency division ratio phase-locked loop, including: a voltage-controlled oscillator, providing multiple oscillation clock signals of different phases; a fractional frequency divider, including: a multi-modulus frequency divider, connected to the voltage-controlled oscillator to receive a first oscillation clock signal and provide a first frequency-divided clock signal; a phase rotator, sampling the first frequency-divided clock signal based on multiple oscillation clock signals to obtain multiple sampling signals; and a phase interpolator, receiving two sampling signals with adjacent phases as a first threshold signal and a second threshold signal, performing linear interpolation between the first threshold signal and the second threshold signal to obtain a second frequency-divided clock signal, and the operating frequency of the phase interpolator is lower than the operating frequency of the voltage-controlled oscillator. Based on the phase rotator and the phase interpolator, the first frequency-divided clock signal provided by the multi-modulus frequency divider is divided to obtain a fractional frequency divider with higher resolution and higher linearity, thereby reducing the quantization noise of the loop.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to an ultra-fine fractional frequency division ratio phase locked loop technology. Background Art

[0002] FPGA (Field Programmable Gate Array) is a semi-custom integrated circuit in the field of ASIC (Application Specific Integrated Circuit). Due to its rich wiring resources, reprogrammability and high integration, FPGA has been widely used in the field of digital circuits. However, the spectrum components of digital signals and clock signals in FPGA contain high-order harmonics. The signal itself and its multiple harmonics will generate electromagnetic interference (EMI) inside the electronic system and between systems. At present, it is often necessary to design a spread spectrum clock generation circuit inside the FPGA to modulate the frequency of the clock signal within a certain frequency range, thereby causing the frequency of the clock signal to jitter and reduce electromagnetic interference (EMI).

[0003] Most of the spread spectrum clock generation circuits are based on PLL (Phase-locked Loop). In the spread spectrum clock generation circuit or phase-locked loop, a delta-sigma modulator is often used for frequency modulation. The waveform modulated by the delta-sigma modulator is similar to the analog signal but has distortion. This distortion is called quantization noise in the circuit. In order to reduce the quantization noise caused by the delta-sigma modulator, technologies such as increasing the reference clock frequency, digital-to-analog converter compensation, finite impulse response filtering, and fractional dividers are often used to suppress the quantization noise. For the fractional divider technology, if the divider accuracy is not high, the effect of suppressing the quantization noise is not good. Summary of the invention

[0004] In order to solve the problems existing in the above-mentioned prior art, the present invention proposes an ultra-fine fractional frequency division ratio phase-locked loop technology by combining a phase rotator and a phase interpolator, so that the quantization noise is very small and may be completely submerged in the loop white noise. The significant reduction in quantization noise brings many benefits, making it possible to increase the bandwidth of the phase-locked loop, improve the performance of the entire loop, and even remove the delta-sigma modulator in the fractional frequency division phase-locked loop.

[0005] According to an embodiment of the present invention, a fractional frequency division ratio phase-locked loop is provided, comprising: a voltage-controlled oscillator, providing a plurality of oscillation clock signals with different phases; and a fractional frequency divider, wherein the fractional frequency divider comprises: a multi-modulus frequency divider, connected to the voltage-controlled oscillator to receive a first oscillation clock signal and provide a first frequency-divided clock signal; a phase rotator, respectively connected to the voltage-controlled oscillator and the multi-modulus frequency divider, sampling the first frequency-divided clock signal based on the plurality of oscillation clock signals and obtaining a plurality of sampling signals; and a phase interpolator, receiving two sampling signals with adjacent phases and using them as a first threshold signal and a second threshold signal, so as to perform linear interpolation between the first threshold signal and the second threshold signal according to a control word to obtain a second frequency-divided clock signal, wherein the operating frequency of the phase interpolator is lower than the operating frequency of the voltage-controlled oscillator.

[0006] Optionally, the phase rotator includes: a sampling unit, including multiple triggers, each trigger sampling the first frequency-divided signal based on an oscillating clock signal to obtain a corresponding sampling signal; and a multiplexer, connected to the sampling unit to receive the multiple sampling signals and output two sampling signals with adjacent phases as a first threshold signal and a second threshold signal.

[0007] Optionally, the sampling unit includes: a first-stage trigger, whose input end is connected to the multi-mode frequency divider and receives the first frequency-divided clock signal, whose clock end is connected to the voltage-controlled oscillator and receives the first oscillation clock signal, and whose output end provides a first intermediate signal; a second-stage trigger, whose input end receives the first intermediate signal, whose clock end receives the fifth oscillation clock signal and whose corresponding output end outputs the second intermediate signal, whose clock end receives the first oscillation clock signal and whose corresponding output end outputs the third intermediate signal; and two groups of third-stage triggers, whose input end receives the second intermediate signal, whose clock end receives the first to fifth oscillation clock signals respectively, whose output end outputs the first to fifth sampling signals respectively, whose input end receives the third intermediate signal, whose clock end receives the sixth to eighth oscillation clock signals and the first oscillation clock signal respectively, whose output end outputs the sixth to ninth sampling signals respectively, wherein the ninth sampling signal is the first sampling signal delayed by one working cycle of the voltage-controlled oscillator.

[0008] Optionally, a phase difference of the fifth oscillation clock signal and the first oscillation clock signal is 180°.

[0009] Optionally, the phase difference between two oscillation clock signals of each group of adjacent phases is the same.

[0010] Optionally, the phase interpolator includes: a decoder, which decodes the control word to obtain a thermometer code; and an interpolation unit, including a first differential pair and a second differential pair, the first differential pair being based on the first threshold signal, the second threshold signal, and the control distribution current source of the thermometer code to obtain a second divided clock signal; the second differential pair being based on the first threshold complementary signal, the second threshold complementary signal, and the control distribution current source of the thermometer code to obtain a second divided clock complementary signal.

[0011] Optionally, a phase difference of 180° between the first threshold signal and the first threshold complementary signal, and a phase difference of 180° between the second threshold signal and the second threshold complementary signal.

[0012] Optionally, the first differential pair includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the first channel end of the first switch tube is connected and grounded via a current source, the current source provides multiple currents, the control end of the first switch tube is connected and receives a first threshold signal output by the phase rotator; the control end of the second switch tube is connected and receives a second threshold signal output by the phase rotator, the first channel end of the second switch tube is connected to the first channel end of the first switch tube; the first channel end of the third switch tube is connected to the second channel end of the first switch tube, the control end of the third switch tube is connected to and receives a thermometer code complementary control word; and the first channel end of the fourth switch tube is connected to the second channel end of the second switch tube, the control end of the fourth switch tube is connected to and receives the thermometer code control word, the second channel end of the third switch tube is connected to the second channel end of the fourth switch tube and serves as the output end of the first differential pair.

[0013] Optionally, the second differential pair includes a fifth switch tube, a sixth switch tube, a seventh switch tube and an eighth switch tube, the first channel end of the fifth switch tube is connected to and grounded via a current source, the current source provides multiple currents, and the control end of the fifth switch tube is connected to and receives the first threshold complementary signal; the control end of the sixth switch tube is connected to and receives the second threshold complementary signal, the first channel end of the sixth switch tube is connected to the first channel end of the fifth switch tube; the first channel end of the seventh switch tube is connected to the second channel end of the fifth switch tube, and the control end of the seventh switch tube is connected to and receives a thermometer code complementary control word; and the first channel end of the eighth switch tube is connected to the second channel end of the sixth switch tube, the control end of the eighth switch tube is connected to and receives the thermometer code control word, and the second channel end of the seventh switch tube is connected to the second channel end of the eighth switch tube and serves as the output end of the second differential pair.

[0014] Optionally, at least one current mirror is connected to the output end of the first differential pair and / or the second differential pair.

[0015] Optionally, the decoder decodes the first N bits of the control word into a thermometer code and uses it as a row address, and decodes the last N bits of the control word into a thermometer code and uses it as a row address. The number of bits of the control word is 2*N, where N is a positive integer.

[0016] Optionally, it also includes: a frequency detector and a phase detector, which receives a reference clock signal and is connected to the fractional divider to receive the second divided clock signal, compares the frequency and phase relationship between the reference clock signal and the second divided clock signal and obtains an indication pulse; a coupled charge pump and a loop filter, which filters the indication pulse and obtains a control voltage.

[0017] Optionally, the voltage-controlled oscillator is connected to the loop filter to obtain the multiple oscillation clock signals according to the control voltage.

[0018] Optionally, it further includes: a digital processing circuit connected to the fractional frequency divider, and providing the control word based on the phase of the fractional frequency divider.

[0019] Optionally, the digital processing circuit includes a delta-sigma modulator, a phase accumulator and a waveform generator.

[0020] The fractional frequency divider in the fractional frequency division ratio phase-locked loop proposed in the embodiment of the present invention, through the cooperation of the phase rotator and the phase interpolator, samples the clock signal provided by the multi-mode frequency divider multiple times based on the multiple oscillation clock signals with different phases provided by the voltage-controlled oscillator, and linearly interpolates between two sampling signals with adjacent phases through the double differential pair structure. In addition, the operating frequency of the phase interpolator is lower than the operating frequency of the voltage-controlled oscillator, so that under the above timing, the frequency resolution and linearity of the fractional frequency divider can be improved. Further, the quantization noise of the fractional frequency divider itself becomes smaller and is submerged in the white noise of the phase-locked loop.

[0021] Optionally, a plurality of current mirror structures are further provided in the phase interpolator and connected to the output ends of the differential pairs, so as to further improve the accuracy of phase interpolation.

[0022] Furthermore, the division ratio of the fractional frequency divider is realized in the digital domain by a digital processing circuit. The phase rotator and the phase interpolator are controlled by obtaining a control word by accumulating the phase of the clock signal. In the digital domain, any arbitrary division ratio can be basically realized by increasing the bit width of the control word. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0024] Figure 1 A structural block diagram of a fractional frequency division ratio phase-locked loop provided in an embodiment of the present application is shown.

[0025] Figure 2a A circuit diagram of a fractional frequency divider provided in an embodiment of the present application is shown. Figure 2b Shows Figure 2a Timing diagram of the phase rotator in FIG.

[0026] Figure 3a FIG. 4 shows a circuit diagram of another fractional frequency divider provided in an embodiment of the present application. Figure 3b Shows Figure 3a Timing diagram of the phase rotator in FIG.

[0027] Figure 4 A circuit diagram of a phase interpolator provided in an embodiment of the present application is shown.

[0028] Figure 5 A schematic diagram showing a fractional frequency divider provided in an embodiment of the present application for suppressing quantization noise is shown. DETAILED DESCRIPTION

[0029] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0030] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0031] It should be understood that the connection / coupling of A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiment of the present application is not limited to this.

[0032] The fractional frequency division ratio phase-locked loop provided in the present application can be applied to FPGA or other integrated circuits, and the generated spread spectrum clock signal can suppress electromagnetic interference (EMI) caused by multiple harmonics of the signal itself in components.

[0033] The fractional frequency division ratio phase-locked loop provided by the present application includes a phase rotator (PR) and a phase interpolator (PI). The phase rotator and the phase interpolator adjust the phase of the sampling clock in very small increments, thereby making the fractional frequency division ratio phase-locked loop have a frequency resolution that is finer than the reference frequency. In addition, the operating frequency of the phase interpolator is lower than the operating frequency of the voltage-controlled oscillator in the fractional frequency division ratio phase-locked loop, so that the phase interpolator has high linearity and high resolution, and the quantization noise introduced by the phase interpolator itself will be drowned by the white noise in the fractional frequency division ratio phase-locked loop.

[0034] The following describes an embodiment of the fractional frequency division ratio phase-locked loop provided by the present application in conjunction with the accompanying drawings.

[0035] Figure 1 A structural block diagram of a fractional frequency division ratio phase-locked loop provided in an embodiment of the present application is shown.

[0036] like Figure 1 As shown, the spread spectrum clock generation circuit 1000 includes a digital processing circuit 1200, a fractional frequency divider 1150, a phase frequency detector 1110, a charge pump 1120, a loop filter 1130, and a voltage controlled oscillator 1140. The digital processing circuit 1200 includes a phase accumulator 1210, a delta-sigma modulator 1220, and a waveform generator 1230.

[0037] The frequency detector 1110 receives the reference clock signal CKref and the second frequency-divided clock signal CKfd provided by the fractional frequency divider 1150, and compares the relationship between the frequency and phase of the reference clock signal CKref and the second frequency-divided clock signal CKfd. Specifically, the rising edge of the reference clock signal CKref precedes (or follows) the rising edge of the second frequency-divided clock signal CKfd, and correspondingly, the frequency detector 1110 generates an upward (or downward) pulse as an indication pulse, and the duration of the indication pulse is the phase difference between the reference clock signal CKref and the second frequency-divided clock signal CKfd.

[0038] The charge pump 1120 is connected to the phase frequency detector 1110 to receive the indication pulse, and the loop filter 1130 is connected to the charge pump 1120 and coupled to filter the indication pulse to provide an increase / decrease control voltage.

[0039] The voltage controlled oscillator (VCO) 1140 is connected to the low pass filter 1130 to increase / decrease the oscillation frequency of the voltage controlled oscillator 1140 based on the aforementioned increased / decreased control voltage control, thereby providing a plurality of oscillation clock signals with the same frequency and different phases. Preferably, the phase difference of two oscillation clock signals of each group of adjacent phases is the same.

[0040] The fractional divider (Fractional Divider) 1150 includes a multi-modulus divider (MMD) 1151, a phase rotator 1152 and a phase interpolator 1153. The multi-modulus divider 1151 receives the first oscillation clock signal provided by the voltage-controlled oscillator 1140 and outputs a first divided clock signal CKmmd. The phase rotator 1152 is respectively connected to the voltage-controlled oscillator 1140 and the multi-modulus divider 1151 to sample the first divided clock signal based on multiple oscillation clock signals and obtain multiple sampling signals. The phase interpolator 1153 is connected to the phase rotator 1152 to perform linear interpolation between two adjacent sampling signals to obtain a second divided clock signal CKfd. Further, the multi-modulus divider 1151, the phase rotator 1152 and the phase interpolator 1153 use different control word groups respectively. The multi-mode frequency divider 1151 uses the first control word group to control the frequency division ratio, the phase rotator 1152 uses the second control word group to select the oscillation clock signal of different phases, and the phase interpolator 1153 uses the third control word group to select different phases. Among them, the operating frequency of the phase interpolator 1153 is the operating frequency of the phase frequency detector 1110, and is lower than the operating frequency of the voltage-controlled oscillator 1140, thereby improving the resolution and linearity of the obtained second frequency-divided clock signal CKfd. The high-linearity, high-resolution phase interpolator 1153 reduces its own quantization noise, so that the quantization noise introduced by itself is completely submerged in the loop white noise of the phase-locked loop.

[0041] The digital processing circuit 1200 is connected to the fractional frequency divider 1150. The phase accumulator 1210 receives the clock signal provided by the fractional frequency divider 1150, performs phase accumulation and provides the first to third control word groups to the fractional frequency divider 1150. The delta-sigma modulator 1220 is connected to the fractional frequency divider 1150 to receive the second frequency-divided clock signal CKfd, and modulates the signal after the phase accumulation. The waveform generator 1230 provides a plurality of output signals including the frequency division ratio, and outputs the spread spectrum clock signal SSC.

[0042] Figure 2a A circuit diagram of a fractional frequency divider provided in an embodiment of the present application is shown. Figure 2b Shows Figure 2a Timing diagram of the phase rotator in FIG.

[0043] like Figure 2a As shown, the fractional divider 1150 includes a multi-mode divider 1151, a phase rotator 1152 and a phase interpolator 1153.

[0044] The multi-mode frequency divider 1151 is connected to the voltage-controlled oscillator 1140 to receive the first oscillation clock signal φ0, perform frequency division processing on it and output a first frequency-divided clock signal CKmmd.

[0045] The phase rotator 1152 includes a sampling unit and a selection unit. The sampling unit samples the first frequency-divided clock signal CKmmd based on a plurality of oscillation clock signals with different phases provided by the voltage-controlled oscillator 1140. Further, the voltage-controlled oscillator 1140 provides eight oscillation clock signals φ0-φ7 with different phases. The sampling unit includes a plurality of first-stage triggers and second-stage triggers. The first-stage trigger includes eight triggers. The input terminal D of each trigger is connected to the multi-mode frequency divider 1151 and receives the first frequency-divided clock signal CKmmd. The clock terminal clk of the trigger is connected to the voltage-controlled oscillator 1140 and receives an oscillation clock signal respectively. The output terminal of the trigger outputs the first sampling signal CK0, the second sampling signal CK1, the third sampling signal CK2, the fourth sampling signal CK3, the fifth sampling signal CK4, the sixth sampling signal CK5, the seventh sampling signal CK6, and the eighth sampling signal CK7 respectively. Among them, the first sampling signal CK0 is obtained by sampling the first frequency-divided clock signal CKmmd based on the first oscillation clock signal φ0. The second sampling signal CK1 is obtained by sampling the first frequency-divided clock signal CKmmd based on the second oscillation clock signal φ1. The third sampling signal CK2 is obtained by sampling the first frequency-divided clock signal CKmmd based on the third oscillation clock signal φ2. The fourth sampling signal CK3 is obtained by sampling the first frequency-divided clock signal CKmmd based on the fourth oscillation clock signal φ3. The fifth sampling signal CK4 is obtained by sampling the first frequency-divided clock signal CKmmd based on the fifth oscillation clock signal φ4. The sixth sampling signal CK5 is obtained by sampling the first frequency-divided clock signal CKmmd based on the sixth oscillation clock signal φ5. The seventh sampling signal CK6 is obtained by sampling the first frequency-divided clock signal CKmmd based on the seventh oscillation clock signal φ6. The eighth sampling signal CK7 is obtained by sampling the first frequency-divided clock signal CKmmd based on the eighth oscillation clock signal φ7. The input end of the second-stage trigger is connected to and receives the first sampling signal, the clock end receives the first oscillation clock signal φ0, and the output end provides the ninth sampling signal CK8. The selection unit includes a multiplexer, the control end of the multiplexer receives the second control word group PR<2:0>, and the input end of the multiplexer is connected to and receives multiple groups of sampling signals, each group of sampling signals includes two adjacent sampling signals, and the adjacent sampling signals are distinguished based on the adjacent phases of the sampling signals. The output end of the multiplexer selects to output two sampled signals of a group of sampled signals.

[0046] The phase interpolator 1153 is connected to the phase rotator 1152 to receive two sampling signals with adjacent phases, and the two sampling signals are input to the phase interpolator 1153 as the first threshold signal CKpr0 and the second threshold signal CKpr1. The first threshold signal CKpr0 and the second threshold signal CKpr1 can be the first sampling signal CK0 and the second sampling signal CK1, or the second sampling signal CK1 and the second sampling signal CK2, etc. The phase interpolator 1153 is controlled by the received third control word group PI<7:0>, and based on the polarity linear interpolation processing of the first threshold signal CKpr0 and the second threshold signal CKpr1 to obtain the second frequency-divided clock signal CKpi.

[0047] It should be noted that the types of the triggers in the phase rotator 1152 are the same, for example, selected from D triggers, but other edge triggers can still be selected for the implementation of this embodiment. It should be noted that at least one sampling can be completed within half a cycle of the first divided clock signal CKmmd to obtain the first to ninth sampling signals.

[0048] like Figure 2b As shown, the first oscillation clock signal φ0 to the eighth oscillation clock signal φ7 are separated by one eighth of a period. Correspondingly, the second sampling signal CK0 to the ninth sampling signal CK8 obtained by the phase rotator of this embodiment can be regarded as a delayed signal of the first sampling signal CK0, and the interval between two sampling signals of adjacent phases is one eighth of a period of the oscillation clock signal.

[0049] Figure 3a FIG. 4 shows a circuit diagram of another fractional frequency divider provided in an embodiment of the present application. Figure 3b Shows Figure 3a Timing diagram of the phase rotator in FIG.

[0050] like Figure 3a As shown, Figure 2a Compared with the fractional frequency divider shown in the foregoing, the implementation manner of the sampling unit in the phase rotator of the fractional frequency divider provided in this embodiment is further improved, and the working principles of other parts are consistent with those shown in the foregoing embodiment.

[0051] The phase rotator 2152 includes a selection unit and a sampling unit, wherein the sampling unit includes a three-stage trigger. The input end of the first-stage trigger is connected to the multi-mode frequency divider 1151 and receives the first frequency-divided clock signal CKmmd, the clock end is connected to the voltage-controlled oscillator 1140 and receives the first oscillation clock signal φ0, and the output end of the first-stage trigger provides the first intermediate signal CKm0. The second-stage trigger includes two triggers, the input end of each second-stage trigger receives the first intermediate signal CKm0, the clock end of one second-stage trigger receives the fifth oscillation clock signal φ4 and the corresponding output end outputs the second intermediate signal CKm4, and the clock end of the other second-stage trigger receives the first oscillation clock signal φ0 and the corresponding output end outputs the third intermediate signal CKm8. The third-stage trigger includes two groups. The first group of third-stage triggers includes 5 triggers. The input end of each trigger is connected to and receives the second intermediate signal CKm4. The clock end of each trigger receives the first oscillation clock signal φ0, the second oscillation clock signal φ1, the third oscillation clock signal φ2, the fourth oscillation clock signal φ3, and the fifth oscillation clock signal φ4. Correspondingly, the first group of third-stage triggers obtains the first sampling signal CK0, the second sampling signal CK1, the third sampling signal CK2, the fourth sampling signal CK3, and the fifth sampling signal CK4. The second group of third-stage triggers includes 4 triggers. The input end of each trigger is connected to and receives the third intermediate signal CKm8. The clock end of each trigger receives the sixth oscillation clock signal φ5, the seventh oscillation clock signal φ6, the eighth oscillation clock signal φ7, and the first oscillation clock signal φ0. Correspondingly, the second group of third-stage triggers obtains the sixth sampling signal CK5, the seventh sampling signal CK6, the eighth sampling signal CK7, and the ninth sampling signal CK8. It should be noted that at least one sampling can be completed within half a cycle of the first frequency-divided clock signal CKmmd to obtain the first to ninth sampling signals.

[0052] It should be noted that the fifth oscillation clock signal φ4 is 180° out of phase with the first oscillation clock signal φ0. The triggers in the phase rotator 2152 are of the same type, for example, D triggers, but other edge triggers can still be selected for implementation of this embodiment.

[0053] like Figure 3b As shown, the phases of the first oscillation clock signal φ0 to the eighth oscillation clock signal φ7 differ from each other by one eighth of a cycle. Correspondingly, the second sampling signal CK0 to the ninth sampling signal CK8 obtained by the phase rotator of this embodiment can be regarded as delayed signals of the first sampling signal CK0, and the interval between two sampling signals of adjacent phases is one eighth of a cycle of the oscillation clock signal. The interval between the first intermediate signal CKm0 and the second intermediate signal CKm4 and the interval between the second intermediate signal CKm4 and the third intermediate signal CKm8 is half of an oscillation cycle.

[0054] The above embodiment adopts three-stage sampling to obtain the sampling signal, so that the sampling signal output by the phase rotator 2152 has higher accuracy.

[0055] Figure 4 A circuit diagram of a phase interpolator provided in an embodiment of the present application is shown.

[0056] Among them, Figure 4 The illustrated implementation of the phase interpolator can be implemented in conjunction with one of the two implementations of the phase rotator provided above to obtain the fractional frequency divider provided in the present application.

[0057] like Figure 4As shown, the phase interpolator 1153 includes a decoder and an interpolation unit. The decoder decodes the third control word group PI<7:0> and obtains the thermometer code control word PIT<255:0> and the thermometer code complementary control word PITb<255:0>. The interpolation unit includes two differential pairs. The first differential pair includes a first switch tube M1, a second switch tube M2, a third switch tube M3 and a fourth switch tube M4. The first channel end of the first switch tube M1 and the first channel end of the second switch tube M2 are connected and grounded via a current source Is, and the current source Is provides a 256 tail current. The control end of the first switch tube M1 is connected to and receives the first threshold signal CKpr0 output by the phase rotator, and the control end of the second switch tube M2 is connected to and receives the second threshold signal CKpr1 output by the phase rotator. The second channel end of the first switch tube M1 is connected to the first channel end of the third switch tube M3, and the second channel end of the second switch tube M2 is connected to the first channel end of the fourth switch tube M4. The second channel end of the third switch tube M3 is connected to the second channel end of the fourth switch tube M4 and serves as the output end of the first differential pair. The control end of the third switch tube M3 is connected to and receives the thermometer complementary control word PITb<255:0>, and the control end of the fourth switch tube M4 is connected to and receives the thermometer control word PIT<255:0>. The second differential pair includes a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7 and an eighth switch tube M8. The first channel end of the fifth switch tube M5 and the first channel end of the sixth switch tube M6 are connected to and grounded via a current source Is, and the current source Is provides a 256 tail current. The control end of the fifth switch tube M5 is connected to and receives the first threshold complementary signal CKpr0-b, and the control end of the sixth switch tube M6 is connected to and receives the second threshold complementary signal CKpr1-b. The second channel end of the fifth switch tube M5 is connected to the first channel end of the seventh switch tube M7, and the second channel end of the sixth switch tube M6 is connected to the first channel end of the eighth switch tube M8. The second channel end of the seventh switch tube M7 is connected to the second channel end of the eighth switch tube M8 and serves as the output end of the second differential pair. The control end of the seventh switch tube M7 is connected to and receives the thermometer code complementary control word PITb<255:0>, and the control end of the eighth switch tube M8 is connected to and receives the thermometer code control word PIT<255:0>. The second frequency-divided clock signal CKpi is output from the output end of the first differential pair, and the second frequency-divided clock complementary signal is output from the output end of the second differential pair.

[0058] The first threshold signal CKpr0 and the first threshold complementary signal CKpr0-b have the same frequency and a phase difference of 180°, the second threshold signal CKpr1 and the second threshold complementary signal CKpr1-b have a phase difference of 180°. Correspondingly, the second divided clock complementary signal and the second divided clock signal have a phase difference of 180°.

[0059] Preferably, in order to improve the accuracy of the phase interpolator, the difference unit of the phase interpolator also includes multiple current mirrors. Specifically, the output end of the first differential pair is connected to the first current mirror, the output end of the first current mirror is connected to the output end of the second current mirror and outputs the second divided clock signal CKpi. The output end of the second differential pair is connected to the third current mirror, the output end of the third current mirror is connected to the output end of the fourth current mirror and outputs the second divided clock complementary signal.

[0060] The first current mirror is composed of the tenth switch tube M10 and the eleventh switch tube M11. The first current mirror is a basic structure. The control end of the tenth switch tube M10 is connected to the control end of the eleventh switch tube M11. The first path end of the short-circuited tenth switch tube M10 is connected to the output end of the first differential pair as the input end of the first current mirror. The second path end of the tenth switch tube M10 is connected to the second path end of the eleventh switch tube M11 and receives a power supply voltage. The first path end of the eleventh switch tube M11 is used as the output end of the first current mirror. Preferably, a grounded capacitor C1 is connected to the middle node where the control end of the tenth switch tube M10 and the control end of the eleventh switch tube M11 are connected.

[0061] The second current mirror is composed of an eighteenth switch tube M18 and a nineteenth switch tube M19. The second current mirror is a basic structure. The control end of the eighteenth switch tube M18 is connected to the control end of the nineteenth switch tube M19. The first channel end of the short-circuited nineteenth switch tube M19 is connected to the power supply voltage via the channel end of the seventeenth switch tube M17 as the input end of the first current mirror. The second channel end of the eighteenth switch tube M18 and the second channel end of the nineteenth switch tube M19 are grounded. The first channel end of the eighteenth switch tube M18 serves as the output end of the second current mirror.

[0062] The third current mirror is composed of a fifteenth switch tube M15 and a sixteenth switch tube M16. The third current mirror is a basic structure. The control end of the fifteenth switch tube M15 is connected to the control end of the sixteenth switch tube M16. The first channel end of the short-circuited fifteenth switch tube M15 is connected to the output end of the second differential pair as the input end of the third current mirror. The second channel end of the fifteenth switch tube M15 is connected to the second channel end of the sixteenth switch tube M16 and receives a power supply voltage. The first channel end of the sixteenth switch tube M16 is used as the output end of the third current mirror. Preferably, a grounded capacitor C2 is connected to the middle node where the control end of the fifteenth switch tube M15 and the control end of the sixteenth switch tube M16 are connected. Among them, the middle node where the control end of the fifteenth switch tube M15 and the control end of the sixteenth switch tube M16 are connected is connected to the control end of the seventeenth switch tube M17.

[0063] The fourth current mirror is composed of the twelfth switch tube M12 and the thirteenth switch tube M13. The fourth current mirror is a basic structure. The control end of the twelfth switch tube M12 is connected to the control end of the thirteenth switch tube M13. The first passage end of the short-circuited thirteenth switch tube M13 is connected to a power supply voltage via the passage end of the fourteenth switch tube M14 as the input end of the fourth current mirror. The second passage end of the twelfth switch tube M12 and the second passage end of the thirteenth switch tube M13 are grounded. The first passage end of the twelfth switch tube M12 is used as the output end of the fourth current mirror. The control end of the fourteenth switch tube M14 is connected to the intermediate node where the control end of the tenth switch tube M10 and the control end of the eleventh switch tube M11 are connected.

[0064] Preferably, a logic unit is connected to the output end of the first current mirror and the output end of the second current mirror, thereby obtaining a second frequency-divided clock signal with higher precision. Specifically, the logic unit includes the first to sixth NOT gates. The first NOT gate U1 and the second NOT gate U2 are connected in series, the input end of the first NOT gate U1 is connected to the output end of the third current mirror, the output end of the first NOT gate U1 is connected to the input end of the second NOT gate U2, and the output end of the second NOT gate U2 outputs the second frequency-divided clock complementary signal. The third NOT gate U3 and the fourth NOT gate U4 are connected in series, the input end of the third NOT gate U3 is connected to the output end of the first current mirror, the output end of the third NOT gate U3 is connected to the input end of the fourth NOT gate U4, and the output end of the fourth NOT gate U4 outputs the second frequency-divided clock signal. The input end of the fifth NOT gate U5 is connected to the output end of the first NOT gate U1, and the output end of the fifth NOT gate U5 is connected to the output end of the third NOT gate U3. The output end of the sixth NOT gate U6 is connected to the output end of the first NOT gate U1, and the input end of the sixth NOT gate U6 is connected to the output end of the third NOT gate U3.

[0065] If the interpolation unit of the phase interpolator is not provided with a structure such as a current mirror, the above-mentioned logic unit can be connected between the output end of the first differential pair and the output end of the second differential pair to obtain a second frequency-divided clock signal with higher accuracy.

[0066] It should be noted that the switch tube can be selected from a transistor, for example, the control terminal is the gate of the transistor, the first channel terminal and the second channel terminal are the source and drain of the transistor, or the drain and source of the transistor.

[0067] It should be noted that the input end of the decoder in the above-mentioned phase interpolator receives a third control word group consisting of eight binary numbers. Preferably, the upper four bits of the third control word group can be decoded into a 15-bit thermometer code control word as a row address, and the lower four bits of the third control word group can be decoded into a 15-bit thermometer code control word as a column address. The decoded row and column codes are used as control words to control the conduction and shutdown of the corresponding switch tubes in the differential pair to perform interpolation operations.

[0068] The phase rotator in the fractional frequency divider provided in the embodiment of the present application achieves 3-bit accuracy, and the phase interpolator achieves 8-bit accuracy. The above-mentioned fractional frequency divider can achieve 11-bit high-precision frequency division operation.

[0069] Figure 5 A schematic diagram showing a fractional frequency divider provided in an embodiment of the present application for suppressing quantization noise is shown.

[0070] like Figure 5 As shown, the horizontal axis is the frequency axis, the vertical axis is the quantization noise axis, L1 is the noise curve of the fractional frequency divider provided by the present application, and L2 is the noise curve of the existing fractional frequency divider. It can be seen that the quantization noise of the fractional frequency divider of the present application can be reduced by about 66dB compared with the quantization noise of the fractional frequency divider of the prior art. That is, the quantization noise of the fractional frequency division ratio phase-locked loop using the fractional frequency divider provided by the present application is significantly reduced.

[0071] The phase interpolator in the fractional frequency divider provided above controls the dual differential pair according to the threshold signal and the threshold complementary signal, as well as the decoded thermometer code, and the phase rotator in the fractional frequency divider performs multiple sampling on the first frequency division clock signal output by the multi-mode frequency divider, so that the frequency resolution and linearity of the fractional frequency divider become higher. The phase interpolator also sets a plurality of current mirror structures connected to the differential pair output end, further improving the accuracy. The operating frequency of the phase interpolator is the same as the operating frequency of the frequency detector and phase detector, and is lower than the operating frequency of the voltage-controlled oscillator, so that the fractional frequency divider has higher resolution and higher linearity. Then the quantization noise of the fractional frequency divider itself becomes smaller and is submerged in the white noise of the phase-locked loop. When a delta-sigma modulator is used in the digital processing circuit of the fractional phase-locked loop, the quantization noise of the phase interpolator is greatly reduced, and the loop bandwidth of the phase-locked loop is increased, thereby enhancing the suppression of the low-frequency noise of the voltage-controlled oscillator and reducing the noise or jitter of the overall loop.

[0072] The frequency division ratio of the fractional frequency divider is realized in the digital domain. The phase is obtained by accumulating the frequency to control the phase rotator and the phase interpolator. By increasing the bit width in the digital domain, a frequency division ratio of arbitrary precision can be realized. The phase control word obtained by accumulating the frequency division ratio is truncated at the low bit, and the high M bits (in this embodiment, M=11, 3 bits of the high M bits are provided to the phase rotator, and the other 8 bits are provided to the phase interpolator) are used to control the phase rotator and the interpolator. The truncation error will be accumulated in the phase domain, thereby controlling the frequency division ratio to jump back and forth between two fractions, with an interval of 1 / 2^M, so that the phase-locked loop can realize an arbitrary frequency division ratio. When the fractional phase-locked loop does not include a delta-sigma modulator, because the resolution of the phase interpolator is high enough, its own quantization noise can be lower than white noise. The fractional phase-locked loop that does not include a delta-sigma modulator works very similarly to an integer phase-locked loop, without the high-frequency quantization noise introduced by the delta-sigma modulator.

[0073] At the same time, those skilled in the art can realize that, in combination with the structures and methods of the various examples described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure, but such implementation should not be considered to be beyond the scope of the present application. In addition, it should be understood that the connection relationship between the various components of the amplifier in the aforementioned figure in the embodiments of the present application is a schematic example and does not impose any limitation on the embodiments of the present application.

[0074] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0075] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A fractional frequency division ratio phase-locked loop, characterized in that: include: A voltage-controlled oscillator, providing multiple oscillation clock signals with different phases; and a fractional frequency divider, the fractional frequency divider comprising: a multi-mode frequency divider connected to the voltage-controlled oscillator to receive a first oscillation clock signal and provide a first frequency-divided clock signal; a phase rotator, connected to the voltage-controlled oscillator and the multi-mode frequency divider, respectively, sampling the first frequency-divided clock signal based on the multiple oscillation clock signals with different phases to obtain multiple sampling signals; and a phase interpolator, receiving two sampling signals with adjacent phases and using them as a first threshold signal and a second threshold signal, and performing linear interpolation between the first threshold signal and the second threshold signal according to a control word to obtain a second frequency-divided clock signal, wherein the operating frequency of the phase interpolator is lower than the operating frequency of the voltage-controlled oscillator, The phase interpolator comprises: A decoder, decoding the control word to obtain a thermometer code; and The interpolation unit includes a first differential pair and a second differential pair, wherein the first differential pair distributes a current source based on the first threshold signal, the second threshold signal, and the control of the thermometer code to obtain a second frequency-divided clock signal; and the second differential pair distributes a current source based on the first threshold complementary signal, the second threshold complementary signal, and the control of the thermometer code to obtain a second frequency-divided clock complementary signal. The phase rotator comprises: a sampling unit, comprising a plurality of triggers, each trigger sampling the first frequency-divided signal based on an oscillating clock signal to obtain a corresponding sampling signal; and A multiplexer is connected to the sampling unit to receive the multiple sampling signals and output two sampling signals with adjacent phases as a first threshold signal and a second threshold signal.

2. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: The sampling unit comprises: A first-stage trigger, wherein the input end is connected to the multi-mode frequency divider and receives the first frequency-divided clock signal, the clock end is connected to the voltage-controlled oscillator and receives the first oscillation clock signal, and the output end provides a first intermediate signal; a second-stage flip-flop, wherein an input terminal of the second-stage flip-flop receives the first intermediate signal, a clock terminal of one second-stage flip-flop receives the fifth oscillation clock signal and a corresponding output terminal outputs the second intermediate signal, and a clock terminal of one second-stage flip-flop receives the first oscillation clock signal and a corresponding output terminal outputs the third intermediate signal; and There are two groups of third-level triggers, the input end of the first group of third-level triggers receives the second intermediate signal, the clock end of the first group of third-level triggers receives the first oscillation clock signal, and the output end outputs the first sampling signal, the clock end of the first group of third-level triggers receives the second oscillation clock signal, and the output end outputs the second sampling signal, the clock end of the first group of third-level triggers receives the third oscillation clock signal, and the output end outputs the third sampling signal, the clock end of the first group of third-level triggers receives the fourth oscillation clock signal, and the output end outputs the fourth sampling signal, the clock end of the first group of third-level triggers receives the fifth oscillation clock signal, and the output end outputs the fifth sampling signal, the input end of the second group of third-level triggers receives the third intermediate signal, the clock end of the second group of third-level triggers receives the sixth oscillation clock signal, and the output end outputs the sixth sampling signal, the clock end of the second group of third-level triggers receives the seventh oscillation clock signal, and the output end outputs the seventh sampling signal, the clock end of the second group of third-level triggers receives the eighth oscillation clock signal, and the output end outputs the eighth sampling signal, and the clock end of the second group of third-level triggers receives the first oscillation clock signal, and the output end outputs the ninth sampling signal.

3. The fractional frequency division ratio phase locked loop according to claim 2, characterized in that: The fifth oscillation clock signal is 180° out of phase with the first oscillation clock signal.

4. The fractional frequency division ratio phase locked loop according to claim 2, characterized in that: The phase difference between the two oscillation clock signals in each group of adjacent phases is the same.

5. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: The first threshold signal and the first threshold complementary signal have a phase difference of 180°, and the second threshold signal and the second threshold complementary signal have a phase difference of 180°.

6. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: The first differential pair includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, A first path end of the first switch tube is connected to and grounded via a current source, the current source provides multiple currents, and a control end of the first switch tube is connected to and receives a first threshold signal output by the phase rotator; The control end of the second switch tube is connected to and receives the second threshold signal output by the phase rotator, and the first channel end of the second switch tube is connected to the first channel end of the first switch tube; The first channel end of the third switch tube is connected to the second channel end of the first switch tube, and the control end of the third switch tube is connected to and receives the thermometer code complementary control word; and The first channel end of the fourth switch tube is connected to the second channel end of the second switch tube, the control end of the fourth switch tube is connected to and receives the thermometer code control word, and the second channel end of the third switch tube is connected to the second channel end of the fourth switch tube and serves as the output end of the first differential pair.

7. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: The second differential pair includes a fifth switch tube, a sixth switch tube, a seventh switch tube and an eighth switch tube, The first channel end of the fifth switch tube is connected to and grounded via a current source, the current source provides multiple currents, and the control end of the fifth switch tube is connected to and receives the first threshold complementary signal; The control end of the sixth switch tube is connected to and receives the second threshold complementary signal, and the first channel end of the sixth switch tube is connected to the first channel end of the fifth switch tube; The first channel end of the seventh switch tube is connected to the second channel end of the fifth switch tube, and the control end of the seventh switch tube is connected to and receives a thermometer code complementary control word; and The first channel end of the eighth switch tube is connected to the second channel end of the sixth switch tube, the control end of the eighth switch tube is connected to and receives the thermometer code control word, and the second channel end of the seventh switch tube is connected to the second channel end of the eighth switch tube and serves as the output end of the second differential pair.

8. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: At least one current mirror is connected to the output end of the first differential pair and / or the second differential pair.

9. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: The decoder decodes the first N bits of the control word into a thermometer code as a row address, and decodes the last N bits of the control word into a thermometer code as a column address. The number of bits of the control word is 2*N, where N is a positive integer.

10. The fractional frequency division ratio phase locked loop according to claim 1, characterized in that: Also includes: A frequency detector and phase detector, receiving a reference clock signal, and connected to the fractional frequency divider to receive the second frequency-divided clock signal, comparing the frequency and phase relationship between the reference clock signal and the second frequency-divided clock signal and obtaining an indication pulse; The coupled charge pump and loop filter filter filter the indication pulse and obtain a control voltage.

11. The fractional frequency division ratio phase locked loop according to claim 10, characterized in that: The voltage-controlled oscillator is connected to the loop filter and obtains the multiple oscillation clock signals with different phases according to the control voltage.

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