Quantum circuit generator, quantum computer and method for reducing quantum circuit delay

Abstract

A quantum circuit generator for a quantum computer includes: a controller; and a plurality of analog conversion units (ACUs) operably connected to the controller, each ACU being operably connected to a corresponding qubit in a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control the quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits in the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits mapped by the controller and based on a delay of the generated quantum circuit, such that the generated quantum circuit has a delay less than a delay threshold.

Description

Technical Field

[0001] The present invention relates generally to quantum computing, and more particularly to methods and apparatus for generating quantum circuits. Background Art

[0002] Quantum programming is the process of assembling sequences of instructions, or quantum programs, that can be run on a quantum computer in the form of one or more quantum circuits. When a conventional quantum program is executed, a result is produced by the quantum computer. A quantum program can be relatively large and can have many quantum circuits working independently. As a result, the time it takes to execute or run a conventional quantum program in the quantum computer and produce or obtain a result from the computer can be relatively high.

[0003] The information stored in a qubit remains coherent in a very small time window, which is the time when quantum computation can be performed. The main delay bottleneck in many quantum circuits (quantum programs) depends on the communication between quantum and classical logic, which can consume most of the coherence budget. This delay is partly due to i) the qubit from quantum readout to classical, and ii) the classical logic after the decision of the next microwave pulse. In superconducting qubits, the delay from quantum readout to classical can be about 100 nanoseconds. The delay due to classical logic followed by the decision of the next microwave pulse is highly dependent on the physical layout and system interconnectivity of the analog conversion units (ACUs) that generate these signals to and from the qubits. These analog conversion units (ACUs) can include digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) for processing signals to and from the qubits in the quantum device, and the spatial relationship and connectivity between the classical registers and the quantum registers cause different delays in the system.

[0004] If a conditional gate is on a qubit, the readout of which is on the same analog conversion unit (ACU), this delay can be about 100 nanoseconds. However, if, on the other hand, the quantum circuit (quantum program) requires communication between different analog conversion units (ACUs), the delay can be as high as about 500 nanoseconds or even about 1 microsecond. This time frame is outside any of today's qubit coherence times, which would make quantum computing inoperable.

[0005] Therefore, a solution is needed to reduce latency or minimize latency in order to achieve efficient quantum computing. Summary of the invention

[0006] One aspect of the present invention is to provide a quantum circuit generator for a quantum computer. The quantum circuit generator includes a controller; a plurality of analog conversion units (ACUs) operably connected to the controller, each ACU operably connected to a corresponding qubit in a plurality of qubits. Each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits mapped by the controller and based on the delay of the generated quantum circuit, so that the generated quantum circuit has a delay less than a threshold delay.

[0007] Another aspect of the present invention is to provide a quantum computer. The quantum computer includes: a refrigeration container defining a refrigeration chamber therein; a quantum processor placed in the refrigeration chamber, the quantum processor including a plurality of qubits, at least two of the plurality of qubits being selectable to generate a quantum circuit having a delay. The quantum processor may be configured to construct a quantum circuit using a quantum circuit generator communicating with the plurality of qubits. The quantum circuit generator includes a controller; a plurality of analog conversion units (ACUs) operably connected to the controller, each ACU being operably connected to a corresponding qubit in the plurality of qubits. Each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate the quantum circuit using at least two of the plurality of qubits, the at least two qubits being selected by the controller based on the corresponding classical bits mapped by the controller and based on the delay of the generated quantum circuit, so that the generated quantum circuit has a delay less than a threshold delay.

[0008] Another aspect of the present invention is to provide a method for reducing the delay of a quantum circuit. The method includes mapping at least two qubits in a plurality of qubits to classical bits; generating a quantum circuit using the at least two qubits in the plurality of qubits, the at least two qubits being selected by a controller based on the corresponding classical bits mapped by the controller; determining a delay of the generated quantum circuit; and selecting the at least two qubits in the plurality of qubits so that the generated quantum circuit has a delay less than a threshold delay.

[0009] A further aspect of the invention is to provide a computer readable medium having non-transitory computer executable code stored thereon, which, when executed by a controller, causes the controller to: map at least two qubits of a plurality of qubits to classical bits; generate a quantum circuit using the at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits mapped by the controller; determine a delay of the generated quantum circuit; and select the at least two qubits of the plurality of qubits such that the generated quantum circuit has a delay less than a threshold delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure, the methods of operation and function of the related structural elements, and the combination and economy of manufacture of the parts, will become more apparent when the following description and appended claims are considered with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals refer to corresponding parts in the different drawings. It should be expressly understood, however, that the drawings are for illustration and description purposes only and are not intended to define the limits of the invention.

[0011] Figure 1 is a schematic diagram of a quantum circuit generator for a quantum computer according to an embodiment of the present invention;

[0012] Figure 2 is a schematic diagram of an example quantum circuit that may be generated by a controller in a quantum circuit generator according to an embodiment of the present invention;

[0013] Figure 3 is a detailed circuit diagram of an analog conversion unit (ACU) according to an embodiment of the present invention, the analog conversion unit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) and a field programmable gate array (FPGA) in a quantum circuit generator;

[0014] Figure 4 is a detailed circuit diagram of an ACU according to another embodiment of the present invention, the ACU including an industry standard arbitrary waveform generator (AWG) in a quantum circuit generator;

[0015] Figure 5 is a schematic diagram of a quantum computer according to one embodiment of the present invention; and

[0016] Figure 6 is a flow chart of a method for reducing delay of a quantum circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Figure 1 FIG. 1 is a schematic diagram of a quantum circuit generator 100 for a quantum computer according to an embodiment of the present invention. Figure 1As shown, a quantum circuit generator 100 for a quantum computer includes a controller 102 and a plurality of analog conversion units (ACUs) 110, which may include one or more digital-to-analog converters (DACs) 104 and analog-to-digital converters (ADCs) 108. The overall concept of the present invention is not limited to any particular number of DACs 104 or ADCs 108 or the total number of ACUs 110. A plurality of ACUs 110 are operably connected to the controller 102. In one embodiment, a plurality of ACUs 110 are physically connected to the controller 102 using wires or cables. In another embodiment, a plurality of ACUs 110 are wirelessly connected to the controller 102. The controller 102 may be, for example, a classical computer. The term "classical computer" should be broadly understood to include any computer based on binary bits, including but not limited to desktop computers, laptop computers, tablet computers, mobile devices, etc. Each DAC 104 and ADC 108 within the ACU 110 is operably connected to a corresponding qubit (Q1, Q2, ..., QN) in the plurality of qubits 106. The plurality of qubits 106 may be two, three or more qubits. The general concepts of the present invention are not limited to any particular number of qubits 106. Each DAC 104 is configured to convert a digital input from the controller 102 into an analog input at a microwave frequency to control the quantum state of the corresponding qubit (Q1, Q2, ..., QN).

[0018] The controller 102 is configured to generate a quantum circuit (i.e., a quantum program) using at least two qubits (e.g., Q1 and Q2) of the plurality of qubits 106. The at least two qubits (e.g., Q1 and Q2) are selected by the controller 102 based on the corresponding classical bits mapped by the controller 102 and based on the delay of the generated quantum circuit, so that the generated quantum circuit has a delay less than a threshold delay. The term "classical bit" is intended to refer to a binary bit that takes only one of two values ​​(e.g., 0 or 1). For example, the controller 102 may use two, three, or more qubits (e.g., 4 qubits) of the plurality of qubits to generate a quantum circuit. However, the overall concept of the present invention is not limited to any particular number of qubits in the total qubits 106 used by the controller 102 to form a quantum circuit. Therefore, the controller 102 is configured to generate a quantum circuit using M qubits (where M is greater than or equal to 2) from a plurality of N qubits (where N is greater than or equal to 2). The number M of qubits used or selected is less than or equal to the total number N of available qubits.

[0019] In one embodiment, the delay of the quantum circuit includes a delay (in Figure 1In one embodiment, the delay of the quantum circuit includes the delay caused by the classical logic processing in the controller 102 and the delay caused by the relative position of the ACU 110.

[0020] Figure 2 2 is a schematic diagram of an example quantum circuit 200 that can be generated by the controller 102 according to one embodiment of the present invention. In this example, the quantum circuit 200 uses four qubits (Q0, Q1, Q2, Q3). Each qubit (Q0, Q1, Q2, Q3) starts at the ground state |0>, and different operations are applied to the state of one or more of the qubits (Q0, Q1, Q2, Q3) using different gates, such as a Hadamard gate 202, a CNOT gate 204, and a Z gate 206. Measurement 208 is performed on the one or more qubits (Q0, Q1, Q2, Q3) to determine the state of the one or more qubits (Q0, Q1, Q2, Q3) at the end of the different operations performed using the different gates. For example, in the quantum circuit 200, the state of the qubit Q0 is measured and the state of the qubit Q1 is also measured. The results of the measurement 208 are converted into classical bits (C0, C1, C2, and C3). For example, in quantum circuit 200, measurement 208 of the state of qubit Q0 is converted to classical bit C2, and measurement of the state of qubit Q1 is converted to classical bit C0.

[0021] In quantum circuit 200, quantum circuit generator 100 recognizes that classical bits C1 and C3 are not written. Therefore, classical bits C1 and C3, which are initially zero, remain zero. Since the only classical bits written are C0 and C2, the quantum circuit generator only needs to map classical bits C0 and C2. In order to reduce the delay to a desired threshold delay, controller 102 of quantum circuit generator 100 can position these two classical bits C0 and C2 as close as possible to ACU 110 near qubit Q3, because qubit Q3 is a qubit that will be conditionally controlled. In this way, in this case, the measured qubits (e.g., Q0 and Q1) are written to C0 and C2, and controller 102 is selected based on the corresponding classical bits C0 and C2 mapped by controller 102 and based on the delay of the generated quantum circuit 200, so that the generated quantum circuit 200 has a delay less than the threshold delay.

[0022] In an embodiment, the threshold delay may be a delay selected by a user. In another embodiment, the delay threshold corresponds to a minimum delay obtained by selecting at least two qubits (e.g., Q1 and Q2) that are closest to each other so as to reduce the relative position of the analog conversion unit (ACU) 110 associated with the at least two qubits (e.g., Q1 and Q2). In some embodiments, the threshold is less than or equal to the coherence time of the generated quantum circuit.

[0023] Thus, in some embodiments, given knowledge of the layout of ACU 110 (including DAC 104 and ADC 108 ), quantum circuit generator 100 positions the ACUs associated with the qubits being used (eg, selected qubits Q1 and Q2 ) as closely as possible in order to reduce latency.

[0024] Figure 3 is a detailed circuit diagram 301 of the ACU 110 in the quantum circuit generator 100 according to an embodiment of the present invention. Figure 4 FIG. 4 is a detailed circuit diagram 401 of the ACU 110 in the quantum circuit generator 100 according to another embodiment of the present invention. In an implementation, as Figure 3 As shown, ACU 301 includes a field programmable gate array (FPGA) 300 as well as a DAC 312 and an ADC 310. An FPGA is a device or integrated circuit designed to be configured by a designer after manufacture. An FPGA contains an array of programmable logic blocks that can be configured by wiring specific blocks together. In another embodiment, as shown in FIG. Figure 4 As shown, ACU 401 includes an arbitrary waveform generator (AWG) 400. AWG is a device that generates a waveform specified by a user. In another embodiment, ACU 110 is an application specific integrated circuit (ASIC). Figure 3 and 4 As shown, each ACU 301, 401 includes a corresponding local oscillator (LO) 302, 402 and one or more mixers 304, 404, wherein the local oscillator (LO) 302, 402 is configured to generate a lower frequency wave radiation, and the one or more mixers 304, 404 are configured to convert the lower frequency wave radiation from the LO 302, 402 into a higher frequency microwave radiation. In one embodiment, as Figure 3 As shown, low frequency wave radiation from LO 302 is input to mixer 304 through splitter 303 to generate higher frequency microwave radiation. The higher frequency microwave radiation is generated to control the quantum state of the corresponding qubit (Q1, Q2 ... QN).

[0025] In one embodiment, Figure 3As shown in , the ACU 301 further includes at least one bandpass filter 306 configured to filter the frequencies of the higher frequency microwave radiation. Figure 3 As shown, ACU 301 includes two bandpass filters 306. One output of one bandpass filter 306 is transmitted directly to the qubit, while one output of the other bandpass filter is switched using switch 308. Switch 308 is selected by a logic output signal from FPGA 300 to increase the transmission speed of microwave radiation to the qubit (Q1, Q2, ..., QN) and thus reduce latency. Switch 308 is controlled and timed by FPGA 300 to increase the throughput of microwave radiation signals input to different qubits (Q1, Q2, ..., QN). Therefore, as can be appreciated, when multiple control signals are input to a qubit (by Figure 3 ), the frequency is upconverted to a higher microwave frequency radiation. However, when reading the state of the qubit, i.e., performing a quantum measurement, the higher frequency microwave radiation output by the qubit is converted back to lower frequency radiation and input back into FPGA 300. FPGA 300 then converts the low frequency radiation signal into a classical bit (i.e., 0 and / or 1). The process of inputting microwave radiation into the qubit and reading the output of the quantum measurement from the qubit is repeated multiple times.

[0026] Figure 5 5 is a schematic diagram of a quantum computer 500 according to an embodiment of the present invention. The quantum computer 500 includes a refrigeration container 502 having a refrigeration chamber 504. The quantum computer 500 further includes a quantum processor 506 arranged in the refrigeration chamber 504. The quantum processor includes a plurality of qubits 508 (Q1, Q2, ..., QN). At least two qubits (e.g., Q1 and Q2) in the plurality of qubits 508 are selectable to generate a quantum circuit (e.g., but not limited to the quantum circuit 200) having a delay. The quantum processor 506 may be configured to construct a quantum circuit (e.g., but not limited to the quantum circuit 200) using a quantum circuit generator 100 in communication with the plurality of qubits 508. The details of the quantum circuit generator 100 are described in detail in the above paragraphs, and therefore will not be repeated in the following paragraphs. As described in the above paragraphs, controller 102 of quantum circuit generator 100 is configured to generate a quantum circuit (e.g., but not limited to quantum circuit 200) using at least two qubits of the plurality of qubits, the at least two qubits being selected by controller 102 based on corresponding classical bits mapped by controller 102 and based on a delay of the generated quantum circuit (e.g., but not limited to, quantum circuit 200), such that the generated quantum circuit (e.g., but not limited to, quantum circuit 200) has a delay less than a threshold delay.

[0027] Figure 6 Flowchart of a method for reducing the delay of a quantum circuit according to an embodiment of the present invention. The method includes mapping at least two qubits (e.g., Q1 and Q2) of a plurality of qubits (Q1, Q2, ..., QN) to classical bits (C1, C2, ..., CN) at S600. The method also includes generating a quantum circuit (e.g., but not limited to, quantum circuit 200) using at least two qubits (e.g., Q1 and Q2) of the plurality of qubits (Q1, Q2, ..., QN) at S602, the at least two qubits being selected by a controller 102 based on the corresponding classical bits (e.g., C1, C2) mapped by the controller 102. The method includes determining the delay of the generated quantum circuit (e.g., quantum circuit 200) at S604. The method further includes selecting at least two qubits of the plurality of qubits so that the generated quantum circuit (e.g., quantum circuit 200) has a delay less than a threshold delay.

[0028] In one embodiment, the method may further include converting a digital input from the controller 102 into an analog input at a microwave frequency to control the quantum state of the corresponding qubit using a plurality of digital-to-analog converters (DACs) 104, each DAC 104 being operatively connected to a corresponding qubit (Q1, Q2, ..., QN) in the plurality of qubits 106 (Q1, Q2, ..., QN).

[0029] In one embodiment, the method may further include selecting at least two qubits that are closest to each other so as to reduce the relative position of the analog conversion units 110 associated with the at least two qubits (e.g., Q1 and Q2). In one embodiment, the delay of the quantum circuit includes a delay of a qubit readout of each of the at least two qubits from quantum to classical. In one embodiment, the delay of the quantum circuit includes a delay caused by classical logic processing in the controller 102 and a delay caused by the relative position of the analog conversion units (ACU) 110.

[0030] Another embodiment of the present invention provides a computer-readable medium having non-transitory computer executable code stored thereon, which, when executed by the controller 102, causes the controller 102 to: (a) map at least two qubits of a plurality of qubits to classical bits; (b) generate a quantum circuit using the at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on the corresponding classical bits mapped by the controller; (c) determine a delay of the generated quantum circuit; and (d) select the at least two qubits of the plurality of qubits such that the generated quantum circuit has a delay less than a threshold delay. In an embodiment, the computer-readable medium may be a memory, a memory stick, a hard disk (HHD), a solid-state drive (SSD), or any other storage medium, such as a network attached storage (NAS) or a storage area network (SAN), etc. In another embodiment, the computer executable code may be downloaded from a remote storage area or from the Internet (e.g., the cloud). In one embodiment, the controller 102 is a classical computer, such as, but not limited to, a desktop computer, a laptop computer, a tablet computer, a handheld computing device, etc.

[0031] In one embodiment, the computer executable code, when executed by the controller 102, causes the controller 102 to control a plurality of analog conversion units (ACUs) 110, each ACU 110 being operatively connected to a corresponding qubit of the plurality of qubits (Q1, Q2, ..., QN) to output a microwave radiation to control a quantum state of the corresponding qubit. In one embodiment, the computer executable code, when executed by the controller 102, causes the controller 102 to select at least two qubits (e.g., Q1 and Q2) that are closest to each other so as to reduce the relative position of the ACUs 110 associated with the at least two qubits (e.g., Q1 and Q2).

[0032] The description of different embodiments of the present invention has been presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A quantum circuit generator for a quantum computer, comprising: Controller; a plurality of analog conversion units (ACUs) operably connected to the controller, each ACU being operably connected to a corresponding qubit of the plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit; wherein the controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits mapped by the controller and based on a delay of the generated quantum circuit, such that the generated quantum circuit has a delay less than a delay threshold, the threshold being less than or equal to a coherence time of the generated quantum circuit.

2. The quantum circuit generator according to claim 1, wherein: The delay of the quantum circuit includes a delay in a qubit readout of each of the at least two qubits from quantum to classical.

3. The quantum circuit generator according to claim 2, wherein: The delay of the quantum circuit includes a delay caused by classical logic processing in the controller and a delay caused by a relative position of the analog conversion unit.

4. The quantum circuit generator according to claim 1, wherein: The delay threshold corresponds to a lowest delay obtained by selecting at least two qubits that are closest to each other so as to reduce a relative position of analog conversion units associated with the at least two qubits.

5. The quantum circuit generator according to claim 1, wherein: Each analog conversion unit ACU includes a field programmable gate array FPGA, an arbitrary waveform generator AWG or an application specific integrated circuit ASIC.

6. The quantum circuit generator according to claim 5, wherein: Each ACU further comprises a local oscillator LO configured to generate low frequency wave radiation and a mixer configured to convert the low frequency wave radiation into higher frequency microwave radiation.

7. The quantum circuit generator according to claim 6, wherein: The higher frequency microwave radiation is generated to control the quantum state of the corresponding qubit.

8. The quantum circuit generator according to claim 6, wherein: Each ACU further comprises at least one bandpass filter configured to filter frequencies of said higher frequency microwave radiation.

9. A quantum computer comprising: a refrigeration container defining a refrigeration chamber therein; a quantum processor disposed inside the refrigeration chamber, the quantum processor comprising a plurality of qubits, at least two qubits of the plurality of qubits being selectable to generate a quantum circuit, the quantum circuit having a delay; wherein the quantum processor may be configured to construct a quantum circuit using a quantum circuit generator in communication with the plurality of qubits, the quantum circuit generator comprising: Controller; a plurality of analog conversion units (ACUs) operably connected to the controller, each ACU being operably connected to a corresponding qubit among the plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit; wherein the controller is configured to generate the quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits mapped by the controller and based on a delay of the generated quantum circuit, such that the generated quantum circuit has a delay less than a delay threshold, the threshold being less than or equal to a coherence time of the generated quantum circuit.

10. The quantum computer according to claim 9, wherein: The controller is a classical computer.

11. The quantum computer according to claim 10, wherein: The delay of the quantum circuit includes a delay in a qubit readout of each of the at least two qubits from quantum to classical.

12. The quantum computer according to claim 11, wherein: The delay of the quantum circuit includes the delay caused by the classical logic processing in the controller and the delay caused by the relative positions of the ACUs.

13. The quantum computer according to claim 9, wherein: The delay threshold corresponds to a lowest delay obtained by selecting at least two qubits that are closest to each other so as to reduce a relative position of digital-to-analog converters associated with the at least two qubits.

14. The quantum computer according to claim 9, wherein: Each ACU includes a field programmable gate array FPGA, an arbitrary waveform generator AWG or an application specific integrated circuit ASIC.

15. The quantum computer according to claim 14, wherein: Each ACU further comprises a local oscillator LO configured to generate low frequency wave radiation and a mixer configured to convert the low frequency wave radiation into higher frequency microwave radiation.

16. A quantum computer according to claim 15, wherein: The higher frequency microwave radiation is generated to control the quantum state of the corresponding qubit.

17. The quantum computer according to claim 15, wherein: Each ACU further comprises at least one bandpass filter configured to filter the frequencies of the higher frequency microwave radiation.

18. A method for reducing delay in a quantum circuit, comprising: mapping at least two qubits of the plurality of qubits to classical bits; generating a quantum circuit using the at least two qubits of the plurality of qubits, the at least two qubits selected by a controller based on corresponding classical bits mapped by the controller; determining the delay of the generated quantum circuit; as well as The at least two qubits of the plurality of qubits are selected such that the generated quantum circuit has a delay less than a delay threshold that is less than or equal to a coherence time of the generated quantum circuit.

19. The method of claim 18, further comprising converting the digital input from the controller into an analog input at a microwave frequency using a plurality of analog conversion units (ACUs), each ACU being operably connected to a corresponding qubit of the plurality of qubits to control the quantum state of the corresponding qubit.

20. The method of claim 19, further comprising selecting at least two qubits that are closest to each other so as to reduce the relative positions of analog conversion units (ACUs) associated with the at least two qubits.

21. The method of claim 19, wherein the delay of the quantum circuit comprises a delay in a qubit readout of each of the at least two qubits from quantum to classical.

22. The method according to claim 21, wherein: The delay of the quantum circuit includes a delay caused by classical logic processing in the controller and a delay caused by a relative position of the analog conversion unit ACU.

23. A computer readable medium having non-transitory computer executable code stored thereon, which, when executed by a controller, causes the controller to: mapping at least two qubits of the plurality of qubits to classical bits; generating a quantum circuit using the at least two qubits of the plurality of qubits, the at least two qubits selected by the controller based on a plurality of corresponding classical bits mapped by the controller; determining a delay of the generated quantum circuit; and The at least two qubits of the plurality of qubits are selected such that the generated quantum circuit has a delay less than a delay threshold that is less than or equal to a coherence time of the generated quantum circuit.

24. The computer readable medium of claim 23, wherein: The computer executable code, when executed by the controller, causes the controller to control a plurality of analog conversion units (ACUs), each ACU being operatively connected to a corresponding qubit of the plurality of qubits, to output microwave radiation to control a quantum state of the corresponding qubit.

25. The computer-readable medium of claim 24, wherein: The computer executable code, when executed by the controller, causes the controller to select at least two qubits that are closest to each other so as to reduce the relative positions of analog conversion units ACU associated with the at least two qubits.

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