Low power current-steering sigma-delta converter

Abstract

Systems and methods in accordance with one or more embodiments provide a low power current-steering digital-to-analog converter. In one example, an apparatus includes a current cell comprising a plurality of switches. The apparatus also includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state prior to the current cell receiving the first data signal. Related systems and methods are also provided.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 16 / 414,600, filed May 16, 2019, entitled “LOW POWER CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER,” which is incorporated herein by reference in its entirety. Technical Field

[0003] According to one or more embodiments, this disclosure relates generally to digital signal processing, and more particularly, for example, to improving the efficiency of low-power digital-to-analog converters. Background Technology

[0004] Many modern devices, such as laptops, tablets, and smartphones, include digital-to-analog converters (DACs) to convert digital audio signals into corresponding analog audio signals. DACs are typically implemented as high-power, high-efficiency current-driven DACs, which include multiple current units configured to generate corresponding analog audio signals. These analog audio signals can then be supplied, for example, to an amplifier output stage to drive speakers. There is a persistent need to reduce the power consumption of modern portable devices and increase their battery life. However, powering down audio circuitry, such as current-driven DACs, can introduce distortion at the DAC's output, leading to a deterioration in audio signal quality. In light of the foregoing, there is a persistent need in the art for improved power efficiency and performance of current-driven DACs. Summary of the Invention

[0005] This document provides novel current-guided digital-to-analog converter systems and methods to address various needs in the art. In one or more embodiments, a device includes a current unit comprising a plurality of switches. The device also includes a current unit controller configured to selectively operate the plurality of switches. The plurality of switches are selectively operated to cause the current unit to generate a current signal in response to a first data signal. The plurality of switches are selectively operated to disable the current unit in the absence of the first data signal. The plurality of switches are selectively operated to transition the current unit to a common-mode state before the current unit receives the first data signal. Related systems and methods are also provided.

[0006] In one or more embodiments, a method of operating a current-directed digital-to-analog converter is provided. The method includes receiving a first data signal by a current unit controller. The method further includes transitioning a current unit to a common-mode state before the current unit receives the first data signal. The method further includes generating a current signal at the current unit in response to the first data signal. The method further includes disabling the current unit in the absence of the first data signal.

[0007] The scope of this disclosure is defined by the claims, which are incorporated herein by reference. A more complete understanding of this disclosure, and the implementation of its additional advantages, will be provided to those skilled in the art through the following detailed description of one or more embodiments. Reference will be made to the accompanying drawings, which will first be briefly described. Attached Figure Description

[0008] A better understanding of aspects and advantages of this disclosure can be achieved by referring to the following accompanying drawings and the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the drawings, wherein the illustrations in the drawings are for illustrative purposes of embodiments of this disclosure and not for limiting the embodiments of this disclosure. The components in the drawings are not necessarily to scale, but rather the emphasis is on clearly illustrating the principles of this disclosure.

[0009] Figure 1 The illustration shows a schematic diagram of an N-bit current-guided digital-to-analog converter according to one or more embodiments of the present disclosure.

[0010] Figure 2A-2D A schematic diagram of a current unit according to one or more embodiments of the present disclosure is illustrated.

[0011] Figure 3 An example current unit switching timing diagram according to one or more embodiments of the present disclosure is illustrated.

[0012] Figure 4 This is a flowchart illustrating a method for operating a current-guided digital-to-analog converter according to one or more embodiments of the present disclosure.

[0013] Figure 5 A block diagram of an example driver amplifier including an N-bit current-guided digital-to-analog converter according to one or more embodiments of the present disclosure is illustrated. Detailed Implementation

[0014] This disclosure describes novel current-guided digital-to-analog converter (DAC) systems and methods that address various needs in the art. For example, the current-guided DACs disclosed herein can be implemented in a variety of devices, such as mobile phones, tablets, wearable devices, listening devices, and portable computers.

[0015] The current-driven DAC disclosed herein can be used, for example, to convert digital audio signals into corresponding analog audio signals for output through a speaker. Many conventional current-driven DACs are implemented for Type A operation, where all current units remain active during periods without a digital input signal. Power savings can be achieved by powering down the DAC current units when there is no digital input signal. However, this approach increases the likelihood of distortion at the DAC output and results in a deterioration in audio signal quality. The systems and methods disclosed herein allow for reduced power consumption of the current-driven DAC without a corresponding degradation in audio signal quality. In various embodiments, for example, the current-driven DAC is implemented in a Type B amplifier driver circuit. It should be understood that the current-driven DAC disclosed herein can be implemented in other types of driver amplifier circuits, such as, for example, Type AB operation and other digital-to-analog implementations.

[0016] Figure 1 A schematic diagram of an exemplary N-bit current-driven digital-to-analog converter 100 according to one or more embodiments of the present disclosure is illustrated. In some embodiments, the N-bit current-driven digital-to-analog converter 100 forms part of an audio amplifier circuit. As illustrated, the N-bit current-driven digital-to-analog converter 100 is implemented as a differential N-bit current-driven digital-to-analog converter.

[0017] like Figure 1 As shown, the N-bit current-guided digital-to-analog converter 100 includes multiple current units 102A-102N, current unit controllers 104A-104N, and delay elements 106A-106N. In some embodiments, the N-bit current-guided digital-to-analog converter 100 includes a conversion circuit 131 to convert a current signal into a corresponding differential voltage signal Vout. The N-bit current-guided digital-to-analog converter 100 includes multiple digital-to-analog converters 101A-101N, wherein each of the digital-to-analog converters 101A-101N includes each of the current units 102A-102N, current unit controllers 104A-104N, and delay elements 106A-106N. In this regard, for example, digital-to-analog converter 101A includes a current unit 102A, a current unit controller 104A, and a delay element 106A; digital-to-analog converter 101B includes a current unit 102B, a current unit controller 104B, and a delay element 106B; and so on for digital-to-analog converters 101C-101N.

[0018] In some embodiments, the N-bit current-guided digital-to-analog converter 100 may be implemented as a 32-bit current-guided digital-to-analog converter, comprising 32 digital-to-analog converters (i.e., 32 current units, 32 current unit controllers, and 32 delay elements). In these embodiments, each of the digital-to-analog converters 101A-101N, current units 102A-102N, current unit controllers 104A-104N, and delay elements 106A-106N may be associated with one bit of the 32-bit current-guided digital-to-analog converter. It should be understood that in other embodiments, N may be greater than or less than 32.

[0019] Each of the digital-to-analog converters 101A-101N receives a corresponding input digital signal 121A-121N. For example, digital-to-analog converter 101A receives input digital signal 121A, digital-to-analog converter 101B receives input digital signal 121B, and so on. It should be understood that the operating characteristics of each of the digital-to-analog converters 101A-101N are the same, and for the sake of brevity, the operation of digital-to-analog converter 101A is described.

[0020] A digital-to-analog converter 101A receives an input digital signal 121A at a delay element 106A. The delay element 106A is coupled between the input digital signal 121A (e.g., an input data signal) and a current unit controller 104A to delay the input digital signal 121A for a certain period of time before it is detected at the current unit controller 104A. At this point, based on the delay applied to the input digital signal 121A by the delay element 106A, the input digital signal 121A is detected (e.g., received by the current unit controller 104A) at a certain time. In some embodiments, the delay element 106A delays the input digital signal 121A for at least one period of clock cycle (e.g., not shown) before passing a delayed input digital signal 114A (e.g., a delayed version of the input digital signal 121A) to the current unit controller 104A. For example, in some cases, the delay element 106A may delay the input digital signal 121A for more than one period of clock cycle. After a delay of one or more clock cycles, the delay element 106A passes the delayed input digital signal 114A to the current unit controller 104A for further processing, as described herein.

[0021] The current unit controller 104A generates a control signal 112A to selectively operate multiple switches of the current unit 102A (e.g., such as...). Figure 2A-2DThe switches 202-207 of the current unit 102 shown are illustrated. The current unit controller 104A can generate a control signal 112A based on (e.g., in response to receiving) an input digital signal 121A and / or a delayed input digital signal 114A, as described herein. In some embodiments, the current unit controller 104A uses the control signal 112A to selectively operate multiple switches of the current unit 102A to cause the current unit 102A to generate a current signal in response to receiving a delayed input digital signal 114A (e.g., an input data signal). Figure 1 As shown, current units 102A-102N provide differential current signals 108A-108N and 109A-109N in the form of differential current signal pairs. At this point, current unit 102A generates differential current signal pairs 108A and 109A, and current units 102B-102N generate their respective differential current signal pairs 108B-N and 109B-N. Additionally, current unit controller 104A selectively operates multiple switches to disable current unit 102A in the absence of a delayed input digital signal 114A (e.g., an input data signal).

[0022] The input digital signal 121A is also received in parallel at the current unit controller 104A and at the delay element 106A. In some embodiments, as described herein, when the input digital signal 121A is received at the current unit controller 104A, the current unit controller 104A selectively operates multiple switches (e.g., such as...) Figure 2A-2D The switches 202-207 of the current unit 102 shown convert the current unit 102A to a common-mode state. In some embodiments, the common-mode state turns on the current unit 102A, and the current of the current unit 102A is confined within the current unit 102A. At this point, in the common-mode state, current does not flow to the output nodes Iop and Ion. With such current flow confined within the current unit 102A, the common-mode voltage associated with the current unit 102A is approximately equal to the common-mode voltage of the conversion circuit 131. The remaining current unit controllers 104B-104N generate corresponding control signals 112B-112N to selectively operate the respective plurality of switches of the current units 102B-102N.

[0023] Conversion circuit 131 is coupled to current units 102A-102N to receive current signals from current units 102A-102N and convert the current signals into corresponding differential voltage signals Vout. At this point, differential current signals 108A-108N and 109A-109N are summed at differential input ports 135 and 136 of differential amplifier 132, respectively. The current signals can be positive, negative, or zero-current (e.g., also referred to as no-current signals). For example, when current unit 102A is in common-mode, the current signal can be zero-current. The voltage signal Vout is provided across differential output ports 138 and 139 of differential amplifier 132. Differential amplifier 132 includes feedback resistors 133 and 134 to convert the current signals (e.g., the total differential current signals 108A-108N and 109A-109N) into the voltage signal Vout.

[0024] Figure 2A-2D A schematic diagram of an exemplary current unit according to one or more embodiments of the present disclosure is illustrated. In particular, Figure 2A-2D Various states of the current unit 102 are shown. In one aspect, the current unit 102 can be... Figure 1 Any one of the current units 102A-102N. Current unit 102 includes switches 202-207 (e.g., using...). Figure 2A-2D The current source is implemented using the p-type metal-oxide-semiconductor (PMOS) transistor 210 in the middle, and (for example, using...) Figure 2A-2D The current sink is implemented using an n-type MOS (NMOS) transistor 212. The current unit controller controls switches 202-207 of the current unit 102 to place the current unit 102 into one of the following states: "off", "1", "-1", or "common-mode". For example, when the current unit 102 is current unit 102A, the current unit controller 104A controls switches 202-207. At this point, Figure 2A , 2B Figures 2C and 2D show the current unit 102 in the "off" state, common mode state, "1" state, and "-1" state, respectively. The "1" state and "-1" state can be referred to as the current conduction state or the "on" state.

[0025] refer to Figure 2AIn the "off" state, switches 202-207 are open, resulting in no current flowing to the differential input ports 135 and 136 of the switching circuit 131. When the current unit 102 is in the "off" state, the node connecting switches 202, 203, and 204 to the drain terminal of the PMOS transistor 210 is approximated as Vdd 231. Vdd 231 is provided at the voltage supply node. In some embodiments, Vdd 231 is a DC voltage source providing approximately 5 volts. In other embodiments, other DC voltages are possible. The node connecting switches 205, 206, and 207 to the drain terminal of the NMOS transistor 212 is approximated as ground 232. Such a node may be referred to as a ground node. Input bias signal 221 is applied to the gate terminal of the PMOS transistor 210, and input bias signal 222 is applied to the gate terminal of the NMOS transistor 212. In one aspect, the input bias signals 221 and 222 are analog bias signals that are nominally maintained at a constant level during the operation of the current unit 102. At this point, the input bias signals 221 and 222 remain unchanged regardless of whether the current unit 102 is in an "off" state, a common-mode state, or a "on" state. For example, at this point, Figure 2A Even when the input bias signals 221 and 222 are at their appropriate bias voltages, the current unit 102 does not generate any current.

[0026] When current unit 102 (e.g., one of current units 102A-102N) transitions from a “off” state to one of a current conduction state (e.g., a “1” state or a “-1” state), an initial current surge flows to the differential input ports 135 and 136 of the differential amplifier 132. This initial current surge generates distortion at the differential output ports 138 and 139 of the differential amplifier 132. A typical method to reduce distortion caused by the change in state of current unit 102 involves maintaining current from current unit 102 to the conversion circuit 131 during the “off” state period. As an example, in audio applications, such a method typically suffers from increased efficiency due to increased power consumption in the N-bit current-guided digital-to-analog converter 100, where there are long periods of low signal (e.g., where most current units are not needed due to low output amplitude) lasting approximately ten to one hundred milliseconds, followed by short periods of high-amplitude signal (e.g., where many current units are needed to construct the high-amplitude signal). In one example, a short period of time can be approximately 1 millisecond. In these applications, for a given current cell, the input digital signal of the current cell can be said to be active during a short period of time when there is an input digital signal provided to the current cell (e.g., 121A is non-zero), and inactive when there is no signal provided to the current cell (e.g., 121A is zero).

[0027] Figure 2B The diagram illustrates the common-mode state of current unit 102 (e.g., 102A). In the common-mode state, switches 203 and 206 are closed. Switches 203 and 206 are associated with a zero-branch path. At this point, the current unit controller (e.g., 104A) receives an input digital signal (e.g., 121A), and if current unit 102 is in the "off" state, the current unit controller generates a control signal (e.g., 112A) to close switches 203 and 206, thereby transitioning current unit 102 from the off state to the common-mode state. The common-mode state turns current unit 102 on and allows current to flow. This current is confined within current unit 102. At this point, in the common-mode state, current does not flow to output nodes Iop and Ion. With such current flow confined within current unit 102, the common-mode voltage associated with the current through the zero-branch path of current unit 102 (e.g., ...) is... Figure 2A-2D As shown, the common-mode voltage of the current unit 102 is approximately equal to that of the switching circuit (e.g., 131). The common-mode state of the current unit 102 provides a short period of time approximately equivalent to one or more clock cycles, such that the common-mode voltages of the current unit 102 and the switching circuit are approximately equal before receiving control signals from the current unit controller (e.g., after those control signals for closing switches 203 and 206) to transition the current unit 102 to the on state, as shown. Figure 2C and 2D As shown in the diagram.

[0028] Figure 2C and 2D The diagram illustrates the conduction state of current unit 102. A current unit controller (e.g., 104A) generates a control signal (e.g., 112A) to close switches 202 and 207, causing current unit 102 to generate differential current signals (e.g., 108A and 109A) to produce a "1" state at the output nodes Iop and Ion of current unit 102. In the "1" state, current flows from the node associated with Vdd 231 through switch 202 to the output node Iop, and current flows from ground 232 through switch 207 to the output node Ion. (Reference) Figure 2D The current unit controller (e.g., 104A) generates control signals (e.g., 112A) to close switches 204 and 205, causing current unit 102 to generate differential current signals (e.g., 108A and 109A) to produce a "-1" state at the output nodes Iop and Ion of current unit 102. In the "-1" state, current flows from the node associated with Vdd 231 through switch 204 and to the output node Ion, and current flows from ground 232 through switch 205 and to the output node Iop. Whether current unit 102 transitions to a "1" state or a "-1" state is based on the value of the input data signal (e.g., an audio signal) provided to current unit 102. In one aspect, the control signal 112A of current unit controller 104A collectively represents control signals for transitioning current unit 102A to a common-mode state and control signals for transitioning current unit 102A to the appropriate on state.

[0029] Figure 3 An exemplary current unit switching timing diagram according to one or more embodiments of the present disclosure is illustrated. Figure 3 A first time period 341 is defined, during which the input digital signal (e.g., 121A) is in an inactive state. In a second time period 344, the input data signal is in an active state, where it is received as an input data pulse signal. When the current unit controller (e.g., 104A) receives the input digital signal (e.g., 121A) and if the current unit 102 is in a "off" state, the current unit controller generates a control signal (e.g., 112A) suitable for closing switches 203 and 206 to transition the current unit 102 from the off state to a common-mode state. During time period 344, the current unit 102 is in a common-mode state. Figure 3As shown, the current unit 102 is in a common-mode state before a delayed version of the input digital signal (e.g., a delayed input digital signal 114A) is provided to the current unit controller by a delay element (e.g., 106A).

[0030] After time period 344, a delayed input digital signal (e.g., 114A) is output from delay element 106 and provided to the current unit controller, which selectively operates switches 202-207 to cause current unit 102 to generate a current signal in response to a first edge transition of the delayed input digital signal (e.g., an input data pulse signal) corresponding to an on state (e.g., a "1" or "-1" state). The value of the delayed input digital signal determines whether current unit 102 is in an "1" state or a "-1" state. During time period 342, the delayed input digital signal is in an active state, and current unit 102 is in an on state. The current unit controller selectively operates switches 202-207 to disable current unit 102 in response to a second edge transition of the delayed input digital signal (e.g., an input data pulse signal) corresponding to an off state. In this respect, current unit 102 is disabled (e.g., placed in a disabled state) by appropriately controlling switches 202-207 by the current unit controller to transition current unit 102 from an on state (e.g., a "1" or "-1" state) to an off state. A second edge transition indicates the delayed input digital signal transitioning from active to inactive.

[0031] During time period 345, the delayed input digital signal is inactive. During time period 347, current unit 102 is in the off state. During time period 348, current unit 102 is in common-mode state. During time period 346, the delayed input digital signal is active, and current unit 102 is in the on state (e.g., based on a 1 or -1 state of the delayed input digital signal). Depending on the situation, the current unit controller selectively operates switches 202-207 to transition between the various states of current unit 102.

[0032] Figure 4 This is a flowchart illustrating a method 400 for operating a current-guided digital-to-analog converter according to one or more embodiments of the present disclosure. Method 400 begins with the operation of step 401. In one embodiment, a current unit (e.g., 102A) receives a delayed input digital signal (e.g., 114A) from a current unit controller (e.g., 104A) and provides the corresponding current signal to a conversion circuit (e.g., 131). For example, the conversion circuit converts the current signal into a voltage signal Vout, which is passed to an amplifier for amplification before being sent to a speaker.

[0033] Method 400 may further include determining whether the next signal is another delayed input digital signal (step 402). If the next signal is another delayed input digital signal, the method proceeds to step 401. In some embodiments, if the next signal is not another delayed input digital signal, method 400 proceeds to step 403. Step 403 may include disabling the current unit in the absence of an input digital signal at the delay element (e.g., 106A). In some embodiments, the current unit controller selectively operates the switches (e.g., 202-207) of the current unit to disable the current unit.

[0034] Method 400 may further include determining whether the next signal is a subsequently delayed input digital signal (step 404). If the next signal is not a subsequently delayed input digital signal, method 400 moves to hold at step 404. If the subsequent signal is a delayed input digital signal, the method moves to step 405. Step 405 may include the operation of a current unit controller receiving an input digital signal (e.g., 121A), and if the current unit is in a "off" state, the current unit controller generates a control signal (e.g., 112A) to selectively operate the switch of the current unit to transition the current unit to a common-mode state. At this point, the current unit is turned on and provides current flow restricted within the current unit. The common-mode voltage associated with the current unit is approximately equal to the common-mode voltage of the switching circuit. Method 400 may then return to step 401, where the next delayed input digital signal 114 is received at current unit 102.

[0035] Figure 5 An exemplary block diagram of a driver amplifier including an N-bit current-guided digital-to-analog converter 100 is illustrated according to one or more embodiments of the present disclosure. Figure 5 As shown, the circuitry for driving speaker 541 may include an N-bit current-guided digital-to-analog converter (DAC) 100 and an amplifier 540. In some embodiments, the N-bit current-guided DAC 100 may operate in a Type B amplifier driver circuit, wherein amplifier 540 is a Type B amplifier. In other embodiments, the N-bit current-guided DAC may operate in a Type AB amplifier driver circuit, wherein amplifier 540 is a Type AB amplifier. In some embodiments, the N-bit current-guided DAC 100 may be implemented as a 32-bit current-guided DAC, but in other embodiments, current-guided DACs with other bit resolutions are possible.

[0036] Where applicable, the various embodiments provided by this disclosure may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, the various hardware and / or software components described herein may be combined into composite components comprising software, hardware, and / or both, without departing from the spirit of this disclosure. Where applicable, the various hardware and / or software components described herein may be divided into sub-components comprising software, hardware, or both, without departing from the scope of this disclosure. Additionally, where applicable, software components are contemplated to be implemented as hardware components. Where applicable, the order of the various steps described herein may be changed, combined into composite steps, and / or divided into sub-steps to provide the features described herein.

[0037] The foregoing disclosure is not intended to limit this disclosure to the precise form disclosed or to any particular field of use. Therefore, various alternative embodiments and / or modifications to this disclosure (whether expressly described or implied herein) are expected to be possible. Embodiments of this disclosure have been so described, and those skilled in the art will recognize that changes in form and detail may be made without departing from the scope of this disclosure. Therefore, this disclosure is limited only by the claims.

Claims

1. A current-steering digital-to-analog converter, comprising: a current cell comprising a plurality of switches; and a current cell controller configured to selectively operate the plurality of switches to: cause the current cell to generate a current signal in response to a first data signal comprising a first input data pulse signal and a second input data pulse signal; enable the current cell in response to a first edge transition of the first input data pulse signal and transition to a common mode state prior to a first edge of the second input data pulse signal; output a differential signal upon occurrence of a first edge transition of the second input data pulse signal; and disable the current cell in response to a second edge transition of the first input data pulse signal.

2. The current-steering digital-to-analog converter of claim 1, wherein the current cell further comprises a current source and / or a current sink coupled to the plurality of switches.

3. The current-steering digital-to-analog converter of claim 1, further comprising a delay element coupled to the current cell controller, wherein the delay element is configured to delay a first transition edge of the first data signal to obtain a first transition edge of a second data signal.

4. The current-steering digital-to-analog converter of claim 1, further comprising a delay element coupled to the current cell controller, wherein the delay element is configured to delay a second transition edge of a second data signal for a period of time to obtain a second transition edge of the first data signal.

5. The current-steering digital-to-analog converter of claim 4, wherein the delay element is configurable.

6. The current-steering digital-to-analog converter of claim 1, further comprising a conversion circuit coupled to the current cell, wherein the conversion circuit is configured to receive the current signal from the current cell and convert the current signal to a corresponding voltage signal. in the common mode state: the current cell is configured to allow current flow from a voltage supply node to a ground node, and 7. The current-steering digital-to- analog converter of claim 6, wherein, a common mode voltage associated with the current cell is approximately equal to a common mode voltage associated with the conversion circuit.

8. The current-steering digital-to-analog converter of claim 1, wherein the current- steering digital-to-analog converter comprises an N-bit digital-to-analog converter comprising a plurality of digital-to-analog converters.

9. The current-steering digital-to-analog converter of claim 8, wherein each digital-to-analog converter comprises at least one of each of the current cell, the current cell controller, and the delay element.

10. The current-steering digital-to-analog converter of claim 1, wherein each of the plurality of switches comprises a metal oxide semiconductor transistor.

11. A method of operating a current-steering digital-to-analog converter, the method comprising: receiving, by a current cell controller, a first data signal comprising a first input data pulse signal and a second input data pulse signal and causing a current cell to generate a current signal in response to the first data signal; enabling the current cell in response to a first edge transition of the first input data pulse signal; ​ ​ transitioning the current cell to a common mode state prior to receiving a first edge of the second input data pulse signal; generating a differential signal upon a first edge transition of the second input data pulse signal; and disabling the current cell in response to a second edge transition of the first input data pulse signal.

12. The method of claim 11, wherein the transitioning comprises selectively operating a plurality of switches of the current cell by the current cell controller.

13. The method of claim 12, wherein the current cell further comprises a current source and / or a current sink coupled to the plurality of switches.

14. The method of claim 11, further comprising delaying a first transition edge of the first data signal by a delay element to obtain a first transition edge of a second data signal.

15. The method of claim 11, further comprising delaying a second transition edge of a second data signal by a delay element for a period of time to obtain a second transition edge of the first data signal.

16. The method of claim 15, further comprising: receiving the second data signal by the current cell controller, and if the current cell is in a disabled state, transitioning the current cell to the common mode state by the current cell controller prior to the current cell receiving the first data signal.

17. The method of claim 11, further comprising: receiving the current signal by a conversion circuit; and converting the current signal to a corresponding voltage signal by the conversion circuit.

18. The method of claim 17, wherein, in the common mode state, the current cell allows current flow from a voltage supply node to a ground node, and a common mode voltage associated with the current cell is approximately equal to a common mode voltage associated with the conversion circuit.

19. The method of claim 11, wherein the current steering digital to analog converter comprises an N-bit digital to analog converter, the N-bit digital to analog converter comprising a plurality of digital to analog converters, and wherein each digital to analog converter comprises at least one of each of the current cell, the current cell controller, and a delay element.

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