Data type selection based on application

Abstract

Methods, systems, and apparatus related to application-based data type selection are described. A processing device performs operations such as monitoring performance characteristics associated with various applications executed by a host computing device to determine whether a threshold performance level has been reached or exceeded. Based at least in part on the determination, operations such as converting data types utilized by the various applications from a first format that supports arithmetic operations at a first level of precision to a second format that supports arithmetic operations at a second level of precision may be performed.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly to devices, systems, and methods for application-based data type selection. Background Art

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits within a computer or other electronic system. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory provides permanent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. For example, data, commands, and / or instructions may be transferred between the host and the memory device during operation of the computing or other electronic system. Summary of the Invention

[0004] Aspects of the present disclosure provide a method for application-based data type selection, wherein the method includes: monitoring, by a processing device 122, performance characteristics associated with at least one application executed by the processing device 122 or a host 102 coupled to the processing device 122; determining, by the processing device 122, that the performance characteristics associated with the at least one application have reached a threshold performance level; and performing, by the processing device 122, at least in part based on the determination, converting a data type utilized by the at least one application from a first format that supports arithmetic operations at a first level of precision to a second format that supports arithmetic operations at a second level of precision.

[0005] Another aspect of the present disclosure provides an apparatus for application-based data type selection, wherein the apparatus includes: a processing device 122 and a memory resource 124 configured as a cache for the processing device 122, wherein the processing device 122 is configured to: monitor performance characteristics associated with execution of applications executed by the processing device 122 or a host 102 coupled to the processing device 122; determine that performance characteristics associated with at least one application using data formatted according to a first format supporting arithmetic operations at a first level of precision has reached a threshold performance level; perform an operation based at least in part on the determination to convert the data utilized by the at least one application from the first format to a second format supporting arithmetic operations at a second level of precision; and cause execution of the at least one application using the data formatted according to the second format.

[0006] Another aspect of the present disclosure provides an apparatus for application-based data type selection, wherein the apparatus includes: a processing device 122 and a memory resource 124 configured as a cache for the processing device 122, wherein the processing device 122 is configured to: monitor characteristics of a plurality of applications executed by the processing device; determine an application type of a particular application based on the monitored characteristics of the particular application; determine a data type utilized by the particular application, wherein the data type includes data formatted in a first format supporting arithmetic operations at a first level of precision or data formatted in a second format supporting arithmetic operations at a second level of precision; determine that a performance characteristic corresponding to one of the first format or the second format is greater than a threshold application performance characteristic; perform an operation of converting the data from the first format or the second format to the other of the first format or the second format based on the determination that the performance characteristic of the particular application using the other of the first format or the second format is greater than the threshold application performance characteristic; and execute the application using the data formatted in the converted format.

[0007] Another aspect of the present disclosure provides a system for application-based data type selection, wherein the system includes: a host 102; a processing device 122 coupled to the host 102; and a component 123 configured to generate performance characteristics, the component 123 being coupled to the processing device 122, wherein the processing device 122 is configured to: receive the performance characteristics generated by the component 123 and corresponding to the execution of an application executed by the host; analyze the performance characteristics to determine that at least one performance characteristic change has occurred relative to at least one application; perform the following operations based at least in part on the determination: convert data utilized by the at least one application from a first format that supports arithmetic operations at a first level of precision to a second format that supports arithmetic operations at a second level of precision; and execute the at least one application using the data formatted according to the second format. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a functional block diagram of an apparatus including a host and a memory device according to several embodiments of the present disclosure.

[0009] Figure 2A is a functional block diagram of a computing system including an apparatus including a host and a memory device according to several embodiments of the present disclosure.

[0010] Figure 2B is another functional block diagram in the form of a computing system including a host, a memory device, an application specific integrated circuit, and a field programmable gate array according to several embodiments of the present disclosure.

[0011] Figure 3 is an instance of n bit positions with es exponent bits.

[0012] Figure 4A is an example of a positive value in the 3-bit position.

[0013] Figure 4B is an instance constructed using the position of two exponent bits.

[0014] Figure 5 is a flowchart representing an example method for application-based data type selection according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Methods, systems, and apparatus related to application-based data type selection are described. A processing device performs operations such as monitoring performance characteristics associated with various applications executed by a host computing device to determine whether a threshold performance level has been reached or exceeded. Based at least in part on the determination, operations such as converting data types utilized by the various applications from a first format that supports arithmetic operations at a first level of precision to a second format that supports arithmetic operations at a second level of precision may be performed.

[0016] As used herein, "precision" refers to the number of bits in a bit string used to perform a calculation using a bit string. For example, if each bit in the bit string is used when performing a calculation using a 16-bit bit string, the bit string can be referred to as having 16 bits of precision. However, if only 8 bits of the bit string are used when performing a calculation using a 16-bit bit string (for example, if the first 8 bits of the bit string are zero), the bit string can be referred to as having 8 bits of precision. As the precision of the bit string increases, calculations can be performed with higher accuracy. On the contrary, as the precision of the bit string decreases, calculations can be performed using lower accuracy. For example, an 8-bit bit string can correspond to a data range consisting of two hundred and fifty-five (256) precision steps, while a 16-bit bit string can correspond to a data range consisting of sixty-five thousand five hundred and thirty-six (63,536) precision steps.

[0017] As used herein, "dynamic range" or "dynamic range of data" refers to the ratio between the maximum and minimum values that can be used for a bit string having a particular precision associated therewith. For example, the maximum numeric value that can be represented by a bit string having a particular precision associated therewith can determine the dynamic range of the data format of the bit string. For a bit string in a general number (e.g., position) format, the dynamic range can be determined by the exponent bit subset of the bit string (e.g., Figure 3 and Figure 4A-4B The value of es) described is determined.

[0018] The dynamic range and / or precision can have a variable range threshold associated with it. For example, the dynamic range of the data can correspond to the applications that use the data and / or the various calculations that use the data. This may be due to the fact that the dynamic range expected by one application may be different from the dynamic range expected by another application, and / or because some calculations may require different dynamic ranges for the data. Therefore, the embodiments herein can allow the dynamic range of the data to be changed to suit the requirements of different applications and / or calculations. In contrast to methods that do not allow the precision, accuracy and / or dynamic range of the data to be manipulated to suit the requirements of different applications and / or calculations, the embodiments herein can improve resource utilization and / or data accuracy by allowing the dynamic range of the data to be changed based on the applications and / or calculations that are going to use the data.

[0019] Additionally, some embodiments may allow for conversion of data between various data types based on the computing application using the data. For example, a data type that may be more suitable for use with a financial computing application may differ from a data type that may be more suitable for use with an astronomical computing application. Similarly, a data type that may be more suitable for use with an edge computing application may differ from a data type that may be more suitable for use with a financial or astronomical computing application. Thus, in some embodiments, conversion between data types may be performed based on the computing application using the data in order to improve the overall performance of the application and / or the computing system executing the application.

[0020] The computing system can be used to perform a wide range of operations using such data (e.g., bit strings), as well as to perform computations using data that can be processed by the computing system to facilitate the operation of the computing system. Such operations can involve large data sets and / or large bit strings and, thus, can require significant computing resources (e.g., processing and / or memory resources) when executed. Some examples of operations that can be performed using the computing system can include arithmetic operations, logical operations, bitwise operations, vector operations, and / or dot product operations, as well as recursive operations such as accumulate operations, multiply-accumulate (MAC) operations, fused multiply-add (FMA) operations, and / or fused multiply-accumulate (FMAC) operations, among others.

[0021] As part of providing functionality associated with the execution of a computing application, these and other operations may be performed during the execution of the computing application. As used herein, a "computing application" generally refers to a program or group of programs that, when executed by a computing system, performs one or more functions or activities. Non-limiting examples of computing applications may include astronomical applications (e.g., computing applications designed to perform calculations related to astronomical imaging, global positioning systems, and / or communication satellites, etc.), atomic applications (e.g., computing applications based on quantum computing in which scalable computing systems utilize the properties of individual atoms to perform various calculations), and / or financial applications (e.g., computing applications designed to perform calculations related to financial technology, or "FinTech," in which specialized computing applications are used to perform financial operations, processing programs, and / or other financial services).

[0022] Additional non-limiting examples of computing applications may include edge computing applications (e.g., applications utilized by distributed computing systems that bring computing and data storage devices physically closer to where the data users are located), such as autonomous vehicle applications, data center applications, personalized medicine applications, network security applications, augmented reality applications, virtual reality applications, Internet of Things applications, smart city embedded applications, and / or portable embedded computer applications, etc.

[0023] Because computing systems can perform a variety of operations, which can include various calculations in the process of executing computing applications, bit strings with varying degrees of accuracy, precision, and / or dynamic range may be required for different operations and / or computing applications. However, computing systems have a limited amount of memory in which to store operands on which calculations are performed. To facilitate performing operations on operands stored by the computing system within the constraints imposed by limited memory resources, operands may be stored in a specific format and / or as a specific data type. For simplicity, such formats are referred to as "floating point" formats or "floating point" (e.g., IEEE 754 floating point format).

[0024] According to the floating-point standard, a bit string (e.g., a bit string that can represent a number), such as a binary number string, is represented in terms of three sets of integers or bits: a one-bit set called the "base," a one-bit set called the "exponent," and a one-bit set called the "mantissa" (or significand). The integer sets or bit sets define the format in which the binary number string is stored and, for simplicity, may be referred to herein as the "numeric format" or "format." For example, the three integer sets (e.g., base, exponent, and mantissa) that define the aforementioned bits of a floating-point bit string may be referred to as a format (e.g., a first format). As described in more detail below, a positional bit string may include four integer sets or bit sets (e.g., sign, base, exponent, and mantissa), which may also be referred to as the "numeric format" or "format" (e.g., a second format). Additionally, according to the floating-point standard, two infinite values (e.g., +∞ and -∞) and / or two types of "not-a-number (NaN)" values (quiet NaN and signaling NaN) may be included in the bit string.

[0025] The floating-point standard has been used in computing systems for several years and defines arithmetic formats, interchange formats, rounding rules, operations, and exception handling for calculations performed by many computing systems. Arithmetic formats may include binary and / or decimal floating-point data, which may include finite numbers, infinite numbers, and / or the special NaN value. Interchange formats may include encodings (e.g., bit strings) that can be used to interchange floating-point data. Rounding rules may include a set of properties that may be satisfied when rounding values during arithmetic operations and / or conversion operations. Floating-point operations may include arithmetic operations and / or other computational operations, such as trigonometric functions. Exception handling may include indications of exceptional conditions, such as division by zero, overflow, and the like.

[0026] An alternative format for floating-point is called a "universal number" (UNUM) format. There are several forms of UNUM formats that can be referred to as "positions" and / or "significands"—Type I UNUM, Type II UNUM, and Type III UNUM. Type I UNUM is a superset of the IEEE 754 standard floating-point format that uses a "ubit" at the end of the mantissa to indicate whether the real number is an exact floating-point number or whether it is in an interval between adjacent floating-point numbers. The sign, exponent, and mantissa bits in a Type I UNUM obtain their definitions from the IEEE 754 floating-point format. However, the length of the exponent and mantissa fields of a Type I UNUM can vary significantly from a single bit to a maximum user-definable length. By obtaining the sign, exponent, and mantissa bits from the IEEE 754 standard floating-point format, a Type I UNUM can behave similarly to a floating-point number. However, the variable bit lengths present in the exponent and fraction bits of a Type I UNUM may require additional management compared to floating-point numbers.

[0027] Type II unums are generally incompatible with floating point numbers, however, they can allow for clean mathematical design based on projected real numbers. A type II unum can contain n bits and can be described in terms of a "u-lattice" where the quadrants of a circular projection are filled with 2 n-3 -1 real number. The values of a Type II unum can be reflected around an axis that divides the circular projection into equal parts, so that positive values are located in the upper right quadrant of the circular projection, while their negative counterparts are located in the upper left quadrant of the circular projection. The lower half of the circular projection representing a Type II unum can contain the reciprocal of the value located in the upper half of the circular projection. Type II unums generally rely on lookup tables for most operations. Therefore, in some cases, the size of the lookup table can limit the effectiveness of Type II unums. However, compared to floating-point numbers under some conditions, Type II unums can provide improved calculation functions.

[0028] The III type unum format is referred to as "position format" or "position" for simplicity herein. Compared with floating-point bit strings, positions can allow higher precision (e.g., wider dynamic range, higher resolution and / or higher accuracy) than floating-point numbers with the same bit width according to certain conditions. This can allow the operations performed by the computing system to be performed at a higher rate (e.g., faster) than when using floating-point numbers when using positions, which in turn can improve the performance of the computing system by, for example, reducing the number of clock cycles used when performing the operations and / or reducing the processing time and / or power consumed when performing such operations. In addition, compared with floating-point numbers, using positions in computing systems can achieve higher accuracy and / or precision, which can further improve the functionality of the computing system compared with certain methods (e.g., methods that rely on floating-point format bit strings).

[0029] Positions can vary greatly in precision and accuracy based on the total number of bits and / or the number of integer sets or bit sets contained in the position. In addition, positions can produce a wide dynamic range. Under certain conditions, the accuracy, precision, and / or dynamic range of a position can be greater than the accuracy, precision, and / or dynamic range of a floating or other digital format, as described in more detail herein. The variable accuracy, precision, and / or dynamic range of a position can be manipulated, for example, based on the application in which the position will be used. In addition, the position can reduce or eliminate overflow, underflow, NaN, and / or other extreme cases associated with floating-point numbers and other digital formats. Furthermore, using positions allows for the use of fewer bits to represent a numerical value (e.g., a number) compared to floating-point numbers or other digital formats.

[0030] In some embodiments, these features can allow for highly reconfigurable locations, which can provide improved application performance compared to methods that rely on floating point numbers or other digital formats. Additionally, these features of locations can provide improved performance in machine learning applications compared to floating point numbers or other digital formats. For example, in machine learning applications where computational performance is critical, locations can be used to train a network (e.g., a neural network) with the same or higher accuracy and / or precision as floating point numbers or other digital formats, but using fewer bits than floating point numbers or other digital formats. Additionally, locations with fewer bits (e.g., a smaller bit width) than floating point numbers or other digital formats can be used to implement inference operations in machine learning scenarios. By using fewer bits than floating point or other digital formats to achieve the same or enhanced results, the use of locations can therefore reduce the amount of time to perform operations and / or reduce the amount of memory space required in an application, which can improve the overall functionality of the computing system in which locations are employed.

[0031] Embodiments herein relate to hardware circuitry (e.g., control circuitry) configured to perform various operations on bit strings to improve the overall functionality of a computing device. For example, embodiments herein are directed to hardware circuitry configured to monitor various performance characteristics of an application during execution (e.g., at runtime) to determine whether application performance can be altered by employing a data type different from the data type currently being used by the application. As used herein, "data type" generally refers to the format in which data, such as a bit string, is provided to an application. Non-limiting examples of data types may include floating-point bit strings, general-purpose bit strings, positional bit strings, and / or fixed-point binary bit strings, among others. The term "data type" may be used interchangeably with the term "data format." In some embodiments, the hardware circuitry may alter the data type currently being used by the application in response to determining that application performance could be improved if a different data type were provided to the application. To achieve this, the hardware circuitry may be configured to perform a conversion operation on the bit string being used by the application to convert the data type from one data type to another and render the converted bit string available to the application.

[0032] Application performance can be measured in terms of various performance characteristics. As used herein, "performance characteristics" can include application response time, number of application errors, collected user satisfaction metrics, application dependency types, transaction traces associated with the application, application errors attributable to iterations, power consumption associated with the application, data precision or accuracy generated when executing the application using data in a first format or data in a second format, latency parameters associated with the application, and / or reliability parameters associated with the application, among others.

[0033] Compared to an approach in which an application is executed using static data types, the embodiments described herein may allow for improved application performance by dynamically adjusting the data types used by the application to maximize application performance. That is, compared to an approach that operates using a single data type (e.g., a floating-point data type) without regard to application performance, the embodiments described herein may allow for conversion of data types (e.g., to a universal number or positional data type) in response to determining that application performance may be improved using a universal number or positional data type.

[0034] Additionally, in approaches that do not allow conversion between data types used by an application based on the application's performance characteristics, the application's performance characteristics may not be monitored or analyzed. In contrast, embodiments herein may allow such performance characteristics to be monitored during application execution, which may provide a more comprehensive understanding of application performance, particularly across different applications that may be executed in a computing system to perform various tasks and / or functions.

[0035] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part hereof and in which is shown by way of illustration the manner in which one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the embodiments of the present disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

[0036] As used herein, designators such as "N" and "M" specifically with respect to a reference numeral in a drawing may include a plurality of the particular feature so designated. It should also be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" may include both singular and plural referents, unless the context clearly dictates otherwise. Additionally, "a plurality," "at least one," and "one or more" (e.g., a plurality of memory banks) may refer to one or more memory banks, while "a plurality" is intended to refer to more than one such thing.

[0037] In addition, the words "may" and "can" are used throughout this application in a permissive sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to". Depending on the context, the term "coupled" or "coupling" means physically connecting or accessing and moving (transmitting) commands and / or data, directly or indirectly. Depending on the context, the terms "bit string", "data" and "data value" are used interchangeably herein and may have the same meaning. In addition, depending on the context, the terms "bit set", "bit subset" and "portion" (in the case of a portion of the bits of a bit string) are used interchangeably herein and may have the same meaning.

[0038] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 120 may represent Figure 1 Component "20" in the example, and similar components can be found in Figure 2A220. Generally, a single reference numeral may be used herein to refer to multiple similar elements or components or groups of elements or components. For example, multiple reference elements 431-1, 431-2, ..., 431-N may be collectively referred to as 431. As will be appreciated, elements shown in the various embodiments herein may be added, exchanged, and / or removed to provide several additional embodiments of the present disclosure. In addition, the proportions and / or relative scales of the elements provided in the drawings are intended to illustrate certain embodiments of the present disclosure and should not be construed in a limiting sense.

[0039] Figure 1 1 is a functional block diagram of a computing system 100 in the form of an apparatus including a host 102 and a memory device 104, according to several embodiments of the present disclosure. As used herein, "apparatus" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. Memory device 104 may include one or more memory modules (e.g., a single in-line memory module, a dual in-line memory module, etc.). Memory device 104 may include volatile memory and / or non-volatile memory. In several embodiments, memory device 104 may include a multi-chip device. A multi-chip device may include several different memory types and / or memory modules. For example, a memory system may include non-volatile or volatile memory on any type of module.

[0040] like Figure 1 As shown, device 100 may include control circuitry 120 and memory array 130. Control circuitry 120 may include processing device 122, application performance management (APM) component 123, and memory resources 124. Each of these components (e.g., host 102, control circuitry 120, processing device 122, memory resources 124, and / or memory array 130) may be individually referred to herein as a "device."

[0041] Memory device 104 can provide main memory for computing system 100 or can be used as additional memory or storage throughout computing system 100. Memory device 104 can include one or more memory arrays 130 (e.g., an array of memory cells), which can include volatile and / or non-volatile memory cells. For example, memory array 130 can be a flash array having a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, memory device 104 can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, flash memory, and the like.

[0042] In embodiments where the memory device 104 includes nonvolatile memory, the memory device 104 may include a flash memory device, such as a NAND or NOR flash memory device. However, embodiments are not limited thereto, and the memory device 104 may include other nonvolatile memory devices, such as nonvolatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices such as variable resistance (e.g., 3-D cross-point (3D XP) memory devices), memory devices including self-select memory (SSM) cell arrays, or the like, or combinations thereof. Variable resistance memory devices can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Additionally, compared to many flash-based memories, variable resistance nonvolatile memories can perform write-in-place operations, where nonvolatile memory cells can be programmed without first erasing the nonvolatile memory cells. Compared to flash-based memories and variable resistance memories, self-select memory cells can include memory cells having a single chalcogenide material that serves as both the switch and the storage element of the memory cell.

[0043] like Figure 1 As illustrated in , host 102 may be coupled to memory device 104. In several embodiments, memory device 104 may be coupled to host 102 via one or more channels (e.g., channel 103). Figure 1 , memory device 104 is coupled to host 102 via channel 103, and memory device 104 control circuitry 120 is coupled to memory array 130 via channel 107. Host 102 may be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, a memory card reader, and / or an Internet of Things (IoT) enabled device, among various other types of hosts.

[0044] The host 102 may include a system motherboard and / or backplane and may include a memory access device, such as a processor (or processing device). One of ordinary skill in the art will understand that a "processor" may be one or more processors, such as a parallel processing system, multiple coprocessors, etc. The system 100 may include a separate integrated circuit or both the host 102 and the memory device 104, and the memory array 130 may be on the same integrated circuit. For example, the system 100 may be a server system and / or a high performance computing (HPC) system and / or a portion thereof. Although Figure 1 The example shown in illustrates a system having a Von Neumann architecture, but embodiments of the present disclosure may be implemented in a non-Von Neumann architecture, which may not include one or more components typically associated with a Von Neumann architecture (e.g., a CPU, ALU, etc.).

[0045] This article is in Figure 2A 104 may include control circuitry 120, which may include processing means 122 and memory resources 124. That is, in some embodiments, control circuitry 120 (as well as processing means 122 and memory resources 124) may reside on memory device 104. As used herein, the term "residing on" refers to something being physically located on a particular component. For example, control circuitry 120 "residing on" refers to a condition in which the hardware, including control circuitry 120, is physically located on memory device 104. The term "residing on" may be used interchangeably herein with other terms such as "deployed on" or "located on"

[0046] The processing device 122 may be provided in the form of an integrated circuit, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a reduced instruction set computer (RISC), an advanced RISC machine, a system on a chip, or other combination of hardware and / or circuitry configured to perform the operations described in more detail herein. In some embodiments, the processing device 122 may include one or more processors (e.g., processing devices, processing units, etc.). The processing device 122 may monitor applications executed by the host 102 to determine performance characteristics of the applications at runtime. In addition, as part of executing a computing application, the processing device may perform operations (e.g., operations to convert bit strings between various data types, recursive operations, or other computing operations described below) using bit strings stored in the memory resources 124, the memory array 130, and / or provided by the host 102.

[0047] The processing device 122 may be configured to monitor performance characteristics of the application during runtime of the application, such as application response time, number of application errors, collected user satisfaction metrics, application dependency types, transaction traces associated with the application, application errors attributable to iterations, power consumption associated with the application, data precision or accuracy generated when executing the application using data in a first format or data in a second format, latency parameters associated with the application, and / or reliability parameters associated with the application, etc.

[0048] Application response time can be the amount of time it takes for an application to return the results of a submitted request to an end user. Application response time can be affected by bandwidth, the number of submitted user requests, and / or processing time. Application response time can also be affected by the type of data being used by the application. For example, because different data types can contain different numbers of bits (e.g., can be of different sizes), can have different accuracy characteristics associated therewith, etc., application response time can depend on the type of data used by the application during application runtime.

[0049] The number of application errors may be the number of errors experienced by an application during runtime. Application errors may be caused by application conflicts or other bugs that may threaten the stability of the application. In some cases, since the application is in use when the error occurs, the number of application errors may be reduced by executing the application using different data types during application runtime.

[0050] The collected user satisfaction metrics may be generated using feedback provided by users of the application. For example, application users may be asked to enter a satisfaction score associated with the use of the application. These satisfaction scores may be aggregated and assigned to different applications. In some embodiments, the user satisfaction metric may be associated with executing a particular application using different data types. If the user satisfaction metric for a particular application corresponds to a higher user satisfaction score when a particular data type is used with the application, the processing device 122 may convert the data used by the application into the data type that exhibits the highest user satisfaction score and execute the application using that data type.

[0051] The types of application dependencies may correspond to the code libraries and parts used when executing a particular computing application. If one or more application dependencies do not function properly, the execution of the application may be adversely affected. Furthermore, the types of data used by the application may influence the dependencies. Therefore, some data types may mitigate issues arising from application dependencies.

[0052] A transaction trace associated with an application may contain a detailed snapshot of a single transaction in the application. In some embodiments, the transaction trace may be monitored and captured by the application performance management (APM) component 123. The transaction trace may provide detailed information about the application's behavior and may accordingly be used to determine whether the application may benefit from using data formatted in a different data type.

[0053] Application errors attributed to iterations may correspond to a tendency for the application to cause more errors over time. For example, for some applications, the longer the application is executed, the greater the number of errors caused during the execution of the application. In some embodiments, such errors can be reduced by selecting data types for use by the application that mitigate the tendency to cause errors over time.

[0054] The power consumption associated with an application may correspond to the amount of power consumed in terms of processing resources used by the executing application and / or in terms of battery consumption in the case of a mobile computing device (e.g., a laptop computer, a smartphone, etc.). In some embodiments, the amount of power consumed when the application executes may be altered based on the type of data used by the application. For example, some data types may correspond to reduced power consumption of the application, while other data types may correspond to increased power consumption of the application.

[0055] The precision or accuracy of data produced when executing an application using data in the first format or data in the second format may correspond to the behavior of the data type when executed by the particular application, such that the precision, accuracy, and / or dynamic range of the output of the application may fluctuate based on the data type used by the application at runtime.

[0056] The latency parameter associated with an application may correspond to the amount of time that elapses between an action and a response to the application. For example, the amount of time between a request to the application to perform a task or function and a request to the application to output the results of the requested task or function. In some embodiments, application latency may be affected by the type of data being used by the application.

[0057] The reliability parameter associated with an application may correspond to a probability that the application will operate without failure within a specified environment for a set duration. In some embodiments, the reliability of an application may correspond to a reliability parameter that may be affected by the type of data being used by the application.

[0058] In some embodiments, processing device 122 may monitor the performance characteristics of an application and determine whether application performance can be improved by providing bit strings having different data types to the application. For example, if the application is an astronomy application, application performance improvements may be realized if the data used by the astronomy application is in a common number or positional format. Additionally, the astronomy application may benefit from increased accuracy, dynamic range, and / or precision when executing using data formatted in a common number or positional format, as compared to a floating point or fixed point binary format. Thus, in some embodiments, processing device 122 and / or APM component 123 may monitor the performance characteristics of the application and determine whether application performance would be improved by converting data from a floating point or fixed point binary format to a common number or positional format, or vice versa.

[0059] In another example, if the application is a financial (e.g., financial technology) application, the processing device 122 and / or the APM component 123 may determine that financial losses may occur if the application is executed with a particular data type. For example, one or more bit subsets of a particular data type may be limited compared to other bit subsets, which may result in a loss of precision, accuracy, and / or dynamic range during the execution of the application. In the case of a financial application, this may be due to rounding or other errors, resulting in financial losses. Therefore, in some embodiments, the processing device 122 and / or the APM component 123 may monitor the application at runtime to determine whether the use of a different data type may improve the performance of the financial application.

[0060] In some embodiments, as part of executing a computing application, the processing device 122 may be configured to perform (or cause to be performed) recursive arithmetic operations, such as addition, subtraction, multiplication, division, fused multiply-add, multiply-accumulate, dot product unit, greater than or less than, absolute value (e.g., FABS()), fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential and / or logarithmic operations, and / or recursive logical operations, such as AND, OR, XOR, NOT, etc., and trigonometric operations, such as sine, cosine, tangent, etc. As will be appreciated, the foregoing list of operations is not intended to be exhaustive, nor is the foregoing list of operations intended to be limiting, and the processing device 122 may be configured to perform (or cause to be performed) other arithmetic and / or logical operations as part of executing a computing application.

[0061] like Figure 1As shown, the processing device 122 may be coupled to an application performance management (APM) component 123. The APM component 123 may include circuitry and / or logic configured to monitor the performance (e.g., performance characteristics) of applications executed by the host 102 and / or the processing device 122. In addition to monitoring the performance characteristics described above, the APM component 123 may also process the monitored information independently or in conjunction with the processing device 122 to determine whether the performance of the application can be improved when executing the application using data having a specific data type associated therewith (e.g., whether one or more performance characteristics of the application can be improved). If the APM component 123 determines that the performance of the application can be improved when executing the application using data having a specific data type associated therewith, the APM component 123 may send one or more commands to the processing device 122 to cause the processing device 122 to convert the data being used by the application into a desired data type.

[0062] Control circuitry 120 may further include memory resources 124, which may be communicatively coupled to processing device 122. Memory resources 124 may include volatile memory resources, nonvolatile memory resources, or a combination of volatile and nonvolatile memory resources. In some embodiments, the memory resources may be random access memory (RAM), such as static random access memory (SRAM). However, embodiments are not limited thereto, and the memory resources may be a cache, one or more registers, NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices such as 3-D crosspoint (3DXP) memory devices, or a combination thereof.

[0063] In a non-limiting example, memory resource 124 may function as a cache for processing device 122. Processing device 122 may monitor performance characteristics associated with the execution of applications executed by host 102 coupled to processing device 122. Processing device 122 may determine that performance characteristics associated with at least one application using data formatted according to a first format supporting arithmetic operations with a first level of precision have reached a threshold performance level. As used herein, "threshold performance level" generally refers to a condition where the performance of the application cannot be improved as long as the application is using bit strings having a particular data type. For example, if the application is using bit strings formatted according to a fixed-point binary format, the execution of the application may be capped as long as the application is using bit strings formatted according to the fixed-point binary format. However, the performance of the application may be improved when the bit strings are formatted according to a different format, such as a floating-point format, a universal number format, a positional format, or the like.

[0064] As described above, the performance of an application may be measured in terms of various performance characteristics, which may include, for example, application response time, number of application errors, collected user satisfaction metrics, application dependency types, transaction traces associated with the application, application errors attributable to iterations, power consumption associated with the application, data precision or accuracy generated when executing the application using data in a first format or data in a second format, latency parameters associated with the application, and / or reliability parameters associated with the application, etc.

[0065] Processing device 122 may, based at least in part on the determination, perform an operation to convert data (e.g., a bit string) utilized by at least one application from a first format to a second format that supports arithmetic operations at a second level of precision. For example, if processing device 122 determines that the performance of the application can be improved if the application uses data formatted according to a format different from the data format currently being used by the application, processing device 122 may convert the data used by the application from one format to another format (e.g., from a fixed-point binary format to a universal number or positional format, or vice versa). Processing device 122 may cause the at least one application to be executed using the data formatted according to the second format.

[0066] As described above, the application may be an application configured to perform astronomical calculations, atomic calculations, financial calculations; edge computing applications, such as autonomous vehicle applications, data center applications, personalized medicine applications, network security applications, augmented reality applications, virtual reality applications, Internet of Things applications, smart city embedded applications, and / or portable embedded computer applications, etc.

[0067] In some embodiments, processing device 122 may be configured to convert data utilized by at least one application from a first format to a second format by changing the number of bits associated with at least one subset of bits contained in the data. For example, processing device 122 may be configured to add or remove bits from one or more subsets of bits contained in the data. In a non-limiting example where the first format is a floating-point format and the second format is a positional format, processing device 122 may be configured to add or remove bits from a subset of bits of a floating-point bit string to convert the floating-point bit string to a positional bit string.

[0068] Processing device 122 may be configured to determine that a performance characteristic associated with at least one application has reached a second threshold performance level and, based at least in part on the determination, perform an operation to convert data utilized by the at least one application from a second format to a third format. For example, processing device 122 may determine that the application has reached the second threshold performance level when the application is executed using data formatted in the second format.

[0069] As a non-limiting example, an application may reach a first threshold performance level when executing using data formatted in a fixed-point format, and processing device 122 may convert the data to a floating-point format. The application may then be executed using the data formatted in the floating-point format. If processing device 122 determines that the application has reached a second threshold performance level when executing using data formatted in a floating-point format, processing device 122 may convert the data to a universal or positional format and may cause the application to be executed using the data formatted in the universal or positional format. As will be appreciated, the formats and conversion orders listed above are merely illustrative, and other formats and / or other conversion orders are contemplated within the scope of the present disclosure.

[0070] In some embodiments, processing device 122 may be configured to determine an application type for the at least one application and to alter the precision of the data in the second format based at least in part on the determined application type of the at least one application.

[0071] In some embodiments, the processing device 122 may be configured to access data generated by the application performance management component 123 to monitor performance characteristics. In addition to the non-limiting performance characteristics described above, other examples of performance characteristics may include identification of network requests (e.g., slowest or fastest network requests, most frequent or least frequent network requests, etc.), key network requests, network transactions, Structured Query Language (SQL) queries (e.g., slowest or fastest SQL queries, most frequent or least frequent SQL queries, etc.), and / or the performance of specific SQL queries, etc. In some embodiments, the performance characteristics monitored by the APM component 123 may be used by the processing device 122 in the manner described above.

[0072] In another non-limiting example, processing device 122 can be coupled to host 102 and application performance management component 123. Processing device 122 can be configured to receive performance characteristics determined by APM 123 and corresponding to execution of applications executed by host 102 and analyze the performance characteristics to determine that a change in at least one performance characteristic has occurred with respect to at least one application. As described above, the performance characteristics can include information corresponding to the health of the applications executed by host 102.

[0073] The processing device 122 may be further configured to, based at least in part on the determination, convert data utilized by the at least one application from a first format supporting arithmetic operations at a first level of precision to a second format supporting arithmetic operations at a second level of precision.

[0074] In some embodiments, the processing device 122 may be configured to determine that a performance characteristic associated with at least one application has reached a second threshold performance level, perform an operation to convert data utilized by the at least one application from the second format to the first format based at least in part on the determination, and / or execute the at least one application using data formatted according to the first format.

[0075] The processing device 122 may be configured to determine that the at least one application is a financial application and, based on the determination, alter a number of bits associated with a subset of mantissa bits of data used by the at least one application.

[0076] In some embodiments, processing device 122 may be configured to determine that at least one application is an astronomy application and, based on the determination, alter a number of bits associated with at least a subset of bits of data used by the at least one application to increase a dynamic range available to the at least one application.

[0077] In some embodiments, the processing device 122 may be configured to determine that at least one application is an atomic application and, based on the determination, change the number of bits associated with at least one subset of bits of data used by the at least one application to increase the dynamic range available to the at least one application.

[0078] In yet another non-limiting example, processing device 122 may be coupled to memory resources 124. In this illustrative example, memory resources 124 may be configured as a cache for processing device 122. Processing device 122 and / or APM component 123 may be configured to monitor characteristics of multiple applications executed by the processing device and determine an application type for a particular application based on the monitored characteristics of the particular application. The performance characteristics may include monitored application response time, application error information, collected user satisfaction metrics, application dependencies among multiple applications, and / or transaction traces associated with a particular application, among other things.

[0079] An application type may correspond to a task or function that the application is designed to perform. As described above, some examples of application types may include astronomy applications, atomic applications, financial applications, edge computing applications, autonomous vehicle applications, data center applications, personalized medicine applications, cybersecurity applications, augmented reality applications, virtual reality applications, Internet of Things applications, smart city embedded applications, and / or portable embedded computer applications, among others.

[0080] The processing device 122 may be configured to determine a type of data utilized by a particular application, where the data type includes data formatted in a first format that supports arithmetic operations at a first level of precision or data formatted in a second format that supports arithmetic operations at a second level of precision and determine that one of the first format or the second format corresponds to a performance characteristic of the particular application that is greater than a threshold application performance characteristic.

[0081] In some embodiments, the processing device 122 may be configured to perform the following operations: based on a determination that the performance characteristics of a particular application using the other of the first format or the second format are greater than a threshold application performance characteristic, convert data from the first format or the second format to the other of the first format or the second format and execute the application using the data formatted in the converted format.

[0082] In some embodiments, processing device 122 may determine that the application type of the application corresponds to a financial application, determine that the first format includes a universal number format and the second format includes an IEEE 754 format or a fixed-point binary format, or vice versa, and perform an operation to convert the data from the first format to the second format.

[0083] In some embodiments, processing device 122 may determine that the application type of the application corresponds to an astronomical computing application, determine that the first format includes IEEE 754 or fixed-point binary format and the second format includes universal number format or positional format, or vice versa, and perform an operation to convert the data from the first format to the second format.

[0084] In some embodiments, processing device 122 may determine that the application type of the application corresponds to an atomic computing application, determine that the first format includes IEEE 754 or fixed-point binary format and the second format includes a universal number format or a positional format, or vice versa, and perform an operation to convert data from the first format to the second format.

[0085] In some embodiments, processing device 122 may be configured to cause execution of the application once the application has been converted to a desired format (eg, from a first format to a second format).

[0086] Figure 1 Embodiments of the present disclosure may include additional circuitry not described to avoid obscuring the embodiments of the present disclosure. For example, memory device 104 may include address circuitry that latches address signals provided on I / O connections by I / O circuitry. The address signals may be received and decoded by row and column decoders to access memory device 104 and / or memory array 130. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of memory device 104 and / or memory array 130.

[0087] Figure 2A is a functional block diagram of a computing system in the form of an apparatus 200 including a host 202 and a memory device 204 according to several embodiments of the present disclosure. The memory device 204 may include a control circuit system 220, which may be similar to Figure 1 Similarly, the host 202 may be similar to the control circuit system 120 described in Figure 1 The host 102 described in FIG, and the memory device 204 may be similar to Figure 1 Each of the components (eg, host 202, control circuitry 220, logic 215, memory resources 124, and / or memory array 230, etc.) may be individually referred to herein as a "device."

[0088] Host 202 may be communicatively coupled to memory device 204 via one or more channels 203, 205. Channels 203, 205 may be interfaces or other physical connections that allow data and / or commands to be transferred between host 202 and memory device 204. For example, commands that cause operations to be initiated using control circuitry 220 (e.g., operations to initiate a recursive operation using one or more bit strings, operations to modify an iterative result of a recursive operation, operations to store the modified results of an iteration of the recursive operation and operations to modify a multiple of the iterative result of the recursive operation in peripheral sense amplifier 211, queries to register 231 and / or multiple register 242) may be transmitted from the host via channels 203, 205. It should be noted that in some embodiments, control circuitry 220 may perform operations in response to one or more initiation commands transmitted from host 202 via channels 203, 205 without an intervening command from host 202. That is, control circuitry 220 may perform an operation once control circuitry 220 has received a command from host 202 to initiate performance of the operation in the absence of additional commands from host 202 .

[0089] like Figure 2AAs shown in , memory device 204 may include a register access component 206, a high-speed interface (HSI) 208, a controller 210, main memory input / output (I / O) circuitry 214, a row address strobe (RAS) / column address strobe (CAS) chain control circuitry 216, a RAS / CAS chain component 218, a control circuitry 220, and a memory array 230.

[0090] Register access component 206 may facilitate the retrieval of data from host 202 and transfer to memory device 204, and the retrieval of data from memory device 204 and transfer to host 202. For example, register access component 206 may store addresses (or facilitate looking up addresses), such as memory addresses, corresponding to data to be transferred from memory device 204 to host 202 or from host 202 to memory device 204. In some embodiments, register access component 206 may facilitate the transfer and retrieval of data to be operated on by control circuitry 220 and / or register access component 206 may facilitate the transfer and retrieval of data that has been operated on by control circuitry 220, or transfer data to host 202 in response to actions taken by control circuitry 220.

[0091] The HSI 208 may provide an interface between the host 202 and the memory device 204 for communicating commands and / or data across the channel 205. The HSI 208 may be a double data rate (DDR) interface, such as a DDR3, DDR4, DDR5, etc. However, embodiments are not limited to a DDR interface, and the HSI 208 may be a quad data rate (QDR) interface, a peripheral component interconnect (PCI) interface (e.g., a peripheral component interconnect express (PCIe)) interface, or other suitable interface for communicating commands and / or data between the host 202 and the memory device 204.

[0092] Controller 210 may be responsible for executing instructions from host 202 and accessing control circuitry 220 and / or memory array 230. Controller 210 may be a state machine, a sequencer, or some other type of controller. Controller 210 may receive commands from host 202 (e.g., via HSI 208) and, based on the received commands, control the operation of control circuitry 220 and / or memory array 230. In some embodiments, controller 210 may receive commands from host 202 to cause operations to be performed using control circuitry 220. In response to receiving such commands, controller 210 may instruct control circuitry 220 to begin performing the operations. As described herein, such operations may include recursive operations using bit strings and / or operations that modify the results of an iteration of a recursive operation by scaling the results by a factor. In some embodiments, the operations may further include causing the modified iteration results to be stored in query register 231 and the scaling factor of the iteration results to be stored in factor register 233.

[0093] In some embodiments, the controller 210 may be a global processing controller and may provide power management functions for the memory device 204. The power management functions may include controlling the power consumed by the memory device 204 and / or the memory array 230. For example, the controller 210 may control the power provided to the various banks of the memory array 230 to control which banks of the memory array 230 are operational at different times during operation of the memory device 204. This may include shutting down certain banks of the memory array 230 while providing power to other banks of the memory array 230 to optimize power consumption by the memory device 230. In some embodiments, the controller 210 controlling power consumption by the memory device 204 may include controlling power to the various cores of the memory device 204 and / or to the control circuitry 220, the memory array 230, etc.

[0094] Main memory input / output (I / O) circuitry 214 may facilitate the transfer of data and / or commands to and from memory array 230. For example, main memory I / O circuitry 214 may facilitate the transfer of bit strings, data, and / or commands from host 202 and / or control circuitry 220 to and from memory array 230. In some embodiments, main memory I / O circuitry 214 may include one or more direct memory access (DMA) components that may transfer bit strings (e.g., positional bit strings stored as data blocks) from control circuitry 220 to memory array 230, and vice versa.

[0095] In some embodiments, main memory I / O circuitry 214 may cause bit strings, data, and / or commands from memory array 230 to be transferred to control circuitry 220 so that control circuitry 220 can perform operations on the bit strings. Similarly, main memory I / O circuitry 214 may cause bit strings on which control circuitry 220 has performed one or more operations to be transferred to memory array 230.

[0096] As described above, bit strings (e.g., data) may be stored and / or retrieved from memory array 230. In some embodiments, main memory I / O circuitry 214 may cause bit strings to be stored to and / or retrieved from memory array 230. For example, main memory I / O circuitry 214 may be enabled to transfer a bit string to memory array 230 for storage, and / or main memory I / O circuitry 214 may cause a bit string (e.g., a bit string representing an operation performed between one or more bit string operands, a modified iterative result of an operation performed between one or more bit string operands, etc.) to be retrieved from memory array 230 in response to a command, for example, from controller 210 and / or control circuitry 220.

[0097] The row address strobe (RAS) / column address strobe (CAS) chain control circuitry 216 and the RAS / CAS chain component 218 may be used in conjunction with the memory array 230 to latch row addresses and / or column addresses to initiate memory cycles. In some embodiments, the RAS / CAS chain control circuitry 216 and / or the RAS / CAS chain component 218 may resolve row and / or column addresses of the memory array 230 at which read and write operations associated with the memory array 230 are to be initiated or terminated. For example, after completing an operation using the control circuitry 220, the RAS / CAS chain control circuitry 216 and / or the RAS / CAS chain component 218 may latch and / or resolve specific locations in the memory array 230 where the bit string that was operated on by the control circuitry 220 is to be stored. Similarly, the RAS / CAS chain control circuit system 216 and / or the RAS / CAS chain component 218 may latch and / or resolve a particular bit in the memory array 230 before or after the control circuit system 220 performs an operation (e.g., a recursive operation) using the bit string from which the bit string will be transmitted to the control circuit system 220.

[0098] The control circuit system 220 may include a processing device (e.g., Figure 1 122) and / or memory resources (e.g., Figure 120). A bit string (e.g., data, a plurality of bits, etc.) may be received by control circuitry 220 from, for example, host 202, memory array 230, and / or an external memory device and stored by control circuitry 220 in, for example, a memory resource of control circuitry 220. Control circuitry (e.g., a processing device of control circuitry 220) may perform a recursive operation (or cause an operation to be performed) using the bit string, modify a result of an iteration of the recursive operation, and cause the modified intermediate result of the operation to be stored in memory array 230.

[0099] In some embodiments, control circuitry 220 may perform (or cause to be performed) recursive arithmetic and / or logic operations using the bit strings. For example, control circuitry 220 may be configured to perform (or cause to be performed) recursive arithmetic operations such as recursive addition, recursive subtraction, recursive multiplication, recursive division, fused multiply-add operations, multiply-accumulate operations, recursive dot product operations, greater than or less than, absolute value (e.g., FABS()), fast Fourier transforms, inverse fast Fourier transforms, sigmoid functions, convolution operations, recursive square root operations, recursive exponential operations, and / or recursive logarithm operations, and / or recursive logic operations such as AND, OR, XOR, NOT, and the like, and recursive trigonometric functions such as sine, cosine, tangent, and the like. As will be appreciated, the foregoing list of operations is not intended to be exhaustive and limiting, and control circuitry 220 may be configured to perform (or cause to be performed) other arithmetic and / or logic operations using the various bit strings.

[0100] In some embodiments, the control circuit system 220 may perform the operations listed above in conjunction with the execution of one or more machine learning algorithms. For example, the control circuit system 220 may perform operations related to one or more neural networks. A neural network may allow the algorithm to be trained over time to determine an output response based on an input signal. For example, over time, the neural network may substantially learn to better maximize the chance of achieving a specific goal. This may be advantageous in machine learning applications because the neural network can be trained over time using new data to better maximize the probability of achieving a specific goal. The neural network can be trained over time to improve the operation of a specific task and / or a specific goal. However, in some approaches, machine learning (e.g., neural network training) may be processing-intensive (e.g., may consume a large amount of computer processing resources) and / or may be time-intensive (e.g., may require performing lengthy calculations that consume multiple cycles).

[0101] By monitoring the performance characteristics of machine learning applications and selectively converting between data types used by such applications, embodiments herein may allow for improved neural network training compared to approaches in which the applications use fixed data types and / or in which the performance characteristics of the applications are not monitored as part of determining the optimized data types used by the applications.

[0102] In some embodiments, the controller 210 may be configured to cause the control circuitry 220 (eg, Figure 1 The processing device 122 and / or APM component 123 described in the embodiment of the present invention performs the operations described herein (e.g., performs operations to monitor an application to determine performance characteristics of the application, determines optimized data types for a particular application, and / or converts data used by the application between different data types, etc.) without interfering with the host 202 (e.g., does not receive intervening commands or commands separate from the command that initiated the operation from the host 202 and / or does not transmit operation results to the host 202). However, embodiments are not limited thereto, and in some embodiments, the controller 210 may be configured to respond to one or more commands asserted by the host 202, causing the control circuit system 220 to perform the operations described herein based on the commands generated by the controller.

[0103] In other words, in some embodiments, host 202 may send a single command to memory device 204, and therefore, to control circuitry 220, to request that the operations described herein be performed. In response to receiving the command requesting the performance of an operation, memory device 204 (e.g., controller 210, control circuitry 220, or other components of memory device 204) may perform the operation without additional commands from host 202. This may reduce traffic on channels 203 / 205, thereby increasing the performance of computing device 200 associated with host 202 and / or memory device 204.

[0104] As above combined Figure 1 As described, for example, the memory array 230 may be a DRAM array, an SRAM array, an STTRAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array, although the embodiments are not limited to these specific examples. The memory array 230 may be used as Figure 2A and 2B In some embodiments, memory array 230 may be configured to store bit strings that control circuitry 220 operates on (e.g., a bit string representing the final result of a recursive operation performed) and / or to store bit strings that are to be transferred to control circuitry 220 before performing an operation using the bit strings.

[0105] Figure 2B 2 is another functional block diagram in the form of a computing system 200 including a host 202, a memory device 204, an application specific integrated circuit 223, and a field programmable gate array 221, according to several embodiments of the present disclosure. Each of the components (e.g., host 202, memory device 204, FPGA 221, ASIC 223, etc.) may be individually referred to herein as a "device."

[0106] like Figure 2B As shown, host 202 may be coupled to memory device 204 via channel 203, which may be similar to Figure 2A 2. A field programmable gate array (FPGA) 221 may be coupled to the host 202 via channel 217, and an application specific integrated circuit (ASIC) 223 may be coupled to the host 202 via channel 219. In some embodiments, channel 217 and / or channel 219 may include a Peripheral Serial Interconnect Express (PCIe) interface; however, embodiments are not limited thereto, and channel 217 and / or channel 219 may include other types of interfaces, buses, communication channels, etc. to facilitate data transfer between the host 202 and the FPGA 221 and / or ASIC 223.

[0107] As described above, the memory device 204 (e.g., Figure 2A The circuitry on the control circuitry 220 described in the accompanying drawings may perform operations such as monitoring an application to determine the performance characteristics of the application, determining an optimized data type for a particular application, and / or converting data used by the application between different data types. However, embodiments are not limited thereto, and in some embodiments, operations such as monitoring an application to determine the performance characteristics of the application, determining an optimized data type for a particular application, and / or converting data used by the application between different data types may be performed by the FPGA 221 and / or the ASIC 223. In embodiments in which the FPGA 221 and / or the ASIC 223 are configured to perform the operations described herein, the FPGA and / or the ASIC 223 may be configured to perform and / or cause the performance of such operations.

[0108] As described above, non-limiting examples of recursive arithmetic and / or recursive logic operations that may be performed by the FPGA 221 and / or the ASIC 223 include arithmetic operations that may be performed as part of executing an application program. Examples of arithmetic and logic operations may include addition, subtraction, multiplication, division, fused multiply-add, multiply-accumulate, dot product units, greater than or less than, absolute value (e.g., FABS()), fast Fourier transforms, inverse fast Fourier transforms, sigmoid functions, convolutions, square roots, exponential and / or logarithmic operations using positional bit strings, and / or logic operations such as AND, OR, XOR, NOT, etc., as well as trigonometric operations such as sine, cosine, tangent, etc.

[0109] FPGA 221 may include a state machine 227 and / or registers 229. State machine 227 may include one or more processing devices configured to perform operations on inputs and generate outputs. For example, FPGA 221 may be configured to perform the above-mentioned operations in conjunction with Figure 1 The operations described by the processing device 122 and / or APM component 123 are described in detail.

[0110] FPGA 221 may include registers 229 and / or buffers, which may be configured to execute the above combined Figure 1 Prior to the operations described in the processing device 122 and / or APM component 123 described in the foregoing, the bit string received from the host 202 is buffered and / or stored.

[0111] ASIC 223 may include logic 215 and / or cache 207. Logic 215 may include circuitry configured to perform operations on inputs and generate outputs. In some embodiments, ASIC 223 is configured to perform the operations described above in conjunction with Figure 1 The operations described by the processing device 122 and / or APM component 123 are described in detail.

[0112] ASIC 223 may include a cache 207 that may be configured to buffer and / or store the bit string received from host 202 before logic 215 performs an operation on the received bit string. In addition, the cache of ASIC 223 may be configured to buffer the bit string received in conjunction with the above. Figure 1 Data corresponding to the operations described by the processing device 122 and / or APM component 123 described in the description.

[0113] Figure 3 is an instance of an n-bit universal number or "unum" with es exponent bits. Figure 3 In the example of , the n-bit unum is the position bit string 331. Figure 3, n-bit positions 331 may include a set of sign bits (e.g., a first subset or sign bits 333), a set of digit bits (e.g., a second subset or digit bits 335), a set of exponent bits (e.g., a third subset or exponent bits 337), and a set of mantissa bits (e.g., a fourth subset or mantissa bits 339). Mantissa bits 339 may be referred to as a "fraction part" or "fraction bits" in the alternative and may represent a portion of the bit string after the decimal point (e.g., a number).

[0114] The sign bit 333 can be a zero (0) for a position and a one (1) for a negative number. The base bit 335 is described below in conjunction with Table 1, which shows a (binary) bit string and its associated numerical meaning k. In Table 1, the numerical meaning k is determined by the run length of the bit string. The letter x in the binary part of Table 1 indicates that the bit value is not relevant for the determination of the base because the (binary) bit string terminates in response to successive bit flips or when the end of the bit string is reached. For example, in the (binary) bit string 0010, the bit string terminates in response to a zero flip to a one and then back to zero. Therefore, the last zero is not relevant to the base and all that is considered for the base is the leading identical bit and the first relative bit of the terminating bit string (if the bit string contains such a bit).

[0115] Binary 0000 0001 001X 01XX 10XX 110X 1110 1111 Number (k) -4 -3 -2 -1 0 1 2 3

[0116] Table 1

[0117] exist Figure 3 In the example, the base digit 335r corresponds to the same bit in the bit string, and the base digit 335 Corresponds to the opposite bit of the termination bit string. For example, for the numeric k value -2 shown in Table 1, the base bit r corresponds to the first two leading zeros, and the base bit Corresponds to one. As described above, the final digit corresponding to the number k represented by X in Table 1 is irrelevant to the base.

[0118] If m corresponds to the number of identical bits in the bit string, then if the bit is zero, then k = -m. If the bit is one, then k = m-1. This is illustrated in Table 1, where for example the (binary) bit string 10XX has a single one and k = m-1 = 1 -1 = 0. Similarly, the (binary) bit string 0001 contains three zeros, so k = -m = -3. The base may indicate the scaling factor used k ,in Several example values of used are shown in Table 2 below.

[0119] es 0 1 2 3 4 used 2 <![CDATA[2 2 =4]]> <![CDATA[4 2 =16]]> <![CDATA[16 2 =256]]> <![CDATA[256 2 =65536]]>

[0120] Table 2

[0121] The exponent bits 337 correspond to the exponent e as an unsigned number. Compared to floating point numbers, the exponent bits 337 described herein may not have a bias associated with them. Therefore, the exponent bits 337 described herein may represent a factor of 2. e Scaling is performed proportionally. Figure 3 As shown in , there may be up to es exponent bits (e1, e2, e3, ..., e es ), which depends on how many bits are left to the right of the base bit 335 of the n-bit position 331. In some embodiments, this can allow for gradually decreasing accuracy of the n-bit position 331, where numbers closer to one in magnitude have higher accuracy than very large or very small numbers. However, because very large or very small numbers may be used infrequently in certain types of operations, Figure 3 The progressively smaller accuracy representation of n-bit positions 331 shown in may be desirable in a wide range of situations.

[0122] Mantissa bits 339 (or fraction bits) represent any additional bits that may be part of n-bit positions 331 located to the right of exponent bits 337. Similar to a floating point bit string, mantissa bits 339 represent a fraction f that may be similar to the fraction 1.f, where f includes one or more bits to the right of the decimal point after one. However, in contrast to a floating point bit string, Figure 3 In the n-bit position 331 shown in , the “hidden bit” (e.g., one) may always be one (e.g., whole), while the floating-point bit string may include a subnormal number with a “hidden bit” of zero (e.g., 0.f).

[0123] As described herein, changing the value or bit amount of one or more of the sign bit 333, the base bit 335, the exponent bit 337, or the mantissa bit 339 can change the precision of the n-bit position 331. For example, changing the total number of bits in the n-bit position 331 can change the resolution of the n-bit position bit string 331. That is, by, for example, increasing the value and / or bit amount associated with one or more of the component bit subsets of the position bit string to increase the position bit string resolution, an 8-bit position can be converted to a 16-bit position. Conversely, by decreasing the value and / or bit amount associated with one or more of the component bit subsets of the position bit string, the resolution of the position bit string can be reduced, for example, from 64-bit resolution to 32-bit resolution.

[0124] In some embodiments, changing the numerical value and / or bit amount associated with one or more of the radix bits 335, the exponent bits 337, and / or the mantissa bits 339 to change the precision of the n-bit position 331 may result in a change in at least one of another of the radix bits 335, the exponent bits 337, and / or the mantissa bits 339. For example, when changing the precision of the n-bit position 331 to increase the resolution of the n-bit position bit string 331 (e.g., when performing an “upcast” operation to increase the bit width of the n-bit position bit string 331), the numerical value and / or bit amount associated with one or more of the radix bits 335, the exponent bits 337, and / or the mantissa bits 339 may be changed.

[0125] In a non-limiting example, where the resolution of n-bit position bit string 331 is increased (e.g., the precision of n-bit position bit string 331 is changed to increase the bit width of n-bit position bit string 331) but the value or bit amount associated with exponent bits 337 is not changed, the value or bit amount associated with mantissa bits 339 may be increased. In at least one embodiment, increasing the value and / or bit amount of mantissa bits 339 while exponent bits 337 remain unchanged may include adding one or more zero bits to mantissa bits 339.

[0126] In another non-limiting example, where the resolution of n-bit position bit string 331 is increased by changing the value and / or bit amount associated with exponent bits 337 (e.g., the precision of n-bit position bit string 331 is changed to increase the bit width of n-bit position bit string 331), the value and / or bit amount associated with base bits 335 and / or mantissa bits 339 may be increased or decreased. For example, if the value and / or bit amount associated with exponent bits 337 is increased or decreased, the value and / or bit amount associated with base bits 335 and / or mantissa bits 339 may produce a corresponding change. In at least one embodiment, increasing or decreasing the value and / or bit amount associated with base bits 335 and / or mantissa bits 339 may include adding one or more zero bits to base bits 335 and / or mantissa bits 339 and / or truncating the value or bit amount associated with base bits 335 and / or mantissa bits 339.

[0127] In another example, where the resolution of the n-bit position bit string 331 is increased (e.g., the precision of the n-bit position bit string 331 is changed to increase the bit width of the n-bit position bit string 331), the value and / or bit amount associated with the exponent bits 337 may increase and the value and / or bit amount associated with the radix bits 335 may decrease. Conversely, in some embodiments, the value and / or bit amount associated with the exponent bits 337 may decrease and the value and / or bit amount associated with the radix bits 335 may increase.

[0128] In a non-limiting example, where the resolution of n-bit position bit string 331 is reduced (e.g., the precision of n-bit position bit string 331 is changed to reduce the bit width of n-bit position bit string 331) but the value or bit amount associated with exponent bits 337 is not changed, the value or bit amount associated with mantissa bits 339 may be reduced. In at least one embodiment, reducing the value and / or bit amount of mantissa bits 339 while exponent bits 337 remain unchanged may include truncating the value and / or bit amount associated with mantissa bits 339.

[0129] In another non-limiting example, where the resolution of n-bit position bit string 331 is reduced by changing the value and / or bit amount associated with exponent bits 337 (e.g., the precision of n-bit position bit string 331 is changed to reduce the bit width of n-bit position bit string 331), the value and / or bit amount associated with base bits 335 and / or mantissa bits 339 may be increased or decreased. For example, if the value and / or bit amount associated with exponent bits 337 is increased or decreased, the value and / or bit amount associated with base bits 335 and / or mantissa bits 339 may produce a corresponding change. In at least one embodiment, increasing or decreasing the value and / or bit amount associated with base bits 335 and / or mantissa bits 339 may include adding one or more zero bits to base bits 335 and / or mantissa bits 339 and / or truncating the value or bit amount associated with base bits 335 and / or mantissa bits 339.

[0130] In some embodiments, changing the values and / or bit amounts in the exponent bit subset can alter the dynamic range of n-bit positions 331. For example, a 32-bit position string with an exponent bit subset containing the value zero (e.g., a 32-bit position string with es=0 or a (32,0) position string) can have a dynamic range of approximately 18 decimal bits. However, a 32-bit position string with an exponent bit subset containing the value 3 (e.g., a 32-bit position string with es=3 or a (32,3) position string) can have a dynamic range of approximately 145 decimal bits.

[0131] Figure 4A is an instance of a positive value in the 3-bit position. Figure 4A In , only the right half of the real numbers is projected. However, it should be understood that the corresponding Figure 4A The negative projection of the real numbers of their positive corresponding values shown in may exist on the curve, which represents the real numbers around Figure 4A The transformation of the y-axis of the curve shown in .

[0132] exist Figure 4A In the example, es = 2, so The accuracy of position 431-1 can be increased by appending bits to the bit string, such as Figure 4B For example, appending a bit with value one (1) to the bit string at position 431-1 would increase the bit string as shown by Figure 4B Similarly, a bit with a value of one is appended to Figure 4B The bit string at position 431-2 in the Figure 4B The following are the accuracy of the position 431-2 shown in the position 431-3 shown in the . Figure 4A The bit string at position 431-1 shown in Figure 4B An example of the interpolation rule for positions 431-2, 431-3 is illustrated in FIG.

[0133] If maxpos is the maximum positive value of the bit string at positions 431-1, 431-2, 431-3 and minpos is the minimum value of the bit string at positions 431-1, 431-2, 431-3, then maxpos may be equal to used and minpos may be equal to Between maxpos and ±∞, the new place value can be maxpos*used and between zero and minpos, the new place value can be These new bit values may correspond to the new base bit 335. At the existing value x=2 m and y = 2 n , where the difference between m and n is greater than one, the new place value is given by the following geometric mean: This corresponds to the new exponent bit 337. If the new bit value is halfway between the existing x value and the immediately following y value, then the new bit value may represent the arithmetic mean This corresponds to the new mantissa digit 339.

[0134] Figure 4B is an instance constructed using the positions of the two exponent bits. Figure 4B In , only the right half of the real numbers is projected. However, it should be understood that the corresponding Figure 4B The negative projection of the real numbers of their positive corresponding values shown in may exist on the curve, which represents the real numbers around Figure 4B The transformation of the y-axis of the curve shown in . Figure 4B The positions 431-1, 431-2, 431-3 shown each contain only two outliers: zero (0) when all bits of the bit string are zero, and ±∞ when the bit string is one (1) followed by all zeros. Note that Figure 4B The values of positions 431-1, 431-2, and 431-3 shown in the table are accurate. k That is, for the base number (for example, the above combined Figure 3 The base digit 335) described above represents the power of the value of k, Figure 4B The values of positions 431-1, 431-2, and 431-3 shown in are exactly used. Figure 4BIn the example, position 431-1 has es=2, so Position 431-2 has es=3, so And position 431-3 has es=4, so

[0135] As bits are added to the 3-bit position 431-1 to produce Figure 4B illustrative example of the 4-bit position 431-2 of , used=256, so the bit string corresponding to used 256 has an extra base bit appended to it and the previous used of 16 has a terminating base bit appended to it As described above, between existing values, the corresponding bit string has an extra exponent bit appended to it. For example, the values 1 / 16, 1 / 4, 1, and 4 will have an exponent bit appended to them. That is, the last one corresponding to the value 4 is the exponent bit, the last zero corresponding to the value 1 is the exponent bit, and so on. This pattern can be further seen in position 431-3, which is a 5-bit position generated from the 4-bit position 431-2 according to the above rules. If another bit is added to Figure 4B Positions 431-3 in the digits to produce 6 positions, then the mantissa bits 339 will be appended to the value between 1 / 16 and 16.

[0136] The following is a non-limiting example of decoding a position (e.g., position 431) to obtain its digital equivalent. In some embodiments, the bit string corresponding to position p is from -2 n-1 to 2 n-1 , k is an integer corresponding to the base bits 335, and e is an unsigned integer corresponding to the exponent bits 337. If the set of mantissa bits 339 is represented by {{f1f2…f fs} and f is composed of 1.f1 f2…f fs denoted by (eg, by one after the decimal point after the mantissa digit 339), then p can be given by the following Equation 1.

[0137]

[0138] Another illustrative example of decoding a position bit string is provided below in conjunction with the position bit string 0000110111011101 shown in Table 3 below.

[0139] symbol Base index mantissa 0 0001 101 11011101

[0140] Table 3

[0141] In Table 3, the position bit string 0000110111011101 is decomposed into its constituent bit sets (e.g., sign bit 333, base bit 335, exponent bit 337, and mantissa bit 339). Since es=3 in the position bit string shown in Table 3 (e.g., because there are three exponent bits), used=256. Because the sign bit 333 is zero, the value of the digital representation corresponding to the position bit string shown in Table 3 is positive. The base bit 335 has a run of three consecutive zeros corresponding to the value -3 (as described above in conjunction with Table 1). Therefore, the scaling factor generated by the base bit 335 is 256. -3 (For example, used k ). The exponent bits 337 represent five (5) as an unsigned integer and thus provide 2 e =2 5 = 32. Finally, the mantissa bits 339 given as 11011101 in Table 3 represent two hundred and twenty one (221) as an unsigned integer, so the mantissa bits 339 given above as f are Using these values and Equation 1, the values corresponding to the position bit strings given in Table 3 are

[0142] Figure 5 is a flow chart representing an example method 540 for application-based data type selection according to several embodiments of the present disclosure. At block 542, the method 540 may include monitoring, by a processing device, a performance characteristic associated with at least one application executed by a host coupled to the processing device. The application may be an application configured to perform personalized medication calculations, automotive calculations, or network security calculations, or any combination thereof. However, the embodiments are not limited in this regard, and the application may be one or more of any type of application described herein, as well as other computing applications configured to perform specific tasks and / or functions when executed by a computing system. The processing device may be similar to the one described herein in Figure 1 The processing device 122 described in .

[0143] As described above, the performance characteristics may include application errors generated due to iterations, power consumption associated with at least one application, precision or accuracy of data generated when executing at least one application using data in a first format or data in a second format, latency parameters associated with at least one application, or reliability parameters associated with at least one application, or any combination thereof. However, embodiments are not limited thereto, and in some embodiments, the performance characteristics may include the health of at least one application when the at least one application performs an operation using data formatted according to the first format, the health of the at least one application when the at least one application performs an operation using data formatted according to the second format, or both.

[0144] At block 544 , method 540 may include determining, by the processing device, that a performance characteristic associated with at least one application has reached a threshold performance level.

[0145] At block 546, method 540 may include, based at least in part on the determination, performing, by the processing device, converting a data type utilized by at least one application from a first format supporting arithmetic operations at a first level of precision to a second format supporting arithmetic operations at a second level of precision. In some embodiments, one of the first format and the second format may be an IEEE 754 format or a fixed-point binary format, and the other of the first format and the second format may be a universal number or positional format. Additionally, in some embodiments, converting the data type utilized by at least one application from the first format to the second format may include changing a number of bits associated with at least one subset of bits contained within the data type.

[0146] Method 540 may further include determining, by the processing device, that at least one performance characteristic associated with at least one application has reached a second threshold performance level, and performing, by the processing device, an operation to convert a data type utilized by the at least one application from a second format to a third format based at least in part on the determination.

[0147] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and not restrictive manner. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims together with the full scope of equivalents to which such claims are given.

[0148] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure necessarily utilize more features than expressly recited in each claim. In fact, as reflected in the appended claims, the present subject matter lies in less than all of the features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for application-based data type selection, comprising: monitoring, by a processing device, a performance characteristic associated with at least one application program executed by the processing device or a host coupled to the processing device; analyzing the performance characteristic to determine that a change in at least one performance characteristic has occurred relative to at least one application; determining, by the processing device based on the analyzed performance characteristics, that the at least one performance characteristic associated with the at least one application has reached a threshold performance level; determining that the at least one application is a financial application; based on determining that the at least one application is the financial application, altering a number of bits associated with a subset of mantissa bits of data used by the at least one application; determining, by the processing device, a probability that the at least one application will operate without failure for a set duration; as well as The processing device performs the following operations based at least in part on determining that the performance characteristic associated with the at least one application has reached the threshold performance level and confirming that the probability of the at least one application running without failure within the set duration meets the threshold duration: converting the data type utilized by the at least one application from an IEEE 754 format or a fixed-point binary format to a positional format. The method of claim 1 , wherein the positional format comprises a sign, a base, an exponent, and a mantissa.

3. The method of claim 1 , wherein the performance characteristics include application errors generated attributable to iterations, power consumption associated with the at least one application, precision or accuracy of data generated when the at least one application is executed using data in a first format or data in a second format, or a reliability parameter associated with the at least one application, or any combination thereof.

4. The method of claim 1 , wherein the performance characteristic comprises a health of the at least one application when the at least one application performs an operation using data formatted according to a first format, a health of the at least one application when the at least one application performs an operation using data formatted according to a second format, or both.

5. The method of claim 1 , further comprising: determining, by the processing device, that the at least one performance characteristic associated with the at least one application has reached a second threshold performance level; and Converting the data type utilized by the at least one application from a second format to a third format is performed by the processing device based at least in part on the determination. 6 . The method of claim 1 , wherein the at least one application comprises an application configured to perform personalized medication calculations, automotive calculations, or network security calculations, or any combination thereof.

7. The method of claim 1, further comprising altering a number of bits associated with at least one subset of bits included in the data type.

8. An apparatus for application-based data type selection, comprising: A processing device and a memory resource configured to function as a cache for the processing device, wherein the processing device and the memory resource reside on a memory device, and wherein the processing device is configured to: monitoring performance characteristics associated with execution of an application program executed by the processing device or a host coupled to the processing device; analyzing the performance characteristic to determine that a change in at least one performance characteristic has occurred relative to at least one application; determining that the at least one performance characteristic associated with the at least one application program using data formatted according to a first format supporting arithmetic operations with a first level of precision has reached a threshold performance level; determining that the at least one application is an astronomy application; based on determining that the at least one application is the astronomical application, altering a number of bits associated with at least a subset of bits of the data used by the at least one application to increase a dynamic range available to the at least one application; determining a probability that the at least one application will operate without failure for a set duration; as well as performing an operation of converting the data utilized by the at least one application from the first format to a second format supporting arithmetic operations at a second level of precision based at least in part on a determination that the performance characteristic has reached the threshold performance level and a determination that the probability of the at least one application operating without failure for the set said duration satisfies the threshold duration; and The at least one application is caused to be executed using the data formatted according to the second format.

9. The apparatus of claim 8, wherein the application comprises an application configured to perform astronomical calculations, atomic calculations, or financial calculations, or any combination thereof.

10. The apparatus of claim 8, wherein the performance characteristics comprise a number of application errors, collected user satisfaction metrics, application dependency types, transaction traces associated with the at least one application, or any combination thereof.

11. The apparatus of claim 8, wherein the processing means is further configured to convert the data utilized by the at least one application from the first format to the second format by altering a number of bits associated with at least one subset of bits contained within the data.

12. The apparatus according to claim 8, wherein the processing device is further configured to: determining that the performance characteristic associated with the at least one application has reached a second threshold performance level; and An operation of converting the data utilized by the at least one application from the second format to a third format is performed based at least in part on the determination.

13. The apparatus according to claim 8, wherein the processing device is further configured to: determining an application type for the at least one application; and A precision of the data in the second format is altered based at least in part on the determined application type of the at least one application.

14. The apparatus of claim 8, further comprising an application performance management component coupled to the processing device, wherein the processing device is further configured to access data generated by the application performance management component to monitor the performance characteristic.

15. An apparatus for application-based data type selection, comprising: A processing device and a memory resource configured as a cache for the processing device, wherein the processing device and the memory resource reside on a memory device, and wherein the processing device is configured to: monitoring characteristics of a plurality of applications executed by the processing device; determining, based on the monitored characteristics of the specific application, that an application type of the specific application is an atomic application; determining a data type utilized by the particular application, wherein the data type comprises data formatted in a first format that supports arithmetic operations at a first level of precision or data formatted in a second format that supports arithmetic operations at a second level of precision; based on determining that the particular application is the atomic application, changing a number of bits associated with at least a subset of bits of the data used by the particular application to increase a dynamic range available to the at least one application; determining that a performance characteristic of one of the first format or the second format corresponding to the particular application is greater than a threshold application performance characteristic; determining the probability that the specific application will operate without failure for a set duration; performing an operation to convert the data from the first format or the second format to the other of the first format or the second format based on a determination that the performance characteristic of the particular application using the other of the first format or the second format is greater than the threshold application performance characteristic and a determination that the probability of the particular application operating without failure for the set duration satisfies the threshold duration; and The particular application is executed using the data formatted in the converted format.

16. The apparatus according to claim 15, wherein the processing means is configured to: determining that the application type of the application corresponds to an astronomical computing application; determining that the first format comprises an IEEE 754 format or a fixed-point binary format and the second format comprises a universal number format or a positional format; and An operation is performed to convert data from the first format to a second format.

17. The apparatus according to claim 15, wherein the processing means is configured to: determining that the application type of the application corresponds to an atomic computing application; determining that the first format comprises an IEEE 754 format or a fixed-point binary format and the second format comprises a universal number format or a positional format; and The operation of converting the data from the first format to the second format is performed.

18. The apparatus of claim 15, wherein the performance characteristics comprise monitored application response times, application error information, collected user satisfaction metrics, application dependencies among the plurality of applications, or transaction traces associated with the particular application, or any combination thereof.

19. A system for application-based data type selection, comprising: Host; a processing device coupled to the host; and a component configured to produce a performance characteristic, the component being coupled to the processing device, wherein the processing device is configured to: receiving the performance characteristics generated by the component and corresponding to execution of an application executed by the host; analyzing the performance characteristic to determine that a change in at least one performance characteristic has occurred relative to at least one application; determining that the at least one application is a financial application; based on determining that the at least one application is the financial application, altering a number of bits associated with a subset of mantissa bits of data used by the at least one application; determining a probability that the at least one application will operate without failure for a set duration; Based at least in part on determining that the change in the at least one performance characteristic has occurred with respect to at least one application and determining the probability that the at least one application will operate without failure for a set duration, converting data utilized by the at least one application from an IEEE 754 format or a fixed-point binary format to a positional format; and The at least one application is executed using the data formatted according to the second format.

20. The system of claim 19, wherein the processing device is further configured to: determining that the performance characteristic associated with the at least one application has reached a second threshold performance level; performing, based at least in part on the determination, an operation of converting the data utilized by the at least one application from the second format to a first format; and The at least one application is executed using the data formatted according to the first format.

21. The system of claim 19, wherein the performance characteristics include information corresponding to a health of the application executed by the host.

22. The system of claim 19, wherein the processing device is further configured to: determining that the at least one application is an astronomy application; and Based on the determination, a number of bits associated with at least a subset of bits of the data used by the at least one application is altered to increase a dynamic range available to the at least one application.

23. The system of claim 19, wherein the processing device is further configured to: determining that the at least one application is an atomic application; and Based on the determination, a number of bits associated with at least a subset of bits of the data used by the at least one application is altered to increase a dynamic range available to the at least one application.

Images