A semiconductor epitaxial structure and its application

Abstract

The present invention provides a semiconductor epitaxial structure and its application, including a substrate; a first semiconductor layer disposed on the substrate; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a hole injection layer disposed on the second semiconductor layer, and the hole injection layer includes a non- or low-doped gallium nitride layer and / or a doped gallium nitride layer. By means of the semiconductor epitaxial structure provided by the present invention, the quality of the semiconductor epitaxial structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a semiconductor epitaxial structure and its application. Background Art

[0002] Gallium nitride (GaN) is a wide-bandgap material with high resistivity. The static charges generated during the production and transportation of GaN-based diode chips are not easily dissipated, and can accumulate to a certain extent to generate a very high static voltage. The positive and negative electrodes of the diode chip on a sapphire substrate are located on the same side of the chip with a very small distance, so the tolerance to static electricity is very small and it is extremely easy to be broken down by static electricity, affecting the life of the device.

[0003] The active region of the semiconductor epitaxial structure of the GaN-based diode adopts a GaN / InGaN quantum well barrier region. However, due to the different lattice constants of GaN / AlGaN materials, polarization effects are likely to occur, causing dislocation defects. If these defects are not effectively controlled, the line dislocations passing through the GaN / InGaN quantum well barrier region will lead to a large number of surface defects, forming leakage channels. The surface defects also affect the ion doping efficiency in the semiconductor layers on both sides of the light-emitting layer, thereby affecting the hole concentration and the light-emitting efficiency of the chip. Summary of the Invention

[0004] In view of the above defects of the prior art, the present invention proposes a semiconductor epitaxial structure and its application, aiming to improve the light-emitting quality of the active layer and the ion doping efficiency in the semiconductor layer, thereby enhancing the light-emitting efficiency of the diode chip.

[0005] To achieve the above and other objects, the present invention proposes a semiconductor device. The semiconductor epitaxial structure includes:

[0006] A substrate;

[0007] A first semiconductor layer disposed on the substrate;

[0008] An active layer disposed on the first semiconductor layer;

[0009] A second semiconductor layer disposed on the active layer; and

[0010] A hole injection layer disposed on the second semiconductor layer, and the hole injection layer includes a non- or low-doped gallium nitride layer and / or a doped gallium nitride layer.

[0011] Optionally, the hole injection layer includes a first doping layer and a second doping layer. The second doping layer is located on the first doping layer, and the doping concentration of the first doping layer is less than that of the second doping layer.

[0012] Optionally, the first doped layer has a first doping concentration, and the range of the first doping concentration is 0 to 1×1019 atom / cm3.

[0013] Optionally, the second doped layer has a second doping concentration, and the range of the second doping concentration is 0 to 1×1019 atom / cm3.

[0014] Optionally, the second semiconductor layer has a third doping concentration, and the third doping concentration is less than the second doping concentration.

[0015] Optionally, the thickness of the first doped layer is 40% to 50% of the thickness of the second doped layer.

[0016] Optionally, the hole injection layer further includes a third doped layer, the third doped layer is located on the second doped layer, and the concentration of the third doped layer is greater than the doping concentration of the second doped layer.

[0017] Optionally, the hole injection layer includes Inx1Gay1N, Inx2Gay2N, and Inx3Gay3N, and X3 < X2 < X1 ≤ 1.

[0018] Optionally, the hole injection layer includes n periodic cycles of alternating Inx1Gay1N and Inx2Gay2N, n ≥ 1, Xn <... < X3 < X2 < X1 ≤ 1.

[0019] The present invention also provides a semiconductor device, including the semiconductor epitaxial structure as described above.

[0020] The present invention also provides a light-emitting diode, characterized in that it includes the semiconductor epitaxial structure as described above.

[0021] The present invention also provides a micro light-emitting diode, characterized in that it includes the semiconductor epitaxial structure as described above.

[0022] The present invention also provides a micro light-emitting diode display, characterized in that it includes the micro light-emitting diode as described above.

[0023] In summary, the present invention provides a semiconductor epitaxial structure and its application. By providing a hole injection layer, through the combination of GaN and InGaN with different thicknesses and concentrations, the lattice mismatch between the AlGaN layer and the P-type doping layer is reduced, the dislocation density is decreased, and the surface morphology is improved. Through In doping with different concentrations, by utilizing the strong activity characteristics of In atoms, the efficiency of P-type Mg doping is further promoted, the hole concentration is increased, thereby increasing the number of photons generated by recombination per unit time, and further enhancing the light emission intensity and efficiency of the light-emitting diode. The present invention provides a semiconductor epitaxial structure and its application, which can obtain a high-quality epitaxial structure, improve the breakdown voltage, and have a relatively high breakdown voltage performance, and improve the quality of the semiconductor epitaxial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 : Schematic diagram of the semiconductor device structure in this embodiment.

[0025] Figure 2 : Schematic diagram of an intermediate cavity structure in this embodiment.

[0026] Figure 3 : Schematic diagram of the cleaning cavity structure in this embodiment.

[0027] Figure 4 : Schematic diagram of the preheating cavity structure in this embodiment.

[0028] Figure 5 : Schematic diagram of the growth cavity structure in this embodiment.

[0029] Figure 6 : Schematic diagram briefly showing the target and the backplane structure in this embodiment.

[0030] Figure 7 : Schematic diagram briefly showing another semiconductor device structure in this embodiment.

[0031] Figure 8 : Schematic diagram of the deposition cavity structure in this embodiment.

[0032] Figure 9 : Schematic diagram of the structure of the first deposition chamber.

[0033] Figure 10 : Schematic diagram of the diffusion plate.

[0034] Figure 11 : Schematic diagram of the structure of the first intake pipeline and the second intake pipeline.

[0035] Figure 12 : Schematic diagram of the substrate inlet.

[0036] Figure 13 : Schematic diagram of the second pipeline.

[0037] Figure 14 : Schematic diagram of the structure of a semiconductor device.

[0038] Figure 15 : Schematic diagram of a semiconductor epitaxial structure provided with a hole injection layer.

[0039] Figure 16 : Schematic diagram of a polar face and a non-polar face.

[0040] Figure 17 : Schematic diagram of a semiconductor epitaxial structure with a stable wavelength.

[0041] Figure 18 : Schematic diagram of a semiconductor epitaxial structure provided with a resistance layer.

[0042] Figure 19 : Figure 18 Equivalent circuit diagram of the semiconductor epitaxial structure shown.

[0043] Figure 20 : Schematic diagram of the structure of a micro light-emitting diode.

[0044] Figure 21 : Schematic diagram of the structure of a large-angle micro light-emitting diode.

[0045] Figure 22 : Schematic diagram of the structure of a small-angle micro light-emitting diode.

[0046] Figure 23 : Figure 21 Schematic diagram of the shielding layer structure shown.

[0047] Figure 24 : Schematic diagram of a shielding layer covering two sides.

[0048] Figure 25 : Schematic diagram of a shielding layer covering four sides.

[0049] Figure 26 : Schematic diagram of the structure of a micro light-emitting diode provided with a planarization layer.

[0050] Figure 27 : Figure 25 Schematic diagram of the structure of the planarization layer shown.

[0051] Figure 28 : Figure 25 Schematic diagram of the force on the micro light-emitting diode soldered on the substrate shown.

[0052] Figure 29 : Schematic diagram of the emission angle of the structure of a micro light-emitting diode without a planarization layer.

[0053] Figure 30 : Figure 25Schematic diagram of the light-emitting angle of the shown micro light-emitting diode.

[0054] Figure 31 : Schematic diagram of a micro light-emitting diode with a metal stack on the electrode.

[0055] Figure 32 : Schematic diagram of a micro light-emitting diode with a special conductive structure.

[0056] Figure 33 : Schematic diagram of a micro light-emitting diode with a waterproof protective layer.

[0057] Figure 34 : Figure 32 Schematic diagram of the structure of the shown protective film layer.

[0058] Figure 35 : Figure 33 Electron microscope image of the shown protruding structure.

[0059] Figure 36 : Schematic diagram of the angle between the tangent of the droplet edge and the reference plane on surfaces with different hydrophobicities.

[0060] Figure 37 : Schematic diagram of a micro light-emitting diode with a support layer arranged between electrodes.

[0061] Figure 38 : Schematic diagram of the structure of a micro light-emitting diode transfer device.

[0062] Figure 39 : Top view of the structure of a micro light-emitting diode transfer device.

[0063] Figure 40 : Schematic diagram of the cutting groove of a micro light-emitting diode transfer device.

[0064] Figure 41 : Schematic diagram of the cutting position of a micro light-emitting diode transfer device.

[0065] Figure 42 : Schematic diagram of the structure of a micro light-emitting diode display panel.

[0066] Figure 43 : Top view of a micro light-emitting diode display panel.

[0067] Figure 44 : Schematic diagram of the structure of an electronic device.

[0068] Figure 45 : Schematic diagram of the structure of a semiconductor device.

[0069] Figure 46 : Schematic diagram of the structure of a radio frequency module. Detailed implementation manners

[0070] The following uses specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] Please refer to Figure 1 , in this embodiment, a semiconductor device 100 is proposed. For example, it can be a chemical vapor deposition device, or a physical vapor deposition device. Of course, it can also be a combination of physical vapor deposition devices, chemical vapor deposition devices, or other semiconductor devices.

[0072] As Figure 1 shown, in an embodiment of the present invention, a plurality of chambers are provided in the semiconductor device 100. In an embodiment of the invention, the semiconductor device 100 may include, for example, a transfer chamber 110, a preheating chamber 140, a cleaning chamber 130, a transition chamber 120, and a plurality of growth chambers 150. During the manufacturing process of semiconductor devices, the substrate can be preheated and plasma cleaned first, and the cleaned substrate is transferred to the growth chamber 150, where film growth is carried out, and then cooling treatment is performed.

[0073] As Figure 1 shown, in this embodiment, the transfer chamber 110 includes a substrate loading and unloading robotic arm 111. The substrate loading and unloading robotic arm 111 can be operated to transfer the substrate between the chambers. The size of the substrate loading and unloading robotic arm 111 can also be adjusted according to the spatial dimensions of different chambers. More specifically, the substrate loading and unloading robotic arm 111 can have double substrate loading and unloading blades suitable for simultaneously transferring two substrates from one chamber to another chamber. The substrate can be transferred between the transfer chamber 110 and other chambers via a slit valve 112. The movement of the substrate loading and unloading robotic arm 111 can be controlled by a motor drive system (not shown), and the motor drive system can include a servo motor or a stepper motor.

[0074] As Figure 1 , in some embodiments, the semiconductor device further includes a manufacturing interface 113. The manufacturing interface 113 includes a cassette and a substrate loading and unloading robotic arm (not shown). The cassette contains the substrates that need to be processed. The substrate loading and unloading robotic arm can include a substrate planning system to load the substrates in the cassette into the transition chamber 120. Specifically, the substrates are placed on the trays of the carriers.

[0075] As Figure 1, in this embodiment, the preheating chamber 140 is connected to the transfer chamber 110. The preheating chamber 140 is located on the side wall of the transfer chamber 110. When the substrate enters the transition chamber 120, the substrate handling robotic arm 111 in the transfer chamber 110 then transfers the substrate from the transition chamber 120 to the preheating chamber 140 for preheating and plasma cleaning.

[0076] As Figure 1 , in this embodiment, a plurality of growth chambers 150 are provided on the side wall of the transfer chamber 110. When the substrate completes the corresponding process, the substrate handling robotic arm 111 in the transfer chamber 110 transfers the substrate into the growth chamber 150 for operation. Since a uniform magnetic field is formed in the growth chamber 150, uniform sputtering ions can thus be formed on the surface of the substrate, thereby forming a uniform thin film on the substrate.

[0077] As Figure 2 , in this embodiment, the transition chamber 120 is connected to the transfer chamber 110, and the transition chamber 120 is located between the manufacturing interface 113 and the transfer chamber 110. The transition chamber 120 provides a vacuum interface between the manufacturing interface 113 and the transfer chamber 110.

[0078] As Figure 1 and Figure 2 , in some embodiments, the transition chamber 120 can implement the processes of substrate transfer, preheating, and cleaning. The transition chamber 120 includes a housing 120a, and the housing 120a is, for example, a sealed cylinder. At the same time, an air extraction port and an exhaust port are provided on the side wall of the housing 120a. The transition chamber 120 is provided with a plurality of gas path channels, such as an air inlet 128. A plurality of gas paths, such as an air inlet 128 and a power supply, are installed in the transition chamber 120 to implement the baking preheating and plasma cleaning processes. A separate pump is used for gas pumping and charging, making the entire process flow more smoothly to save the overall time consumption.

[0079] As Figure 2 , in some embodiments, a stage 122 is provided in the transition chamber 120. The stage 122 is fixed to the bottom of the housing 120a through a lifting base motor 121. A tray 123 can be provided on the stage 122, and a multi-layer open-type transfer box 124 can be provided on the tray 123 to serve the function of simultaneously transferring wafers. In this embodiment, the stage 122 can be, for example, cylindrical or rectangular or other shapes, and the stage 122 can be fixed in the housing 120a through the lifting base motor 121, for example. A laser sensor 125 can be provided inside the housing 120a. The transition chamber 120 allows multiple wafers to enter simultaneously. Only vacuum pumping is required once at the beginning and air filling is required once at the end, saving the frequent pumping and filling time during intermediate wafer transfer and reducing the pumping and filling time consumption at the transfer nodes.

[0080] As Figure 1 and Figure 2, in some embodiments, the transition chamber 120 further includes an air extraction port, which is connected to a vacuum pump 327, and the transition chamber 120 is evacuated through the vacuum pump 127. A plurality of additional N2 gas paths are added in the transition chamber 120 to introduce gas, so as to provide air cooling to replace the cooling chamber when the chamber is not transferring wafers.

[0081] Please refer to Figure 1 and Figure 2 , in another embodiment of the present invention, the transition chamber 120 only realizes the transfer function of the substrate, and the plasma cleaning and cooling of the substrate are realized in the cleaning chamber 130. In this embodiment, the cleaning chamber 130 is connected to the transfer chamber 110, and the cleaning chamber 130 is located on the side wall of the transfer chamber 110. When the substrate enters the transition chamber 120, the substrate loading and unloading robotic arm 111 in the transfer chamber 110 then transfers the substrate from the transition chamber 120 to the cleaning chamber 130 for cleaning. After a thin film is grown on the substrate, the substrate is transferred to the cleaning chamber 130 for cooling.

[0082] As Figure 3 , in the cleaning chamber 130, a substrate support assembly 131 is provided. The substrate support assembly 131 is arranged at the bottom of the cleaning chamber 130 and does not contact the cleaning chamber 130. The substrate support assembly 131 includes a pedestal electrode 1311 and an electrostatic chuck 1312. The electrostatic chuck 1312 is arranged on the pedestal electrode 1311. The electrostatic chuck 1312 is used to place the substrate. At least one substrate can be placed on the electrostatic chuck 1312. In some embodiments, multiple substrates can be arranged on the electrostatic chuck 1312 to perform cleaning work on multiple substrates simultaneously, thereby improving work efficiency.

[0083] As Figure 3 , in this embodiment, the substrate support assembly 131 is connected to a lifting and rotating mechanism 134. Specifically, the lifting and rotating mechanism 134 is connected to the pedestal electrode 1311. Through the lifting and rotating mechanism 134, the lifting or rotation of the substrate support assembly 131 can be realized, indirectly realizing the lifting or rotation of the substrate. When the substrate support assembly 131 rotates up or down, the distance between the substrate and the electrode 132 changes to adjust the electric field strength between the pedestal electrode 1311 and the electrode 132, so that the plasma can better clean the substrate.

[0084] As Figure 3, in this embodiment, the cleaning chamber 130 further includes an electrode 132, which is disposed above the substrate support assembly 131 relatively, and the electrode 132 does not contact the top of the cleaning chamber 130. In some embodiments, the distance between the electrode 132 and the substrate support assembly 131 can be 2 - 25 cm. The electrode 132 is also connected to a lifting and rotating mechanism 133, and the structure of the lifting and rotating mechanism 133 is the same as that of the lifting and rotating mechanism 134. When the electrode 132 rotates, ascends or descends, the distance between the electrode 132 and the substrate changes to adjust the electric field strength between the electrode 132 and the substrate, so that the plasma can clean the substrate evenly. When the electrode 132 and the substrate support assembly 131 rotate simultaneously, the rotation speed of the electrode 132 and the rotation speed of the substrate support assembly 131 can be the same or there can be a certain speed difference, so that the plasma can clean the substrate evenly.

[0085] As Figure 3 , in this embodiment, the substrate support assembly 131 is also connected to at least one radio frequency bias power supply 138. Specifically, the radio frequency bias power supply 138 is connected to the pedestal electrode 1311. The radio frequency of the radio frequency bias power supply 138 can be high frequency, medium frequency or low frequency. The radio frequency power supply 137 and the radio frequency bias power supply 138 are both driven by synchronous pulses, can be switched on and off simultaneously, reduce the electron temperature in the cleaning chamber 130, and the synchronous pulses have good control over the cleaning (etching depth) of the dense substrate area.

[0086] As Figure 3 , in this embodiment, the cleaning chamber 130 further includes an air inlet, which is close to the electrode 132. The air inlet is connected to a gas source 135, and the gas source 135 is used to transport gas into the cleaning chamber 130. The gas is a precursor gas for cleaning applications. In this embodiment, the cleaning chamber 130 further includes an air extraction port, which is close to the substrate support assembly 131. The air extraction port is connected to a vacuum pump 136, and the vacuum pump 136 is used to extract the gas in the cleaning chamber 130.

[0087] As Figure 1 、 Figure 3 and Figure 4 As shown in

[0088] As Figure 4 shown, in another embodiment of the present invention, the preheating chamber 140 includes a housing 140a. A bracket 141 is provided at the bottom of the housing 140a. The bracket 141 can be, for example, a hollow structure. Then, a wire is placed in the internal structure of the bracket 141 and connected to a heater 142. In this embodiment, the bracket 141 can be made of, for example, a high-temperature resistant material.

[0089] As Figure 4 , a heater 142 is provided in the preheating chamber 140. The heater 142 is fixed on the bracket 141. The heater 142 can include a chassis and a heating coil provided at the bottom of the chassis. A plurality of measurement points are further provided on one side of the tray 143 close to the substrate 144. Then, the plurality of measurement points are connected to a temperature measurement device. The temperature measurement device can be provided inside the preheating chamber 140 or outside the preheating chamber 140. The temperature on the substrate 144 can be measured in real time through the temperature measurement device, so as to control the surface temperature and thermal uniformity of the substrate 144.

[0090] As Figure 4 , at least one air extraction port can be further provided at the bottom of the preheating chamber 140. The air extraction port is connected to a vacuum pump 145. The preheating chamber 140 is evacuated through the vacuum pump 145 to obtain a preheating chamber 140 in a vacuum state. At least one heater 142 is provided in the preheating chamber 140. It should be noted that a plurality of heaters 142 can also be provided on the side wall of the preheating chamber 140, or a plurality of heaters can be provided on the top of the preheating chamber 140 to ensure the uniformity of the overall temperature of the preheating chamber 140.

[0091] Please refer to Figure 4 again. At the top of the preheating chamber 140 and above the substrate 144, at least one electrode 149 can be provided. The electrode 149 does not contact the top of the preheating chamber 140, and the distance between the electrode 149 and the substrate 144 can be 2 - 25 cm, for example, 10 - 20 cm, or for example, 16 - 18 cm. The electrode 149 is also connected to a lifting and rotating mechanism 146. The structure of the lifting and rotating mechanism 146 can be the same as that of the lifting and rotating mechanism 133 in Figure 3 . When the electrode 149 rotates, rises or descends, the distance between the electrode 149 and the substrate changes to adjust the electric field strength between the electrode 149 and the substrate, so that the plasma can uniformly clean the substrate.

[0092] Please refer to Figure 3 and Figure 4, a lifting and rotating mechanism 134 and a radio frequency bias power supply 138 may also be provided on the bracket 141 and the heater 142. When the electrode 149 and the substrate 144 rotate simultaneously, the rotation speed of the electrode 149 may be the same as or have a preset speed difference from the rotation speed of the substrate 144 on the heater 142, so as to uniformly clean the substrate with plasma. And the electrode 149 is also connected to at least one radio frequency power supply 148, and the radio frequency power supply 148 is set in the same way as the Figure 3 radio frequency power supply 148 shown.

[0093] Please refer to again Figure 4 , an air inlet is also provided on the side wall of the preheating chamber 140. The air inlet is close to the electrode 149, and the air inlet is connected to a gas source 147. A gas is transported into the preheating chamber 140 through the gas source 147, and the gas is a precursor gas for cleaning applications.

[0094] Please refer to together Figure 1 , Figure 3 and Figure 4 , the process of plasma cleaning needs to be carried out in a high-temperature and constant environment. A plasma cleaning device is installed in the preheating chamber 140. While preheating the substrate, the substrate can be synchronously plasma cleaned. After the substrate is heated in the preheating chamber 140, it does not need to be transferred to the cleaning chamber 130 for cleaning. After preheating and cleaning in the preheating chamber 140, it can be directly transferred to the growth chamber 150 to form a thin film.

[0095] Please refer to Figures 5 to 7 , the growth chamber 150 includes a growth chamber housing 151, a base 152, a target 153 and a magnet 154. A circulating water cooling device 1508 is installed inside or on the side wall of the growth chamber 150, as shown in Figure 5 . The base 152 can be arranged at the bottom end of the growth chamber housing 151, and one or more substrates 155 are allowed to be placed on the base 152. The base 152 can be formed of a variety of materials, including silicon carbide or graphite coated with silicon carbide. The base 152 is also connected to a driving unit 156, and the driving unit 156 is connected to a control unit (not shown). The driving unit 156 is used to drive the base 152 to rise or fall. The driving unit 156 can adopt a driving device such as a servo motor or a stepping motor. The control unit is used to control the driving unit 156 to drive the base 152 to rise during the magnetron sputtering process, so that the distance between the target 153 and the base 152 always remains a predetermined value unchanged.

[0096] Please refer to Figures 5 to 7, in this embodiment, the target 153 is disposed at the top of the growth chamber housing 151. The target 153 is electrically connected to a sputtering power supply (not shown). During the magnetron sputtering process, the sputtering power supply outputs sputtering power to the target 153, so that the plasma formed in the growth chamber housing 151 etches the target 153. At least one surface portion of the target 153 is composed of a material that will be sputter-deposited on the substrate 155 disposed on the susceptor 152. When the magnet 154 in the machine process chamber is as large as the tray, for example, when it is less than or equal to 330 mm, the thickness of the aluminum nitride deposition at the outer position of the outer ring of the tray is relatively thin, which will affect the overall thickness uniformity. In this embodiment, the target 153 and the backplane 1509 are enlarged as a whole, and the diameter of the bombarded surface of the target 153 is set to be greater than or equal to, for example, 400 mm to 600 mm, so that the diameter of the coverage area of the magnet operation is greater than or equal to 400 mm to 600 mm. On the outside of the target 153 and the backplane 1509, a protective ring 1510 is used to surround them, and the protective ring is a ceramic ring or a stainless steel ring. In some embodiments, after the substrate 155 is loaded into the growth chamber housing 151, a continuous aluminum nitride thin film can be deposited on the substrate 155 by using an aluminum-containing target and a nitrogen-containing processing gas. The processing gas used during the sputtering process may include, but is not limited to, nitrogen-containing gases and inert gases.

[0097] Please refer to Figures 5 to 7, in this embodiment, the magnet 154 is located above the target 153. The magnet 154 rotates around the central axis of the target 153, and the magnet 154 can rotate around the central axis of the target 153 by any angle. In this embodiment, the magnet 154 is connected to a driving mechanism. While driving the magnet 154 to rotate, the driving mechanism can also perform reciprocating up and down movements. The driving mechanism includes a first motor 157, a transmission rod 158, a second motor 159 and a lifting assembly. The first motor 157 is connected to the second motor 159 through the transmission rod 158. The first motor 157 can drive the second motor 159 to perform reciprocating up and down movements through the transmission rod 158. Driving the transmission rod 158 by the first motor 157 to rotate forward or backward can make the second motor 159 perform reciprocating movements. In this embodiment, the lifting assembly includes an outer shaft 1501 and an inner shaft 1502. In this embodiment, the second motor 159 is connected to the inner shaft 1502 through an output shaft 1504. A part of the output shaft 1504 is located inside the outer shaft 1501. The second motor 159 can drive the inner shaft 1502 to rotate through the output shaft 1504. At the same time, the first motor 157 drives the second motor 159 to perform reciprocating up and down movements through the transmission rod 158. When the first motor 157 and the second motor 159 are turned on simultaneously, the inner shaft 1502 can perform rotational movements while performing reciprocating up and down movements, so as to drive the magnet 154 on the inner shaft 1502 to perform corresponding movements. When the first motor 157 is turned on and the second motor 159 is turned off, the inner shaft 1502 can only perform reciprocating up and down movements. When the first motor 157 is turned off and the second motor 159 is turned on, the inner shaft 1502 can only perform rotational movements. Thus, the staff can select to turn on and / or turn off the first motor 157 and / or the second motor 159 according to the actual situation.

[0098] Please refer to Figures 5 to 7 , in some embodiments, when the magnet 154 is performing rotational movements, the target 153 can remain stationary or rotate around its own central axis, but there is a speed difference between the target 153 and the magnet 154. The relative movement between the target 153 and the magnet 154 can make the magnetic field generated by the magnet 154 uniformly scan the sputtering surface of the target 153. And since in this embodiment the electric field and the magnetic field uniformly distributed on the sputtering surface of the target 153 act on the secondary electrons at the same time, the movement trajectories of the secondary electrons can be adjusted to increase the number of collisions between the secondary electrons and argon atoms, so that the argon atoms near the sputtering surface of the target 153 are fully ionized to generate more argon ions. And by bombarding the target 153 with more argon ions, the sputtering utilization rate and sputtering uniformity of the target 153 can be effectively improved, and further the quality and uniformity of the deposited thin film can be improved.

[0099] In an embodiment of the present invention, for a semiconductor device capable of realizing preheating and cleaning functions in a preheating chamber, the present application also proposes a method for using a semiconductor device, including:

[0100] S11: Place the multi-layer open transfer cassette in the transition chamber on the tray, and transfer the substrate to the preheating chamber;

[0101] S12: Bake and preheat in the preheating chamber, and introduce gas for plasma cleaning;

[0102] S13: Grow a thin film in the growth chamber;

[0103] S14: Introduce gas into the cleaning chamber to cool the tray.

[0104] As Figure 1 and Figure 8 shown, in an embodiment of the present invention, in a semiconductor device 100, for example, a chemical vapor deposition device, on the side wall of the transfer chamber 110, a plurality of deposition chambers are provided. Four deposition chambers are shown in this embodiment, namely the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163, and the fourth deposition chamber 164. The robotic arm 311 in the transfer chamber 110 can sequentially send the substrate or wafer into the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163, and the fourth deposition chamber 164 to form a thin film on the substrate or wafer. In this embodiment, at least one of the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163, and the fourth deposition chamber 164 includes a detachable cavity, and the detachable cavity means that the cavity can be detached separately without affecting the operation of the entire semiconductor device 100. In this embodiment, for example, the first deposition chamber 161 is set as a detachable cavity. In other embodiments, a detachable cavity can be set separately.

[0105] As Figure 9 shown, Figure 9 It shows a cross-sectional view of the first deposition chamber 161. As can be seen from the figure, the first deposition chamber 161 includes a main cavity 101, and a base 102 is arranged in the main cavity 101. The base 102 can be arranged at the bottom of the main cavity 101. A radio frequency component 103 is arranged at the top of the main cavity 101, and the radio frequency component 103 and the base 102 are arranged opposite to each other. The radio frequency component 103 and the base 102 form a plasma generation region. The material of the main cavity 101 is, for example, stainless steel. In some embodiments, the radio frequency component 103 can also rotate during deposition, so that the thin film deposition is more uniform.

[0106] As Figure 9 shown, in some embodiments, the base 102 can also be connected to a rotation unit for rotating the base 102 during film deposition to further improve the thickness uniformity of the coating and the stress uniformity of the coating.

[0107] As Figure 9As shown, of course, in some embodiments, a heating unit may also be provided on the back of the base 102, and the substrate can be heated through this heating unit. In some embodiments, the heating unit may specifically be a radio frequency heater, an infrared radiation heater, a resistance heater, etc., and different selections can be made according to the size and material of the main cavity 101. In the radio frequency heating mode, the graphite base 102 is heated by induction coupling with a radio frequency coil, and this heating form can be applied to a large main cavity 101.

[0108] As Figure 9 shown, in this embodiment, the radio frequency component 103 is also connected to a radio frequency power supply, and a voltage is provided to the radio frequency component 103 through the radio frequency power supply, thereby ionizing the reaction source gas into plasma.

[0109] As Figure 9 shown, in this embodiment, a gas inlet is further included at the top of the main cavity 101. An intake pipe 104 is connected to this gas inlet. One end of the intake pipe 104 is connected to the gas inlet, and the other end of the intake pipe 104 is connected to an external gas source 105. Through this external gas source 105, the intake pipe 104 and the gas inlet can transport the reaction gas into the main cavity 101.

[0110] As Figure 9 shown, in this embodiment, the gas inlet is provided on one side of the radio frequency component 103. The intake pipe 104 includes a first pipe 1041 and a second pipe 1042. One end of the first pipe 1041 is connected to the external gas source 105, and the other end of the first pipe 1041 is connected to the second pipe 1042. The first pipe 1041 is connected to the second pipe 1042 through a quick connector 107, for example. By rotating this quick structure 107, the first pipe 1041 and the second pipe 1042 can be connected or separated. A first valve body 106 is provided on the first pipe 1041. When transporting gas into the main cavity 101, the first valve body 106 is in an open state, for example. When the cavity needs to be disassembled, the first valve body 106 is in a closed state, for example, so as to prevent heavy metal dust from entering the clean room.

[0111] As Figure 9 and Figure 10 shown, in this embodiment, one end of the second pipe 1042 extends into the main cavity 101, and a diffusion plate 108 is provided at one end of the second pipe 1042. The diffusion plate 108 has a plurality of diffusion holes 1081. The reaction gas can be evenly diffused into the main cavity 101 through the diffusion holes 1081. It should be noted that the diameters of these diffusion holes 1081 can be the same or different, and the arrangement density of these diffusion holes 1081 can also be changed.

[0112] As Figure 9 and Figure 11As shown, in some embodiments, a plurality of air inlets may also be provided at the top of the main cavity 101, that is, a plurality of air inlet pipelines 104 are provided. For example, a first air inlet pipeline 104a and a second air inlet pipeline 104b are provided. The first air inlet pipeline 104a may be connected to a first air inlet device, and the second air inlet pipeline 104b may be connected to a second air inlet device. The first air inlet pipeline 104a and the second air inlet pipeline 104b are located on both sides of the main cavity 101, and the height of the first air inlet pipeline 104a is greater than the height of the second air inlet pipeline 104b. Due to the height difference between the first air inlet pipeline 104a and the second air inlet pipeline 104b, the gases delivered to the main cavity 101 through the first air inlet pipeline 104a and the second air inlet pipeline 104b will not affect each other.

[0113] As Figure 9 shown, in this embodiment, at least one exhaust port is further provided at the bottom of the main cavity 101. One end of an exhaust pipeline 109 is connected to the exhaust port, and the other end is connected to an air extraction pump 1013. The air extraction pump 1013 is used to perform an air extraction operation on the main cavity 101 to extract excess plasma, thereby reducing the probability of excess ions falling onto the thin film and improving the quality of the thin film. A second valve body 1014 is further provided at the bottom of the main cavity 101. The second valve body 1014 is located on the exhaust port. When performing the air extraction operation, the second valve body 1014 is in an open state. When the deposition operation is completed, the second valve body 1014 may be in a closed state to prevent the plasma from diffusing out.

[0114] As Figure 8 and Figure 12 shown, in this embodiment, the main cavity 101 further includes a substrate inlet. A robotic arm in the transfer chamber 110 places the substrate into the main cavity 101 through this substrate inlet. The substrate inlet includes two retractable doors 1011. When the two retractable doors 1011 are opened, that is, the substrate inlet is opened. When the two retractable doors 1011 are closed, that is, the substrate outlet is closed. The main cavity 101 is further connected to a locking unit 1012. When disassembling the main cavity 101, the locking unit 1012 can keep the substrate inlet in a locked state, that is, when the main cavity 101 is powered off, the locking unit 1012 can keep the substrate inlet in a closed or locked state. When the substrate inlet is in a locked state, it can prevent the remaining plasma in the main cavity 101 from diffusing into the clean room, thereby preventing heavy metal pollution in the clean room.

[0115] As Figure 9As shown, in this embodiment, the substrate inlet can also serve as the substrate outlet, that is, the robotic arm can put the substrate into the main cavity 101 or take the substrate out of the main cavity 101 through the substrate inlet. In some embodiments, the main cavity 101 can also include a substrate outlet, that is, the substrate outlet is disposed opposite to the substrate inlet. Therefore, when the robotic arm places the substrate in the main cavity 101 through the substrate inlet and then takes the substrate out of the main cavity 101 through the substrate outlet. Since the substrate outlet and the substrate inlet are disposed opposite to each other, when the substrate outlet is opened, the heavy metal dust in the main cavity 101 will not spread into the clean room, so the clean room will not be polluted.

[0116] As Figure 13 shown, in some embodiments, the end of the second pipeline 1042 can also be designed to be bent, and the bent shape faces between the radio frequency component 103 and the base 102, so that the gas diffuses between the radio frequency component 103 and the base 102.

[0117] As Figure 1 and Figure 9 shown, in this embodiment, the semiconductor device 100 includes a transfer chamber 110 and a detachable cavity. The robotic arm 111 in the transfer chamber 110 transfers or transfers out the substrate from the detachable cavity. When the operation is completed in any one of the cavities (including preheating, cleaning, deposition, growth, and cooling), by closing the first valve body and the second valve body, the gas in the gas source cannot enter the detachable cavity, and at the same time, the reaction gas in the detachable cavity cannot be discharged from the exhaust port. At the same time, the substrate inlet of the detachable cavity is closed by the locking unit, and then the detachable cavity is moved to another clean room, the substrate inlet is opened, and then the substrate is taken out, so as to avoid heavy metal pollution of the original clean room. Then the detachable cavity can be maintained, and then the detachable cavity is arranged outside the 310 of the transfer chamber.

[0118] As Figure 14 , in some embodiments, a plurality of reaction chambers 170 are provided in the coating system 180 of the semiconductor device 100. The reaction chamber 170 can be a growth chamber in a physical vapor deposition device or a deposition chamber in a chemical deposition device. In this embodiment, the reaction chamber 170 includes, for example, a first reaction chamber 171 and a second reaction chamber 172. And two chamber doors are provided on both the first reaction chamber 171 and the second reaction chamber 172, for example, a first chamber door 173 and a second chamber door 174. Each chamber door corresponds to a substrate loading and unloading robotic arm 111 for transfer, for example, a first robotic arm 111a corresponding to the first chamber door 173 and a second robotic arm 111b corresponding to the second chamber door 174. And an intake pipeline 183 and a transfer track 181 are provided on one side of the reaction chamber 170. And the first reaction chamber 171 and the second reaction chamber 172 are connected by an opening and closing valve, which can facilitate the transportation of the substrate and improve the processing efficiency.

[0119] As shown Figure 14 in FIG. 3, the first chamber door 173 and the second chamber door 174 are disposed on the first reaction chamber 171 and the second reaction chamber 172. In some embodiments, the first chamber door 173 and the second chamber door 174 are disposed on the same side of the reaction chamber. In other embodiments, the first chamber door 173 and the second chamber door 174 are disposed on opposite sides of the reaction chamber. The specific structures of the first chamber door 173 and the second chamber door 174 may be Figure 12 the retractable doors shown in FIG. 4, which will not be described again here. And during the actual film growth process, the first chamber door 173 serves as the substrate inlet / substrate outlet, and the second chamber door 174 serves as the substrate outlet / substrate inlet. Separating the substrate outlet from the substrate inlet can reduce the contamination of the substrate. The substrate loading and unloading robotic arm 111 corresponding to the chamber door includes a first robotic arm 111a and a second robotic arm 111b. During the transfer of the substrate, the first robotic arm 111a can, for example, introduce the substrate into the reaction chamber 170 through the first chamber door 173, and the second robotic arm 111b can, for example, take the substrate out of the reaction chamber 170 through the second chamber door 174. Setting two robotic arms can facilitate the picking up of the substrate, introduce and take out the substrate simultaneously, and differentiating the substrate loading and unloading robotic arms 111 for introduction and taking out can further reduce the contamination of the substrate, thereby improving the quality and uniformity of the deposited film.

[0120] As shown Figure 14 in FIG. 5, the susceptor 152 (or the base 102) is disposed on the top of the reaction chamber 170, and the target 153 (or the RF component 103) is disposed at the bottom of the reaction chamber 170. Opposite to the position in Figure 5 (or Figure 9 ), the reactants move from bottom to top. In some embodiments, the susceptor 152 has a fixed buckle for fixing the substrate. In this embodiment, the susceptor 152 is a magnetic susceptor, and multiple magnetic susceptors are allowed to be placed on the opposite side of the target 153. At this time, the susceptor 152 can directly adsorb the substrate on the susceptor 152 without the need for other structures to fix the substrate. The susceptor 152 can be made of materials such as sapphire, silicon carbide, silicon, gallium nitride, diamond, lithium aluminate, zinc oxide, tungsten, copper, and / or aluminum gallium nitride, etc., and a metal layer can be deposited on the susceptor 152 to make the susceptor 152 metallic. A magnet is disposed inside the susceptor 152 to make the susceptor 152 have an adsorption function. When the magnet rotates, the susceptor 152 can rotate around its own central axis. When the magnet rotates, the susceptor 152 can be driven to rotate around its own central axis by a power source such as a motor, so that the magnetic field generated by the magnet tightly adsorbs the susceptor 152, further improving the quality and uniformity of the deposited film, and the size of the susceptor 152 is, for example, 2 - 12 inches.

[0121] As shown Figure 14As shown, the transfer track 181 connects the reaction chamber 170 to other semiconductor devices, such as connecting the chamber door to other semiconductor devices, where the other semiconductor devices can be cleaning devices, preheating devices or other semiconductor devices. The inlet pipeline 182 is connected to an external gas source, and the external gas source sends gas into the reaction chamber 170 through the inlet pipeline 182. The inlet pipeline 182 may include a first inlet pipeline and a second inlet pipeline. The first inlet pipeline is connected to the first reaction chamber 171, and the second inlet pipeline is connected to the second reaction chamber 172. This design of the inlet pipeline facilitates the input and output of gas.

[0122] The semiconductor device of the present application can fabricate high-quality and pollution-free thin films, such as metal thin films, semiconductor thin films, insulating thin films, compound thin films or thin films of other materials.

[0123] As Figure 15 shown, in an embodiment of the present invention, when using the semiconductor device of the present disclosure to fabricate a semiconductor epitaxial structure 20, the semiconductor epitaxial structure 20 may include a substrate 200, and a first semiconductor layer 203, an active layer 204 and a second semiconductor structure 21 sequentially disposed on the substrate 200.

[0124] As Figure 15 shown, the substrate 200 may be a sapphire substrate 200. In other embodiments, the substrate 200 may also be made of materials such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc.

[0125] As Figures 15 to 16 shown, in some embodiments, the substrate 200 may be made of a crystal axis material with non-polarization reaction. The material of the substrate 200 has a crystal axis without piezoelectric effect, or a special flattening layer is formed on the substrate 200 to select the crystal phase direction of the substrate 200 and eliminate the influence of the piezoelectric effect on the substrate 200. In some embodiments, the substrate 200 may be made of materials with N-plane (1100) or A-plane (1120), such as GaN, AlN and InN, etc. In other embodiments, when the substrate 200 is other substrates 200, such as silicon-based materials such as SiCO3 and SiC, a flattening layer may be formed on the substrate 200 to eliminate lattice defects. The material of the flattening layer may be a compound composed of Group IIA elements and nitrogen, specifically, non-polar AlN material or non-polar GaN material. Selecting a special crystal axis material or setting a flattening layer can avoid the generation of lattice torsion in the substrate 200 when a large current is introduced, and further generate piezoelectric voids, resulting in heat cracking of the material.

[0126] As Figure 15As shown, in some embodiments, in order to obtain a flat surface of the substrate 200, after grinding and polishing the surface of the substrate 200, stress marks exist on the surface of the substrate 200, which will form defects with the semiconductor layer disposed thereon. The broken crystal particles on the surface of the substrate 200 can be oxidized to form broken crystal oxides, and then the broken crystal oxides can be cleaned with an oxide etching solution, thereby obtaining a flat surface of the substrate 200. In a specific embodiment, the substrate 200 is, for example, a silicon substrate, and preliminary surface processing can be performed through processes such as grinding or polishing to form broken crystal particles of silicon on the surface of the substrate 200. The generation of broken crystal particles results in stress marks on the crystal lattice, affecting the growth of the crystal. Therefore, it is necessary to process the broken crystal particles. In this embodiment, physical or chemical methods can be selected to eliminate the influence brought by the broken crystal particles. When using the physical method, the substrate 200 can be heated in a preheating chamber so that the surface temperature of the substrate 200 reaches, for example, 300 to 400 degrees, and at the same time, oxygen or other oxides are introduced into the chamber to cause the broken crystal particles to undergo an oxidation reaction to generate broken crystal oxides. When using the chemical method, an oxidant such as hydrogen peroxide can be used to react with the broken crystal particles to generate broken crystal oxides. During the reaction process, the oxidation reaction rate can be increased by raising the temperature, and the temperature range is, for example, 40 to 80 degrees. In this embodiment, the broken crystal oxide is silicon dioxide. After oxidation, a dense silicon dioxide layer is formed on the surface of the substrate 200, which can be cleaned with an oxide etching solution, thereby obtaining a substrate 200 with a complete crystal form and making the substrate 200 free of broken crystal defects. In this embodiment, hydrofluoric acid or ammonium sulfide can be used to remove the broken crystal oxides. In other embodiments, the material of the substrate 200 is not limited to a silicon substrate, and SiC substrates and other substrates can also be selected. Due to the different materials of the substrate 200, different methods can be used to oxidize the broken crystal particles and different solutions can be used to remove the broken crystal oxides.

[0127] As Figure 15As shown, in some embodiments, a buffer layer 201 is disposed between the first semiconductor layer 203 and the substrate 200 to mitigate the lattice mismatch between the first semiconductor layer 203 and the substrate 200, which may otherwise lead to defects such as dislocations, stacking faults, or voids. The material of the buffer layer 201 may include, but is not limited to, materials such as aluminum nitride and gallium nitride. However, the buffer layer 201 is not sufficient to solve the lattice mismatch problem, resulting in voids. In this embodiment, by disposing a transition metal layer between the substrate 200 and the buffer layer 201, the lattice mismatch problem between the first semiconductor layer 203 and the buffer layer 201 can be further alleviated. The material of the transition metal layer may be selected from Group IIA elements. For example, aluminum can be selected as the lattice paving layer. After depositing the transition metal layer on the substrate 200, the transition metal layer is annealed to form an annealing interface between the surface of the silicon substrate 200 and the transition layer. During annealing, the cavity is filled with an inert gas, such as nitrogen. During the annealing process, at the interface between the transition metal layer and the substrate 200, the lattice conversion of the metal Al in the transition metal layer and the Si in the substrate 200 reduces defects such as dislocations generated when directly growing the buffer layer 201 on the silicon substrate. The annealing temperature range can be, for example, 400 to 600 degrees, and the specific temperature can be, for example, 520 degrees. The annealing time range can be, for example, 5 to 30 minutes.

[0128] As Figure 15 shown, in other embodiments, the buffer layer 201, for example, includes periodic aluminum nitride layers and blocking layers. Since there are too many defects when only the aluminum nitride layer serves as the buffer layer, blocking layers can be periodically inserted into the aluminum nitride layer to block the defects and thus improve the lattice defects. For example, the temperature of the reaction chamber can be set to, for example, 500 to 1000 degrees, and a buffer layer 201 with a thickness of, for example, 20 to 300 nm is grown. Specifically, an aluminum nitride layer with a thickness of, for example, 10 to 25 nm is first grown and then the growth is stopped. At this time, the surface of the aluminum nitride layer is purged with nitrogen oxides or oxygen for 30 to 60 seconds, and an aluminum oxide layer with a thickness of, for example, 3 to 5 nm is formed on the surface of the aluminum nitride layer as the blocking layer. The blocking layer is, for example, spherical aluminum oxide. Disposed at the location of the defects, it can block the lattice defects. As the thickness of the buffer layer 201 increases, the lattice defects become fewer, thus improving the quality of the buffer layer 201. The nitrogen oxides can be nitrous oxide (N2O) or nitrogen dioxide (NO2). This process of growing the aluminum nitride layer and then forming the blocking layer on the aluminum nitride layer is repeated until a buffer layer 201 with a thickness of, for example, 20 to 300 nm is finally formed. Each blocking layer can mitigate the lattice defects in the aluminum nitride layer above it, such that the higher the thickness of the buffer layer 201, the fewer the defects. The thickness of the aluminum nitride layer grown each time can be specifically set according to the required thickness of the buffer layer 201, and the present application has no limitation on this.

[0129] As Figure 15As shown, in other embodiments, the buffer layer 201 is, for example, a gallium nitride layer. Specifically, ammonia gas and trimethylgallium (TMGa) can be introduced into the reaction chamber under conditions such as a temperature of, for example, 500 to 850 °C, or for example, 500 to 550 °C, and a reaction chamber pressure of, for example, 100 Torr to 650 Torr, or for example, 200 to 500 Torr, so as to grow a layer of gallium nitride with a thickness of, for example, 200 to 400 angstroms or 400 to 600 angstroms on the substrate 200 to form the buffer layer 201.

[0130] As Figure 15 shown, after the buffer layer 201 is formed, an undoped gallium nitride layer 202 can be grown on the buffer layer 201. Specifically, ammonia gas and trimethylgallium (TMGa) can be introduced into the reaction chamber under conditions such as a temperature of, for example, 1000 to 1200 °C, or for example, 1050 °C to 1200 °C, and a reaction chamber pressure of, for example, 100 Torr to 500 Torr, or for example, 200 to 500 Torr, so as to grow a layer of gallium nitride with a thickness of, for example, 10,000 to 30,000 angstroms on the buffer layer 201 to form the undoped gallium nitride layer 202. By providing the buffer layer 201 and the undoped gallium nitride layer 202 between the substrate 200 and the first semiconductor layer 203, the lattice mismatch problem between the substrate 200 and the first semiconductor layer 203 can be alleviated, and the quality of the semiconductor epitaxial structure 20 can be improved.

[0131] As Figure 15 shown, the first semiconductor layer 203 is, for example, a first-type gallium nitride layer, specifically, an N-type gallium nitride layer, and the doping ions of the first semiconductor layer 203 can be silicon. In this embodiment, ammonia gas, trimethylgallium (TMGa), and silane (SiH4) can be introduced into the reaction chamber under conditions such as a temperature of, for example, 1000 to 1200 °C, or for example, 1050 °C to 1200 °C, and a reaction chamber pressure of, for example, 100 Torr to 600 Torr, or for example, 200 to 500 Torr, so as to grow an N-type gallium nitride layer with a thickness of, for example, 10,000 to 30,000 angstroms, or for example, 20,000 to 40,000 angstroms on the undoped gallium nitride layer 202. The ion concentration of silicon ions in the first semiconductor layer 203 is, for example, 1×10 18 ~7×10 18 atom / cm 3 ³, or for example, 8×10 18 ~2×10 19 atoms / cm3. In some embodiments, the first semiconductor layer 203 can be a superlattice structure of an N-type gallium nitride layer doped with silicon ions and an undoped gallium nitride layer. In other embodiments, the first semiconductor layer 203 can include an N-type gallium nitride layer and a superlattice structure provided on the N-type gallium nitride.

[0132] As Figure 15 shown, the active layer 204 is located on the first semiconductor layer 203. In this embodiment, the active layer 204 includes one or more periodically formed alternating quantum barrier layers and quantum well layers. The quantum barrier layer includes, for example, a GaN / AlGaN superlattice structure, and the quantum well layer includes, for example, InGaN. The thickness of the active layer 204 is, for example, 200 nm to 300 nm, the thickness of each period of the quantum well layer is, for example, 3 nm to 4 nm, and the thickness of each period of the quantum barrier layer is, for example, 12 nm to 16 nm. Among them, the thickness of GaN in the quantum barrier layer is, for example, 1.5 nm to 3 nm, and the thickness of AlGaN in the quantum barrier layer is, for example, 1.5 nm to 3 nm. The active layer 204 in this embodiment adopts a modulation-doped GaN / AlGaN superlattice structure, which can effectively guide the impact current, enable the pulsed current to conduct in the two-dimensional electron gas of the GaN / AlGaN structure in the transverse direction, make the density distribution of the pulsed current more uniform, and effectively improve the recombination efficiency of electrons and holes.

[0133] As Figure 15 shown, a layer of GaN with a thickness of, for example, 1 nm to 3 nm can be grown under conditions such as a temperature of 810 to 860 °C and a pressure of 200 to 500 Torr, and then a layer of modulation-doped AlGaN with a thickness of, for example, 1 nm to 3 nm is grown on the GaN. GaN and AlGaN form a superlattice unit structure, and 2 to 6 cycles of the superlattice unit structure are alternately and continuously grown to form the quantum barrier layer of the superlattice structure. After forming the quantum barrier layer, the growth conditions are changed, and under conditions such as a temperature of 710 to 760 °C and a pressure of 200 to 500 Torr, InGaN with a thickness of, for example, 2 to 6 nm is grown on the quantum barrier layer to form the quantum well layer, where the indium source is, for example, trimethylindium (TMIn). By alternately and continuously growing 2 to 6 or 9 to 12 cycles of the quantum barrier layer and the quantum well layer, the active layer 204 can be formed.

[0134] As Figure 15 shown, in some embodiments, the second semiconductor structure 21 may include a second semiconductor layer 205 and a hole injection layer 22. The second semiconductor layer 205 is located on the active layer 204, and the hole injection layer 22 is located on the second semiconductor layer 205. The second semiconductor layer 205 is an electron blocking layer, which can be a second-type gallium nitride layer, or can be a second-type aluminum gallium nitride layer, or can be made of AlGaN with non- or low-doped magnesium. In some embodiments, the second semiconductor layer 205 includes 3 to 10 cycles of P-type GaN layers and P-type AlGaN layers.

[0135] Specifically, as Figure 15As shown, in one embodiment, when the second semiconductor layer 205 is a P-type AlGaN layer, AlGaN with a thickness of 5 - 10 nm can be grown on the active layer 204 under conditions such as a temperature of 700 - 950 °C and a pressure of 50 - 500 Torr to form a P-type AlGaN layer, where the Mg doping concentration is 0 - 1×10 16 atom / cm3.

[0136] Specifically, as Figure 15 shown, in other embodiments, when the second semiconductor layer 205 includes a single layer of P-type GaN layer and P-type AlGaN layer, GaN with a thickness of, for example, 20 - 30 nm can be grown under conditions such as a temperature of 700 - 900 °C and a pressure of 200 - 500 Torr to form a P-type GaN layer, where the Mg doping concentration is 1×10 19 ~1×10 20 atom / cm3. Then, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 - 500 Torr, AlGaN with a thickness of, for example, 5 - 10 nm is grown on the P-type GaN layer to form a P-type AlGaN layer, where the Mg doping concentration is, for example, 1×10 19 atom / cm3.

[0137] Specifically, as Figure 15 shown, in yet another embodiment, when the second semiconductor layer 205 includes periodic P-type GaN layers and P-type AlGaN layers, GaN with a thickness of, for example, 5 - 10 nm can be grown on the active layer 204 under conditions such as a temperature of 700 - 800 °C and a pressure of 200 - 500 Torr to form a P-type GaN layer, where the Mg doping concentration is 1×10E 19 atom / cm3. Under conditions such as a temperature of 700 - 950 °C and a pressure of 50 - 500 Torr, AlGaN with a thickness of, for example, 5 - 10 nm is grown on the P-type GaN layer to form a P-type AlGaN layer, where the Mg doping concentration is 0 - 1×10E16 atom / cm3. And the P-type GaN layer and the P-type AlGaN layer are alternately and continuously grown for 3 - 10 cycles.

[0138] As Figure 15 shown, the hole injection layer 22 is located on the second semiconductor layer 205, and the hole injection layer 22 includes a non- or lightly doped In x Ga y N layer, and / or a doped In x Ga y N layer, that is, the hole injection layer 22 includes In x Ga yN layers, where 0 ≤ x ≤ 1 and 0 ≤ y ≤ 1. Among them, undoped In x Ga y The N layer is an In x Ga y N layer doped with In x Ga y The N layer is, for example, In x Ga y N made by doping with Mg.

[0139] As Figure 15 shown, in a specific embodiment, the second semiconductor layer 205 is, for example, a P-type aluminum gallium nitride layer, and the hole injection layer 22 provided thereon includes at least a first doping layer 206 and a second doping layer 207. The first doping layer 206 is located on the second semiconductor layer 205, and the second doping layer 207 is located on the first doping layer 206. The first doping layer 206 is a non- or lightly doped InxGayN layer, and the doping concentration of the first doping layer 206 is, for example, the first doping concentration. The second doping layer 207 is a doped InxGayN layer, and the doping concentration of the second doping layer 207 is, for example, the second doping concentration. The second semiconductor layer 205 has, for example, a third doping concentration. Among them, the first doping concentration is less than the second doping concentration, the third doping concentration is less than the second doping concentration, and the range of the first doping concentration is 0 to 1×10 19 atom / cm 3 . And the thickness of the first doping layer 206 is less than the thickness of the second doping layer 207. The thickness of the first doping layer 206 is, for example, 40% - 50% of the thickness of the second doping layer 207, specifically, for example, 30% of the thickness of the second doping layer 207.

[0140] As Figure 15 shown, in another embodiment of the present invention, the hole injection layer 22 includes a first doping layer 206 and a second doping layer 207, and the first doping layer 206 is an undoped InxGayN layer, and the second doping layer 207 is a doped InxGayN layer, that is, the first doping concentration of the first doping layer 206 is zero, and the second doping layer 207 is an InxGayN layer doped with magnesium.

[0141] As Figure 15 shown, in other embodiments, the hole injection layer 22 further includes a third doping layer. The third doping layer is located on the second doping layer 207. The third doping layer is, for example, InxGayN doped with magnesium, and the fourth doping concentration of the third doping layer is greater than the second doping concentration.

[0142] As Figure 15As shown, in a specific embodiment, the first doped layer 206 is an undoped InxGayN layer, the second doped layer 207 is a lightly doped InxGayN layer, and the third doped layer is a doped InxGayN layer. Then, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 - 500 Torr, GaN with a thickness of, for example, 2 - 5 nm is grown, and the formed undoped InxGayN layer is the first doped layer 206. Next, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 - 500 Torr, GaN with a thickness of, for example, 5 - 50 nm is grown, wherein the doping concentration of magnesium is, for example, 1×10 16 ~1×10 17 atom / cm3, and the formed lightly doped InxGayN layer is the second doped layer 207. Finally, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 - 500 Torr, GaN with a thickness of, for example, 10 - 20 nm is grown, wherein the doping concentration of magnesium is 1×10 18 ~1×10 19 atom / cm3, and the formed doped InxGayN layer is the third doped layer.

[0143] As Figure 15 shown, in another embodiment of the present invention, the doped In x Ga y N layer includes, but is not limited to, the superposition of n layers of In x1 Ga y1 N, In x2 Ga y2 N, In x3 Ga y3 N, or an n - cycle loop of alternating In x1 Ga y1 N and In x2 Ga y2 N, where n≥1, X3 < X2 < X1 ≤ 1, Xn <... < X3 < X2 < X1 ≤ 1. In a specific embodiment, N is equal to 3, X1 is equal to 1, X2 is equal to 0.2, and X3 is equal to 0.05, that is, the hole injection layer 22 includes InN, In 0.2 Ga 0.8 N, In 0.05 Ga 0.95 N doped layers arranged in sequence. The hole injection layer 22 described in the present invention can effectively increase the hole concentration of the epitaxial structure and improve the light - emitting efficiency.

[0144] As Figure 17As shown, in another embodiment of the present invention, a semiconductor epitaxial structure 20 with good high-wavelength stability is further provided, and the semiconductor epitaxial structure 20 is a green-light epitaxial structure. The active layer 204 includes, for example, a stress relaxation layer 208, a first active layer 209, and a second active layer 210. The first active layer 209 is located on the stress relaxation layer 208, and the second active layer 210 is located on the first active layer 209.

[0145] As Figure 17 shown, the material of the stress relaxation layer 208 is InxGa(1-x)N and GaN, where 0.17 < x < 0.35, and GaN is doped with silicon ions. The doping concentration of the silicon ions is, for example, a, and the range of a is 5×10 17 ~1×10 18 atoms / cm 3 , and the thickness of the stress relaxation layer 208 is 3 - 40 nm. Specifically, the stress relaxation layer 208 may include periodically cycled quantum well layers and quantum barrier layers, and the growth period of the stress relaxation layer 208 is, for example, 2 - 6, or for example, 3. In this embodiment, ammonia (NH3) with a flow rate of, for example, 30000 - 60000 sccm, triethylgallium (TEGa) with a flow rate of 50 - 100 sccm, trimethylindium (TMIn) with a flow rate of 500 - 1000 sccm, and nitrogen (N2) with a flow rate of 100 - 130 L / min may be introduced under the conditions that the temperature is, for example, 750 - 950 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, so as to grow a 1 nm - 3 nm thick InGaN layer on the first semiconductor layer 203 to form a quantum well layer. Then, under the conditions that the temperature is, for example, 750 - 950 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, ammonia (NH3) with a flow rate of 30000 - 60000 sccm, trimethylgallium (TMGa) with a flow rate of 100 - 200 sccm, nitrogen (N2) with a flow rate of 100 - 130 L / min, and silane (SiH4) with a flow rate of 1 - 2 sccm may be introduced to grow a 30 - 40 nm thick N-type GaN layer on the quantum well layer to form a quantum barrier layer. By repeating the growth of the quantum well layer and the quantum barrier layer for 2 - 6 cycles, the stress relaxation layer 208 can be obtained.

[0146] As Figure 17 shown, the first active layer 209 includes, for example, 3 - 8 periodically cycled barrier layers and well layers, and the specific number of cycles is, for example, 5. In some embodiments, the material of the barrier layer is, for example, AlzGa(1-z)N, where 0 ≤ z < 0.3, and the material of the well layer is, for example, InyGa(1-y)N, where 0.17 < y < 0.4. The barrier layer is doped with silicon ions, and the doping concentration of the silicon ions is b, and a > b, and the range of b is 5×10 16 ~1×10 17atoms / cm 3 。In other embodiments, the material of the barrier layer may also be GaN, or a superlattice layer of 2 to 6 cycles of alternating growth of AlGaN and GaN. The thickness L1 of the barrier layer is, for example, 70 to 150 angstroms, or for example, 120 angstroms. In this embodiment, ammonia gas (NH3) with a flow rate of 50,000 - 70,000 sccm, triethylgallium (TEGa) with a flow rate of 200 - 1000 sccm, silane (SiH4) with a flow rate of 1 - 2 sccm, and nitrogen gas (N2) with a flow rate of 100 - 130 L / min may be introduced into the reaction chamber under the conditions of a temperature of, for example, 750 - 900 °C and a reaction chamber pressure of, for example, 200 - 500 Torr, so as to grow an N-type GaN layer with a thickness of 1 nm to 3 nm on the stress release layer 208 to form the barrier layer. Further, under the conditions of a temperature of, for example, 710 - 760 °C and a reaction chamber pressure of, for example, 200 - 500 Torr, an InGaN layer with a thickness of 2 - 6 nm is grown on the barrier layer to form the quantum well layer. Repeating the growth of the barrier layer and the quantum well layer for 3 - 8 cycles can form the first active layer 209.

[0147] As Figure 17 shown, the second active layer 210 includes 2 to 6 cycles of In u Ga 1-u N and GaN. The specific number of cycles is, for example, 3. The indium content of In u Ga 1-u N in the second active layer 210 is 0.17 < u < 0.40. The GaN in the second active layer 210 is doped with silicon ions, and the doping concentration of the silicon ions is c, and a > c > b. The range of c is 5 × 10 16 -1 × 10 17atoms / cm3 and c can be 1.4 times that of b. In a specific embodiment of the present invention, the second active layer 210 includes a quantum well layer made of N-type GaN and a quantum barrier layer made of InGaN. In other embodiments, the quantum well layer can also be a superlattice layer of GaN doped with undoped Si and GaN doped with Si layer. In this embodiment, for example, under the conditions that the temperature is, for example, 750-900 °C and the reaction chamber pressure is, for example, 200-500 Torr, ammonia gas (NH3) with a flow rate of, for example, 50000-70000 sccm, triethylgallium (TEGa) with a flow rate of 200-1000 sccm, silane (SiH4) with a flow rate of 1-2 sccm, and nitrogen gas (N2) with a flow rate of 100-130 L / min are introduced into the reaction chamber, and then a layer of 1 nm to 3 nm of N-type GaN is grown on the first active layer 209 to form a quantum well layer. The thickness L2 of the quantum well layer ranges from 70 to 150 Å, and L1 > L2 = 100 Å. Further, under the conditions that the temperature is, for example, 710-760 °C and the reaction chamber pressure is, for example, 200-500 Torr, a layer of InGaN with a thickness of 2-6 nm is grown on the quantum barrier layer to form a quantum well layer. By repeating the growth of the quantum barrier layer and the quantum well layer for 2-6 cycles, the second active layer 210 can be formed.

[0148] As Figure 17 shown, the second semiconductor structure 21 includes a second semiconductor layer 205, a third semiconductor layer 211, and a fourth semiconductor layer 212. The third semiconductor layer 211 is located on the second semiconductor layer 205, and the fourth semiconductor layer 212 is located on the third semiconductor layer 211. The second semiconductor layer 205 is a P-type AlGaN layer, and the third semiconductor layer 211 and the fourth semiconductor layer 212 are P-type GaN layers. The P-type GaN layer is, for example, a GaN layer doped with Mg, and the doping concentration of the fourth semiconductor layer 212 is greater than that of the third semiconductor layer 211. In this embodiment, under the conditions that the temperature is, for example, 700-800 °C and the reaction chamber pressure is, for example, 200-500 Torr, AlGaN with a thickness of 5-10 nm is grown on the active layer 204 to form the second semiconductor layer 205. Among them, the doping concentration of Mg in the second semiconductor layer 205 is 1×10 18 ~1×10 19 atom / cm3. Then, under the conditions that the temperature is, for example, 800-950 °C and the reaction chamber pressure is, for example, 200-500 Torr, GaN with a thickness of 20-30 nm is grown to form the third semiconductor layer 211. Among them, the doping concentration of Mg is 1×10 19 ~1×10 20atom / cm3. Finally, under the conditions that the temperature is, for example, 800 - 950 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, GaN with a thickness of 10 - 20 nm is grown to form the fourth semiconductor layer 212. Among them, the doping concentration of Mg is 1×10 18 ~1×10 19 atom / cm3.

[0149] As Figure 18 shown, in another embodiment of the present invention, to ensure that the formed light-emitting diode does not flicker due to too fast reaction, a resistor layer 214 with a special structure can be provided between the first semiconductor layer 203 and the active layer 204, which can delay the extinction time of the diode. And the semiconductor epitaxial structure 20 with the resistor layer 214 having a special structure can be made into a light-emitting diode. When used in conjunction with an energy-saving power supply, the total power-on time can be reduced to save energy consumption. At the same time, the same brightness can be maintained for the human eye to feel, the influence brought by flicker can be reduced, and thus the harm of strong light to the human eye can be reduced.

[0150] As Figure 18 shown, the first semiconductor layer 203 is a gallium nitride layer, and a superlattice structure 213 is provided on the gallium nitride layer. The resistor layer 214 is provided on the gallium nitride layer and is located between the gallium nitride layer and the superlattice structure 213. In this embodiment, the gallium nitride layer includes, for example, a lightly doped N-type gallium nitride layer 203a and a heavily doped N-type gallium nitride layer 203b. A resistor layer 214 is provided on the heavily doped N-type gallium nitride layer 203b, and a superlattice structure 213 is provided on the resistor layer 214. The active layer 204 is located on the superlattice structure 213. The resistor layer 214 provided in this embodiment can slow down the discharge speed of the finally formed light-emitting diode, extend the discharge time of the light-emitting diode, and avoid the flicker of the light-emitting diode caused by unstable power supply or low duty cycle.

[0151] As Figure 18As shown, the material of the resistor layer 214 is, for example, AlxGa1-xN, and x < 0.15. The thickness of the resistor layer 214 is, for example, 50 - 200 nm, which can avoid the problem that the resistor layer 214 is too thin to control the growth and the problem that the resistor layer 214 is too thick and cracks. A plurality of openings 215 are etched in the photoresist layer. The direction of the openings 215 is parallel to the growth direction of the resistor layer 214, and the diameter of the openings 215 is, for example, 3 - 20 μm, and the distance between adjacent openings 215 is, for example, 3 - 10 μm. In this embodiment, trimethylgallium (TEGa), trimethylaluminum (TMAL), and ammonia (NH3) can be introduced into the reaction chamber under the conditions that the temperature is, for example, 700 - 900 and the pressure of the reaction chamber is, for example, 500 mbar, and the resistor layer 214 is formed by metalorganic chemical vapor deposition (MOCVD). After the formed resistor layer 214, an inductively coupled plasma etching method is used to etch the resistor layer 214 to form the openings 215, and the openings 215 penetrate the resistor layer 214 and contact the heavily doped N-type gallium nitride layer 203b.

[0152] As Figure 19 shown in the equivalent circuit of the etched semiconductor epitaxial structure 20, C is the equivalent capacitance of the semiconductor epitaxial structure 20 without adding the resistor layer 214, R0 is the equivalent resistance of the semiconductor epitaxial structure 20 without adding the resistor layer 214, R L is the equivalent resistance of the resistor layer 214, and R L can be adjusted by adjusting the number or diameter of the openings on the resistor layer 214. E is the voltage across the semiconductor epitaxial structure 20. Then the discharge formula of the capacitor is: Vt = E×(exp(-t / R*C)), and the discharge time of the capacitor is: t = RC×Ln[E / Vt], and R = R0 + R L . It can be seen from the above formula that the length of the discharge time is proportional to the resistance R. The larger the resistance R, the more difficult the electron flow is, and the longer the discharge time is. The size of R L can be adjusted according to actual needs, that is, the equivalent resistance of the resistor layer 214 can be adjusted by the number and diameter of the openings 215. The more the number of the openings and the larger the diameter, the smaller the equivalent resistance of the resistor layer 214, and the openings can also limit the current outflow.

[0153] The high-quality thin film formed in this application can be applied to various semiconductor structures, electronic components or electronic devices, such as switching elements, power elements, radio frequency elements, light-emitting diodes, micro light-emitting diodes, display panels, mobile phones, watches, laptop computers, carrier devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles or other electronic devices.

[0154] As Figure 20As shown, the invention in this embodiment and subsequent embodiments is applicable to micro light-emitting diodes, including microLEDs, and can also be miniLEDs, or other light-emitting diodes. In this application, micro light-emitting diodes are taken as an example. Among them, the micro light-emitting diode includes a substrate 200 and a semiconductor epitaxial structure 20 disposed on the substrate 200, and the semiconductor epitaxial structure 20 includes a first semiconductor layer 203, an active layer 204, and a second semiconductor structure 21. The micro light-emitting diode further includes a first electrode 226 connected to the first semiconductor layer 203 and a second electrode 227 connected to the second semiconductor structure 21. And the substrate 200 is, for example, a sapphire substrate 200, and the semiconductor epitaxial structure 20 can be, for example, Figure 15 , Figure 16 or Figure 17 the semiconductor epitaxial structure 20 shown. In some embodiments, on one side of the semiconductor epitaxial structure 20, such as Figure 15 and Figure 16 shown, a notch 23 can be provided. The notch 23 is provided on one side of the semiconductor epitaxial structure 20, and the bottom of the notch 23 is in contact with the first semiconductor layer 203. In some embodiments, the notch 23 is in contact with the surface of the first semiconductor layer 203. In other embodiments, the second semiconductor structure 21, the active layer 204, and a part of the first semiconductor layer 203 can be etched to form the notch 23.

[0155] Such as Figure 20 shown, a transparent conductive layer 220 is formed on the second semiconductor structure 21. The transparent conductive layer 220 covers the second semiconductor structure 21, and the transparent conductive layer 220 can be made of materials such as indium tin oxide, zinc gallium oxide, zinc oxide, or indium zinc oxide. In some embodiments, the transparent conductive layer 220 covers a part of the second semiconductor structure 21. On both sides of the transparent conductive layer 220, the transparent conductive layer 220 and the second semiconductor layer form a step 228. In other embodiments, the transparent conductive layer 220 can completely cover the second semiconductor structure 21. When the notch 23 is provided on the semiconductor epitaxial structure 20, the transparent conductive layer 220 can cover the first semiconductor layer 203.

[0156] Such as Figure 20As shown, after forming the transparent conductive layer 220, a metal material can be deposited on the first semiconductor layer 203 and the transparent conductive layer 220 respectively, for example, depositing a titanium / titanium nitride barrier layer and tungsten metal, forming a first conductive plug 221 on the first semiconductor layer 203, and forming a second conductive plug 222 on the transparent conductive layer 220. The first conductive plug 221 and the second conductive plug 222 are flush, and the first conductive plug 221 covers a part of the first semiconductor layer 203, and the second conductive plug 222 covers a part of the transparent conductive layer 220. In some embodiments, an opening can be formed on one side of the semiconductor epitaxial structure 20, and the bottom wall of the opening is in contact with the first semiconductor layer 203. An insulating material is laid on the side wall of the opening, and the first conductive plug 221 is formed in the opening and on the opening. In other embodiments, a notch 23 is provided on the semiconductor epitaxial structure 20, and the first conductive plug 221 can be directly formed on the notch 23.

[0157] As Figure 20 As shown, after forming the first conductive plug 221 and the second conductive plug 222, a reflective layer 223 and a protective layer 224 are sequentially deposited on the first semiconductor layer 203 and the transparent conductive layer 220. The reflective layer 223 covers the transparent conductive layer 220 and the step 228, and exposes part of the first conductive plug 221 and the second conductive plug 222. The protective layer 224 covers the reflective layer 223, and part or all of the first conductive plug 221 and the second conductive plug 222. After forming the reflective layer 223 and the protective layer 224, the protective layer 224, the reflective layer 223 and the semiconductor epitaxial structure 20 outside the diode chip are etched to form a trench 229. An insulating layer 225 is deposited in the trench 229 and on the protective layer 224, and the insulating layer 225 completely covers the first conductive plug 221 and the second conductive plug 222. The insulating layer 225 and the protective layer 224 are etched to form an opening above the first conductive plug 221 and the second conductive plug 222. The opening exposes part of the first conductive plug 221 and part of the second conductive plug 222, and the area of the opening is larger than the radial dimensions of the first conductive plug 221 and the second conductive plug 222. Metal is deposited in the opening to form a first electrode 226 connected to the first conductive plug 221 and a second electrode 227 connected to the second conductive plug 222. After laser cutting and splitting, after dot separation is completed, a micro light-emitting diode is formed.

[0158] As Figure 21As shown, other structures can be added to the light-emitting diode to change the light-emitting direction of the micro light-emitting diode. Specifically, the light-emitting direction of the micro light-emitting diode can be changed according to specific requirements. When the micro light-emitting diode is used as a backlight, in order to reduce the light mixing distance and thus meet the ultra-thin requirements of electronic devices such as displays, large-angle micro light-emitting diodes can be set. In one embodiment, a light-scattering stack 230 can be provided on the substrate 200 of the micro light-emitting diode and on the side relative to the semiconductor epitaxial structure 20 to increase the light-emitting angle of the micro light-emitting diode, so that the angle of the micro light-emitting diode is greater than or equal to 160 degrees. For convenience of description, in this application, the side where the semiconductor epitaxial structure 20 is located is defined as the upper surface of the substrate 200, and the side of the substrate 200 relative to the semiconductor epitaxial structure 20 is defined as the lower surface.

[0159] As Figure 21 shown, the light-scattering stack 230 includes a light-guiding layer 231, a first reflective layer 232, a light oscillation layer 233, and a second reflective layer 234 provided on the lower surface of the substrate 200. Specifically, the light-guiding layer 231 covers the lower surface of the light-guiding layer 231, and the refractive index of the light-guiding layer 231 is the same as that of the substrate 200, which can ensure that the light does not deflect on the light-guiding layer 231. The thickness of the light-guiding layer 231 can be set according to the wavelength of the light emitted by the light-emitting layer and the thickness of the light-guiding layer 231, and the relationship satisfied by the thickness of the light-guiding layer 231 is: the thickness of the light-guiding layer 231 = wavelength / 4 × refractive index. In some embodiments, the substrate 200 is a sapphire substrate 200, and the refractive index of sapphire is 1.77. Then, the light-guiding layer 231 is made of aluminum oxide (Al2O3) or magnesium oxide (MgO) with the same refractive index as sapphire. The thickness of the light-guiding layer 231 is specifically, for example, 10 to 200 nm, or for example, 60 to 80 nm. In other embodiments, when the substrate 200 is made of other materials, the corresponding material of the light-guiding layer 231 can be selected, and the thickness of the light-guiding layer 231 can be set correspondingly.

[0160] As Figure 21As shown, the first reflective layer 232 is located on the side of the light guiding layer 231 relative to the substrate 200, and the first reflective layer 232 covers the light guiding layer 231. The first reflective layer 232 is a forward reflective layer 223, allowing the light emitted from the direction of the substrate 200 to pass through the first reflective layer 232, and the light emitted from the first reflective layer 232 relative to the substrate 200 direction will be reflected by the first reflective layer 232. In some embodiments, the first reflective layer 232 is a periodically grown layer of titanium dioxide (Ti2O3) and silicon dioxide (SiO2), and the first reflective layer 232 includes, for example, 4 to 6 cycles of Ti2O3 and SiO2, or, for example, 5 cycles of Ti2O3 and SiO2. Among them, the titanium dioxide layer covers the light guiding layer 231, and the thickness of the titanium dioxide layer is, for example, 55 to 60 nm, the silicon dioxide layer covers the titanium dioxide layer, and the thickness of the silicon dioxide layer is, for example, 90 to 100 nm.

[0161] As Figure 21 shown, the optical oscillation layer 233 is located on the side of the first reflective layer 232 relative to the light guiding layer 231, and the optical oscillation layer 233 covers the first reflective layer 232. The refractive index of the optical oscillation layer 233 is less than that of the substrate 200. In some embodiments, the optical oscillation layer 233 can be made of one or more of silicon dioxide (SiO2) with a refractive index of 1.46, magnesium fluoride (MgF2) with a refractive index of 1.38, titanium nitride (TiN) with a refractive index of 1.351, or calcium fluoride (CaF2) with a refractive index of 1.433. The thickness of the optical oscillation layer 233 is, for example, 100 to 500 nm, or, for example, 300 to 400 nm, which can avoid the optical oscillation layer 233 being too thick and prone to cracking, and the oscillation layer being too thin, resulting in too much brightness loss and the light finally emitted by the micro light emitting diode being weak in intensity.

[0162] As Figure 21 shown, the second reflective layer 234 is located on the side of the optical oscillation layer 233 relative to the first reflective layer 232, and the second reflective layer 234 covers the optical oscillation layer 233. The second reflective layer 234 is a reverse reflective layer 223, and the light emitted from the second reflective layer 234 relative to the substrate 200 direction passes through, and the light emitted from the substrate 200 direction will be reflected by the second reflective layer 234. In some embodiments, the second reflective layer 234 is a periodically grown layer of silicon dioxide (SiO2) and titanium dioxide (Ti2O3), and the second reflective layer 234 includes, for example, 2 to 3 cycles of SiO2 and Ti2O3, and the thickness of the silicon dioxide layer is, for example, 90 to 100 nm, the titanium dioxide layer covers the silicon dioxide layer, and the thickness of the titanium dioxide layer is, for example, 55 to 60 nm.

[0163] As Figure 21As shown, by providing a light-scattering laminate 230 on the lower surface of the substrate 200 of the micro light-emitting diode, when the light emitted by the semiconductor epitaxial structure 20 sequentially passes through the light-guiding layer 231, the first reflective layer 232, and the optical oscillation layer 233, it is reflected by the second reflective layer 234 and deflected within the optical oscillation layer 233. When the light is reflected by the optical oscillation layer or the first reflective layer 232, it is reflected by the first reflective layer 232 again and finally overflows from the side of the optical oscillation layer 233. As a result, the angle formed by the finally emitted light and the plane where the substrate 200 is located is greater than 160 degrees.

[0164] As Figure 22 shown, in another embodiment, to avoid the excessive light-emitting angle of the micro light-emitting diode when forming a display device or a lighting device, which may cause color interference between adjacent micro light-emitting diodes of different colors. A shielding layer 235 can also be added outside the substrate 200 to narrow the light-emitting angle of the micro light-emitting diode. In this embodiment, the shielding layer 235 can be formed outside the micro light-emitting diode to narrow the light-emitting angle.

[0165] As Figure 22 shown, the shielding layer 235 is provided outside the micro light-emitting diode, specifically as Figure 23 , Figure 24 and Figure 25 shown, the shielding layer 235 is provided outside the substrate 200 and is in contact with the side wall of the substrate 200. The shielding layer 235 can cover one or more sides of the substrate 200. By providing the shielding layer 235 at different positions on the side wall of the substrate 200, the light-emitting range of the micro light-emitting diode can be changed. In some embodiments, as Figure 24 shown, the shielding layer 235 can cover, for example, two opposite sides of the substrate 200. At this time, the range of the light-emitting angle of the micro light-emitting diode is, for example, 90 to 115 degrees, and the maximum light-emitting angle is, for example, 115 degrees. In other embodiments, as Figure 25 shown, the shielding layer 235 can cover, for example, four sides of the substrate 200. At this time, the range of the light-emitting angle of the micro light-emitting diode is, for example, 90 to 105, and the maximum light-emitting angle is, for example, 105 degrees. In other embodiments, the shielding layer 235 covers, for example, one side of the substrate 200. At this time, the range of the light-emitting angle of the micro light-emitting diode is, for example, 90 to 120, and the maximum light-emitting angle is, for example, 120 degrees. The shielding layer 235 covers, for example, three sides of the substrate 200. At this time, the range of the light-emitting angle of the micro light-emitting diode is, for example, 90 to 110, and the maximum light-emitting angle is, for example, 110 degrees.

[0166] As Figure 23, the light shielding layer 235 includes a reduction layer 236 and a coating layer 237, wherein the reduction layer 236 is formed by recrystallizing and roughening the surface of the sidewall of the substrate 200. In this embodiment, the substrate 200 is, for example, a sapphire substrate 200, and the sidewall of the substrate 200 can be recrystallized and roughened by laser scribing. The wavelength of the laser light is, for example, 800 - 1200 nm. The sapphire substrate 200 (Al2O3) is recrystallized into Al or AlO by the laser, and finally the surface of the sidewall of the recrystallized substrate 200 can be naturally roughened. Both Al or AlO formed by recrystallization are light-impermeable layers and can reflect light, and the naturally roughened sidewall of the substrate 200 can also increase reflection.

[0167] Such as Figure 22 and Figure 23 , the coating layer 237 covers the reduction layer 236, and for example, it can be in a vacuum environment, and under the condition that the pressure is, for example, 1×10 3 ~9×10 3 torr, the coating layer 237 is formed on the reduction layer 236 by evaporation or sputtering. The coating layer 237 includes multiple composite layers, for example, including a first composite layer 238 and a second composite layer 239, and the second composite layer 239 covers the first composite layer 238. The coating layer 237 can be a composite layer of metal layers or a composite layer of oxide layers. In some embodiments, the material of the first composite layer 238 is Al, or Al and Ni, the material of the second composite layer 239 is Ti or Pt, and the thickness of the coating layer 237 is, for example, 20 - 300 nm. In other embodiments, the material of the first composite layer 238 is SiO2 or MgF2, the material of the second composite layer 239 is Ti2O5 or SiNx, and the thickness of the coating layer 237 is, for example, 50 - 100 nm. Among them, when the coating layer 237 is an oxide composite layer, the coating layer 237 can include multiple cyclically arranged first composite layers 238 and second composite layers 239.

[0168] Such as Figure 26 As shown, in some embodiments, during the crystal growth process of the semiconductor epitaxial structure, the surface of the semiconductor epitaxial structure may have uneven defects, resulting in poor performance of the reflective layer 223. A micro light-emitting diode provided in this embodiment can fill the surface of the semiconductor epitaxial structure, while ensuring the stress balance of the overall film layer, avoiding cracking of the coating layer due to tensile stress, and can also increase the light output effect.

[0169] Such as Figure 26 As shown, there are uneven defects on the surface of the semiconductor epitaxial structure 20 in contact with the transparent conductive layer 220, which can be in Figure 20 , Figure 21 or Figure 22Based on the micro light-emitting diodes shown, a composite filling layer 240 is provided between the transparent conductive layer 220 and the reflective layer 223 to improve the defects on the semiconductor epitaxial structure. A pressing layer 243 is provided between the protective layer 224 and the insulating layer 225 to ensure the overall film stress balance and avoid film cracking caused by tension.

[0170] As Figures 26 to 27 , the filling layer 240 is located on the side of the transparent conductive layer 220 relative to the semiconductor epitaxial structure and covers the transparent conductive layer 220. The filling layer 240 is transparent and non-conductive, and the particles in the filling layer 240 are first coarse and then fine. Specifically, the filling layer 240 includes a first filling layer 240a and a second filling layer 240b. The first filling layer 240a covers the transparent conductive layer 220, and the thickness of the first filling layer 240a is, for example, 200 - 500 nm, specifically, for example, 250 nm or 300 nm, to completely cover the defects on the semiconductor epitaxial structure. The second filling layer 240b covers the first filling layer 240a, and the thickness of the second filling layer 240b is, for example, 50 - 300 nm, to fill the gaps between the particles in the first filling layer 240a.

[0171] As Figures 26 to 27 , in this embodiment, the filling layer 240 can be formed on the transparent conductive layer 220 by PECVD deposition or evaporation. The particle density of the first filling layer 240a is, for example, 3 - 4 g / cm 3 , and the material of the first filling layer 240a is, for example, alumina (Al2O3) or magnesium fluoride (MgF3). The density of alumina is 3.5 - 3.9 g / cm 3 , and the density of magnesium fluoride is 3.148 g / cm 3 . The particle density of the second filling layer 240b is, for example, 1.5 - 3 g / cm 3 , and the material of the second filling layer 240b is, for example, silicon dioxide (SiO2) or silicon nitride (SiN). The density of silicon dioxide is 2.2 g / cm 3 , and the density of silicon nitride is 1.8 - 2.7 g / cm 3 . The filling layer 240 first uses coarse particles to form the first filling layer 240a with a fast plating speed, and then fills in fine particles to form the second filling layer 240b, so there will be no voids, and the film material is good and not easily detached.

[0172] As Figures 26 to 27, there are multiple openings 241 provided on the planarization layer 240, and the multiple openings 241 are arranged in an array. For example, the openings 241 can be wet-etched using BOE etchant, or dry-etched using inductively coupled plasma (ICP) etching method. The openings 241 are arranged in a columnar shape and penetrate through the first planarization layer 240a and the second planarization layer 240b, and the cross-section of the opening 241 can be circular, square, polygonal or other shapes. In this embodiment, the aperture of the opening 241 is, for example, 3 - 5um, and the spacing between adjacent openings 241 is, for example, 3 - 5um. The settings of the aperture and the spacing between adjacent openings 241 can prevent the openings 241 from having too small a spacing to meet the process requirements, and at the same time prevent the opening from being too large, resulting in too small a contact area between the planarization layer 240 and the conductive layer, and causing too high a voltage difference on both sides of the planarization layer 240.

[0173] As Figure 26 shown, the protective layer 224 covers the reflective layer 223, the lamination layer 243 covers the protective layer 224, and the insulating layer 225 covers the lamination layer 243. The lamination layer 243 includes a first lamination layer and a second lamination layer, and the second lamination layer covers the first lamination layer. At room temperature, the thickness ratio of the first lamination layer to the second lamination layer is, for example, 3:8. And the thickness of the first lamination layer and the second lamination layer is, for example, 30 - 600nm, which can prevent the lamination layer 243 from being too thin to function and too thick to cause cracking and other problems. In some embodiments, the lamination layer 243 includes, for example, 1 layer of the first lamination layer and, for example, 1 second lamination layer. In other embodiments, the lamination layer 243 includes multiple cycles of the first lamination layer and the second lamination layer.

[0174] As Figure 26 and Figure 27 shown, the lamination layer 243 can be formed on the transparent conductive layer 220 by PECVD deposition or evaporation. The material of the first lamination layer is, for example, silicon dioxide (SiO2), and the material of the second lamination layer is, for example, titanium dioxide (TiO2) or Ti2O5.

[0175] Please combine Figure 26 and Figure 28As shown, when the micro light-emitting diode is mounted on the substrate 244, the first electrode 226 can be soldered to the substrate 244 through the first pad 245, and the second electrode 227 can be soldered to the substrate 244 through the second pad 246. When the substrate 244 exhibits compressive stress and the thin film provided on the substrate 244 exhibits tensile stress, both sides of the substrate 244 and the thin film will warp towards the thin film side. When the substrate 244 exhibits tensile stress and the thin film provided on the substrate 244 exhibits compressive stress, both sides of the substrate 244 and the thin film will warp towards the substrate 244 side. In this embodiment, the substrate 244 exhibits a small tensile stress at room temperature, and the stress change of the thin film of the lamination layer 243 is as follows: when the thickness of the second lamination layer (TiO2 or Ti2O5) is 300 nm, it exhibits tensile stress at room temperature, for example, 114 Mpa; when the thickness of the first lamination layer (SiO2) is 400 nm, it exhibits compressive stress at room temperature, for example, -56 Mpa. Since the substrate 244 itself has tensile stress in another direction, the thickness ratio of the first lamination layer to the second lamination layer should be 3:8. At this time, the stress exhibited by the lamination layer 243 is nearly 0, and there is a little more compressive stress, which can offset the tensile stress exhibited by the substrate 244. At other temperatures, the substrate 244 will warp due to excessive stress, and the stress of the thin film can be adjusted to balance the substrate 244 and the thin film on the substrate 244.

[0176] As Figure 29 and Figure 30 shown, in order to meet the requirement of high efficiency and energy saving of the micro light-emitting diode, the brightness of the flip chip also needs to be higher and higher. During the crystal growth process of the semiconductor epitaxial structure, since defects are easily formed on the surface, resulting in uneven surface, after the reflector is plated later, a complete mirror surface will not be formed, resulting in dispersion and non-concentrated light. After being packaged into white light, the light efficiency is poor. The flip-chip micro light-emitting diode provided in this embodiment, as Figure 29 and Figure 30 shown, uses a special composite planarization layer 240 to planarize the epitaxial surface and increase the light vertical reflection ability. At the same time, a lamination layer 243 is used to ensure the overall film stress balance, avoid cracking of the coating layer 237 caused by tensile stress. At the same time, these two designs also strengthen the light vertical reflection ability required for the flip chip to increase the light extraction efficiency.

[0177] As Figure 31As shown, when a micro light-emitting diode is in use, it needs to be welded to a circuit through a solder pad. During welding, voids are likely to occur between the solder pad and the electrode. A metal stack 250 with a special shape can be formed on the electrode to increase the yield of the solderability of the electrode. In this embodiment, the thickness of the metal stack 250 is, for example, 20 to 100 μm, and it includes a dielectric layer 251 and a soft metal layer 252. The dielectric layer 251 is disposed on the first electrode 226 and the second electrode 227, and the soft metal layer 252 is disposed on the dielectric layer 251. Specifically, the dielectric layer 251 is made of an alloy and, for example, includes a nickel (Ni) layer and an alloy of gold (Au) and tin (Sn). Under yellow light conditions, a nickel layer with a thickness of, for example, 10 to 15 nm can be first evaporated or sputtered on the first electrode 226 and the second electrode 227, and then an alloy of gold and tin with a thickness of, for example, 30 to 1000 nm can be evaporated or sputtered on the nickel to form the dielectric layer 251, and the ratio of gold to tin in the gold-tin alloy is, for example, 80:20. The dielectric layer 251 has the same thickness at each point and is columnar in shape, specifically, it can be cylindrical. Forming a dielectric layer 251 on the first electrode 226 and the second electrode 227 can prevent the diffusion of the soft metal layer 252.

[0178] As Figure 31 shown, the soft metal layer 252 is disposed on the dielectric layer 251 and covers the dielectric layer 251. The soft metal layer 252 is made of a metal or an alloy, for example, made of gold (Au), tin (Sn), or silver (Ag), or made of an alloy of tin (Sn). Under yellow light conditions, a metal or an alloy with a thickness of, for example, 20 to 100 μm can be plated or sputtered on the dielectric layer to form the soft metal layer 252. As the thickness of the soft metal layer 252 increases, the radius of the soft metal layer 252 gradually decreases, and the soft metal layer 252 can be specifically arranged in a frustum shape. When the micro light-emitting diode is welded to the solder pad, the voids between the solder pad and the electrode can be driven out, and then, by using the characteristics of the soft metal, the uneven solder pad area can be filled, and the window for allowing the substrate 200 to warp can be increased, thereby increasing the reliability of the product.

[0179] As Figure 32As shown, in another embodiment, a special pad can replace the functions of the conductive plug and the electrode. For example, the first conductive structure 260 is used to replace the first conductive plug 221 and the first electrode 226, and the second conductive structure 261 is used to replace the second conductive plug 222. The first conductive structure 260 and the second conductive structure 261 are stretchable. It can be the use of an uneven substrate and the defects caused by the stress generated by the thermal expansion during reflow soldering, while reducing the encapsulation void ratio. In this embodiment, the first conductive structure 260 is electrically connected to the first semiconductor layer, and the second conductive structure 261 is electrically connected to the second semiconductor layer. The first conductive structure 260 includes a planarizing layer 262, an adhesive layer 263, a stretchable layer 264, a stacked layer 265, and a soldering layer 266. The second conductive structure 261 includes an adhesive layer 263, a stretchable layer 264, a stacked layer 265, and a soldering layer 266.

[0180] As Figure 32 shown, the planarizing layer 262 is disposed on the first semiconductor layer of the semiconductor epitaxial structure 20, and the height of the planarizing layer 262 is equal to the height of the transparent conductive layer 220. By providing the planarizing layer 262, the heights of the first conductive structure 260 and the second conductive structure 261 can be made equal to avoid skewing. A layer of planarizing layer 262 can be deposited on the first semiconductor layer by chemical vapor deposition under the condition of 200 - 300 degrees. The material of the planarizing layer 262 is, for example, SiO2, SiNx, Al2O3, MgO, or AlN, and the thickness of the planarizing layer 262 is, for example, 900 - 1500 nm, and specifically can be the same as the height of the transparent conductive layer 220.

[0181] As Figure 32 shown, the adhesive layer 263 of the first conductive structure 260 is disposed on the planarizing layer 262, and the adhesive layer 263 of the second conductive structure 261 is disposed on the transparent conductive layer 220. The heights of the adhesive layers 263 of the first conductive structure 260 and the second conductive structure 261 are equal. A layer of adhesive layer 263 can be evaporated or sputtered on the planarizing layer 262 or the transparent conductive layer 220 under the condition of opening the light yellow. The material of the adhesive layer 263 is, for example, Cr, Ni, Ti, or indium tin oxide (ITO). The thickness of the adhesive layer 263 is, for example, 5 - 100 nm, and the adhesive layer 263 is lower than the height of the insulating layer 225.

[0182] As Figure 32As shown, a telescopic layer 264 is provided on the adhesive layer 263 of the first conductive structure 260 and the second conductive structure 261, and the telescopic layers 264 on the first conductive structure 260 and the second conductive structure 261 are of equal height. A telescopic layer 264 can be vapor-deposited or sputtered on the adhesive layer 263 under the condition of yellow light on. The telescopic layer 264 is, for example, a composite layer formed by an alloy of titanium and aluminum (Ti / Al), an alloy of nickel and aluminum (Ni / Al), an alloy of titanium and silver (Ti / Ag), or an alloy of nickel and silver (Ni / Ag). The telescopic layer 264 is higher than the insulating layer 225, and the thickness of the telescopic layer 264 is, for example, (50 - 200)*N nm, where the range of N is 3 - 9. When the value of N is too small, the telescopic layer 264 has no telescopic effect; when the value of N is too large, the voltage of the telescopic layer 264 is too high.

[0183] As Figure 32 As shown, a stacked layer 265 is provided on the telescopic layer 264 of the first conductive structure 260 and the second conductive structure 261, and the stacked layers 265 on the first conductive structure 260 and the second conductive structure 261 are of equal height. A stacked layer 265 can be vapor-deposited or sputtered on the telescopic layer 264 under the condition of yellow light on. The material of the stacked layer 265 is, for example, an alloy of platinum (Pt) and titanium (Ti), or an alloy of titanium (Ti) and nickel (Ni), and the thickness of the stacked layer 265 is, for example, 100 - 300 nm.

[0184] As Figure 32 As shown, a welding layer 266 is provided on the stacked layer 265 of the first conductive structure 260 and the second conductive structure 261, and the welding layers 266 on the first conductive structure 260 and the second conductive structure 261 are of equal height. A welding layer 266 can be vapor-deposited or sputtered on the stacked layer 265 under the condition of yellow light on. The material of the welding layer 266 is, for example, tin (Sn) or a gold-tin alloy (AuSn), and the thickness of the welding layer 266 is, for example, 80000 - 100000 nm.

[0185] As Figure 33 As shown, when micro light-emitting diodes are used for backlighting and lighting, due to the influence of various adverse environments, micro light-emitting diodes often fail, especially the infiltration of water vapor, which causes particularly serious damage to micro light-emitting diodes. The present invention provides a micro light-emitting diode, on which a special waterproof protective layer 270 is provided on the light-emitting area and the electrode, which can prevent water from staying on the chip, keep the chip dry, and thus avoid the adverse effects of water vapor and prevent water vapor from invading.

[0186] As Figure 33As shown, the waterproof protective layer 270 includes a protective film layer 271, a hydrophobic film layer 272, and a water barrier layer 273. Among them, the waterproof protective layer 270 is disposed on the transparent conductive layer 220, as well as on a part of the first electrode 226 and the second electrode 227. The hydrophobic film layer 272 is disposed on the waterproof protective layer 270, and the water barrier layer 273 is disposed on the hydrophobic film layer 272. Please refer to Figure 32 As shown, the waterproof protective layer 270 covers the transparent conductive layer 220, extends toward the first electrode 226 and the second electrode 227, and covers the sidewalls and a part of the top walls of the first electrode 226 and the second electrode 227. As Figure 34 As shown, the protective film layer 271 includes a first waterproof protective layer 274, a second waterproof protective layer 275, and a third waterproof protective layer 276. The second waterproof protective layer 275 is disposed on the first waterproof protective layer 274, and the third waterproof protective layer 276 is disposed on the second waterproof protective layer 275. The first waterproof protective layer 274, the second waterproof protective layer 275, and the third waterproof protective layer 276 can be deposited by plasma enhanced chemical vapor deposition method respectively. Among them, the first waterproof protective layer 274 is an oxide layer, and the thickness is, for example, 100 - 300 nm. The second waterproof protective layer 275 is a gradient layer of an oxide layer and a nitride layer, and the thickness is, for example, 20 nm. The third waterproof protective layer 276 is a nitride layer of a non-hydrophilic material, and the thickness is, for example, 20 - 50 nm. Specifically, the material of the first waterproof protective layer 274 is, for example, silicon dioxide (SiO2), the material of the second waterproof protective layer 275 is, for example, silicon oxynitride (SiON), and the material of the third waterproof protective layer 276 is, for example, silicon nitride (SiNx).

[0187] As Figure 33 As shown, the hydrophobic film layer 272 is disposed on the waterproof protective layer 270 and covers the waterproof protective layer 270. The hydrophobic film layer 272 can be formed by electron beam evaporation. The thickness of the hydrophobic film layer 272 is, for example, 2 - 5 μm. Among them, the hydrophobic film layer 272 is a super-hydrophobic nitride layer, for example, it can be a metal nitride layer, specifically, it can be boron nitride (BN) or aluminum nitride (AlN), and other super-hydrophobic metal nitride layers.

[0188] As Figure 33 and Figure 35As shown, the water barrier layer 273 is disposed on the hydrophobic film layer 272. By annealing and recrystallizing the hydrophobic film layer 272, a plurality of protruding structures can be formed on the hydrophobic film layer 272 to form the water barrier layer 273. The thickness of the water barrier layer 273 is greater than or equal to 1 um, specifically 2 um for example, and the thickness of the water barrier layer 273 is specifically the height of the protruding structure. Specifically, when forming the hydrophobic film layer 272, a relatively thick hydrophobic film layer 272 can be set. Specifically, the thickness of the hydrophobic film layer 272 before annealing and crystallization is equal to the sum of the thickness of the finally formed hydrophobic film layer 272 and the thickness of the water barrier layer 273. After forming the hydrophobic film layer 272, the top of the hydrophobic film layer 272 is subjected to rapid high-temperature annealing or furnace tube annealing at 200 - 300 degrees for 30 - 60 minutes, and then the top surface of the hydrophobic film layer 272 is granulated to form protruding structures, and the plurality of protruding structures form the water barrier layer 273.

[0189] As Figure 36 (a) shows that the angle between the tangent of the droplet edge and the reference plane on a general hydrophilic surface is less than 90 degrees. As Figure 36 (b) shows that the angle range between the tangent of the droplet edge and the reference plane on a hydrophobic surface can be, for example, 90 - 150 degrees. As Figure 36 (c) shows that the angle between the tangent of the droplet edge and the reference plane on a superhydrophobic surface is greater than 150 degrees. The hydrophobicity of the protective film layer 271 provided by the present invention gradually increases, a superhydrophobic surface is formed on the outermost layer of the protective film layer 271, and a water barrier layer 273 with protruding structures is formed on the superhydrophobic metal nitride layer surface to further prevent water vapor intrusion.

[0190] As Figure 37 As shown, after transferring the light-emitting diode to the display substrate, the substrate 200 needs to be peeled off to improve the brightness. Since the electrodes are disposed on both sides of the semiconductor epitaxial structure and there is a cavity structure between the two electrodes, when the substrate 200 is peeled off, the semiconductor epitaxial structure is likely to crack, resulting in leakage and dead lights. The present invention provides a micro light-emitting diode that can prevent the semiconductor epitaxial structure from breaking when the substrate 200 is peeled off.

[0191] As Figure 37As shown in the figure, a micro light-emitting diode provided in this embodiment forms a support layer 280 between a first electrode 226 and a second electrode 227, and the support layer 280 fills the gap between the first electrode 226 and the second electrode 227. Specifically, methods such as evaporation coating, sputtering, or chemical vapor deposition can be used to form the support layer 280, and the material of the support layer 280 is, for example, SiO2, SiNx, Al2O3, or diamond-like carbon film (DLC). The height of the support layer 280 is not higher than that of the first pad 245 and the second pad 246, and the thickness of the support layer 280 can be specifically, for example, 300 - 4000 nm. By using a special support layer 280, this micro light-emitting diode can form a support for the part that would otherwise crack, preventing it from cracking, avoiding damage to the crystal during crystal picking, and also avoiding leakage caused by the diffusion of the underlying flux or solder paste.

[0192] As Figure 38 , after forming the micro light-emitting diodes, it is necessary to transfer multiple micro light-emitting diodes to a substrate. The present invention provides a semiconductor device that can cut and transfer multiple micro light-emitting diodes to a substrate. Among them, the semiconductor device described in this embodiment is, for example, a micro light-emitting diode transfer device. A matrix cutting bar is provided on the micro light-emitting diode transfer device, which can divide multiple micro light-emitting diodes on a substrate into independent wafers, and each wafer includes at least one Mini LED or Micro LED. The matrix suction cup can transfer the micro light-emitting diodes to the substrate. The micro light-emitting diode transfer device provided in this embodiment can perform integrated cutting, improving the operation efficiency.

[0193] As Figure 38 As shown in the figure, the micro light-emitting diode transfer device includes a base 301. A cylinder base 302 is arranged above the base 301, and an empty slot is provided inside the cylinder base 302. The neutral line of the empty slot coincides with the neutral line of the cylinder base 302. A lifting platform 303 is arranged in the empty slot, and the top surface of the lifting platform 303 is higher than the top surface of the cylinder base 302. A rotating platform 304 is arranged on the lifting platform 303. One end of a cantilever 305 is connected to the rotating platform 304, and a fixed arm 306 is connected to the end of the cantilever 305 away from the rotating platform 304. A transfer plate 308 is arranged below the fixed arm 306. A matrix cutting bar 309 and a matrix suction cup 310 are fixed on the transfer plate 308, and the matrix suction cup 310 is located between adjacent matrix cutting bars 309.

[0194] As Figure 38, the base 301 is disposed at the bottom of the micro light-emitting diode transfer device, providing support for the entire micro light-emitting diode transfer device. And in some embodiments, in order to enable the movement of the micro light-emitting diode transfer device, the base 301 may be provided with a set of moving wheels, and the set of moving wheels may be configured with a stop plate. With the cooperation of the set of moving wheels and the stop plate, the position of the entire micro light-emitting diode transfer device can be flexibly adjusted. Above the base 301, a cylinder base 302 may be provided. An empty slot may be provided inside the cylinder base 302, and a lifting table 303 is disposed in the empty slot. The lifting table 303 may be a cylinder. The top of the lifting table 303 protrudes above the cylinder base 302, and a lifting motor is provided inside the lifting table 303 to control the movement of the lifting table 303 in the vertical direction.

[0195] As Figure 38 , a rotating table 304 is disposed on the lifting table 303. The rotating table 304 may be a cylinder. The central axis of the rotating table 304 coincides with the central axis of the lifting table 303, and the diameter of the rotating table 304 is smaller than the diameter of the lifting table 303. In some embodiments, a rotating motor is provided inside the rotating table 304 to control the rotating table 304 to perform a two-way circular motion. The side of the rotating table 304 is connected to a cantilever 305. The cantilever 305 is welded to the rotating table 304. The inside of the cantilever 305 may be a hollow structure and may be provided with reinforcing ribs. The cantilever 305 performs a two-way circular motion along the movement trajectory line 314 of the cantilever end under the drive of the rotating motor inside the rotating table 304.

[0196] As Figure 38 and Figure 39 , a transfer plate 308 is disposed below the fixed arm 306. Bolt holes are provided at positions corresponding to the fixed arm 306 on the upper surface of the transfer plate 308. The transfer plate 308 is connected to the fixed plate 306 through bolts 307. The transfer plate 308 performs a two-way circular motion along the movement trajectory line 314 of the cantilever end under the drive of the rotating motor inside the rotating table 304 through the cantilever 305, realizing the transfer of the wafer among different processing process chambers. Matrix cutting strips 309 and matrix suction cups 310 are provided on the lower surface of the transfer plate 308. The connection transfer plate 308 and the matrix cutting strips 309 are fixed below the transfer plate 308, and the matrix suction cups 310 are located between adjacent matrix cutting strips 309. The matrix suction cups 310 can batch extract and fix the wafer 311 bare chips to be transferred to the target array substrate.

[0197] As Figure 38 and Figure 39, the matrix cutting bars 309 and the matrix suction cups 310 are fixed to the lower surface of the transfer plate 308, and the matrix cutting bars 309 can be distributed in a grid pattern. The matrix suction cups 310 are cross - arranged in the areas between adjacent cutting bars of the matrix cutting bars 309. The height of the matrix suction cups 310 is less than the height of the matrix cutting bars. The end of the matrix cutting bar 309 can be an inverted trapezoidal structure, a pyramidal structure, or a combination or combination of other similar structures.

[0198] As Figure 38 and Figure 41 , the wafers 311 complete different processing technological processes on the carrier 12, and cutting grooves are formed between adjacent wafers. The cutting grooves can be divided into transverse cutting grooves 315 and longitudinal cutting grooves 316, and the number of cutting grooves varies according to the number of different wafers to be processed. In some embodiments, h1 - h8 are transverse cutting grooves 315, and S1 - S8 are longitudinal cutting grooves 316. The matrix cutting bars 309 correspond to the transverse cutting grooves 315 and the longitudinal cutting grooves 316, and integrally cut the wafers 311, dividing different wafers 311 in the transverse and longitudinal directions. As Figure 39 shown, saw force lines 317 can be determined between adjacent wafers 311, and the cutting surface with the vertical distance of the saw force lines 317 is the stress - concentration surface 318. The cutting force acts on the stress - concentration surface 318 by the saw force lines 317. After the division is completed, the matrix suction cups 310 adsorb and fix the wafers 311. The adsorbed wafers 311 move along the movement trajectory line 314 of the cantilever end in a two - way circular motion driven by the rotation motor of the rotating table 304 with the transfer plate 308. In other embodiments of the present invention, the matrix suction cups can be replaced with matrix adsorbents using similar principles such as mechanical grasping, adhesives, electrostatic adsorption, gas adsorption, electromagnetic adsorption, etc., to achieve the integrated cutting and transfer of the wafers 311.

[0199] As Figure 41 , in this embodiment, the saw blade passes over the surface of the wafer 311. For thin wafers, the saw blade descends to the surface of the wafer to scratch a shallow groove that penetrates 1 / 3 of the wafer thickness. The chip separation method still uses the cylindrical roller pressing described in the scribing method and the diamond scribing method to complete.

[0200] As Figures 42 to 43 , in some embodiments, after transferring the micro - light - emitting diodes to the substrate 244, a driving circuit 296 is provided on the substrate 244, and the light - emitting diodes are connected to the driving circuit 296 through pads, and a micro - light - emitting diode display panel can be formed. In this embodiment, a micro - light - emitting diode display panel is also provided, including the substrate 244 and a micro - light - emitting diode having a plurality of nanopores provided on the substrate 244, and quantum dots are provided in the nanopores.

[0201] As Figures 42 to 43, the micro light-emitting diode in this embodiment includes a first semiconductor layer 291 and a second semiconductor layer 292 disposed on the first semiconductor layer 291. Among them, the first semiconductor layer 291 can be connected to an electrode, and the first semiconductor layer 291 is, for example, an N-type gallium nitride layer. The second semiconductor layer 292 is disposed on the first semiconductor layer 291, and the second semiconductor layer 292 is also a gallium nitride layer, and is, for example, an N-type gallium nitride layer. A plurality of array-shaped nanopores 293 are disposed on the second semiconductor layer 292. Specifically, the N-type gallium nitride layer can be immersed in an acidic solution and a bias voltage can be applied to form nanoscale pores in the N-type gallium nitride layer, thereby driving the electrochemical etching of the N-type gallium nitride layer to form the nanopores 293, and the density and size of the nanopores 293 can be changed by changing the applied bias voltage or the silicon doping concentration in GaN. The diameter of the nanopores 293 is, for example, 50 to 200 nm, and the distance between adjacent nanopores 293 is, for example, 30 to 300 nm.

[0202] As Figures 42 to 43 , in this embodiment, the nanopores 293 penetrate through the second semiconductor layer 292. When no quantum dots are disposed in the nanopores 293, the micro light-emitting diode emits ultraviolet light or blue light. When red quantum dots 295 are disposed in the nanopores 293, the micro light-emitting diode can emit red light. When green quantum dots 294 are disposed in the nanopores 293, the micro light-emitting diode can emit green light. In some embodiments, the red quantum dots 295, the green quantum dots 294, and the vacant nanopores 293 are arranged in sequence on the second semiconductor layer 292. In other embodiments, the second semiconductor layer 292 includes a plurality of first-type light-emitting arrays, second-type light-emitting arrays, and third-type light-emitting arrays that are sequentially disposed. Among them, the nanopores 293 in the first-type light-emitting arrays are filled with red quantum dots 295, the nanopores 293 in the second-type light-emitting arrays are filled with green quantum dots 294, and the nanopores 293 in the third-type light-emitting arrays are vacant nanopores 293. The shapes and sizes of the first-type light-emitting arrays, the second-type light-emitting arrays, and the third-type light-emitting arrays are equal to make the light emitted by the formed micro light-emitting diode more uniform, and the length of the array is, for example, 100 to 2000 nm, and the width is also, for example, 100 to 2000 nm. Disposing the quantum dots in the nanopores 293 can improve the absorption rate of the quantum dots and extend the service life of the quantum dots.

[0203] As Figures 42 to 43, when forming a micro-light emitting diode display panel, a driving circuit 296 is provided on a substrate 244, and the driving circuit 296 can be disposed on the surface of the substrate 244 or within the substrate 244. After bonding the micro-light emitting diodes to the substrate 244, the driving circuit 296 can drive the micro-light emitting diodes to emit light. By providing nanopores 293 in the micro-light emitting diodes and filling different colors of quantum dots in the nanopores 293, sorting of different color light emitting diodes can be avoided, and the production cost can be reduced.

[0204] Please refer to Figure 44 , the present disclosure also provides an electronic device, the electronic device includes a micro-light emitting diode panel 300 and an electronic device body 401, the micro-light emitting diode panel 300 is connected to the electronic device body 401, wherein the micro-light emitting diode panel 300 includes a circuit substrate and a plurality of micro-light emitting diode chips. The electronic device body 401 includes a controller 402, a memory 403, and a power supply 404. Among them, the power supply 404 can convert the commercial power (220V alternating current) into the direct current required by the controller 402 and the memory 403, and at the same time provide power for the micro-light emitting diode panel 300. The memory 403 is connected to the power supply 404 and is used to store relevant data for the operation of the electronic device. The controller 402 is connected to the power supply 404 and is also connected to the memory 403. The power supply 404 is used to supply power to the controller 402, and the controller executes the program in the memory 403 to control the electronic device. Among them, the electronic device can be, for example, a display panel, a mobile phone, a watch, a laptop computer, a projection device, a charging device, a charging pile, a virtual reality (VR) device, an augmented reality (AR) device, a portable electronic device, a game console or other electronic devices.

[0205] As Figure 45 shown, when applying the semiconductor epitaxial structure of the present disclosure to manufacture a semiconductor device, the semiconductor device includes a substrate 200, a buffer layer 201, a first semiconductor layer 203, a second semiconductor layer 205, a source electrode 501, a drain electrode 502, and a gate electrode 503. Among them, the buffer layer 1401 is disposed on the substrate 200, the first semiconductor layer 203 is disposed on the buffer layer 201, the second semiconductor layer 205 is disposed on the first semiconductor layer 203, the source electrode 501 is formed on the second semiconductor layer 205, the drain electrode 502 is formed on the second semiconductor layer 205, the gate electrode 503 is formed on the second semiconductor layer 203 and is located between the source electrode 501 and the drain electrode 502. An active doping region 505 and a drain doping region 504 are provided on the second semiconductor layer 205, and the source doping region 505 and the drain doping region 504 are, for example, N-type heavily doped regions, and the source electrode 501 is disposed on the source doping region 505, and the drain electrode 502 is disposed on the drain doping region 504.

[0206] As Figure 46When applying the semiconductor device of the present disclosure to a radio frequency module, the radio frequency module includes the semiconductor device. The radio frequency module mainly includes a radio frequency (RF) switching device 611, a radio frequency (RF) active device 614, a radio frequency (RF) passive device 612, and a control device 613. Among them, the radio frequency (RF) active device 614 may be the semiconductor device in this application, and the radio frequency (RF) passive device 612 may be passive devices such as capacitors, resistors, and inductors. Among them, the radio frequency (RF) switching device 611, the radio frequency (RF) active device 614, the radio frequency (RF) passive device 612, and the control device 613 are all formed on a semiconductor substrate 200.

[0207] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

[0208] Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of the present invention, the remaining technical features are not described herein again.

Claims

1. A semiconductor epitaxial structure, characterized in that, Comprising: A substrate; A first semiconductor layer disposed on the substrate; An active layer disposed on the first semiconductor layer; A second semiconductor layer disposed on the active layer; And A hole injection layer is disposed on the second semiconductor layer, and the hole injection layer includes a non- or low-doped indium gallium nitride layer, and / or a doped indium gallium nitride layer, and the hole injection layer includes In x1 Ga y1 N, In x2 Ga y2 N and In x3 Ga y3 N, and X3 < X2 < X1 ≤ 1; Wherein, the hole injection layer includes a first doped layer and a second doped layer, the second doped layer is located on the first doped layer, and the doping concentration of the first doped layer is less than the doping concentration of the second doped layer; Wherein, the thickness of the first doped layer is 40% to 50% of the thickness of the second doped layer Wherein, the hole injection layer further includes a third doped layer, and the third doped layer is located on the second doped layer, and the concentration of the third doped layer is greater than the doping concentration of the second doped layer.

2. The semiconductor epitaxial structure according to claim 1, wherein The first doping layer has a first doping concentration, and the range of the first doping concentration is 0 to 1×10 19 atom / cm 3 .

3. The semiconductor epitaxial structure according to claim 1, wherein The second doping layer has a second doping concentration, and the range of the second doping concentration is 0 to 1×10 19 atom / cm 3 .

4. The semiconductor epitaxial structure according to claim 3, wherein The second semiconductor layer has a third doping concentration, and the third doping concentration is less than the second doping concentration.

5. The semiconductor epitaxial structure according to claim 1, wherein The hole injection layer includes alternating In x1 Ga y1 N and In x2 Ga y2 n cycles of N, where n ≥ 1 and Xn <... < X3 < X2 < X1 ≤ 1.

6. A semiconductor device, characterized in that, Comprising the semiconductor epitaxial structure as claimed in claim 1.

7. A light-emitting diode, characterized in that, Comprising the semiconductor epitaxial structure as claimed in claim 1.

8. A micro light-emitting diode, characterized in that, Comprising the semiconductor epitaxial structure as claimed in claim 1.

9. A micro light-emitting diode display, characterized in that, Comprising the micro light-emitting diode as claimed in claim 8.

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