Display device

Abstract

A display device includes a display panel including a main display area in which a main display element is located, an assembly area in which an auxiliary display element and a transmission area are located, and a peripheral area located outside the main display area; wherein the display panel further includes a substrate, an initialization voltage line located in the main display area and extending in a first direction, a bottom metal layer located in the assembly area and between the substrate and the auxiliary display element, and a bias line located in the main display area and extending in the first direction, the bias line being connected to the bottom metal layer and being located at the same layer as the initialization voltage line, wherein the bias line and the initialization voltage line are alternately arranged along a second direction intersecting the first direction in a first area of the main display area surrounding the assembly area.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0070970, filed on June 11, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to display devices, and more specifically, to display panels and display devices including the display panels, the display panels including extended display areas so as to display images even in areas where components (i.e., electronic components) are arranged. Background Technology

[0004] Recently, the applications of display devices have diversified. Furthermore, as display devices become thinner and lighter, their range of uses has gradually expanded.

[0005] With the wide variety of uses of display devices, there are many ways to design the shape of display devices, and the number of functions that can be combined or associated with display devices has increased. Summary of the Invention

[0006] One or more embodiments include a display panel and a display device including the display panel, the display panel including an extended display area so that images are displayed even in areas where components (i.e., electronic components) are arranged. However, it should be understood that the embodiments described herein should be considered in a descriptive sense only and not as a limitation of this disclosure.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned from practice of the embodiments given in this disclosure.

[0008] According to one or more embodiments, a display device includes a display panel, the display panel including: a main display area, a main display element located in the main display area; a component area, an auxiliary display element and a transmissive area located in the component area; and a peripheral area located outside the main display area; wherein the display panel further includes: a substrate; an initialization voltage line located in the main display area and extending in a first direction; a bottom metal layer located in the component area and between the substrate and the auxiliary display element; and a bias line located in the main display area and extending in the first direction, the bias line being connected to the bottom metal layer and located on the same layer as the initialization voltage line, wherein, in a first region of the main display area surrounding the component area, the bias line and the initialization voltage line are alternately arranged along a second direction intersecting the first direction.

[0009] The initialization voltage line may include a first initialization voltage line and a second initialization voltage line, wherein, in the first region of the main display area, the bias line, the first initialization voltage line and the second initialization voltage line may be arranged alternately along a second direction that intersects the first direction.

[0010] In the main display area other than the first area, the first initialization voltage line and the second initialization voltage line may be arranged alternately along the second direction.

[0011] The display panel may further include a bias voltage supply line disposed in the peripheral area, wherein the bias line may be connected to the bias voltage supply line.

[0012] The bias voltage applied to the bias line may be different from the initialization voltage applied to the initialization voltage line.

[0013] The display panel may further include: main pixel circuits, respectively connected to the main display element and corresponding to the main display area; and auxiliary pixel circuits, respectively connected to the auxiliary display element and corresponding to the component area, wherein the bottom metal layer may be located between the substrate and the circuit layer including the auxiliary pixel circuits.

[0014] The main pixel circuit may include a left main pixel circuit and a right main pixel circuit that are symmetrical with respect to the bias line.

[0015] The main pixel circuit may include: a pair of first main pixel circuits symmetrical with respect to the bias line; and a pair of second main pixel circuits symmetrical with respect to the initialization voltage line, wherein the pair of second main pixel circuits is adjacent to the pair of first main pixel circuits in the second direction.

[0016] The display panel may further include: a first horizontal voltage line extending in the second direction and connected to the first initialization voltage line; and a second horizontal voltage line extending in the second direction and connected to the second initialization voltage line.

[0017] The display panel may further include a dummy line arranged in a second region of the main display area and extending in the first direction, wherein the dummy line, the first initialization voltage line and the second initialization voltage line may be arranged alternately in the second region along the second direction.

[0018] The dummy line can be located on the same layer as the offset line.

[0019] The display panel may further include a driving voltage line located on the bias line and extending in the first direction.

[0020] The display panel may also include a data line located on the bias line and extending in the first direction.

[0021] The bottom metal layer may include a bottom hole corresponding to the transmission region.

[0022] The first initialization voltage line and the second initialization voltage line can be located on different layers.

[0023] The dummy line can be electrically connected to the first initialization voltage line or the second initialization voltage line.

[0024] The first initialization voltage line in the first region and the first initialization voltage line in the second region can be integrally formed, and the second initialization voltage line in the first region and the second initialization voltage line in the second region can be integrally formed.

[0025] According to one or more embodiments, a display device includes a display panel, the display panel including a main display area and a component area, a main display element located in the main display area, and an auxiliary display element and a transmissive area located in the component area; wherein, the display panel further includes: a substrate; a first initialization voltage line located in the main display area and including a first vertical voltage line and a first horizontal voltage line, the first vertical voltage line extending in a first direction, and the first horizontal voltage line extending in a second direction intersecting the first direction and connected to the first vertical voltage line; a second initialization voltage line located in the main display area and including a second vertical voltage line and a second horizontal voltage line, the second vertical voltage line extending in the first direction, and the second horizontal voltage line extending in the second direction and connected to the second vertical voltage line; a bottom metal layer located in the component area and between the substrate and the auxiliary display element, the bottom metal layer being configured to drive the auxiliary display element; and a bias line along the main display area, the bias line being connected to the bottom metal layer and extending in the first direction, wherein the bias line, the first vertical voltage line, and the second vertical voltage line are alternately arranged in the second direction in a first region of the main display area surrounding the component area.

[0026] The bias voltage applied to the bias line may be different from the voltage applied to the first initialization voltage line and the second initialization voltage line.

[0027] The first vertical voltage line and the second vertical voltage line can be arranged alternately along the second direction in the second region of the main display area.

[0028] The display panel may further include a dummy line located in a second region of the main display area and extending along the first direction, wherein the dummy line, the first vertical voltage line and the second vertical voltage line may be arranged alternately along the second direction in the second region.

[0029] The bias line, the first vertical voltage line, and the second vertical voltage line can be located on the same layer.

[0030] The display panel may further include a main pixel circuit located in the main display area and configured to drive the main display element, wherein the main pixel circuit may include a left main pixel circuit and a right main pixel circuit that are symmetrical with respect to the offset line. Attached Figure Description

[0031] The above and other aspects, features, and characteristics of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a perspective view of a display device according to one or more example embodiments;

[0033] Figure 2 This is a cross-sectional view of a portion of a display device according to one or more example embodiments;

[0034] Figure 3 It is a plan view of a display panel according to one or more example embodiments;

[0035] Figure 4 It is a plan view of a portion of a display panel according to one or more example embodiments;

[0036] Figure 5 It is a view of the pixel arrangement structure in the main display area according to one or more example embodiments;

[0037] Figure 6A and Figure 6B It is a view of the pixel arrangement structure in the component area according to one or more example embodiments;

[0038] Figure 7 It is a cross-sectional view of a portion (main display area and component area) of a display panel according to one or more example embodiments;

[0039] Figure 8 It is an equivalent circuit diagram of a pixel circuit configured to drive a sub-pixel according to one or more example embodiments;

[0040] Figure 9 It is a plan view of the arrangement of sub-pixels, some wiring and bottom metal layer of a display panel according to one or more example embodiments;

[0041] Figure 10 It is arranged in Figure 9 A magnified planar view of the pixel circuitry in region A;

[0042] Figure 11 It is along Figure 10 A cross-sectional view of the pixel circuit intercepted by line I-I';

[0043] Figure 12 It is along Figure 10 A cross-sectional view of the pixel circuit cut by line II-II';

[0044] Figure 13 It is arranged in Figure 9 A magnified planar view of the pixel circuitry in region B;

[0045] Figure 14 It is along Figure 13 A cross-sectional view of the pixel circuit cut by line III-III';

[0046] Figure 15 It is arranged in Figure 9 A magnified planar view of the pixel circuitry in region D;

[0047] Figure 16 It is along Figure 15 A cross-sectional view of the pixel circuit cut by line IV-IV';

[0048] Figure 17 It is arranged in Figure 9 Enlarged plan view of the vertical wiring in region E;

[0049] Figure 18 It is arranged in Figure 9 Enlarged plan view of the vertical wiring in region F;

[0050] Figure 19 It is a plan view of a portion of a display panel according to one or more example embodiments; and

[0051] Figure 20 It is arranged in Figure 19 A magnified plan view of the vertical wiring in region G. Detailed Implementation

[0052] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0053] Because this disclosure can have a wide variety of modified embodiments, exemplary embodiments are shown in the accompanying drawings and described in the detailed description. The effects and features of this disclosure, as well as methods of implementing them, will become apparent when the embodiments described with reference to the accompanying drawings. However, this disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0054] One or more embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. Elements that are identical or corresponding to each other are given the same reference numerals and are independent of the drawing numbers, and redundant descriptions are omitted.

[0055] It will be understood that when a layer, region, or element is referred to as being "formed" "on" another layer, region, or element, that layer, region, or element may be formed directly or indirectly on the other layer, region, or element. For example, intermediate layers, regions, or components may exist. For ease of illustration, the dimensions of elements in the figures may be enlarged or reduced. In other words, because the dimensions and thicknesses of elements in the figures are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0056] As used herein, "in a plan view" refers to a portion of the object viewed from above, and "in a cross-sectional view" refers to a cross-section of the object viewed from the side, taken perpendicularly. As used herein, when referring to the first element and the second element as "overlapping," the first element is positioned above or below the second element.

[0057] As used herein, "ON" in association with a component state indicates the active state of the component, while "OFF" indicates the inactive state. "ON" in association with a signal received by the component indicates a signal that activates the component, while "OFF" indicates a signal that deactivates the component. A component can be activated by either a high-level or low-level voltage. For example, a p-channel transistor is activated by a low-level voltage, while an n-channel transistor is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages used for p-channel and n-channel transistors are opposite voltage levels (low and high).

[0058] In the examples below, the x, y, and z directions are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0059] Figure 1 This is a perspective view of a display device 1 according to one or more example embodiments.

[0060] Reference Figure 1 The display device 1 includes a display area DA and a peripheral area DPA located outside the display area DA. The display area DA includes a component area CA and a main display area MDA that at least partially surrounds the component area CA. For example, the component area CA and the main display area MDA can display images independently or can cooperate to display images. The peripheral area DPA may include a non-display area in which no display elements are disposed. The display area DA may be completely surrounded by the peripheral area DPA along the edge or periphery of the display area DA.

[0061] exist Figure 1The diagram illustrates a component region CA arranged within the main display area MDA. In another embodiment, the display device 1 may include two or more component regions CA. The shapes and sizes of the multiple component regions CA can differ from each other. Viewed in a direction substantially perpendicular to the top surface of the display device 1, the component regions CA can have various shapes, such as circular, elliptical, and polygonal shapes including quadrilaterals, hexagons, octagons, stars, or rhombuses. Furthermore, although in Figure 1 As shown, when viewed in a direction approximately perpendicular to the top surface of the display device 1, the component region CA is arranged at the top (positive (+)y direction) center of the main display region MDA, which has an approximately quadrilateral shape. However, the component region CA may be arranged on one side of the main display region MDA, which has an approximately quadrilateral shape, such as the upper right or upper left side.

[0062] The display device 1 can display an image by using multiple main sub-pixels Pm and multiple auxiliary sub-pixels Pa, with the main sub-pixels Pm arranged in the main display area MDA and the auxiliary sub-pixels Pa arranged in the component area CA.

[0063] See below for reference. Figure 2 As described, component 40, as an electronic element, can be arranged below display panel 10 in component region CA, with component 40 arranged corresponding to component region CA. Component 40 may include a camera using infrared or visible light, and may include an imaging element. In some embodiments, component 40 may include a solar cell, a flash, a proximity sensor, an illuminance sensor, and an iris sensor. In some other embodiments, component 40 may have the function of receiving sound. To prevent the function of component 40 from being limited, component region CA may include a transmission region TA through which light and / or sound can pass, and light and / or sound are output from component 40 to the outside or propagate from the outside toward component 40. In display panel 10 and display device 1 including display panel 10 according to one or more example embodiments, when light passes through component region CA, the transmittance may be 10% or greater, more preferably, 40% or greater, 25% or greater, 50% or greater, 85% or greater, or 90% or greater.

[0064] Multiple auxiliary subpixels Pa can be arranged in the component region CA. These auxiliary subpixels Pa can display an image by emitting light. The image displayed in the component region CA may include auxiliary images and may have a lower resolution than the image displayed in the main display region MDA. For example, the component region CA includes a transmissive region TA through which light and sound can pass. When the auxiliary subpixels Pa are not arranged in the transmissive region TA, the number of auxiliary subpixels Pa that can be arranged per unit area in the component region CA may be less than the number of main subpixels Pm that can be arranged per unit area in the main display region MDA.

[0065] Figure 2 This is a cross-sectional view of a portion of a display device 1 according to one or more example embodiments.

[0066] Reference Figure 2 The display device 1 may include a display panel 10 and a component 40 overlapping the display panel 10. A cover window (not shown) may be further arranged on the display panel 10, and the cover window (not shown) may protect the display panel 10.

[0067] The display panel 10 includes a component area CA and a main display area MDA. The component area CA overlaps with the component 40, and the main display area MDA displays the main image. The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical functional layer OFL, and a panel protection member PB located on the substrate 100. The panel protection member PB is disposed below the substrate 100.

[0068] The display layer DISL may include a circuit layer PCL, a display element layer EDL, and a sealing member ENCM such as a thin-film encapsulation layer TFEL or a sealing substrate (not shown). The circuit layer PCL includes thin-film transistors, such as a main thin-film transistor TFT and an auxiliary thin-film transistor TFT', and the display element layer EDL includes light-emitting diodes (LEDs) as display elements, such as a main LED ED and an auxiliary LED ED'. An insulating layer IL may be disposed inside the display layer DISL, and an insulating layer IL' may be disposed between the substrate 100 and the display layer DISL. For example, the insulating layer IL' may be located between the substrate 100 and the circuit layer PCL, and the insulating layer IL and the circuit layer PCL may be at substantially the same level on the insulating layer IL'.

[0069] The substrate 100 may include insulating materials such as glass, quartz, and polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable.

[0070] The main sub-pixel Pm and the main thin-film transistor TFT can be arranged in the main display area MDA of the display panel 10. The main sub-pixel Pm includes a main light-emitting diode ED and a main thin-film transistor TFT connected to the main sub-pixel Pm. The auxiliary sub-pixel Pa and the auxiliary thin-film transistor TFT' can be arranged in the component area CA. The auxiliary sub-pixel Pa includes an auxiliary light-emitting diode ED' and an auxiliary thin-film transistor TFT' connected to the auxiliary sub-pixel Pa. The area of ​​the component area CA in which the auxiliary sub-pixel Pa is arranged can be an auxiliary display area ADA.

[0071] Within the component area CA, a transmissive area TA, in which no display element is disposed, may be arranged. The transmissive area TA may include an area through which light and / or signals emitted from component 40 or incident on component 40 can pass. Component 40 is arranged corresponding to component area CA. Auxiliary display area ADA and transmissive area TA may be arranged alternately within component area CA.

[0072] A bottom metal layer (BML) can be disposed within the component region CA. The bottom metal layer (BML) can be disposed below the circuit layer (PCL) including the auxiliary thin-film transistor (TFT). For example, the bottom metal layer (BML) can be disposed between the auxiliary thin-film transistor (TFT) and the substrate 100. The bottom metal layer (BML) can block external light from reaching the auxiliary thin-film transistor (TFT). In some embodiments, a constant voltage or signal can be applied to the bottom metal layer (BML).

[0073] The display element layer (EDL) may be covered by a thin-film encapsulation layer (TFEL) or a sealing substrate (not shown). In some embodiments, the thin-film encapsulation layer (TFEL) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In some embodiments, the thin-film encapsulation layer (TFEL) may include a first inorganic encapsulation layer 131 and a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 located therebetween.

[0074] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may comprise at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 132 may comprise a polymeric material. Examples of polymeric materials may include acrylic resin, epoxy resin, polyimide, and / or polyethylene.

[0075] When the display element layer EDL is sealed by a sealing substrate (not shown), the sealing substrate (not shown) may face the substrate 100, with the display element layer EDL located between them. A gap may exist between the sealing substrate (not shown) and the display element layer EDL. The sealing substrate (not shown) may include glass. A sealant, comprising glass frit, may be disposed between the substrate 100 and the sealing substrate (not shown) and is disposed in the peripheral region DPA. The sealant disposed in the peripheral region DPA surrounds the display region DA while preventing moisture from penetrating into the display region DA through its side surfaces.

[0076] The Touch Screen Layer (TSL) can obtain coordinate information corresponding to external inputs (e.g., touch events). The TSL may include touch electrodes and touch wiring connected to the touch electrodes. The TSL can sense external inputs using either self-capacitance or mutual capacitance methods.

[0077] The touch screen layer (TSL) can be located on the thin-film encapsulation layer (TFEL). In some embodiments, the touch screen layer (TSL) can be formed separately on the touch screen and then bonded to the thin-film encapsulation layer (TFEL) via an adhesive layer such as an optically clear adhesive (OCA). In some embodiments, the touch screen layer (TSL) can be formed directly on the thin-film encapsulation layer (TFEL). In this case, the adhesive layer may not be disposed between the touch screen layer (TSL) and the thin-film encapsulation layer (TFEL).

[0078] The optical functional layer (OFL) may include an anti-reflective layer. The anti-reflective layer can reduce light incident on the display device 1 from the outside (e.g., external light).

[0079] In some embodiments, the optical functional layer OFL may include a polarizing film. The optical functional layer OFL may include an opening OFL_OP corresponding to the transmission region TA. Therefore, the transmittance of the transmission region TA can be significantly improved. A transparent material such as optically transparent resin (OCR) can fill the opening OFL_OP.

[0080] In some embodiments, the optical functional layer OFL may include a filter plate, which includes a black matrix and color filters.

[0081] A cover window (not shown) may be disposed on the display panel 10 to protect the display panel 10. The optical functional layer OFL may be attached to the cover window (not shown) using an optically clear adhesive, or it may be attached to the touch screen layer TSL using an optically clear adhesive.

[0082] A panel protection member PB can be attached to the bottom of the substrate 100 to support and protect the substrate 100. The panel protection member PB may include an opening PB_OP corresponding to the component region CA. Because the opening PB_OP is formed in the panel protection member PB, the transmittance of the component region CA can be improved. The panel protection member PB may include polyethylene terephthalate (PET) or polyimide (PI).

[0083] The component region CA can have a larger area than the area where the component 40 is arranged. Therefore, the area of ​​the opening PB_OP formed in the panel protection member PB may not be the same as the area of ​​the component region CA.

[0084] In some embodiments, multiple components 40 may be arranged in the component area CA. The functions of the multiple components 40 may differ from each other. For example, the multiple components 40 may include at least two of the following: a camera (imaging element), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor.

[0085] Figure 3 This is a plan view of the display panel 10 according to one or more example embodiments.

[0086] Reference Figure 3 Various components constituting the display panel 10 are arranged on the substrate 100. The display panel 10 includes a display area DA and a peripheral area DPA surrounding the display area DA along its outer periphery. The display area DA includes a main display area MDA in which a main image is displayed and a component area CA including a transmissive area TA in which an auxiliary image is displayed. The auxiliary image may cooperate with the main image to form a single complete image, or it may be an image independent of the main image.

[0087] Multiple primary sub-pixels Pm are arranged in the main display area MDA. Each primary sub-pixel Pm can include, for example, a primary organic light-emitting diode (OLED) (see [link to OLED display]). Figure 7 The display element consists of multiple main sub-pixels Pm, each capable of emitting light such as red, green, blue, or white. The main display area MDA can be covered by a packaging component, thus protecting it from the effects of ambient air or moisture.

[0088] As described above, the component region CA can be arranged on one side of the main display region MDA, or arranged inside the display region DA and surrounded by the main display region MDA. Multiple auxiliary sub-pixels Pa are arranged within the component region CA. Each of the multiple auxiliary sub-pixels Pa can include, for example, an auxiliary organic light-emitting diode (OLED) (see [link]). Figure 7The display element consists of multiple auxiliary sub-pixels Pa, each capable of emitting light such as red, green, blue, or white. The component area CA can be covered by an encapsulation component, thus protecting it from the effects of ambient air or moisture.

[0089] The component region CA may include a transmission region TA. The transmission region TA may be arranged to surround a plurality of auxiliary sub-pixels Pa. However, in some embodiments, the transmission region TA may be arranged as a mesh structure with a plurality of auxiliary sub-pixels Pa.

[0090] Because the component area CA has a transmissive area TA, the resolution of the component area CA can be lower than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA can be approximately 400 ppi or greater, and the resolution of the component area CA can be approximately 200 ppi or approximately 100 ppi.

[0091] The pixel circuits driving the primary sub-pixel Pm and the auxiliary sub-pixel Pa can be electrically connected to external circuits arranged in the peripheral region DPA. The first scan driving circuit SDRV1, the second scan driving circuit SDRV2, the terminal portion PAD, the driving voltage supply line 11, the common voltage supply line 13, and the initialization voltage supply line 15 can be arranged in the peripheral region DPA. In some embodiments, the bias voltage supply line 17 can be arranged in the peripheral region DPA, and the bias voltage supply line 17 applies a bias voltage to the bottom metal layer BML.

[0092] The first scan drive circuit SDRV1 can apply a scan signal to each pixel circuit configured to drive the main sub-pixel Pm and the auxiliary sub-pixel Pa via the scan line SL. The first scan drive circuit SDRV1 can apply an emission control signal to each pixel circuit via the emission control line EL. The second scan drive circuit SDRV2 can be arranged in the peripheral region DPA on the opposite side of the first scan drive circuit SDRV1, with the main display region MDA located between them, and the second scan drive circuit SDRV2 can be approximately parallel to the first scan drive circuit SDRV1. Some pixel circuits of the main sub-pixel Pm in the main display region MDA can be electrically connected to the first scan drive circuit SDRV1, and the remaining pixel circuits can be electrically connected to the second scan drive circuit SDRV2. Some pixel circuits of the auxiliary sub-pixel Pa in the component region CA can be electrically connected to the first scan drive circuit SDRV1, and the remaining pixel circuits can be electrically connected to the second scan drive circuit SDRV2. In some embodiments, the second scan drive circuit SDRV2 can be omitted.

[0093] The terminal portion PAD can be disposed on one side of the substrate 100. The terminal portion PAD can be exposed because it is not covered by the insulating layer, and can be connected to the display circuit board 30. The display driver 32 can be disposed on the display circuit board 30.

[0094] The display driver 32 can generate control signals that are transmitted to the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. The display driver 32 generates data signals. The generated data signals can be transmitted to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa through the fan-out line FW and the data line DL connected to the fan-out line FW.

[0095] The display driver 32 can drive voltage ELVDD (see...). Figure 8 ) is supplied to drive voltage supply line 11, and the common voltage ELVSS (see Figure 8 Supply to common voltage supply line 13. Drive voltage ELVDD (see...) Figure 8 The pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa can be applied through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS (see...) Figure 8 The voltage can be applied to the opposite electrode of the display element via the common voltage supply line 13.

[0096] The display driver 32 can supply an initialization voltage to the initialization voltage supply line 15. The initialization voltage can be applied to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa via the initialization voltage line VL.

[0097] The display driver 32 can supply a bias voltage to the bias voltage supply line 17. The bias voltage can be applied to the bottom metal layer BML via the bias line BW branching from the bias voltage supply line 17 (see...). Figure 2 The bias line BW can be formed on the same layer as the bias voltage supply line 17 and can be provided as a single body (i.e., integrally formed with each other), or it can be formed on a different layer from the bias voltage supply line 17 and can be connected to the bias voltage supply line 17 via a contact hole. In some embodiments, the bias line BW can extend in the negative (-)y direction.

[0098] The bias voltage supply line 17 in the peripheral region DPA can be adjacent to the component region CA. As an example, when the component region CA is arranged on the top side of the display region DA, the bias voltage supply line 17 can extend in the x-direction in the peripheral region DPA adjacent to the top side of the display region DA. The bias voltage supply line 17 can be connected to the terminal portion PAD via the connecting line 17a arranged in the peripheral region DPA, and can receive the bias voltage supplied by the display driver 32.

[0099] The drive voltage supply line 11 can be connected to the terminal portion PAD on the bottom side of the main display area MDA and can extend in the x direction. The common voltage supply line 13 can be connected to the terminal portion PAD and can be a loop shape with an open side to partially surround the main display area MDA along its outer periphery. The initialization voltage supply line 15 can be connected to the terminal portion PAD on the bottom side of the main display area MDA and can extend in the x direction.

[0100] Figure 4 It is a plan view of a portion of the display panel 10 according to one or more example embodiments.

[0101] Reference Figure 4 Component regions CA can be set to multiple. Component regions CA can include a first component region CA1 and a second component region CA2 that are parallel to each other in the x-direction. In this case, the first component region CA1 can be separate from the second component region CA2. Both the first component region CA1 and the second component region CA2 can be surrounded by the main display area MDA.

[0102] The size of the first component region CA1 may differ from the size of the second component region CA2. In some embodiments, the shape of the first component region CA1 may differ from the shape of the second component region CA2.

[0103] The bias voltage supply line 17 can be arranged in the peripheral region DPA adjacent to the first component region CA1 and the second component region CA2. The bias line BW can connect the bias voltage supply line 17 to the bottom metal layer BML arranged in the first component region CA1 and the second component region CA2 (see...). Figure 2 ).

[0104] Figure 5 It is a view of the pixel arrangement structure in the main display area MDA according to one or more example embodiments.

[0105] Reference Figure 5 Multiple main subpixels Pm can be arranged in the main display area MDA. In this specification, a subpixel is the smallest unit for displaying an image and may include an emission region. When using an organic light-emitting diode as the display element, the emission region of the subpixel may be defined by an opening in the emission layer or the pixel-defining layer. This will be described later.

[0106] exist Figure 5 In the main display area MDA, the region divided by solid lines includes the pixel circuit area PCA, where the pixel circuits are arranged. Main pixel circuit PC (see...) Figure 7 It can be connected to the primary sub-pixel Pm.

[0107] The primary sub-pixel Pm can include a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb. The red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb can display red, green, and blue, respectively.

[0108] Red subpixels Pr and blue subpixels Pb are alternately arranged in the first sub-row 1SN of each row N, and green subpixels Pg are separated from each other by a predetermined interval in the second sub-row 2SN adjacent to the first sub-row 1SN. This pixel arrangement can be repeated up to the Nth row. In this case, blue subpixels Pb and red subpixels Pr can be larger than green subpixels Pg. Red subpixels Pr and blue subpixels Pb in the first sub-row 1SN and green subpixels Pg in the second sub-row 2SN can be arranged alternately. Therefore, red subpixels Pr and blue subpixels Pb are alternately arranged in the first column 1M, and green subpixels Pg are separated from each other by a predetermined interval in the second column 2M adjacent to the first column 1M. Blue subpixels Pb and red subpixels Pr are alternately arranged in the third column 3M adjacent to the second column 2M containing green subpixels Pg, and green subpixels Pg are separated from each other by an interval (e.g., a predetermined interval) in the fourth column 4M adjacent to the third column 3M. This pixel arrangement can be repeated up to the Mth column.

[0109] A pixel arrangement structure can be represented as follows: red sub-pixels Pr are positioned at the first and third vertices of the virtual quadrilateral VS, green sub-pixels Pg are centered at the center of the virtual quadrilateral VS, and blue sub-pixels Pb are positioned at the second and fourth vertices of the virtual quadrilateral VS. In this case, the virtual quadrilateral VS can be modified to be a rectangle, rhombus, square, etc.

[0110] This pixel arrangement structure can be called an RGBG matrix structure (e.g., Matrix structure) or RGBG structure (e.g., structure). It is a registered trademark of Samsung Display Inc. of South Korea. High resolution can be achieved with a small number of pixels by using a rendering method where the colors of individual pixels are represented by sharing the colors of their neighboring pixels.

[0111] Despite Figure 5 The diagram shows multiple principal sub-pixels Pm. The structural arrangement is as described, but the example embodiments are not limited thereto. In one or more example embodiments, multiple principal sub-pixels Pm can be arranged in various configurations such as strip structures, mosaic arrangements, and triangular arrangements.

[0112] Figure 6A and Figure 6BIt is a view of the pixel arrangement structure in the component region CA according to one or more example embodiments.

[0113] Reference Figure 6A Multiple auxiliary subpixels Pa can be arranged in the component region CA. Each auxiliary subpixel Pa can emit light of any color: red, green, blue, or white.

[0114] The component region CA may include an auxiliary display region ADA and a transmissive region TA, and the pixel group PG includes at least one auxiliary sub-pixel Pa disposed in the auxiliary display region ADA. The auxiliary display region ADA and the transmissive region TA may be arranged alternately in the x and y directions, and for example, in a grid configuration. In this case, the component region CA may include multiple auxiliary display regions ADA and multiple transmissive regions TA.

[0115] exist Figure 6A In the auxiliary display area ADA, the area divided by solid lines includes the pixel circuit area PCA, where the auxiliary pixel circuit PC' connected to the auxiliary sub-pixel Pa (see...) Figure 7 It is arranged in the pixel circuit area PCA.

[0116] A pixel group PG can be defined as a set of subpixels comprising multiple auxiliary subpixels Pa, defined by a preset unit. For example, ... Figure 6A As shown, a pixel group PG can include... The structure consists of eight auxiliary sub-pixels Pa. For example, a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb.

[0117] Within the component region CA, basic units U can be repeatedly arranged in the x and y directions, and a preset number of pixel groups PG and a preset number of transmission regions TA are defined within each basic unit U. Figure 6A In this context, the basic unit U can have a shape that defines two pixel groups PG and two transmission regions TA within a quadrilateral. The basic unit U includes repeating shapes that are separate and do not imply a discontinuous construction.

[0118] like Figure 5As shown, the corresponding unit U' can be disposed in the main display area MDA. The corresponding unit U' can have the same area as the basic unit U. In this case, the number of main sub-pixels Pm included in the corresponding unit U' can be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. For example, the number of auxiliary sub-pixels Pa included in the basic unit U is 16, and the number of main sub-pixels Pm included in the corresponding unit U' is 32. The number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm per equal area (e.g., U or U') can be provided in a 1:2 ratio.

[0119] Similar to the arrangement of the primary sub-pixels Pm in the main display area MDA, the four auxiliary sub-pixels Pa can be arranged at the vertices of the virtual quadrilateral VS'. The resolution of the component area CA is half the resolution of the main display area MDA. The pixel arrangement structure of the component area CA is called 1 / 2. Structure. The number and arrangement of auxiliary subpixels Pa in pixel group PG can be modified according to the resolution of component region CA.

[0120] Reference Figure 6B The pixel arrangement structure of the component region CA can include 1 / 4 Structure. In this embodiment, although the 8 auxiliary sub-pixels Pa are in pixel group PG... The structural arrangement is as follows, but the basic unit U may consist of only one pixel group PG. The remaining area of ​​the basic unit U can be provided as a transmission region TA. Therefore, the number of auxiliary sub-pixels Pa and the number of primary sub-pixels Pm per equal area (e.g., U and U') can be provided in a 1:4 ratio. In this case, a pixel group PG can be surrounded by the transmission region TA.

[0121] Despite Figure 6A and Figure 6B The diagram shows multiple auxiliary sub-pixels Pa. The structural arrangement is possible, but the embodiments are not limited to this. As an example, multiple auxiliary sub-pixels Pa can be arranged in various configurations such as strip structures, mosaic arrangements, and triangular arrangements.

[0122] In addition, although in Figure 6A and Figure 6B The dimensions of the auxiliary sub-pixel Pa are shown in the figure. Figure 5The main sub-pixel Pm has the same size, but this disclosure is not limited thereto. The size of the auxiliary sub-pixel Pa can be larger than the size of the main sub-pixel Pm emitting the same color. For example, the size of the blue sub-pixel Pb, which is an auxiliary sub-pixel Pa, can be larger than the size of the blue sub-pixel Pb, which is a main sub-pixel Pm. The size difference can be designed by taking into account the difference in brightness and / or resolution between the component area CA and the main display area MDA.

[0123] Figure 7 It is a cross-sectional view of a portion (main display area MDA and component area CA) of a display panel 10 according to one or more example embodiments.

[0124] Reference Figure 7 The display panel 10 includes a main display area MDA and a component area CA. A main sub-pixel Pm is disposed in the main display area MDA, and an auxiliary sub-pixel Pa and a transmissive area TA are disposed in the component area CA. A main pixel circuit PC and a main organic light-emitting diode (OLED) serving as a display element can be disposed in the main display area MDA. The main pixel circuit PC includes a main thin-film transistor (TFT) and a main capacitor Cst, and the main OLED is connected to the main pixel circuit PC. An auxiliary pixel circuit PC' and an auxiliary organic light-emitting diode (OLED) serving as a display element can be disposed in the component area CA. The auxiliary pixel circuit PC' includes an auxiliary thin-film transistor (TFT) and an auxiliary capacitor Cst, and the auxiliary OLED is connected to the auxiliary pixel circuit PC'.

[0125] Although this embodiment uses organic light-emitting diodes as the display element, in another embodiment, inorganic light-emitting diodes or quantum dot light-emitting diodes can be used as the display element.

[0126] The following describes the component stack structure of the display panel 10. The display panel 10 may include a substrate 100, a buffer layer 111, a circuit layer PCL, and a display element layer EDL. Figure 2 As shown, the sealing component ENCM and the optical functional layer OFL can be further stacked on the display element layer EDL.

[0127] The substrate 100 may include insulating materials such as glass, quartz, and polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable.

[0128] The buffer layer 111 may be located on the substrate 100 and may reduce or prevent foreign matter, moisture, or ambient air from penetrating into the display panel 10 from below the substrate 100, and may provide a flat surface on the substrate 100 (e.g., planarizing the top surface of the substrate 100). The buffer layer 111 may comprise inorganic materials such as oxides or nitrides, or organic materials, or organic-inorganic composite materials, and may have a single-layer structure or a multi-layer structure comprising inorganic or organic materials. A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111 to prevent the penetration of external air. In some embodiments, the buffer layer 111 may comprise silicon oxide (SiO2). x ) or silicon nitride (SiN) x The buffer layer 111 may have a structure in which the first buffer layer 111a and the second buffer layer 111b are stacked.

[0129] In the component region CA, the bottom metal layer BML can be located between the first buffer layer 111a and the second buffer layer 111b. In another embodiment, the bottom metal layer BML can be located between the substrate 100 and the first buffer layer 111a. The bottom metal layer BML can be disposed below the auxiliary pixel circuit PC' and can prevent the characteristics of the auxiliary thin-film transistor TFT' from being affected by, for example, component 40 (see component 40). Figure 2 Degraded by emitted light. The bottom metal layer BML can prevent (or substantially prevent) degradation from component 40 (see... Figure 2 ) etc., launching or oriented toward component 40 (see Figure 2 The traveling light is diffracted through the narrow gap between the wiring connected to the auxiliary pixel circuit PC'. The bottom metal layer BML is absent in the transmission region TA.

[0130] In some embodiments, the bottom metal layer BML can be connected to a bias line BW disposed on a different layer via a contact hole BCNT. The bottom metal layer BML can receive a constant voltage or signal from the bias line BW. For example, the bottom metal layer BML can receive a bias voltage. The brightness difference between the component area CA and the main display area MDA, which are allocated according to the process, can be adjusted by adjusting the bias voltage.

[0131] In some embodiments, because a bias voltage is applied to the bottom metal layer BML, the auxiliary thin-film transistor TFT' can be implemented as a dual-gate transistor comprising two gate electrodes facing each other with a semiconductor layer located between them, thus allowing the characteristics of the auxiliary thin-film transistor TFT' to be adjusted.

[0132] The bias voltage can be changed according to the driving mode of the display device 1. For example, it can be applied to the bias supply line 17 (see...). Figure 3The bias voltage of the display device 1 can vary depending on the driving mode, such as high brightness mode, low brightness mode (e.g., low-power display mode for displaying clock, date, etc.), and normal mode. Therefore, the brightness of the component area CA can be adjusted for each driving mode.

[0133] The base metal layer (BML) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The base metal layer (BML) may be a single layer or multiple layers comprising the above materials.

[0134] The circuit layer PCL can be disposed on the buffer layer 111 and can include pixel circuits (e.g., main pixel circuit PC and auxiliary pixel circuit PC'), a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114 and a planarization layer 117.

[0135] The main thin-film transistor (TFT) and / or the auxiliary thin-film transistor (TFT) may be located above the buffer layer 111. The main TFT includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary TFT may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main TFT can be connected to the main organic light-emitting diode (OLED) to drive the OLED. The auxiliary TFT can be connected to the auxiliary organic light-emitting diode (OLED) to drive the OLED.

[0136] The first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111 and may comprise polycrystalline silicon. In another embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may comprise amorphous silicon. According to another embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may comprise an oxide of at least one element selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1 and the second semiconductor layer A2 may comprise a channel region, a source region, and a drain region, wherein the source region and the drain region are doped with impurities.

[0137] The second semiconductor layer A2 may overlap with the bottom metal layer BML, with the second buffer layer 111b located between them. In some embodiments, the width of the second semiconductor layer A2 may be smaller than the width of the bottom metal layer BML, so that when projected in a direction perpendicular to the substrate 100, the second semiconductor layer A2 may completely overlap with the bottom metal layer BML.

[0138] The first gate insulating layer 112 may cover the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x The first gate insulating layer 112 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), or zinc peroxide (ZnO2).

[0139] The first gate electrode G1 and the second gate electrode G2 are disposed on the first gate insulating layer 112, overlapping the first semiconductor layer A1 and the second semiconductor layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may comprise a single layer or multiple layers. For example, the first gate electrode G1 and the second gate electrode G2 may comprise a single Mo layer.

[0140] The second gate insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x The second gate insulating layer 113 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0141] The first top electrode CE2 of the main capacitor Cst and the second top electrode CE2' of the auxiliary capacitor Cst' can be arranged on the second gate insulating layer 113.

[0142] The first top electrode CE2 can overlap with the first gate electrode G1 located below it in the main display area MDA. The overlapping first gate electrode G1 and the first top electrode CE2 can form the main capacitor Cst, and the second gate insulating layer 113 is located between the first gate electrode G1 and the first top electrode CE2. The first gate electrode G1 can be used as the first bottom electrode CE1 of the main capacitor Cst.

[0143] The second top electrode CE2' can overlap with the second gate electrode G2 located below it in the component region CA. The overlapping second gate electrode G2 and the second top electrode CE2' can form an auxiliary capacitor Cst', with the second gate insulating layer 113 located between the second gate electrode G2 and the second top electrode CE2'. The second gate electrode G2 can serve as the second bottom electrode CE1' of the auxiliary capacitor Cst'.

[0144] The first top electrode CE2 and the second top electrode CE2' may include one or more of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may include a single layer or multiple layers containing one or more of the above materials.

[0145] Interlayer insulating layer 114 may cover the first top electrode CE2 and the second top electrode CE2'. Interlayer insulating layer 114 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x The materials used may be silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The interlayer insulation layer 114 may include a single layer or multiple layers containing the above inorganic insulating materials.

[0146] Assuming the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114 are collectively referred to as the inorganic insulating layer IIL, the inorganic insulating layer IIL may include a first aperture H1 corresponding to the transmission region TA. The first aperture H1 may expose a portion of the top surface of the buffer layer 111 or the substrate 100. The first aperture H1 may include openings in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114, all corresponding to and overlapping the transmission region TA. These openings may be formed individually by separate processes or simultaneously by the same process. When these openings are formed by separate processes, the inner surface of the first aperture H1 may be non-smooth and may have steps, such as a stepped shape.

[0147] In some embodiments, the inorganic insulating layer IIL may include a groove instead of the first hole H1 exposing the buffer layer 111. In some other embodiments, the inorganic insulating layer IIL may not have a first hole H1 or a groove corresponding to the transmission region TA. Because the inorganic insulating layer IIL comprises an inorganic insulating material with excellent light transmittance, even if the inorganic insulating layer IIL does not include a first hole H1 or a groove corresponding to the transmission region TA, component 40 (see...) Figure 2 It can still send / receive a sufficient amount of light.

[0148] The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can be disposed on the interlayer insulating layer 114. The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can comprise a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can comprise a single layer or multiple layers comprising the above materials. In some embodiments, the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can have a Ti / Al / Ti multilayer structure.

[0149] The planarization layer 117 can be arranged to cover the first source electrode S1 and the second source electrode S2, as well as the first drain electrode D1 and the second drain electrode D2. The planarization layer 117 can have a flat top surface, so that the first pixel electrode 121 and the second pixel electrode 121' located thereon are formed flat.

[0150] The planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. The planarization layer 117 may comprise a first planarization layer 117a and a second planarization layer 117b. Therefore, conductive patterns, such as wiring, can be disposed between the first planarization layer 117a and the second planarization layer 117b, thus facilitating high integration.

[0151] Planarization layer 117 may include commercial polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), phenolic polymer derivatives, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, or vinyl alcohol polymers. Planarization layer 117 may include silicon dioxide (SiO2). x ), silicon nitride (SiN) x Inorganic insulating materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When forming planarization layer 117, a layer can be formed, and then the top surface of the layer can be chemically and mechanically polished to provide a flat top surface.

[0152] like Figure 7 As shown, the bias line BW can be disposed on the inorganic insulating layer IIL. In another embodiment, the bias line BW can be disposed between the first planarization layer 117a and the second planarization layer 117b. The bias line BW can be electrically connected to the bottom metal layer BML through the contact hole BCNT, and the bottom metal layer BML is disposed in the component region CA.

[0153] The first planarization layer 117a can cover the main pixel circuit PC and the auxiliary pixel circuit PC'. The second planarization layer 117b can be disposed on the first planarization layer 117a and can have a flat top surface, so that the first pixel electrode 121 and the second pixel electrode 121' are formed flat.

[0154] The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') are arranged on the second planarization layer 117b. The first pixel electrode 121 of the main organic light-emitting diode (OLED) and the second pixel electrode 121' of the auxiliary organic light-emitting diode (OLED') can be connected to the pixel circuit, i.e., the main pixel circuit PC and the auxiliary pixel circuit PC', respectively, through the connection electrodes CM and CM' located on the planarization layer 117b.

[0155] The connecting electrodes CM and CM' can be disposed between the first planarization layer 117a and the second planarization layer 117b. The connecting electrodes CM and CM' can include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can comprise a single layer or multiple layers comprising the above materials. For example, the connecting electrodes CM and CM' can have a Ti / Al / Ti multilayer structure.

[0156] The planarization layer 117 may have a second aperture H2 corresponding to the transmission region TA. The second aperture H2 may overlap with the first aperture H1. Figure 7 The diagram shows that the second hole H2 is larger than the first hole H1. In another embodiment, the planarization layer 117 may cover the edge of the first hole H1 in the inorganic insulating layer 111, therefore, the area of ​​the second hole H2 may be smaller than the area of ​​the first hole H1.

[0157] The planarization layer 117 may have a via through which one of the first source electrode S1 and the first drain electrode D1 of the main thin-film transistor TFT is exposed, and the first pixel electrode 121 may contact the first source electrode S1 or the first drain electrode D1 through the via and be electrically connected to the main thin-film transistor TFT. The planarization layer 117 may include another via through which one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin-film transistor TFT' is exposed, and the second pixel electrode 121' may contact the second source electrode S2 or the second drain electrode D2 through the other via and be electrically connected to the auxiliary thin-film transistor TFT'.

[0158] The first pixel electrode 121 and the second pixel electrode 121' may comprise conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first pixel electrode 121 and the second pixel electrode 121' may comprise a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or combinations thereof. For example, both the first pixel electrode 121 and the second pixel electrode 121' may have a structure including a layer comprising ITO, IZO, ZnO, or In2O3 located above / below the aforementioned reflective layer. In this case, both the first pixel electrode 121 and the second pixel electrode 121' may have an ITO / Ag / ITO stacked structure.

[0159] The pixel defining layer 119 covers the edges of the first pixel electrode 121 and the second pixel electrode 121' located on the planarization layer 117, and may include a first opening OP1 and a second opening OP2 that respectively expose the central portions of the first pixel electrode 121 and the second pixel electrode 121'. The size and shape of the emission regions of the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED) ' (i.e., the size and shape of the main sub-pixel Pm and the auxiliary sub-pixel Pa) are defined by the first opening OP1 and the second opening OP2.

[0160] The pixel defining layer 119 can prevent electric arcing or the like at the edges of the first pixel electrode 121 and the second pixel electrode 121' by increasing the distance between the edges of the first pixel electrode 121 and the opposing electrode 123 located above the first pixel electrode 121 and the second pixel electrode 121'. The pixel defining layer 119 may include organic insulating materials such as PI, polyamide, acrylic resin, BCB, HMDSO and phenolic resin, and can be formed by spin coating.

[0161] The pixel defining layer 119 may include a third aperture H3 disposed in the transmissive region TA. The third aperture H3 may overlap with the first aperture H1 and the second aperture H2. Due to the first aperture H1 to the third aperture H3, the light transmittance in the transmissive region TA can be improved. Although in Figure 7 The buffer layer 111 is shown to be continuously arranged corresponding to the transmission region TA, but the buffer layer 111 may include a first hole H1, a second hole H2, and a third hole H3 located in the transmission region TA. A portion of the opposing electrode 123 described below may be disposed on the inner surfaces of the first hole H1, the second hole H2, and the third hole H3.

[0162] The first emitting layer 122b and the second emitting layer 122b' are disposed inside the first opening OP1 and the second opening OP2 of the pixel defining layer 119, and the first emitting layer 122b and the second emitting layer 122b' correspond to the first pixel electrode 121 and the second pixel electrode 121', respectively. The first emitting layer 122b and the second emitting layer 122b' may include high molecular weight materials or low molecular weight materials, and may emit red light, green light, blue light or white light.

[0163] The organic functional layer 122e may be disposed on and / or below the first emission layer 122b and the second emission layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. In some other embodiments, the first functional layer 122a and / or the second functional layer 122c may be omitted.

[0164] The first functional layer 122a may be disposed below the first emitting layer 122b and the second emitting layer 122b'. The first functional layer 122a may comprise a single layer or multiple layers containing organic materials. The first functional layer 122a may be a hole transport layer (HTL) as a single layer. In some other embodiments, the first functional layer 122a may comprise a hole injection layer (HIL) and an HTL. The first functional layer 122a may be provided integrally to correspond to the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') included in the main display area MDA and the component area CA.

[0165] The second functional layer 122c may be disposed on the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may comprise a single layer or multiple layers containing organic materials. The second functional layer 122c may comprise an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may be provided integrally to correspond to the main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED' included in the main display area MDA and the component area CA.

[0166] The counter electrode 123 is located above the second functional layer 122c. The counter electrode 123 may comprise a conductive material having a low work function. For example, the counter electrode 123 may comprise a (semi-)transparent layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys of these materials. In some other embodiments, the counter electrode 123 may also comprise a layer such as ITO, IZO, ZnO, or In2O3 located on a (semi-)transparent layer comprising any of the materials described above. The counter electrode 123 may be formed as a body corresponding to the main organic light-emitting diode (OLED) in the main display area MDA and the auxiliary organic light-emitting diode (OLED') in the component area CA.

[0167] The layer formed in the main display area MDA from the first pixel electrode 121 to the opposite electrode 123 can constitute a main organic light-emitting diode (OLED). The layer formed in the component area CA from the first pixel electrode 121' to the opposite electrode 123 can constitute an auxiliary organic light-emitting diode (OLED').

[0168] Top layer 150 may be formed on the counter electrode 123. Top layer 150 may include an organic material. Top layer 150 may be provided to protect the counter electrode 123 and improve light extraction efficiency. Compared to the counter electrode 123, top layer 150 may include an organic material with a higher refractive index. In some other embodiments, top layer 150 may include a stack of layers with different refractive indices. For example, top layer 150 may include a stack of high refractive index layers and / or low refractive index layers and / or high refractive index layers. In this case, the refractive index of the high refractive index layer may be about 1.7 or greater, and the refractive index of the low refractive index layer may be about 1.3 or less.

[0169] The top layer 150 may additionally include lithium fluoride (LiF). In some other embodiments, the top layer 150 may additionally include silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic insulating materials.

[0170] The first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the top layer 150 may all include a transmission aperture TAH corresponding to the transmission region TA. That is, the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the top layer 150 may all have an opening corresponding to the transmission region TA. These openings may have substantially the same area. For example, the area of ​​the opening of the counter electrode 123 may be substantially the same as the area of ​​the transmission aperture TAH.

[0171] When the transmission aperture TAH corresponds to the transmission region TA, it can be understood that the transmission aperture TAH overlaps with the transmission region TA. In this case, the area of ​​the transmission aperture TAH can be smaller than the area of ​​the first aperture H1 formed in the inorganic insulating layer IIL. Therefore, in Figure 7 The diagram shows that the width Wt of the transmission aperture TAH is smaller than the width of the first aperture H1. Here, the area of ​​the transmission aperture TAH can be defined as the area of ​​the opening with the smallest area among the openings constituting the transmission aperture TAH. The area of ​​the first aperture H1 can be defined as the area of ​​the opening with the smallest area among the openings constituting the first aperture H1.

[0172] Because of the transmission aperture TAH, a portion of the relative electrode 123 is removed from the transmission region TA. This configuration improves (e.g., significantly improves) the transmittance of the transmission region TA. The relative electrode 123 including the transmission aperture TAH can be formed by various methods. According to some embodiments, after depositing material for forming the relative electrode 123 onto the entire surface of the substrate 100, the portion of the deposited material corresponding to the transmission region TA is removed by laser lift-off, thus forming the relative electrode 123 with the transmission aperture TAH. According to another embodiment, the relative electrode 123 with the transmission aperture TAH can be formed by metal self-patterning (MSP). In another embodiment, the relative electrode 123 with the transmission aperture TAH can be formed by depositing the relative electrode 123 using a fine metal mask (FMM).

[0173] The bottom metal layer BML of the component region CA can correspond to the entire component region CA. In this case, the bottom metal layer BML may include a bottom hole BMLH overlapping the transmission region TA. In some embodiments, the shape and size of the transmission region TA may be defined by the shape and size of the bottom hole BMLH.

[0174] In some embodiments, the bottom metal layer (BML) may not be disposed in the main display area (MDA). When the bottom metal layer (BML) is disposed over the entire surface of the substrate 100 or a considerable portion of the substrate 100, defects may occur during the process of crystallizing the first semiconductor layer A1 of the main thin-film transistor (TFT) using a laser.

[0175] In this embodiment, because the bottom metal layer BML is arranged to correspond only to the component region CA, the defect rate in the process can be reduced.

[0176] Figure 8 It is an equivalent circuit diagram of a pixel circuit configured to drive a sub-pixel according to one or more example embodiments.

[0177] exist Figure 8 The pixel circuit shown in the figure illustrates the main pixel circuit PC of the main sub-pixel Pm.

[0178] The main pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a main capacitor Cst and a second capacitor Cbt. The main pixel circuit PC may be connected to a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. In some embodiments, the main pixel circuit PC may be connected to a first initialization voltage line VL1, a second initialization voltage line VL2, and a driving voltage line PL. The main pixel circuit PC may be connected to the main organic light-emitting diode (OLED) as a display element.

[0179] The drive voltage line PL can transmit the drive voltage ELVDD to the first transistor T1. The first initialization voltage line VL1 can transmit the first initialization voltage Vint1 to initialize the first transistor T1. The second initialization voltage line VL2 can transmit the second initialization voltage Vint2 to initialize the main organic light-emitting diode OLED.

[0180] exist Figure 8 The diagram shows that among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, the third transistor T3 and the fourth transistor T4 are implemented as n-channel metal-oxide-semiconductor field-effect transistors (NMOS), and the remaining transistors are implemented as p-channel metal-oxide-semiconductor field-effect transistors (PMOS).

[0181] The first transistor T1 is connected between the first node N1 and the third node N3. The first transistor T1 is connected to the drive voltage line PL via the first node N1 and the fifth transistor T5, and can be electrically connected to the main organic light-emitting diode (OLED) via the third node N3 and the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the second node N2. The first transistor T1 acts as a drive transistor, receiving the data signal DATA from the data line DL via the second transistor T2 and the first node N1 according to the switching operation of the second transistor T2, and driving the drive current I via the third node N3 and the sixth transistor T6. OLED It is supplied to the main organic light-emitting diode (OLED). The gate electrode of the first transistor T1 can be connected to the second node N2.

[0182] A second transistor T2 (e.g., a switching transistor) is connected between the data line DL and the first node N1. The second transistor T2 is connected to the power supply voltage line PL via the first node N1 and the fifth transistor T5. The gate electrode of the second transistor T2 is connected to the first scan line SL1. The second transistor T2 is turned on in response to a first scan signal SS1 having a gate on-state voltage (e.g., a low-level voltage) transmitted to its gate electrode via the first scan line SL1, and performs a switching operation to transmit the data signal DATA transmitted via the data line DL to the first node N1.

[0183] A third transistor T3 (e.g., a compensation transistor) is connected between the second node N2 and the third node N3. The third transistor T3 is connected to the main organic light-emitting diode (OLED) via the third node N3 and the sixth transistor T6. The gate electrode of the third transistor T3 is connected to the second scan line SL2. The third transistor T3 is turned on according to a second scan signal SS2 having a gate on-state voltage (e.g., a high-level voltage) transmitted to the gate electrode of the third transistor T3 via the second scan line SL2, and is diode-connected to the first transistor T1. The third transistor T3 compensates for the threshold voltage of the first transistor T1. The second scan signal SS2 may include an inverted signal of the first scan signal SS1. The second scan signal SS2 may be applied at the same timing as the first scan signal SS1.

[0184] A fourth transistor T4 (e.g., a first initialization transistor) is connected between the second node N2 and the first initialization voltage line VL1. The gate electrode of the fourth transistor T4 is connected to the third scan line SL3. The fourth transistor T4 is turned on in response to a third scan signal SS3 having a gate on-state voltage (e.g., a high-level voltage) delivered to the gate electrode of the fourth transistor T4 via the third scan line SL3, and the voltage of the gate electrode of the first transistor T1 is initialized by delivering a first initialization voltage Vint1 to the gate electrode of the first transistor T1. The first initialization voltage Vint1 comes from the first initialization voltage line VL1. The third scan signal SS3 can be applied at a timing prior to the first scan signal SS1.

[0185] A fifth transistor T5 (e.g., a first emitter control transistor) is connected between the drive voltage line PL and the first node N1. A sixth transistor T6 (e.g., a second emitter control transistor) is connected between the third node N3 and the main organic light-emitting diode OLED. The gate electrode of each of the fifth transistor T5 and the sixth transistor T6 is connected to the emitter control line EL, and the fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on in response to an emitter control signal En having a gate turn-on voltage (e.g., a low-level voltage), forming a current path such that the drive current I... OLEDThe current flows from the driving voltage line PL to the main organic light-emitting diode (OLED).

[0186] A seventh transistor T7 (e.g., a second initialization transistor) is connected between the main organic light-emitting diode (OLED) and the second initialization voltage line VL2. The gate electrode of the seventh transistor T7 is connected to the fourth scan line SL4. The seventh transistor T7 is turned on in response to a fourth scan signal SS4 having a gate on-state voltage (e.g., a low-level voltage) delivered to the gate electrode of the seventh transistor T7 via the fourth scan line SL4, and the main organic light-emitting diode (OLED) is initialized by delivering a second initialization voltage Vint2 to the OLED. The second initialization voltage Vint2 originates from the second initialization voltage line VL2. The fourth scan signal SS4 can be applied at a timing prior to the first scan signal SS1, or at a timing later than the first scan signal SS1. The seventh transistor T7 can be omitted.

[0187] The main capacitor Cst includes a first bottom electrode CE1 and a first top electrode CE2. The first bottom electrode CE1 is connected to the gate electrode of the first transistor T1 via a second node N2, and the first top electrode CE2 is connected to the drive voltage line PL. The main capacitor Cst serves as a storage capacitor and can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and holding a voltage corresponding to the voltage difference between the two opposite ends of the drive voltage line PL and the gate electrode of the first transistor T1.

[0188] The second capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 is connected to the gate electrode of the first scan line SL1 and the second transistor T2. The fourth electrode CE4 is connected via the second node N2 to the gate electrode of the first transistor T1 and the first bottom electrode CE1 of the main capacitor Cst. The second capacitor Cbt serves as a boost capacitor. When the first scan signal SS1 of the first scan line SL1 is a voltage that turns off the second transistor T2 (e.g., when the first scan signal SS1 has a high level voltage), the second capacitor Cbt can reduce the voltage used to display black (e.g., black voltage) by increasing the voltage of the second node N2.

[0189] The main organic light-emitting diode OLED includes a first pixel electrode 121 and a counter electrode 123 (see...). Figure 7 Relative electrode 123 (see) Figure 7 It can receive the common voltage ELVSS. The main organic light-emitting diode (OLED) receives a drive current I from the first transistor T1. OLED And the emission and drive current I OLED The corresponding light is used to display the image.

[0190] The main pixel circuit PC is not limited to the reference. Figure 8 The number of transistors, the number of capacitors, and the circuit design are described, and various modifications can be made. The auxiliary pixel circuit PC' configured to drive the auxiliary sub-pixel Pa can be the same as or different from the main pixel circuit PC of the main sub-pixel Pm.

[0191] Figure 9 It is a plan view of the arrangement of sub-pixels Pm and Pa, some wiring and bottom metal layer BML of display panel 10 according to one or more example embodiments. Figure 9 A portion of the component area CA and a portion of the main display area MDA, located outside the component area CA, are shown. Although Figure 9 Only the wiring required for the description is shown, but more wiring may have been omitted.

[0192] Reference Figure 9 The scan line SL can extend in the x-direction and transmit the scan signal to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa. The data line DL can extend in the y-direction, intersecting the scan line SL, and transmit the data signal to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa.

[0193] The first initialization voltage line VL1 may include a first vertical voltage line and a first horizontal voltage line arranged at different layers, the first vertical voltage line and the first horizontal voltage line extending in the y direction and the x direction, respectively. The second initialization voltage line VL2 may include a second vertical voltage line and a second horizontal voltage line arranged at different layers, the second vertical voltage line and the second horizontal voltage line extending in the y direction and the x direction, respectively (see example...). Figure 17 Extending upwards. The first vertical voltage line and the first horizontal voltage line may be electrically connected to each other in the crossing region or around the crossing region. The second vertical voltage line and the second horizontal voltage line may be electrically connected to each other in the crossing region or around the crossing region. Figure 9 The first initialization voltage line VL1 and the second initialization voltage line VL2 shown can be the first vertical voltage line and the second vertical voltage line, respectively.

[0194] The first initialization voltage line VL1 transmits a first initialization voltage (e.g., Vint1) to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa. The second initialization voltage line VL2 transmits a second initialization voltage (e.g., Vint2) to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa. The first initialization voltage line VL1 and the second initialization voltage line VL2 can be arranged alternately in the x-direction.

[0195] Some of the first initialization voltage lines VL1 and the second initialization voltage lines VL2 (e.g., initialization voltage line 41) may be disconnected around the component region CA and may not cross the component region CA. Some of the first initialization voltage lines VL1 and the second initialization voltage lines VL2 (e.g., initialization voltage line 43) may be electrically connected to the main pixel circuit PC of the main sub-pixel Pm arranged in the same column inside the main display region MDA arranged below the component region CA, and may be electrically connected across the transmission region TA to the main pixel circuit PC of the main sub-pixel Pm arranged in the same column inside the main display region MDA arranged above the component region CA. Some of the first initialization voltage lines VL1 and the second initialization voltage lines VL2 (e.g., initialization voltage line 45) may be electrically connected to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa arranged in the same column inside the main display region MDA and the component region CA. Some of the first initialization voltage lines VL1 and the second initialization voltage lines VL2 (e.g., initialization voltage line 47) may be electrically connected to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa arranged in the same column inside the main display area MDA and the component area CA, and may not be connected to the main pixel circuit PC of the main sub-pixel Pm arranged in the same column inside the main display area MDA on the top side.

[0196] Scan line SL may include scan line SL1 and scan line SLb. Scan line SL1 may extend in the x-direction and may be electrically connected to the main pixel circuit PC of the main sub-pixel Pm arranged in the same row inside the main display area MDA, and may be arranged to cross the transmission area TA without being connected to the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa. Scan line SLb may extend in the x-direction and may be electrically connected to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa arranged in the same row inside the main display area MDA and the component area CA. Scan lines SL1 and SLb each include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4, and are shown as a single scan line for ease of description.

[0197] Data lines DL can include data lines DLa and DLb. Data line DLa can extend generally in the y-direction and can be electrically connected to the main pixel circuit PC of the main sub-pixel Pm arranged in the same column inside the main display area MDA located below the component area CA. It can also be electrically connected across the transmission area TA of the component area CA to the main pixel circuit PC of the main sub-pixel Pm arranged in the same column inside the main display area MDA located above the component area CA. Data line DLb can extend in the y-direction and is electrically connected to the main pixel circuit PC of the main sub-pixel Pm and the auxiliary pixel circuit PC' of the auxiliary sub-pixel Pa, both arranged in the same column inside the main display area MDA and the component area CA. Data lines DL can be arranged on a different layer than scan lines SL.

[0198] Despite Figure 9 The diagram shows that scan lines SL and data lines DL are continuously arranged in the main display area MDA and component area CA, but scan lines SL and data lines DL can be connected to bridging lines arranged on different layers in some areas.

[0199] like Figure 9 As shown, to improve light transmittance, the first initialization voltage line VL1 and the second initialization voltage line VL2, the scan line SL, and the data line DL arranged in the component region CA can be arranged not in the central portion of the transmission region TA, but rather offset to one side. Therefore, the scan line SL and the data line DL arranged in the component region CA can be substantially curved. Thus, the spacing of the scan lines SL passing between mutually separated pixel groups PG can be smaller than the spacing of the scan lines SL passing through sub-pixels within pixel groups PG. Similarly, the spacing of the data lines DL passing between mutually separated pixel groups PG can be smaller than the spacing of the data lines DL passing through sub-pixels within pixel groups PG.

[0200] In some embodiments, data lines DLa arranged between separate pixel groups PG can be biased to the left, and data lines DLb can be biased to the right. In some embodiments, scan lines SLa arranged between separate pixel groups PG can be biased to the bottom, and scan lines SLb can be biased to the top. In some embodiments, some of the first initialization voltage lines VL1 and the second initialization voltage lines VL2 arranged between separate pixel groups PG can be biased to the left, and some of the first initialization voltage lines VL1 and the second initialization voltage lines VL2 can be biased to the right.

[0201] Depending on the wiring layout, the transmittance of the transmission region TA and the transmittance of the entire module region CA can be improved. When the spacing of the wiring in the module region CA is narrow, light diffraction may occur. Therefore, the bottom metal layer BML can be arranged to overlap with the wiring arranged in the module region CA.

[0202] The bottom metal layer BML can be arranged to correspond to the entire component area CA, and can include a bottom hole BMLH corresponding to the transmission area TA. The bottom metal layer BML may not be arranged in the main display area MDA.

[0203] The bottom metal layer BML can be connected to the bias voltage supply line 17 arranged in the peripheral area DPA via the bias line BW. The bias line BW can be connected via the contact hole BCNT (e.g., as shown in the image). Figure 7 (As shown in the diagram) connects to the edge portion of the bottom metal layer BML.

[0204] Depending on whether a bias line BW is installed, the main display area MDA can be divided into a first area BWA and a second area excluding the first area BWA. The first area BWA includes the area located between the bias voltage supply line 17 and the component area CA, and this area includes the portion of the main display area MDA in which the bias line BW is installed. The second area includes the portion of the main display area MDA in which the bias line BW is not installed.

[0205] The first initialization voltage line VL1 and the second initialization voltage line VL2 arranged in the first region BWA can be respectively connected to the first initialization voltage line VL1 and the second initialization voltage line VL2 arranged in the second region. For example, the first initialization voltage line VL1 arranged in the first region BWA extends to the second region through the component region CA; therefore, the first initialization voltage line VL1 arranged in the first region BWA and the first initialization voltage line VL2 arranged in the second region can be integrated wiring. Similarly, the second initialization voltage line VL2 arranged in the first region BWA extends to the second region through the component region CA; therefore, the second initialization voltage line VL2 arranged in the first region BWA and the second initialization voltage line VL2 arranged in the second region can be integrated wiring.

[0206] Figure 10 It is arranged in Figure 9 A magnified plan view of the pixel circuitry in region A. Figure 11 It is along Figure 10 A cross-sectional view of the pixel circuit cut by line I-I'. Figure 12 It is along Figure 10 A cross-sectional view of the pixel circuit taken from line II-II'. In the following text, details related to... Figure 7 The same components are described in detail.

[0207] Figure 10 The diagram shows pairs of main pixel circuits PCa and PCb (i.e., the left main pixel circuit PCa and the right main pixel circuit PCb described below) arranged in the same row of adjacent columns in the main display area MDA. Figure 10 The main pixel circuits PCa and PCb are shown arranged in a portion of the second region of the main display area MDA. Figure 10 The left main pixel circuit PCa and the right main pixel circuit PCb shown have a vertically symmetrical structure (e.g., vertically line symmetrical).

[0208] The main pixel circuits PCa and PCb can be connected to a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, an emission control line EL, a first horizontal voltage line VL1b of a first initialization voltage line VL1, and a second horizontal voltage line VL2b of a second initialization voltage line VL2, all extending in the x-direction. In some embodiments, the main pixel circuits PCa and PCb can be connected to a data line DL, a drive voltage line PL, and a first vertical voltage line VL1a of the first initialization voltage line VL1.

[0209] The main pixel circuits PCa and PCb may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a main capacitor Cst, and a second capacitor Cbt.

[0210] In some embodiments, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may comprise thin-film transistors comprising silicon semiconductors. The third transistor T3 and the fourth transistor T4 may comprise thin-film transistors comprising oxide semiconductors. Hereinafter, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be represented by the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7.

[0211] Also refer to Figure 7 A first semiconductor layer A1 may be disposed above the substrate 100. The first semiconductor layer A1 may include a silicon semiconductor. As another example, a buffer layer 111 may be formed on the substrate 100, and the first semiconductor layer A1 may be formed on the buffer layer 111. Figure 7 As shown, the buffer layer 111 may have a structure in which a first buffer layer 111a and a second buffer layer 111b are stacked. The first semiconductor layer A1 may include polysilicon.

[0212] The substrate 100 may include glass, ceramic materials, metallic materials, or flexible or bendable materials. When the substrate 100 is flexible or bendable, it may include polymeric resins such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyaryl compounds, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).

[0213] The substrate 100 may have a multilayer structure. For example, the substrate 100 may have a structure in which a first substrate layer 101, a first barrier layer 103, a second substrate layer 105, and a second barrier layer 107 are sequentially stacked. The first substrate layer 101 and the second substrate layer 105 may comprise a polymer resin. The first barrier layer 103 and the second barrier layer 107 can prevent the penetration of external foreign matter and may comprise materials such as silicon nitride (SiN). x ) and silicon dioxide (SiO) x (a single or multiple layer of inorganic materials).

[0214] Some regions of the first semiconductor layer A1 can form the semiconductor layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0215] First transistor T1 (e.g.) Figure 7 The semiconductor layers of the main thin-film transistor (TFT), the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may respectively include a channel region, source regions S1, S2, S5, S6, and S7, and drain regions D1, D2, D5, D6, and D7. The source regions S1, S2, S5, S6, and S7 and the drain regions D1, D2, D5, D6, and D7 may be located on two opposite sides of the channel region. For example, the source and drain regions may be doped with impurities, and may include p-type impurities. The source and drain regions may respectively correspond to the source electrode and drain electrode of the transistor (e.g., a suitable transistor among transistors T1 to T7). The source and drain regions may be interchanged depending on the characteristics of the transistor. In the following text, the terms "source region" and "drain region" are used instead of source electrode and drain electrode. Figure 11 and Figure 12 The diagram shows the channel region C1 of the first thin-film transistor T1, the channel region C6 of the sixth thin-film transistor T6, and the channel region C7 of the seventh thin-film transistor T7.

[0216] The first gate insulating layer 112 may be disposed on the first semiconductor layer A1. The first gate electrode G1, the first scan line SL1, the fourth scan line SL4, and the emission control line EL of the first thin film transistor T1 may be disposed on the first gate insulating layer 112. The first scan line SL1, the fourth scan line SL4, and the emission control line EL may extend in the x-direction and be separated from each other.

[0217] The first gate electrode G1 of the first thin-film transistor T1 has an isolated pattern and overlaps with the channel region C1, while the first gate insulating layer 112 is located between the first gate electrode G1 and the channel region C1.

[0218] The region where the first scan line SL1 overlaps with the channel region of the second thin-film transistor T2 may include the second gate electrode G2 of the second thin-film transistor T2. The region where the fourth scan line SL4 overlaps with the channel region C7 of the seventh thin-film transistor T7 may include the gate electrode G7 of the seventh thin-film transistor T7. The regions where the emitter control line EL overlaps with the fifth thin-film transistor T5 and the sixth thin-film transistor T6 may include the gate electrode G5 of the fifth thin-film transistor T5 and the gate electrode G6 of the sixth thin-film transistor T6, respectively.

[0219] The second gate insulating layer 113 can be disposed on the first gate electrode G1, the first scan line SL1, the fourth scan line SL4 and the emission control line EL of the first thin film transistor T1.

[0220] The electrode voltage line HL, the first horizontal voltage line VL1b of the first initialization voltage line VL1, the bottom scan line 143 of the second scan line SL2, and the bottom scan line 165 of the third scan line SL3 can all extend in the x direction and can be separated from each other.

[0221] The electrode voltage line HL may cover at least a portion of the first gate electrode G1 of the first thin-film transistor T1 and may serve as the first top electrode CE2 of the main capacitor Cst. The electrode voltage line HL may include an opening SOP (see [link to SOP]). Figure 11 The main capacitor Cst includes a first bottom electrode CE1 and a first top electrode CE2, and may overlap with the first thin-film transistor T1. The first gate electrode G1 of the first thin-film transistor T1 may also be used as the first bottom electrode CE1 of the main capacitor Cst. For example, the first gate electrode G1 and the first bottom electrode CE1 of the first thin-film transistor T1 may be formed into a single body.

[0222] An interlayer insulating layer 114 may be disposed on the second gate insulating layer 113. A second semiconductor layer A2 may be disposed on the interlayer insulating layer 114. The second semiconductor layer A2 may include a semiconductor layer of each of the third thin-film transistor T3 and the fourth thin-film transistor T4. The second semiconductor layer A2 may include a zinc oxide (Zn) based material, such as zinc oxide (Zn), indium (In) zinc oxide (Zn), and gallium (Ga) indium (In) zinc oxide (Zn). In embodiments, the second semiconductor layer A2 may include an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor comprising metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO.

[0223] The semiconductor layers of the third thin-film transistor T3 and the fourth thin-film transistor T4 may each include channel regions C3 and C4, source regions S3 and S4, and drain regions D3 and D4. Source regions S3 and S4 and drain regions D3 and D4 are located on two opposite sides of channel regions C3 and C4, respectively. The source regions S3 and D3 of the third thin-film transistor T3 and the source regions S4 and D4 of the fourth thin-film transistor T4 can be formed by adjusting the carrier concentration of the oxide semiconductor and making the source and drain regions conductive. The source regions S3 and D3 of the third thin-film transistor T3 and the source regions S4 and D4 of the fourth thin-film transistor T4 can be formed by increasing the carrier concentration via plasma processing performed on the oxide semiconductor, using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0224] The second semiconductor layer A2 may include the fourth electrode CE4 of the second capacitor Cbt. The fourth electrode CE4 of the second capacitor Cbt may be disposed between the semiconductor layers of the third thin-film transistor T3 and the fourth thin-film transistor T4. The fourth electrode CE4 may extend from the semiconductor layer of the third thin-film transistor T3 or the semiconductor layer of the fourth thin-film transistor T4. The portion where the first scan line SL1 overlaps with the fourth electrode CE4 of the second capacitor Cbt may include the third electrode CE3 of the second capacitor Cbt.

[0225] The third gate insulating layer 115 can be disposed on the second semiconductor layer A2. The second horizontal voltage line VL2b of the second initialization voltage line VL2, the top scan line 163 of the second scan line SL2, and the top scan line 145 of the third scan line SL3 can extend in the x direction on the third gate insulating layer 115. That is, the second scan line SL2 and the third scan line SL3 can each include two conductive layers disposed on different layers.

[0226] The top scan line 163 of the second scan line SL2 may overlap with at least a portion of the bottom scan line 143. The top scan line 145 of the third scan line SL3 may overlap with at least a portion of the bottom scan line 165.

[0227] The portion where the bottom scan line 143 of the second scan line SL2 overlaps with the second semiconductor layer A2 may include the bottom gate electrode G3a of the gate electrode G3 of the third thin-film transistor T3 (see...). Figure 12 Furthermore, the portion where the top scan line 163 overlaps with the second semiconductor layer A2 may include the top gate electrode G3b of the gate electrode G3 of the third thin-film transistor T3 (see...). Figure 12 ).

[0228] The portion where the bottom scan line 165 of the third scan line SL3 overlaps with the second semiconductor layer A2 may include the bottom gate electrode G4a of the gate electrode G4 of the fourth thin-film transistor T4 (see...). Figure 11 Furthermore, the portion where the top scan line 145 overlaps with the second semiconductor layer A2 may include the top gate electrode G4b of the gate electrode G4 of the fourth thin-film transistor T4 (see [link to relevant documentation]). Figure 11 For example, the third thin-film transistor T3 and the fourth thin-film transistor T4 can both have a dual-gate structure, in which the control electrodes are respectively disposed on the upper and lower parts of the semiconductor layer.

[0229] In some embodiments, the third gate insulating layer 115 may be patterned to a shape corresponding to the top scan line 163 of the second scan line SL2 and the top scan line 145 of the third scan line SL3.

[0230] The second interlayer insulating layer 116 may cover the third thin-film transistor T3 and the fourth thin-film transistor T4 located on the third gate insulating layer 115. The first vertical voltage line VL1a of the first initialization voltage line VL1, the node electrode 171, and the connecting electrodes 172, 173, 174, 175, and 176 may be arranged on the second interlayer insulating layer 116.

[0231] The first vertical voltage line VL1a of the first initialization voltage line VL1, the node electrode 171, and the connecting electrodes 172, 173, 174, 175, and 176 may comprise a material with high conductivity, such as a conductive oxide. For example, the first vertical voltage line VL1a of the first initialization voltage line VL1, the node electrode 171, and the connecting electrodes 172, 173, 174, 175, and 176 may each comprise a single layer or multiple layers comprising at least one of aluminum (Al), copper (Cu), and titanium (Ti). In some embodiments, the first vertical voltage line VL1a of the first initialization voltage line VL1, the node electrode 171, and the connecting electrodes 172, 173, 174, 175, and 176 may each comprise three layers of Ti / Al / Ti arranged in sequence.

[0232] The second interlayer insulating layer 116 may include an inorganic material, including oxides or nitrides. For example, the second interlayer insulating layer 116 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2).

[0233] The third gate insulating layer 115 and the second interlayer insulating layer 116 can cooperate with the first gate insulating layer 112, the second gate insulating layer 113 and the interlayer insulating layer 114 to form a structure. Figure 7 The inorganic insulating layer IIL is shown in the figure.

[0234] The first vertical voltage line VL1a of the first initialization voltage line VL1 can extend in the y-direction and be arranged between the left main pixel circuit PCa and the right main pixel circuit PCb. For example, the left main pixel circuit PCa and the right main pixel circuit PCb can be symmetrical with respect to the first vertical voltage line VL1a of the first initialization voltage line VL1.

[0235] The first vertical voltage line VL1a of the first initialization voltage line VL1 can contact and connect to the first horizontal voltage line VL1b of the first initialization voltage line VL1 through a contact hole (e.g., contact hole 37). Therefore, the wiring configured to apply the first initialization voltage Vint1 can have a mesh structure.

[0236] The first vertical voltage line VL1a may include a protruding VL1ap that protrudes in the x-direction and overlaps with the first horizontal voltage line VL1b. The protruding VL1ap of the first vertical voltage line VL1a may contact and be electrically connected to the source region S4 of the fourth thin-film transistor T4 and the first horizontal voltage line VL1b through contact holes 36 and 37, respectively.

[0237] Node electrode 171 can contact the first gate electrode G1 and the second semiconductor layer A2 of the first thin-film transistor T1 through contact holes, and can be electrically connected to the first gate electrode G1 and the second semiconductor layer A2 of the first thin-film transistor T1. One end of node electrode 171 can be opened through the opening SOP of the first top electrode CE2 of the main capacitor Cst (see...). Figure 11 The first gate electrode G1 of the first thin-film transistor T1 is connected to the second gate electrode G1. The other end of the node electrode 171 can be connected to the fourth electrode CE4 of the second capacitor Cbt.

[0238] One end of the connecting electrode 172 can be electrically connected to the drain region D1 of the first thin-film transistor T1 and the source region S6 of the sixth thin-film transistor T6 through a contact hole. The other end of the connecting electrode 172 can be electrically connected to the drain region D3 of the third thin-film transistor T3 through a contact hole.

[0239] The connecting electrode 173 can be electrically connected to the source region S2 of the second thin-film transistor T2 through the contact hole.

[0240] The connecting electrode 174 can be electrically connected to the source region S5 and the electrode voltage line HL of the fifth thin film transistor T5 through the contact hole, respectively.

[0241] One end of the connecting electrode 175 can be electrically connected to the drain region D7 of the seventh thin-film transistor T7 through a contact hole. The other end of the connecting electrode 175 can be electrically connected to the second horizontal voltage line VL2b of the second initialization voltage line VL2 through a contact hole.

[0242] The connecting electrode 176 can be electrically connected to the drain region D6 of the sixth thin-film transistor T6 through the contact hole.

[0243] The first planarization layer 117a and the second planarization layer 117b can be stacked on the second interlayer insulating layer 116. Data lines DL, drive voltage lines PL, and connecting metal CM (i.e., Figure 7 The main connection electrode can be arranged between the first planarization layer 117a and the second planarization layer 117b.

[0244] The data line DL, drive voltage line PL, and connecting metal CM may include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may comprise a single layer or multiple layers. For example, the data line DL, drive voltage line PL, and connecting metal CM may comprise a Ti / Al / Ti multilayer structure.

[0245] The data line DL can be electrically connected to the source region S2 of the second thin-film transistor T2 via a contact hole to the connection electrode 173.

[0246] The drive voltage line PL can be electrically connected to the electrode voltage line HL (e.g., the first top electrode CE2 of the main capacitor Cst) via a contact hole to the connection electrode 174. Therefore, the wiring configured to apply the drive voltage ELVDD can have a mesh structure.

[0247] The connecting metal CM can be connected to the connecting electrode 176 through a contact hole, and the first pixel electrode 121 (see...) Figure 7 The first pixel electrode 121 (see via) can be connected to the connecting metal CM through the through-hole VIA. Figure 7 It can be electrically connected to the main pixel circuit PC (see...) Figure 7 ).

[0248] First pixel electrode 121 (see Figure 7 The first pixel electrode 121 is disposed on the second planarization layer 117b, and the pixel defining layer 119 is disposed on the second planarization layer 117b and covers the first pixel electrode 121 (see [link]). Figure 7 The edge of ). Although Figure 11 and Figure 12 Only the first emission layer 122b is shown, but various functional layers can be further arranged on and / or below the first emission layer 122b, such as in Figure 7 As described in [the text].

[0249] Including with Figure 10 The pixel circuits PCa and PCb shown in the diagram have multiple master sub-pixels Pm that can be arranged in both the x and y directions. In this case, the first scan line SL1 and the fourth scan line SL4 can be shared by two pixel circuits that are adjacent to each other in the y direction.

[0250] For example, the fourth scan line SL4 can be electrically connected to the line arranged in the positive (+)y direction in the attached figure. Figure 10 The second thin-film transistor T2 of other pixel circuits PCa and PCb shown above pixel circuits PCa and PCb. Therefore, the fourth scan signal SS4 applied to the fourth scan line SL4 can be transmitted as a second scan signal to the second thin-film transistor T2 of other pixel circuits PCa and PCb. Similarly, the first scan line SL1 can be electrically connected to the second thin-film transistor T2 of other pixel circuits PCa and PCb arranged in the negative (-)y direction in the figure. Figure 10 The image shows the seventh thin-film transistor T7 of the other pixel circuits PCa and PCb below the pixel circuits PCa and PCb. Therefore, the first scan signal SS1 applied to the first scan line SL1 can be transmitted as the fourth scan signal to the seventh thin-film transistor T7 of the other pixel circuits PCa and PCb.

[0251] Figure 13 It is arranged in Figure 9 A magnified planar view of the pixel circuitry in region B. Figure 14 It is along Figure 13 A cross-sectional view of the pixel circuit taken from line III-III'. In the following text, details related to... Figures 10 to 12 The components are the same as those of the components, and the main difference is described.

[0252] Figure 13 The diagram shows pairs of main pixel circuits PCd and PCe (i.e., the left main pixel circuit PCd and the right main pixel circuit PCe described below) arranged in the same row of adjacent columns in the main display area MDA. Figure 13 The main pixel circuits PCd and PCe are shown in a portion of the second region of the main display area MDA.

[0253] Reference Figure 13 The second vertical voltage line VL2a of the second initialization voltage line VL2 can extend in the y-direction and be arranged between the left main pixel circuit PCd and the right main pixel circuit PCe. For example, the left main pixel circuit PCd and the right main pixel circuit PCe can be symmetrical with respect to the second vertical voltage line VL2a of the second initialization voltage line VL2.

[0254] Reference Figure 14 as well as Figure 13 The second vertical voltage line VL2a of the second initialization voltage line VL2 can contact and be electrically connected to the second horizontal voltage line VL2b of the second initialization voltage line VL2 through the contact hole 43. Therefore, the wiring configured to apply the second initialization voltage Vint2 can have a mesh structure.

[0255] The second vertical voltage line VL2a can be connected to the first vertical voltage line VL1a of the first initialization voltage line VL1 (see...). Figure 10 They are arranged on the same layer. The second vertical voltage line VL2a can be arranged on the second interlayer insulation layer 116.

[0256] The second vertical voltage line VL2a may further include a first protrusion VL2ap that protrudes in the x-direction and overlaps with the second horizontal voltage line VL2b. The second vertical voltage line VL2a may also include a second protrusion 175' that protrudes from the first protrusion VL2ap in the positive (+)y direction. The second vertical voltage line VL2a, the first protrusion VL2ap, and the second protrusion 175' may be formed as a single body. The second vertical voltage line VL2a may be electrically connected to the second horizontal voltage line VL2b via a contact hole 43 in the region where the first protrusion VL2ap and the second protrusion 175' intersect. One end of the second protrusion 175' may be electrically connected to the drain region D7 of the seventh thin-film transistor T7 via a contact hole 42. The second protrusion 175' may have a... Figure 10 The shape corresponding to the connection electrode 175 shown in the figure can be used to connect the seventh thin-film transistor T7 to the second horizontal voltage line VL2b.

[0257] The connecting electrode 177 can be further arranged above the second interlayer insulating layer 116. The connecting electrode 177 can be arranged through contact holes 36 and 37 respectively (see...). Figure 10 It can contact the source region S4 of the fourth thin-film transistor T4 and the first horizontal voltage line VL1b and can be electrically connected to the source region S4 of the fourth thin-film transistor T4 and the first horizontal voltage line VL1b.

[0258] The second vertical voltage line VL2a and the connecting electrode 177 may each comprise a single layer or multiple layers containing at least one of aluminum (Al), copper (Cu), and titanium (Ti). In some embodiments, the second vertical voltage line VL2a and the connecting electrode 177 may each comprise three layers of Ti / Al / Ti arranged in sequence.

[0259] Figure 15 It is arranged in Figure 9 A magnified planar view of the pixel circuitry in region D. Figure 16 It is along Figure 15 A cross-sectional view of the pixel circuit cut by line IV-IV'. Figure 15 The pixel circuitry is shown within a portion of the first region BWA of the main display area MDA. In the following text, details related to... Figures 10 to 12 The components are the same as those of the components, and the main difference is described.

[0260] Figure 15 The diagram shows pairs of main pixel circuits PC arranged in the same row of adjacent columns in the first region BWA of the main display area MDA.

[0261] Reference Figure 15 The bias line BW can extend in the y-direction and can be positioned between the left main pixel circuit PCf and the right main pixel circuit PCg. For example, the left main pixel circuit PCf and the right main pixel circuit PCg can be symmetrical with respect to the bias line BW.

[0262] The bias line BW may intersect with the first horizontal voltage line VL1b of the first initialization voltage line VL1 and the second horizontal voltage line VL2b of the second initialization voltage line VL2, and may extend in the y-direction. (See also...) Figure 16 The bias line BW can be arranged on the second interlayer insulation layer 116, and can be connected to the first vertical voltage line VL1a of the first initialization voltage line VL1 (see...). Figure 10 ) and the second vertical voltage line VL2a of the second initialization voltage line VL2 (see Figure 14 They are arranged on the same floor.

[0263] The connecting electrode 177 can be further arranged above the second interlayer insulating layer 116. The connecting electrode 177 can be arranged through contact holes 36 and 37 respectively (see...). Figure 10 It can contact the source region S4 of the fourth thin-film transistor T4 and the first horizontal voltage line VL1b and can be electrically connected to the source region S4 of the fourth thin-film transistor T4 and the first horizontal voltage line VL1b.

[0264] The bias line BW and the connecting electrode 177 may each comprise a single layer or multiple layers, wherein the single layer or multiple layers comprise at least one of aluminum (Al), copper (Cu), and titanium (Ti). In some embodiments, the bias line BW and the connecting electrode 177 may each comprise three layers of Ti / Al / Ti arranged in sequence.

[0265] The bias line BW can be connected to the bottom metal layer BML arranged to correspond to the component region CA. The bias line BW can be connected to the bottom metal layer BML through contact holes BCNT passing through the inorganic insulating layer IIL and the second buffer layer 111b. In some embodiments, unlike the figures, an intermediate intermediate electrode layer may be further provided to connect the bias line BW to the bottom metal layer BML.

[0266] Figure 17 It is arranged in Figure 9 A magnified plan view of the vertical wiring in region E.

[0267] Reference Figure 17 The vertical wiring may include a bias line BW that extends in the y direction, a first vertical voltage line VL1a of the first initialization voltage line VL1, and a second vertical voltage line VL2a of the second initialization voltage line VL2.

[0268] In the first region BWA of the main display area MDA, bias lines BW can be arranged at intervals (e.g., a preset interval) in the x-direction. The first vertical voltage line VL1a of the first initialization voltage line VL1 and the second vertical voltage line VL2a of the second initialization voltage line VL2 can be arranged alternately between pairs of bias lines BW. For example, bias lines BW, the first vertical voltage line VL1a, and the second vertical voltage line VL2a can be arranged alternately along the x-direction in the first region BWA. In the first region BWA, one of the bias lines BW, the first vertical voltage line VL1a, and the second vertical voltage line VL2a can extend in the y-direction between pairs of adjacent columns. In the first region BWA, bias lines BW, the first vertical voltage line VL1a, and the second vertical voltage line VL2a can be arranged alternately at intervals of two columns. Assuming the width of the pixel circuit region PCA in the x direction is the circuit gap SG, the bias line BW can be arranged along the x direction with six circuit gaps SG. For example, there can be six circuit gaps SG between the two closest bias lines BW along the x direction.

[0269] The first vertical voltage line VL1a of the first initialization voltage line VL1 can be electrically connected to the first horizontal voltage line VL1b disposed on a different layer. For example, the first vertical voltage line VL1a may include a protruding portion VL1ap overlapping the first horizontal voltage line VL1b, and the protruding portion VL1ap can contact and be connected to the first horizontal voltage line VL1b through contact hole 37. The first vertical voltage line VL1a can be disposed between pixel circuits disposed in pairs of left / right pixel circuit regions PCA.

[0270] The second vertical voltage line VL2a of the second initialization voltage line VL2 can contact and be electrically connected to the second horizontal voltage line VL2b disposed on a different layer. For example, the second vertical voltage line VL2a may include a first protrusion VL2ap overlapping the second horizontal voltage line VL2b, and the first protrusion VL2ap can contact and be electrically connected to the second horizontal voltage line VL2b through contact hole 43. The second vertical voltage line VL2a may also include a second protrusion 175' protruding from the first protrusion VL2ap. The second protrusion 175' can also serve as a connection electrode. The second vertical voltage line VL2a can be disposed between pixel circuits, which are disposed in pairs of left / right pixel circuit regions PCA.

[0271] The bias line BW can pass through the first region BWA and can be connected to the edge portion of the bottom metal layer BML through the contact hole BCNT. The bias line BW can be arranged between pixel circuits arranged in paired left / right pixel circuit regions PCA. The bias line BW can cross (or overlap) with the first horizontal voltage line VL1b of the first initialization voltage line VL1 and the second horizontal voltage line VL2b of the second initialization voltage line VL2.

[0272] Figure 18 It is arranged in Figure 9 A magnified plan view of the vertical wiring in region F.

[0273] Reference Figure 18 Vertical wiring may include a first vertical voltage line VL1a of a first initialization voltage line VL1 and a second vertical voltage line VL2a of a second initialization voltage line VL2, both extending in the y direction.

[0274] Reference Figure 18In the second region of the main display area MDA, excluding the first region BWA, the first vertical voltage line VL1a of the first initialization voltage line VL1 and the second vertical voltage line VL2a of the second initialization voltage line VL2 can be arranged alternately in the x-direction. In the second region, the first vertical voltage line VL1a and the second vertical voltage line VL2a can be arranged alternately at two-column intervals. That is, one of the first vertical voltage line VL1a and the second vertical voltage line VL2a can extend in the y-direction between pairs of adjacent columns in the second region. The first vertical voltage line VL1a of the first initialization voltage line VL1 and the second vertical voltage line VL2a of the second initialization voltage line VL2 can be arranged with four circuit gaps SG in the x-direction; for example, along the x-direction, four circuit gaps SG can exist between any two first vertical voltage lines VL1a or any two second vertical voltage lines VL2a.

[0275] Figure 19 It is a plan view of a portion of the display panel 10 according to one or more example embodiments. Figure 20 It is arranged in Figure 19 A magnified plan view of the vertical wiring in region G. Figure 19 A portion of the component area CA and a portion of the main display area MDA, located outside the component area CA, are shown. Although Figure 19 Only the wiring required for the description is shown, but more wiring may have been omitted.

[0276] Reference Figure 19 and Figure 20 In the first region BWA of the main display area MDA, bias lines BW are arranged at intervals (e.g., a preset interval) in the x-direction, and a first initialization voltage line VL1 and a second initialization voltage line VL2 can be arranged between pairs of bias lines BW. A first vertical voltage VL1a of the first initialization voltage line VL1 and a second vertical voltage line VL2a of the second initialization voltage line VL2 can be alternately arranged between pairs of bias lines BW. For example, in the first region BWA, one of the bias lines BW, the first vertical voltage line VL1a, and the second vertical voltage line VL2a can extend in the y-direction between pairs of adjacent columns.

[0277] In some embodiments, in a second region of the main display area MDA other than the first region BWA, dummy lines DBW can be arranged at the same interval as the bias lines BW in the first region BWA. First initialization voltage lines VL1 and second initialization voltage lines VL2 can be arranged between pairs of dummy lines DBW. For example, the first vertical voltage line VL1a of the first initialization voltage line VL1 and the second vertical voltage line VL2a of the second initialization voltage line VL2 can be arranged alternately between pairs of dummy lines DBW (e.g., see...). Figure 19).

[0278] The dummy line DBW can be disposed on the same layer as the bias line BW. The dummy line DBW can be disposed above the second interlayer insulation layer 116. The dummy line DBW can comprise a single layer or multiple layers, which include at least one of aluminum (Al), copper (Cu), and titanium (Ti). In some embodiments, the dummy line DBW can comprise three layers of Ti / Al / Ti arranged in sequence.

[0279] The dummy line DBW may include a floating electrode that is not connected to the bias voltage supply line 17 and is not subject to voltage and / or signal. Because the dummy line DBW is arranged in areas of the main display area MDA other than the first area BWA, the pattern throughout the main display area MDA can be uniform. The dummy line DBW may be disconnected around the component area CA, and therefore may not be arranged in the component area CA.

[0280] In another embodiment, the dummy line DBW can be electrically connected to either the first initialization voltage line VL1 or the second initialization voltage line VL2.

[0281] In some embodiments, since a portion of the wiring that extends vertically across the panel is used as a connection wiring (e.g., a bias line) to apply a bias voltage to the bottom metal layer BML of the component region CA, a separate space for arranging the connection wiring may not be required.

[0282] While the above embodiments include pixel circuits comprising n-channel metal-oxide-semiconductor (NMOS) field-effect transistors (FETs) and p-channel metal-oxide-semiconductor (PMOS) field-effect transistors (FETs), the example embodiments are not limited thereto. For example, one or more embodiments can similarly be applied to display panels comprising sub-pixels connected to pixel circuits comprising only NMOSFETs or pixel circuits comprising only PMOSFETs and including vertical wiring such as initialization voltage lines.

[0283] Although the above embodiments describe a display panel in which two types of initialization voltage lines are repeatedly arranged in a vertical wiring configuration in the horizontal direction, the exemplary embodiments are not limited thereto. For example, the embodiments can be similarly applied to a display panel in which one type of initialization voltage line is repeatedly arranged in a vertical wiring configuration in the horizontal direction. For example, bias lines and initialization voltage lines may be arranged alternately in the horizontal direction in the first region BWA of the main display area MDA, and initialization voltage lines may be repeatedly arranged in the horizontal direction in the remaining regions, or dummy lines and initialization voltage lines may be repeatedly arranged in the horizontal direction.

[0284] Although the first initialization voltage line VL1 and the second initialization voltage line VL2 are arranged on the same layer in the above embodiment, the embodiment is not limited thereto. For example, the first initialization voltage line VL1 and the second initialization voltage line VL2 may be arranged on different layers, and the bias line BW may be arranged on the same layer as the first initialization voltage line VL1 or the second initialization voltage line VL2.

[0285] As described above, the display panel and display device according to this embodiment include a bias line disposed on the same layer as vertical wiring such as an initialization voltage line, wherein the bias line is connected to a bottom metal layer of the component region. Therefore, by adjusting the brightness using a voltage applied to the bottom metal layer via the bias line, changes in the characteristics of the display panel can be prevented. However, the scope of this disclosure is not limited by this effect.

[0286] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising a display panel, the display panel comprising: The main display area, in which the main display element is located; The component area, auxiliary display element, and transmissive area are located in the component area; as well as The peripheral area is located outside the main display area; The display panel further includes: substrate; An initialization voltage line is located in the main display area and extends in a first direction; A bottom metal layer is located in the component region and between the substrate and the auxiliary display element; and The offset line is located in the main display area and extends in the first direction. The bias line is connected to the bottom metal layer and is located on the same layer as the initialization voltage line. The bias line applies a bias voltage to the bottom metal layer to cause the auxiliary thin-film transistor connected to the auxiliary display element to be formed as a dual-gate transistor. In the first region surrounding the component region of the main display area, the bias line and the initialization voltage line are arranged alternately along a second direction that intersects the first direction.

2. The display device according to claim 1, wherein, The initialization voltage line includes a first initialization voltage line and a second initialization voltage line, wherein, in the first region of the main display area, the bias line, the first initialization voltage line and the second initialization voltage line are alternately arranged along a second direction that intersects the first direction.

3. The display device according to claim 2, wherein, In the second region of the main display area, the first initialization voltage line and the second initialization voltage line are arranged alternately along the second direction.

4. The display device according to claim 2, wherein, The bias voltage applied to the bias line is different from the initialization voltage applied to the initialization voltage line.

5. The display device according to claim 2, wherein, The display panel also includes: The main pixel circuits are respectively connected to the main display elements in the main display area; and Auxiliary pixel circuits are respectively connected to the auxiliary display elements in the component area. The bottom metal layer is located between the substrate and the auxiliary pixel circuit, and the auxiliary pixel circuit includes the auxiliary thin-film transistor.

6. The display device according to claim 5, wherein, The main pixel circuit includes a left main pixel circuit and a right main pixel circuit that are symmetrical with respect to the bias line.

7. The display device according to claim 5, wherein, The main pixel circuit includes: The paired first master pixel circuits are symmetrical with respect to the bias line; and The paired second main pixel circuits are symmetrical with respect to the initialization voltage line, and the paired second main pixel circuits are adjacent to the paired first main pixel circuits in the second direction.

8. The display device according to claim 2, wherein, The display panel also includes: A first horizontal voltage line extends in the second direction and connects to the first initialization voltage line; and The second horizontal voltage line extends in the second direction and is connected to the second initialization voltage line.

9. The display device according to claim 2, wherein, The display panel also includes a dummy line arranged in a second region of the main display area and extending in the first direction. The dummy line, the first initialization voltage line, and the second initialization voltage line are arranged alternately along the second direction in the second region.

10. The display device according to claim 9, wherein, The dummy line and the offset line are located on the same layer.

11. The display device according to claim 10, wherein, The dummy line is electrically connected to either the first initialization voltage line or the second initialization voltage line.

12. The display device according to claim 10, wherein, The first initialization voltage line in the first region and the first initialization voltage line in the second region are integrally formed, and The second initialization voltage line in the first region and the second initialization voltage line in the second region are integrally formed.

13. The display device according to claim 2, wherein, The first initialization voltage line and the second initialization voltage line are located on different layers.

14. The display device according to claim 1, wherein, The display panel also includes a bias voltage supply line disposed in the peripheral area, wherein the bias line is connected to the bias voltage supply line.

15. The display device according to claim 1, wherein, The display panel also includes a driving voltage line located on the bias line and extending in the first direction.

16. The display device according to claim 1, wherein, The display panel also includes a data line located on the bias line and extending in the first direction.

17. The display device according to claim 1, wherein, The bottom metal layer includes a bottom hole corresponding to the transmission region.

18. A display device, wherein, The display device includes a display panel; The display panel includes a main display area and a component area, wherein the main display element is located in the main display area, and the auxiliary display element and the transmissive area are located in the component area; The display panel further includes: substrate; A first initialization voltage line is located in the main display area and includes a first vertical voltage line and a first horizontal voltage line. The first vertical voltage line extends in a first direction, and the first horizontal voltage line extends in a second direction that intersects the first direction and is connected to the first vertical voltage line. A second initialization voltage line is located in the main display area and includes a second vertical voltage line and a second horizontal voltage line. The second vertical voltage line extends in the first direction, and the second horizontal voltage line extends in the second direction and is connected to the second vertical voltage line. A bottom metal layer is located in the component region and between the substrate and the auxiliary display element; and A bias line, located in the main display area, is connected to the bottom metal layer and extends in the first direction. The bias line applies a bias voltage to the bottom metal layer to cause the auxiliary thin-film transistor connected to the auxiliary display element to be formed as a dual-gate transistor. The bias line, the first vertical voltage line, and the second vertical voltage line are arranged alternately along the second direction in a first region of the main display area surrounding the component region.

19. The display device according to claim 18, wherein, The bias voltage applied to the bias line is different from the voltage applied to the first initialization voltage line and the voltage applied to the second initialization voltage line.

20. The display device according to claim 18, wherein, The first vertical voltage line and the second vertical voltage line are arranged alternately along the second direction in the second region of the main display area.

21. The display device according to claim 18, wherein, The display panel also includes a dummy line located in a second region of the main display area and extending along the first direction. The dummy line, the first vertical voltage line, and the second vertical voltage line are arranged alternately along the second direction in the second region.

22. The display device according to claim 21, wherein, The bias line, the first vertical voltage line, and the second vertical voltage line are located on the same layer.

23. The display device according to claim 18, wherein, The display panel also includes a main pixel circuit located in the main display area and configured to drive the main display elements. The main pixel circuit includes a left main pixel circuit and a right main pixel circuit that are symmetrical with respect to the bias line.

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