Display device and electronic equipment

Abstract

The present disclosure relates to a display device and an electronic apparatus. A display device includes a substrate; a plurality of pixel circuits each including a sampling transistor, a driving transistor, a first switching transistor, a second switching transistor, a capacitive element, and a light emitting element; a plurality of scan lines including a first scan line, a second scan line, and a third scan line, the first scan line connected to a control terminal of the sampling transistor, the second scan line connected to a control terminal of the first transistor, and the third scan line connected to a control terminal of the second transistor; and a plurality of signal lines, and the signal line connected to a first terminal of the sampling transistor, wherein the first scan line and the second scan line are in a first interconnection layer, the signal line is in a second interconnection layer, the first scan line and the second scan line extend in a first direction, the signal line extends in a second direction perpendicular to the first direction, and the first interconnection layer is between the substrate and the second interconnection layer.

Description

[0001] This application is a divisional application of the PCT international application No. PCT / JP2017 / 027160, international filing date of 27 July 2017, title of invention "Display device and electronic apparatus", designating all countries. This application claims priority from Japanese Patent Application No. 2017-152593, filed on August 8, 2017, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a display device and an electronic apparatus. BACKGROUND

[0003] A display device that can be driven by a so-called active matrix system generally has a configuration in which light emitting elements and pixel circuits including a drive circuit for causing the light emitting elements to be driven are provided at positions corresponding to each intersection of a plurality of scan lines extending in a lateral direction of a display surface (hereinafter, sometimes referred to as a horizontal direction) and are placed so as to be arranged in a vertical direction of the display surface (hereinafter, sometimes referred to as a vertical direction) and a plurality of data lines (signal lines) extending in the vertical direction, and are placed so as to be arranged in the horizontal direction. One pixel circuit corresponds to one pixel or a sub-pixel. The potential of the scan line and the signal line is changed at an appropriate timing; thereby, the on / off of an active element (transistor or the like) in the drive circuit provided in the pixel circuit is appropriately controlled, and the light emission of the light emitting element in the pixel circuit is controlled. As a display device that can be driven by an active matrix system, for example, a display device in which an organic light emitting diode (OLED) is used as a light emitting element (hereinafter, sometimes referred to as an organic electroluminescence (EL) display device) has been developed (for example, Patent Literatures 1 to 4).

[0004] Bibliographic details

[0005] Patent Literature

[0006] Patent Literature 1: JP 2015-55763

[0007] Patent Literature 2: JP 2016-53636

[0008] Patent Literature 3: JP 2016-53640

[0009] Patent Literature 4: JP 2016-53641A SUMMARY

[0010] TECHNICAL PROBLEM

[0011] In this connection, for example, in display devices, in order to realize display with higher definition and mount it in relatively small electronic devices such as wearable devices, it is necessary to reduce the pixel size. When the pixel size is reduced, the layout of the pixel circuit is also miniaturized, and thus the following problems can occur. That is, the problems are the deterioration of the luminance uniformity due to the noise interference between electrodes caused by the increase in the parasitic capacitance between the wirings, the deterioration of the luminance uniformity caused by the noise resistance due to the stress on the area of the electrode of the capacitance element, the failure of the short circuit between the wirings due to the wirings becoming dense, the failure of the open circuit of the wirings (so-called jump film) due to the failure to normally form the wiring pattern of small area, and the like. In order to realize a display device with high definition and high reliability, it is necessary to suppress the occurrence of these problems.

[0012] Therefore, the present disclosure proposes a new and improved display device and electronic device that is capable of further improving reliability.

[0013] Solution to the problem

[0014] According to the present disclosure, there is provided a display device including: a substrate; a plurality of pixel circuits each including a sampling transistor, a driving transistor, a first switching transistor, a second switching transistor, a capacitance element, and a light emitting element; a plurality of scan lines including a first scan line, a second scan line, and a third scan line, the first scan line being connected to a control terminal of the sampling transistor, the second scan line being connected to a control terminal of the first transistor, and the third scan line being connected to a control terminal of the second transistor; and a plurality of signal lines, and the signal line being connected to a first terminal of the sampling transistor, wherein the first scan line and the second scan line are in a first interconnection layer, the signal line is in a second interconnection layer, the first scan line and the second scan line extend in a first direction, the signal line extends in a second direction perpendicular to the first direction, and the first interconnection layer is between the substrate and the second interconnection layer.

[0015] Further, according to the present application, there is provided an electronic device including a display device that performs display based on a video signal, wherein the display device includes a substrate, a plurality of pixel circuits each including a sampling transistor, a drive transistor, a first switching transistor, a second switching transistor, a capacitor element, and a light emitting element, a plurality of scan lines including a first scan line, a second scan line, and a third scan line, the first scan line being connected to a control terminal of the sampling transistor, the second scan line being connected to a control terminal of the first transistor, and the third scan line being connected to a control terminal of the second transistor, and a plurality of signal lines, and the signal lines being connected to a first terminal of the sampling transistor, wherein the first scan line and the second scan line are in a first interconnection layer, the signal lines are in a second interconnection layer, the first scan line and the second scan line extend in a first direction, the signal lines extend in a second direction perpendicular to the first direction, and the first interconnection layer is between the substrate and the second interconnection layer.

[0016] According to the present disclosure, as for two types of orthogonal wirings (scan lines and signal lines) provided for a pixel unit, the one of the two types of wirings provided for one pixel circuit which is more in number is formed in a wiring layer of a lower layer. Thus, it is possible to make the wiring pattern in the wiring layer of a higher layer relatively sparse. Further, an electrode of a capacitor element included in the pixel circuit is formed in a wiring layer in which any one of the two types of wirings is provided. That is, since the electrode of the capacitor element can be provided in the wiring layer having the relatively sparse wiring pattern, it is possible to improve the degree of freedom of arrangement of the electrode and sufficiently secure the area of the electrode. Thus, it is possible to solve the problem caused by the relatively dense wiring pattern, the problem caused by the area of the electrode of the capacitor element not being able to be sufficiently secured, and the like. Thus, it is possible to realize a display device having higher reliability.

[0017] Advantages of the Invention

[0018] As described above, according to the present disclosure, it is possible to further improve the reliability. Note that the above effects are not necessarily restrictive. Any of the effects described in this specification or other effects that can be grasped from this specification can be achieved with the above effects or instead of the above effects. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic view showing the overall configuration of a display device according to the present embodiment.

[0020] Figure 2 is a schematic view showing the configuration of the pixel unit, the scan unit, and the selection unit shown in Figure 1 is a schematic view showing the configuration of the pixel unit, the scan unit, and the selection unit shown in

[0021] Figure 3 is a schematic view showing a configuration example of the pixel circuit shown in Figure 2 is a schematic view showing a configuration example of the pixel circuit shown in

[0022] Figure 4 is a diagram for describing the operation of the pixel circuit according to the present embodiment.

[0023] Figure 5 is a diagram showing another configuration example of the pixel circuit according to the present embodiment.

[0024] Figure 6 is a cross-sectional view showing a stacked structure of the pixel circuit.

[0025] Figure 7 is a diagram for describing an example of the layout of the wiring layer according to the present embodiment.

[0026] Figure 8 is a diagram for comparing the layout shown in Figure 7 , and is a diagram showing an example of the layout in the case where the H scan line and the V signal line are formed in the wiring layer, which is different from the case where the H scan line and the V signal line are formed in the first wiring layer and the second wiring layer in the present embodiment.

[0027] Figure 9 is a diagram for describing another example of the layout of the wiring layer according to the present embodiment.

[0028] Figure 10 is a diagram for comparing the layout shown in Figure 9 , and is a diagram showing an example of the layout in the case where the H scan line and the V signal line are formed in the wiring layer, which is different from the case where the H scan line and the V signal line are formed in the first wiring layer, the second wiring layer, and the third wiring layer in the present embodiment.

[0029] Figure 11 is a diagram showing an example of arranging the third via hole in the three sub-pixels in the case where one pixel is formed in the three sub-pixels.

[0030] Figure 12 is a diagram showing an example of arranging the third via hole in the four sub-pixels in the case where one pixel is formed in the four sub-pixels.

[0031] Figure 13 is a cross-sectional view showing a specific configuration example of the display device according to the present embodiment.

[0032] Figure 14 is a diagram showing the appearance of a smartphone, which is an example of an electronic device in which the display device according to the present embodiment can be used.

[0033] Figure 15 is a diagram showing the appearance of a digital camera, which is another example of an electronic device in which the display device according to the present embodiment can be used.

[0034] Figure 16 FIG. 1A is a diagram illustrating an appearance of a digital camera which is another example of an electronic device that can use the display device according to the present embodiment.

[0035] Figure 17 FIG. 1B is a diagram illustrating an appearance of a head-mounted display which is another example of an electronic device that can use the display device according to the present embodiment. DETAILED DESCRIPTION

[0036] Hereinafter, a preferred embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Note that, in this specification and the accompanying drawings, structural elements having substantially the same function and structure are denoted with the same reference numerals, and repeated explanation is omitted.

[0037] Note that, in the drawings, the size and the like of some layers and some regions in a cross-sectional view of a layout and in a top view can be exaggerated for the purpose of explanation. The relative sizes of the layers, regions, and the like shown in the drawings are not necessarily precise.

[0038] Further, hereinafter, an embodiment in which the display device is an organic EL display device will be described as an example of the present disclosure. However, the present disclosure is not limited to this example, and the display device that is the object of the present disclosure can be various display devices as long as they are display devices that can be driven by an active matrix type drive system.

[0039] Note that, the order of explanation is as follows.

[0040] 1. Overall configuration of display device

[0041] 2. Pixel circuit configuration

[0042] 3. Operation of pixel circuit

[0043] 4. Layout of wiring layer

[0044] 5. Specific configuration example of display device

[0045] 6. Application example

[0046] 7. Supplement

[0047] (1. Overall configuration of display device)

[0048] The overall configuration of the display device according to the embodiment of the present disclosure will now be described with reference to Figure 1 and Figure 2 Figure 1 FIG. 1 is a schematic diagram illustrating the overall configuration of the display device according to the present embodiment. Figure 2 FIG. 2 is a more detailed diagram illustrating Figure 1 ​A schematic view of the configuration of the pixel unit, the scanning unit, and the selection unit shown.

[0049] Referring to Figure 1 In the display device 1 according to the present embodiment, the pixel unit 20, the scanning unit 30, and the selection unit 40 are arranged on the display panel 10. As Figure 2 shown, in the pixel unit 20, a plurality of pixel circuits 210 are arranged in a matrix form. Note that, although written as the pixel circuit 210 for convenience, the pixel circuit 210 includes a wiring layer of the pixel circuit 210 and a portion other than the wiring layer. Figure 2 The "pixel circuit 210" shown in FIG. 1A shows a portion other than the wiring layer of the pixel circuit 210; in fact, in the pixel circuit 210, a wiring (a wiring extending from the scanning unit 30 and the selection unit 40, a power supply line 332, and the like, which are described later) can be connected to the "pixel circuit 210" shown in FIG. 1A. That is, these wirings can be commonly provided for a plurality of pixel circuits 210, but they can also be a part of the pixel circuit 210; therefore, in the present specification, a portion other than the wiring layer of the pixel circuit 210 is shown as the pixel circuit 210 for convenience. In the present specification, in the case written as the "pixel circuit 210", for convenience, therefore the component can refer to only a portion other than the wiring layer of the pixel circuit 210. Figure 2 Figure 2 The "pixel circuit 210" shown in FIG. 1A shows a portion other than the wiring layer of the pixel circuit 210; in fact, in the pixel circuit 210, a wiring (a wiring extending from the scanning unit 30 and the selection unit 40, a power supply line 332, and the like, which are described later) can be connected to the "pixel circuit 210" shown in FIG. 1A. That is, these wirings can be commonly provided for a plurality of pixel circuits 210, but they can also be a part of the pixel circuit 210; therefore, in the present specification, a portion other than the wiring layer of the pixel circuit 210 is shown as the pixel circuit 210 for convenience. In the present specification, in the case written as the "pixel circuit 210", for convenience, therefore the component can refer to only a portion other than the wiring layer of the pixel circuit 210.

[0050] One pixel circuit 210 corresponds to one sub-pixel. Here, the display device 1 is a display device capable of color display, and one pixel serving as a unit of forming a color image includes a plurality of sub-pixels. Specifically, one pixel includes three sub-pixels of a sub-pixel that emits red light, a sub-pixel that emits green light, and a sub-pixel that emits blue light. In Figure 2 In each pixel circuit 210, a color (R, G, or B) corresponding to each sub-pixel is written analogically. The emission in each pixel circuit 210 (i.e., each sub-pixel) is controlled as appropriate, thereby displaying a desired image in the pixel unit 20. Therefore, the pixel unit 20 corresponds to a display surface in the display device 1.

[0051] ​However, in this embodiment, the combination of subpixels included in a pixel is not limited to the combination of subpixels of the three primary colors of RGB. For example, in a pixel, subpixels of one or more colors can be further added to the subpixels of the three primary colors. Specifically, for example, in a pixel, a subpixel emitting white light can be added to the subpixels of the three primary colors to improve brightness; or in a pixel, at least one subpixel emitting complementary color light can be added to the subpixels of the three primary colors to expand the color reproduction range. Alternatively, in the display device 1, subpixels may not exist, and one pixel circuit 210 may correspond to one pixel. Furthermore, alternatively, the display device 1 may not be a display device capable of color display, and may be a display device performing monochrome display.

[0052] The scanning unit 30 is placed on one side of the pixel unit 20 in the horizontal direction. Multiple wirings arranged vertically extend horizontally from the scanning unit 30 toward the pixel unit 20. Specifically, as... Figure 2 As shown, the scanning unit 30 includes a write scanning unit 301, a first driving scanning unit 311, and a second driving scanning unit 321. Multiple write scan lines 302 extend from the write scanning unit 301 toward respective rows of the pixel circuits 210, multiple first driving lines 312 extend from the first driving scanning unit 311 toward respective rows of the pixel circuits 210, and multiple second driving lines 322 extend from the second driving scanning unit 321 toward corresponding rows of the pixel circuits 210. Each of the multiple wirings (write scan lines 302, first driving lines 312, and second driving lines 322) is connected to a respective pixel circuit 210. The write scanning unit 301, the first driving scanning unit 311, and the second driving scanning unit 321 appropriately change the potential of these multiple wirings, thereby controlling the operation of each pixel circuit 210 so that the desired image can be displayed across the entire display surface. See below. Figure 3 The document describes the details of the connection state between the write scan line 302, the first drive line 312, the second drive line 322 and the pixel circuit 210, as well as the functions of the write scan unit 301, the first drive scan unit 311 and the second drive scan unit 321.

[0053] The selection unit 40 is placed on one side of the pixel unit 20 in the vertical direction. Multiple wirings arranged horizontally extend vertically from the selection unit 40 toward the pixel unit 20. Specifically, as... Figure 2As shown, selection unit 40 includes signal output unit 401. Multiple signal lines 402 extend from signal output unit 401 toward respective columns of pixel circuits 210. Each of the multiple signal lines 402 is connected to a respective pixel circuit 210 in pixel unit 20. Signal output unit 401 appropriately changes the potential of the multiple signal lines 402, thereby controlling the operation of each pixel circuit 210 so that the desired image can be displayed across the entire display surface. (See below for further details.) Figure 3 Details describe the connection state between signal line 402 and pixel circuit 210, as well as the function of signal output unit 401.

[0054] Therefore, wiring extending horizontally from the scanning unit 30 is configured to correspond to the rows of the pixel circuits 210 arranged in a matrix, and the wiring is connected to each pixel circuit 210. Furthermore, wiring extending vertically from the selection unit 40 is configured to correspond to the columns of the pixel circuits 210 arranged in a matrix, and is connected to the corresponding pixel circuits 210. Then, by appropriately changing the potential of the plurality of wirings through the scanning unit 30 and the selection unit 40, the operation of each pixel circuit 210 of the pixel unit 20 is controlled.

[0055] (2. Pixel Circuit Configuration) Now refer to Figure 3 describe Figure 2 The configuration of the pixel circuit 210 shown. Figure 3 It is shown Figure 2 A schematic diagram of the configuration of the pixel circuit 210 is shown. Figure 3 It shows Figure 2 The circuit configuration of one of the multiple pixel circuits 210 shown is illustrated, and the connection state of the pixel circuit 210 for writing scan line 302, first drive line 312, second drive line 322 and signal line 402 is shown.

[0056] like Figure 3 As shown, pixel circuit 210 includes an organic light-emitting diode (OLED) 211 as a light-emitting element and a driving circuit that drives the OLED 211 by passing current through it. The driving circuit includes four transistors: an active element (driving transistor 212, sampling transistor 213, light-emitting control transistor 214, and switching transistor 217) and a capacitive element (holding capacitor 215 and auxiliary capacitor 216). In pixel circuit 210, wiring (the aforementioned write scan line 302, first driving line 312, second driving line 322, and signal line 402, power line 332, etc., described later) connects to these elements.

[0057] Note that an organic light-emitting diode 211 having a general structure can be used. Further, each of the drive transistor 212, the sampling transistor 213, the light-emitting control transistor 214, and the switching transistor 217 is a P-channel four-terminal (source / gate / drain / back gate) transistor formed over a semiconductor such as silicon (Si), and the structure can be similar to that of a general P-channel four-terminal transistor. Thus, detailed description of the structures of the organic light-emitting diode 211, the drive transistor 212, the sampling transistor 213, the light-emitting control transistor 214, and the switching transistor 217 is omitted here.

[0058] The cathode of the organic light-emitting diode 211 is connected to a common power supply line 331 (potential: V CATH ), which is commonly provided for all pixel circuits 210 of the pixel unit 20. The drain of the drive transistor 212 is connected to the anode of the organic light-emitting diode 211.

[0059] The drain of the light-emitting control transistor 214 is connected to the source of the drive transistor 212, and the source of the light-emitting control transistor 214 is connected to a power supply line 332 (potential: V cc ; V cc is a power supply potential). Further, the gate of the drive transistor 212 is connected to the drain of the sampling transistor 213, and the source of the sampling transistor 213 is connected to a signal line 402.

[0060] Thus, by bringing the sampling transistor 213 into an on state, a potential corresponding to the potential of the signal line 402 is applied to the gate electrode of the drive transistor 212 (the potential of the signal line 402 is written), and the drive transistor 212 is brought into an on state. Further, in this case, by bringing the light-emitting control transistor 214 into an on state, a potential corresponding to the signal potential V cc is applied to the source of the drive transistor 212, and a drain-source current I ds is generated in the drive transistor 212; thus, the organic light-emitting diode 211 is driven. In this case, the magnitude of the drain-source current I ds varies depending on the gate potential V g of the drive transistor 212, and thus, the luminance of the organic light-emitting diode 211 is controlled in accordance with the gate potential V g of the drive transistor 212, i.e., the potential of the signal line 402 written by the sampling transistor 213.

[0061] Thus, the drive transistor 212 has a function of causing the organic light-emitting diode 211 to be driven by the drain-source current I dsThe sampling transistor 213 controls the gate voltage of the driving transistor 212 based on the potential of the signal line 402, i.e., controls the on / off state of the driving transistor 212; therefore, the sampling transistor 213 has the function of writing the potential of the signal line 402 onto the pixel circuit 210 (i.e., it has the function of sampling the pixel circuit 210 to write the potential of the signal line 402 onto it). Furthermore, the light-emitting control transistor 214 controls the potential of the source of the driving transistor 212, thereby controlling the drain-source current I of the driving transistor 212. ds Therefore, the light-emitting control transistor 214 has the function of controlling the light-emitting / non-light-emitting of the organic light-emitting diode 211.

[0062] Holding capacitor 215 is connected between the gate of driving transistor 212 (i.e., the drain of sampling transistor 213) and the source of driving transistor 212. In other words, holding capacitor 215 maintains the gate-source voltage V of driving transistor 212. gs An auxiliary capacitor 216 is connected between the source of the driving transistor 212 and the power supply line 332. The auxiliary capacitor 216 has the function of suppressing the source potential change of the driving transistor 212 when writing the potential of the signal line 402.

[0063] The signal output unit 401 appropriately controls the potential (signal line voltage Date) of the signal line 402, thereby writing the potential of the signal line 402 into the pixel circuit 210 (specifically, as described above, writing the potential of the signal line 402 into the pixel circuit 210 selected by the sampling transistor 213). In this embodiment, the signal output unit 401 selectively outputs a signal voltage V corresponding to the video signal via the signal line 402. sig First reference voltage V ref Second reference voltage V ofs Here, the first reference voltage V ref This is the reference voltage used to reliably extinguish the organic light-emitting diode 211. Additionally, the second reference voltage V... ofs It is the signal voltage V used to correspond to the video signal. sig The reference voltage (e.g., equal to the black level of the video signal) is used, and a second reference voltage V is used when performing the threshold correction operation described later. ofs .

[0064] The write scan line 302 is connected to the gate electrode of the sampling transistor 213. The write scan unit 301 controls the on / off state of the sampling transistor 213 by changing the potential of the write scan line 302 (scan line voltage WS), and performs the operation of changing the potential of the aforementioned signal line 402 (e.g., the signal voltage V corresponding to the video signal) on the pixel circuit 210. sig The writing process. In fact, as shown in the reference...Figure 2 The plurality of write scan lines 302 extend to each row of the plurality of pixel circuits 210 arranged in a matrix form. When the potential of the signal line 402 is written on each pixel circuit 210, the write scan unit 301 sequentially supplies the scan line voltage WS of a predetermined value to the plurality of write scan lines 302, thereby scanning the pixel circuits 210 row by row.

[0065] Note that, similarly to the signal line 402, actually, the plurality of signal lines 402 extend to each column of the plurality of pixel circuits 210 arranged in a matrix form, as described with reference to Figure 2 The signal voltage V sig corresponding to the video signal, which is alternately output from the signal output unit 401, the first reference voltage V ref , and the second reference voltage V ofs are written to the pixel circuit 210 in units of pixels selected by the scan of the write scan unit 301 via the plurality of signal lines 402. That is, the signal output unit 401 writes the potential of the signal line 402 in rows.

[0066] The first drive line 312 is connected to the gate electrode of the light emission control transistor 214. The first drive scan unit 311 controls the on / off of the light emission control transistor 214 by changing the potential (first drive line voltage DS) of the first drive line 312, and performs a process of controlling the light emission / non-emission of the organic light emitting diode 211 described above. Actually, as described with reference to Figure 2 The plurality of first drive lines 312 extend to each row of the plurality of pixel circuits 210 arranged in a matrix form. In synchronization with the scan of the write scan unit 301, the first drive scan unit 311 sequentially supplies the first drive line voltage DS of a prescribed value to the plurality of first drive lines 312, thereby appropriately controlling the light emission / non-emission of each pixel circuit 210.

[0067] Here, in the pixel circuit 210, in addition, the source of the switch transistor 217 is connected to the anode of the organic light emitting diode 211. The drain electrode of the switch transistor 217 is connected to the ground line 333 (potential: V SS ; V SS is a ground potential). The current flowing through the drive transistor 212 during the non-emission period of the organic light emitting diode 211 flows through the ground line 333 through the current path formed by the switch transistor 217.

[0068] Here, as described later, when the pixel circuit 210 is driven according to the present embodiment, a threshold correction operation of correcting the threshold voltage V th of the drive transistor 212 is performed, and further, a threshold correction preparation operation is performed as a preceding stage of performing the threshold correction operation. In the threshold correction preparation operation, initialization of the gate potential Vg and the source potential V s of the operation, and thus the gate-source voltage V gs of the drive transistor 212 becomes greater than the threshold voltage V th of the drive transistor 212. This is because, if the gate-source voltage V gs of the drive transistor 212 is not set to be greater than the threshold voltage V th of the drive transistor 212, the threshold correction operation cannot be properly performed.

[0069] Therefore, if the operation of setting the gate potential V g and the source potential V s of the above-described drive transistor 212 is performed, the case where the anode potential V ano of the organic light emitting diode 211 exceeds the threshold voltage V thel of the organic light emitting diode 211 can occur, although the organic light emitting diode 211 is in a non-light emitting period. Therefore, current flows from the drive transistor 212 into the organic light emitting diode 211, and the phenomenon where the organic light emitting diode 211 emits light occurs, although in a non-light emitting period.

[0070] Therefore, in the present embodiment, the current circuit using the above-described switching transistor 217 is provided to prevent such a phenomenon. By this, current from the above-described drive transistor 212 does not flow into the organic light emitting diode 211, but flows into the current circuit, and unintended emission of the organic light emitting diode 211 can be prevented.

[0071] The second drive line 322 is connected to the gate electrode of the switching transistor 217. The second drive scanning unit 321 controls the on / off of the switching transistor 217 by changing the potential (second drive line voltage AZ) of the second drive line 322. Specifically, the second drive scanning unit 321 appropriately changes the second drive line voltage AZ, thereby setting the switching transistor 217 to the on state and opening the above-described current circuit during the light emission receiving period, more specifically, at least during the period where the gate-source voltage V gs of the drive transistor 212 is set to be greater than the threshold voltage V th of the drive transistor 212 by performing the threshold correction preparation operation. In practice, as described with reference to Figure 2 , a plurality of second drive lines 322 extend to each row of the plurality of pixel circuits 210 arranged in a matrix form. The second drive scanning unit 321 sequentially supplies the second drive line voltage AZ of a predetermined value to the plurality of second drive lines 322 in synchronization with the scanning of the writing scanning unit 301, and thereby appropriately controls the drive of the switching transistor 217 so that the switching transistor 217 is in the on state during the above-described period.

[0072] Note that the writing scan unit 301, the first drive scan unit 311, the second drive scan unit 321, and the signal output unit 401 can be obtained using known technology by various circuits capable of realizing the above-described functions, such as a shift register circuit, and thus a detailed circuit configuration of these parts is omitted here.

[0073] In the above, the configuration of the pixel circuit 210 according to the present embodiment is described.

[0074] (3. Operation of the pixel circuit) The operation of the pixel circuit 210 described above will now be described. Figure 4 is a diagram for describing the operation of the pixel circuit 210 according to the present embodiment. Figure 4 A timing waveform diagram of signals related to the operation of the pixel circuit 210 is shown. Specifically, Figure 4 the potential of the signal line 402 (signal line voltage Date), the potential of the writing scan line 302 (scan line voltage WS), the potential of the first drive line 312 (first drive line voltage DS), the potential of the second drive line 322 (second drive line voltage AZ), the source potential V s of the drive transistor 212, and the gate potential V g of the drive transistor 212 in one horizontal period (one H period) are shown.

[0075] Note that since each of the sampling transistor 213, the light emission control transistor 214, and the switching transistor 217 is of the P-channel type, these transistors are in the on state, i.e., the on state when the scan line voltage WS, the first drive line voltage DS, and the second drive line voltage AZ are in the low potential state, and these transistors are in the off state, i.e., the non-conductive state when the scan line voltage WS, the first drive line voltage DS, and the second drive line voltage AZ are in the high potential state, respectively. Similarly for the drive transistor 212, the drive transistor 212 is in the on state when the gate potential V g is the low potential, and the drive transistor 212 is in the off state when the gate potential V g is the high potential. Further, as described above, any one of the signal voltage V sig corresponding to the video signal, the first reference voltage V ref , and the second reference voltage V ofs is optionally selected for the signal line voltage Date. As an example, in the waveform diagram shown in Figure 4 V ref = V cc (power supply potential).

[0076] At the end of the light emission period of the organic light emitting diode 211, the scan line voltage WS is shifted from the high potential to the low potential, and the sampling transistor 213 enters the on state (time tl). On the other hand, at the time tl, the signal line voltage Date is in a state controlled to the first reference voltage V ref . Thus, by the shift of the scan line voltage WS from the high potential to the low potential, the gate-source voltage V gs of the drive transistor 212 becomes smaller than or equal to the threshold voltage V th of the drive transistor 212, so that the drive transistor 212 is turned off. If the drive transistor 212 is turned off, the path for supplying the current to the organic light emitting diode 211 is cut off, so that the anode potential V ano of the organic light emitting diode 211 is gradually reduced. With the passage of time, if the anode potential V ano becomes smaller than or equal to the threshold voltage V thel of the organic light emitting diode 211, the organic light emitting diode 211 completely enters the light extinction state (time tl to time t2 period; light extinction period).

[0077] After the light extinction period, a period (time t2 to time t3 period; threshold value correction preparation period) in which a preparation operation (threshold value correction preparation operation) to be performed before the threshold value correction operation to be described later is performed is provided. At the time t2, that is, at the timing at which the threshold value correction preparation period starts, the scan line voltage WS is shifted from the high potential to the low potential, so that the sampling transistor 213 enters the on state. On the other hand, at the time t2, the signal line voltage Date is in a state controlled to the second reference voltage V ofs . By the sampling transistor 213 entering the on state in the state in which the signal line voltage Date is the second reference voltage V ofs , the gate potential V g of the drive transistor 212 becomes the second reference voltage V ofs .

[0078] Further, at the time t2, the first drive line voltage DS is in the low potential state, and the light emission control transistor 214 is set to the on state. Thus, the source potential V s of the drive transistor 212 is the power supply voltage V cc . In this case, the gate-source voltage V gs of the drive transistor 212 is V gs = V ofs - V cc .

[0079] Here, in order to perform the threshold value correction operation, it is necessary to set the gate-source voltage V gs of the drive transistor 212 to be larger than the threshold voltage V th of the drive transistor 212.. Thus, each voltage value is set to |V g | = |V ofs cc | > |V th .

[0080] Thus, the gate potential V g of the drive transistor 212 is set to the second reference voltage V ofs and the source potential V s of the drive transistor 212 is set to the power supply voltage V cc The initialization operation is a threshold value correction preparation operation. That is, the second reference voltage V ofs and the power supply voltage V cc are initialization voltages of the gate potential V g and the source potential V s of the drive transistor 212, respectively.

[0081] If the threshold value correction preparation period ends, then a threshold value correction operation of correcting the threshold voltage V th of the drive transistor 212 is performed next (time t3 to time t4 period; threshold value correction period). In the period in which the threshold value correction operation is performed, first, at time t3 which is the timing at which the threshold value correction period starts, the first drive line voltage DS is transitioned from a low potential to a high potential, and the light emission control transistor 214 enters a non-conducting state. Thereby, the source potential V s of the drive transistor 212 enters a floating state. On the other hand, at time t3, the scan line voltage WS is in a state in which it is controlled to be a high potential, and the sampling transistor 213 is in a non-conducting state. Thus, at time t3, the gate potential V g of the drive transistor 212 is also in a floating state, and the source electrode and the gate electrode of the drive transistor 212 enter a state in which they are connected together via the holding capacitor 215, in a state in which they are floating from each other. Thereby, as shown in the figure, the source potential V s and the gate potential V g of the drive transistor 212 gradually change to a prescribed value in accordance with the threshold voltage V th of the drive transistor 212.

[0082] Thus, using the initialization voltage V g of the gate potential V ofs of the drive transistor 212 and the initialization voltage V cc of the drive transistor 212 and the source potential V s as a reference, the source potential V th and the gate potential V s of the drive transistor 212 are changed in accordance with the threshold voltage V g of the drive transistor 212 in a floating state.The operation that changes the value to a specified value is a threshold correction operation. If the threshold correction operation is performed, the gate-source voltage V of the driving transistor 212 is... gs It stabilizes over time at the threshold voltage V of the driving transistor 212. th Equal to the threshold voltage V th The voltage is maintained in the holding capacitor 215.

[0083] Here, of course, there exists a threshold voltage V for driving transistor 212. th The design value; however, due to manufacturing variations, etc., the actual threshold voltage V th It does not always match the design value. In this regard, by performing a threshold correction operation similar to that described above, the actual threshold voltage V can be adjusted before the organic light-emitting diode 211 emits light. th An equal voltage is maintained in holding capacitor 215. Therefore, thereafter, when driving transistor 212 is driven to make organic light-emitting diode 211 emit light, the threshold voltage V of driving transistor 212 can be eliminated. th The changes are as follows. Therefore, the driving of the driving transistor 212 can be controlled more precisely, and the desired brightness can be obtained more advantageously.

[0084] If the threshold correction period ends, then the signal voltage V corresponding to the video signal is written. sig The signal writing operation (time period t4 to t5: signal writing period). During the signal writing period, at time t4, which marks the beginning of the signal writing period, the scan line voltage WS changes from a high potential to a low potential, and the sampling transistor 213 turns on. On the other hand, at time t4, the signal line voltage Date is controlled to the signal voltage V according to the video signal. sig The state, therefore, is based on the signal voltage V of the video signal. sig The holding capacitor 215 is written. When the signal voltage V corresponding to the video signal is written... sig At this time, the auxiliary capacitor 216 connected between the source of the driving transistor 212 and the power supply line 332 suppresses the source potential V of the driving transistor 212. s The effect of changes. Then, the signal voltage V of the video signal is written. sig At that time, that is, when the signal voltage V of the video signal is... sig When the gate electrode of the driving transistor 212 is applied and the driving transistor 212 is driven, as a result of the threshold correction operation, the threshold voltage V of the driving transistor 212... th The threshold voltage V held by capacitor 215 is equal to the threshold voltage V held by capacitor 215. th The voltage cancellation. In other words, by performing the above threshold correction operation, the threshold voltage V of the driving transistor 212 between pixel circuits 210 is eliminated.th of the change.

[0085] At time t5, the scan line voltage WS is transitioned from the low potential to the high potential, and the sampling transistor 213 enters the non-conductive state; thus, the signal write period ends. If the signal write period ends, then, the light emission period starts from time t6. At time t6, which is the timing at which the light emission period starts, the first drive line voltage DS is transitioned from the high potential to the low potential, thereby causing the light emission control transistor 214 to enter the conductive state. Thus, a current is supplied from the power supply line 332 having the power supply voltage VDD via the light emission control transistor 214 to the source of the drive transistor 212. cc

[0086] In this case, since the sampling transistor 213 is in the non-conductive state, the gate electrode of the drive transistor 212 is electrically separated from the signal line 402, and is in the floating state. When the gate electrode of the drive transistor 212 is in the floating state, the sustain capacitor 215 is connected between the gate and the source of the drive transistor 212, so that the gate potential V g varies in accordance with the change in the source potential V s of the drive transistor 212. That is, the source potential V s and the gate potential V g of the drive transistor 212 rise while the gate-source voltage V gs retained in the sustain capacitor 215 is maintained. Then, the source potential V s of the drive transistor 212 rises to the light emission voltage V oled of the organic light emitting diode 211 in accordance with the saturation current of the transistor.

[0087] The gate potential V g of the drive transistor 212 varies in this manner along with the change in the source potential V s . This operation is referred to as a bootstrap operation. In other words, the bootstrap operation is an operation in which the gate potential V g and the source potential V s of the drive transistor 212 vary while the gate-source voltage V gs retained in the sustain capacitor 215 (i.e., the voltage across the sustain capacitor 215) is maintained.

[0088] Then, the drain-source current I ds of the drive transistor 212 starts to flow through the organic light emitting diode 211, so that the anode potential V ano of the organic light emitting diode 211 rises in accordance with the drain-source current I ds . Over time, if the anode potential V ano of the organic light emitting diode 211 exceeds the threshold voltage V​thel Then, the drive current starts to flow through the organic light emitting diode 211, and the organic light emitting diode 211 starts to emit light.

[0089] The above operation is performed in each pixel circuit 210 for one H period. Note that, as described above, the switching transistor 217 is a switching transistor for preventing unintended emission of light of the organic light emitting diode 211 due to the current flowing from the drive transistor 212 to the organic light emitting diode 211 in a non-emission period; thus, the second drive line voltage AZ is appropriately controlled so that the switching transistor 217 is in an on state in the non-emission period. In the illustrated example, the second drive line voltage AZ is transitioned from the high potential to the low potential at the time t1 at which the emission period ends; and the second drive line voltage AZ is transitioned from the low potential to the high potential immediately before the time t6 at which the next emission period ends or starts.

[0090] Note that, regarding the overall configuration of the display device 1, the configuration of the pixel circuit 210, and the operation of the pixel circuit 210 according to the above-described embodiment, reference can be made to the prior application of the present applicant, WO 2014 / 103500, except for aspects described later in (4. Layout of wiring layer). In other words, the overall configuration of the display device 1, the configuration of the pixel circuit 210, and the operation of the pixel circuit 210 according to the embodiment can be similar to those described in WO 2014 / 103500, except for aspects described later in (4. Layout of wiring layer). However, the above description is merely one example, and the present embodiment is not limited to this example. The aspects described in (4. Layout of wiring layer) below are sufficient to be reflected in the display device 1 according to the present embodiment, and various known configurations used in ordinary display devices can be used for other aspects.

[0091] For example, in the above-described configuration example, the pixel circuit 210 includes four transistors, but the configuration of the pixel circuit 210 is not limited to such an example. Figure 5 Another configuration example of the pixel circuit applicable to the display device 1 is shown in FIG. 18. Figure 5 is a schematic view showing another configuration example of the pixel circuit according to the present embodiment.

[0092] Referring to Figure 5 The pixel circuit 220 includes the organic light emitting diode 221, five transistors 222, 223, 224, 225, and 226, and one holding capacitor 227. The configuration and operation of the pixel circuit 220 are the same as those of a general pixel circuit including five transistors, and thus detailed description thereof will be omitted here. In this way, in the present embodiment, various known configurations can be applied as the configuration of the pixel circuit.

[0093] (4. Layout of wiring layers) Each of the pixel circuits 210 and 220 is configured by stacking a plurality of wiring layers (metal layers) in which wirings are formed in upper layers of a diffusion layer in which transistors are formed, and further forming the organic light emitting diode 211 in an upper layer thereof. The layout of the wiring layers in each of the pixel circuits 210 and 220 will be described. Here, as an example, the layout of the wiring layers in the pixel circuit 220 shown in FIG. 2B will be described. Figure 5 The layout of the wiring layers in the pixel circuit 220 shown in FIG. 2B.

[0094] Note that, although detailed description is omitted above, wirings extending in the horizontal direction are also connected to the gate electrodes of each of the transistors (transistors 222, 223, 225, and 226 in the Figure 5 configuration example shown in FIG. 2B) in the pixel circuit 220, similarly to the pixel circuit 210. Although Figure 5 only one pixel circuit 220 is shown, these wirings are actually provided in respective rows of a plurality of pixel circuits 220 arranged in a matrix. In the following description, the wirings extending in the horizontal direction in response to respective rows of the plurality of pixel circuits 220 are also referred to as h-scan lines. As Figure 5 shown in FIG. 2B, there are four H-scan lines 228 (in Figure 5 which the actual shapes in the wiring layers are imitated) in one pixel circuit 220.

[0095] Further, similarly to the pixel circuit 210, in the pixel circuit 220 as well, wirings (signal lines) extending in the vertical direction for supplying a signal voltage corresponding to a video signal and the like are connected. Although only one pixel circuit 220 is shown in Figure 5 , wirings are actually provided for respective columns of a plurality of pixel circuits 220 arranged in a matrix. In the following description, the wirings extending in the vertical direction in response to respective columns of the plurality of pixel circuits 220 are also referred to as v-signal lines. As Figure 5 shown in FIG. 2B, there is one V-signal line 229 (in Figure 5 which the actual shapes in the wiring layers are imitated) in one pixel circuit 220.

[0096] First, the stack structure of the pixel circuit 220 will be described with reference to Figure 6 FIG. 3A. Figure 6 is a cross-sectional schematic view showing the stack structure of the pixel circuit 220. In Figure 6 FIG. 3B, the stack structure of the pixel circuit 220 from the diffusion layer to the anode of the organic light emitting diode 221 is schematically shown.

[0097] Referring to Figure 6The pixel circuit 220 is configured with a plurality of wiring layers 234, 237, and 240 formed in an upper layer of the diffusion layer 231. In the diffusion layer 231, transistors (transistors 222 to 226) are formed by forming, for example, a semiconductor substrate, active regions serving as source regions, drain regions, and channel regions, a gate insulating film, a gate electrode, and the like. Note that, in Figure 6 , for convenience, elements such as transistors formed in the diffusion layer are not illustrated.

[0098] An insulating layer 232 (hereinafter referred to as a first insulating layer 232) is stacked on the diffusion layer 231. The first insulating layer 232 is formed by stacking an insulator such as silicon oxide (SiO2) to a prescribed thickness (the same applies to a second insulating layer 235, a third insulating layer 238, and a fourth insulating layer 241 to be described later).

[0099] In the first insulating layer 232, a contact 233 that electrically connects a region of the wiring layer in the upper layer of each electrode (source electrode, drain electrode, gate electrode), and the like of each transistor of the diffusion layer 231 to a wiring formed in the first wiring layer 234 to be described later in the upper layer is formed at a position corresponding to the region. The contact 233 is formed by forming a through-hole (contact hole) in the first insulating layer 232, and then embedding a conductor such as tungsten (W) in the through-hole.

[0100] The wiring layer 234 (hereinafter referred to as the first wiring layer 234) is formed on the first insulating layer 232 in which the contact 233 is formed. The first wiring layer 234 is formed by stacking a conductor such as aluminum (Al) to a prescribed thickness, and then patterning the conductor film into a prescribed shape (the same applies to the second wiring layer 237 and the third wiring layer 240 to be described later). In the first wiring layer 234, the second wiring layer 237, and / or the third wiring layer 240, wirings (various wirings including the H scan line 228 and the V signal line 229) shown in FIG. 2 are formed. Figure 5

[0101] The insulating layer 235 (hereinafter referred to as the second insulating layer 235) is formed on the first wiring layer 234. In the second insulating layer 235, a through-hole 236 (hereinafter referred to as a first through-hole 236) for electrically connecting a corresponding wiring formed in the first wiring layer 234 of the lower layer and a corresponding wiring formed in the second wiring layer 237 to be described later of the upper layer to each other is formed. The first through-hole 236 is formed by forming a through-hole (through-hole) in the second insulating layer 235, and then embedding a conductor such as W in the through-hole (the same applies to a second through-hole 239 and a third through-hole 242 to be described later).

[0102] ​A wiring layer 237 (hereinafter referred to as the second wiring layer 237) is formed on a second insulating layer 235 in which the first through-hole 236 is formed. An insulating layer 238 (hereinafter referred to as the third insulating layer 238) is formed on the second wiring layer 237. A through-hole 239 (hereinafter referred to as the second through-hole 239) is formed in the third insulating layer 238, which is used to electrically connect the corresponding wiring formed in the lower second wiring layer 237 and the upper third wiring layer 240, which will be described later, to each other.

[0103] A wiring layer 240 (hereinafter referred to as the third wiring layer 240) is formed on the third insulating layer 238, in which the second through-hole 239 is formed. An insulating layer 241 (hereinafter referred to as the fourth insulating layer 241) is formed on the third wiring layer 240. A through-hole 242 (hereinafter referred to as the third through-hole 242) is formed in the fourth insulating layer 241, which is used to electrically connect the corresponding wiring formed in the lower third wiring layer 240 and the corresponding wiring formed in the upper anode 243, which will be described later, to each other.

[0104] The pixel circuit 210 is fabricated by forming an organic light-emitting diode 211 on a fourth insulating layer 241 in which a third through-hole 242 is formed. Although Figure 6 Only the anode 243 of the organic light-emitting diode 211 is shown, but the organic light-emitting diode 211 is formed by sequentially stacking an organic layer and a cathode, which serves as the light-emitting layer, on the anode 243.

[0105] Here, in this embodiment, capacitor elements are formed in the second wiring layer 237 and the third wiring layer 240. Figure 5 (The capacitor 227 is shown). Specifically, the lower electrode of the capacitor element (lower electrode 251) is formed in the second wiring layer 237. The upper electrode of the capacitor element (upper electrode 252) is formed in the upper layer of the second wiring layer 237 by an insulator having a thickness corresponding to the capacitance of the capacitor element. The upper electrode 252 is disposed inside the third insulating layer 238. That is, although the description is omitted above, the third insulating layer 238 is actually stacked in two levels with the upper electrode 252 as the boundary. After the second wiring layer 237 is formed, an insulator having a thickness corresponding to the capacitance of the capacitor element is stacked, and the upper electrode 252 is formed on the insulator by the same method as the wiring layer. Thereafter, the third insulating layer 238 is formed by further stacking an insulator having a predetermined thickness.

[0106] In the third insulating layer 238, a second via hole 239 is also provided at a position corresponding to the capacitor upper electrode 252. Further, the capacitor upper electrode 252 is electrically connected to an electrode 254 formed in the third wiring layer 240 through the second via hole 239. Since the electrode 254 is an electrode for extracting the potential of the capacitor upper electrode 252, and is an electrode having the same potential as the capacitor upper electrode 252, the electrode 254 will also be referred to as the capacitor upper electrode 254 hereinafter.

[0107] Here, a specific layout of the wirings (i.e., the H scan line 228, the V signal line 229, and the like) and the capacitor element (i.e., the holding capacitor 227) included in the pixel circuit 210 will be examined. As described above, these wirings are formed in the first wiring layer 234, the second wiring layer 237, and / or the third wiring layer 240. Further, the capacitor lower electrode 251 and the capacitor upper electrode 254 of the capacitor element are formed in the second wiring layer 237 and the third wiring layer 240, respectively. In this way, the wirings and the capacitor lower electrode 251 and the capacitor upper electrode 254 of the capacitor element can be formed within the same wiring layer.

[0108] Here, since a reduction in the pixel size is attempted for reasons such as an improvement in the resolution of the display in the display device 1, various problems that hinder the normal operation of the pixel circuit 220 can occur. Examples of such problems include a deterioration in the luminance uniformity due to noise interference between electrodes caused by an increase in the parasitic capacitance between the wirings, a deterioration in the luminance uniformity caused by a deterioration in the noise resistance due to a stress on the area of the electrode of the capacitor element, a failure of a short circuit between the wirings caused by the wirings becoming dense, a failure of an open circuit of the wirings caused by a film skipping of a wiring pattern having a small area, and the like. Therefore, in a case where a relatively small pixel size is particularly required, it is important to design the layout of the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 so as to prevent the occurrence of these problems to the maximum extent while maintaining a small pixel size.

[0109] The present inventors conceived, through intensive studies, preferred layouts of the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 that can avoid the above problems. In the following, these preferred layouts will be described in detail with reference to the drawings.

[0110] Figure 7 is a diagram for describing an example of a layout of a wiring layer according to the present embodiment. In Figure 7 and Figure 8 to 10 , the layouts of the diffusion layer 231, the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 are schematically shown.

[0111] Note that, in Figure 7and Figure 8 to Figure 10 In the middle, the layout of the wiring layer is described, and therefore only the layout of the contact 233 with respect to the diffusion layer 231 is shown. Furthermore, the connection state between the wiring layers with respect to the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 is shown, and therefore the layout of the first via 236, the second via 239, and the third via 242 is also shown together with the layout of the wirings within the wiring layer.

[0112] Furthermore, in the later-described Figure 7 and Figure 8 to Figure 10 In the middle, the layout of the wiring layer is described, and therefore only the layout of the contact 233 with respect to the diffusion layer 231 is shown. Furthermore, the connection state between the wiring layers with respect to the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 is shown, and therefore the layout of the first via 236, the second via 239, and the third via 242 is also shown together with the layout of the wirings within the wiring layer.

[0113] Furthermore, in the later-described Figure 7 and Figure 8 to Figure 10 In the middle, the layout of the wiring layer is described, and therefore only the layout of the contact 233 with respect to the diffusion layer 231 is shown. Furthermore, the connection state between the wiring layers with respect to the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 is shown, and therefore the layout of the first via 236, the second via 239, and the third via 242 is also shown together with the layout of the wirings within the wiring layer.

[0114] Figure 7 An example of the layout in the case where the H scan line 228 and the V signal line 229 are formed in the first wiring layer 234 and the second wiring layer 237 is shown. As Figure 7 indicated in the middle, in this embodiment, the one of the H scan line 228 and the V signal line 229 that is provided in a larger number for one pixel circuit 220 is formed in the lower layer. In Figure 5In the case of the configuration example of the pixel circuit 220 shown, as described above, the number of H scan lines 228 provided for one pixel circuit 220 is greater than the number of V signal lines 229. Therefore, as shown in the drawing, in the case where the H scan lines 228 and the V signal lines 229 are formed in the first wiring layer 234 and the second wiring layer 237, the H scan lines 228 are formed in the first wiring layer 234, and the V signal lines 229 are formed in the second wiring layer 237.

[0115] In this case, as Figure 7 shown, in the first wiring layer 234, the wiring for connecting the counter electrode of the diffusion layer 231 to the anode 243 formed in the upper layer of the third wiring layer 240 (the wiring represented by a broken line in the drawing, hereinafter also referred to as the connection wiring related to the anode 243), the wiring for connecting the counter electrode of the diffusion layer 231 to the lower electrode 251 of the capacitive element formed in the second wiring layer 237 (the wiring represented by a thick solid line in the drawing, hereinafter also referred to as the connection wiring related to the capacitive element), and the wiring for connecting the counter electrode of the diffusion layer 231 to the V signal line 229 formed in the second wiring layer 237 (the wiring indicated by alternate broken lines in the drawing, hereinafter also referred to as the connection wiring related to the V signal line 229) are formed together with the H scan line 228. Further, in the second wiring layer 237, the lower electrode 251 of the capacitive element and the connection wiring related to the anode 243 are formed together with the V signal line 229. Further, in the third wiring layer 240, the upper electrode 254 of the capacitive element and the connection wiring related to the anode 243 are formed. Note that the number of each of the connection wiring related to the anode 243, the connection wiring related to the capacitive element, and the connection wiring related to the V signal line 229 formed in each wiring layer is 1.

[0116] Here, for comparison, Figure 8 an example of the layout of the wiring layer different from the wiring layer in the case where the H scan line 228 and the V signal line 229 are formed in the first wiring layer 234 and the second wiring layer 237 in the present embodiment is shown. Figure 8 is a drawing for comparison with Figure 7 the layout shown, and is a drawing showing an example of the layout in the case where the H scan line 228 and the V signal line 229 are formed in the wiring layer different from the wiring layer in the case where the H scan line 228 and the V signal line 229 are formed in the first wiring layer 234 and the second wiring layer 237 in the present embodiment. As Figure 8 shown, the Figure 7On the other hand, in the layout according to the present embodiment shown in FIG. 8, the H scan lines 228 and the V signal lines 229 are formed in the first wiring layer 234 and the second wiring layer 237, respectively. In other words, the H scan lines 228 are formed in the second wiring layer 237, and the V signal lines 229 are formed in the first wiring layer 234.

[0117] In this case, as shown in FIG. 9, the connection wiring related to the anode 243, the connection wiring related to the capacitor element, and the wiring for connecting the corresponding electrode of the diffusion layer 231 to the H scan line 228 formed in the second wiring layer 237 (the wiring indicated by a thin solid line in the drawing, hereinafter also referred to as the connection wiring related to the H scan line 228) are formed in the first wiring layer 234 together with the V signal line 229. Figure 8 In the first wiring layer 234, the number of the connection wiring related to the H scan line 228 is formed corresponding to the number of the H scan line 228. Further, in the second wiring layer 237, the capacitor element lower electrode 251 and the connection wiring related to the anode 243 are formed together with the number more of the H scan line 228. Further, in the third wiring layer 240, the capacitor element upper electrode 254 and the connection wiring related to the anode 243 are formed.

[0118] Comparing the layout according to the present embodiment shown in FIG. 8 with the layout shown in FIG. 9, in the layout according to the present embodiment, the H scan line 228 as the number more of the wiring is formed in the first wiring layer 234 as the lower layer, and thus the wiring pattern of the first wiring layer 234 becomes relatively dense. On the other hand, in the layout shown in FIG. 9, the H scan line 228 as the number more of the wiring is not formed in the first wiring layer 234, but the connection wiring related to the H scan line 228 as the number corresponding to the number of the H scan line 228 in the first wiring layer 234 is required to be formed. Therefore, it can be said that the area of the connection wiring related to the H scan line 228 is smaller than the area of the H scan line 228, and thus the density of the wiring pattern in the first wiring layer 234 is not much lower than that of the layout according to the present embodiment. Figure 7 Figure 8 Comparing the layout according to the present embodiment shown in FIG. 8 with the layout shown in FIG. 9, in the layout according to the present embodiment, the H scan line 228 as the number more of the wiring is formed in the first wiring layer 234 as the lower layer, and thus the wiring pattern of the first wiring layer 234 becomes relatively dense. On the other hand, in the layout shown in FIG. 9, the H scan line 228 as the number more of the wiring is not formed in the first wiring layer 234, but the connection wiring related to the H scan line 228 as the number corresponding to the number of the H scan line 228 in the first wiring layer 234 is required to be formed. Therefore, it can be said that the area of the connection wiring related to the H scan line 228 is smaller than the area of the H scan line 228, and thus the density of the wiring pattern in the first wiring layer 234 is not much lower than that of the layout according to the present embodiment. Figure 8

[0119] On the other hand, in the layout according to the present embodiment, the V signal line 229 as the number less of the wiring is formed in the second wiring layer 237, and thus the wiring pattern of the second wiring layer 237 becomes relatively sparse. On the other hand, in the layout shown in FIG. 9, the H scan line 228 as the number more of the wiring is formed in the second wiring layer 237, and thus the wiring pattern of the second wiring layer 237 becomes relatively dense. Figure 8

[0120] ​​​In this way, according to the present embodiment, with respect to the H scan line 228 and the V signal line 229, it is possible to make the wiring pattern in the second wiring layer 237, which is the higher layer, more sparse by configuring the layout of the first wiring layer 234 and the second wiring layer 237, thereby forming the H scan line 228, which is the number of wirings provided for one pixel circuit 220 in the first wiring layer 234, which is the lower layer, more.

[0121] The wiring pattern in the second wiring layer 237 becomes more sparse, and thus it is possible to suppress the occurrence of deterioration in luminance uniformity due to an increase in parasitic capacitance between wirings in the second wiring layer 237, short-circuit failure between wirings, and the like, as described above. Further, in the present embodiment, since the capacitor lower electrode 251 is provided in the second wiring layer 237, the wiring pattern of the second wiring layer 237 becomes sparse, and thus the degree of freedom of the layout of the capacitor lower electrode 251 increases, and with respect to the capacitor lower electrode 251, it is possible to secure a sufficient area capable of achieving a desired capacitance. Thus, it is possible to suppress deterioration in luminance uniformity due to pressure on the area of the electrode of the capacitor, the occurrence of wiring open-circuit failure due to the absence of a wiring pattern (electrode) having a small area being provided, and the like. Thus, it is possible to suppress the occurrence of these various problems, and it is possible to achieve a display device 1 having higher reliability and higher definition.

[0122] Here, Figure 7 An example of the layout in the case where the H scan line 228 and the V signal line 229 are formed in the first wiring layer 234 and the second wiring layer 237, respectively, is shown, but the present embodiment is not limited to such an example. Even in the case where the H scan line 228 and the V signal line 229 are formed in other wiring layers, the layout method (i.e., the method of forming the one of the H scan line 228 and the V signal line 229 provided for one pixel circuit 220 in a larger number) can be applied.

[0123] Reference will be made to Figure 9 Another example of the layout of the wiring layer according to the present embodiment will be described. Figure 9 is a view for describing another example of the layout of the wiring layer according to the present embodiment.

[0124] Figure 9 An example of the layout in the case where the H scan line 228 and the V signal line 229 are formed in the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 is shown. As Figure 9As shown, even in this case, in the present embodiment, one of the H scan lines 228 and the V signal lines 229 provided for one pixel circuit 220 which is larger in number is formed in a lower layer. Thus, for example, as shown, the H scan lines 228 are formed in the first wiring layer 234 and the second wiring layer 237, and the V signal lines 229 are formed in the third wiring layer 240.

[0125] In this case, as Figure 9 shown, for example, in the first wiring layer 234, the connection wiring related to the anode 243, the connection wiring related to the capacitor element, and the connection wiring related to the V signal line 229 are formed together with some of the H scan lines 228 (three H scan lines in the example shown in the figure). Further, in the second wiring layer 237, the capacitor element lower electrode 251, the connection wiring related to the anode 243, and the connection wiring related to the V signal line 229 are formed together with the remaining H scan line 228 (one H scan line in the example shown in the figure). Further, in the third wiring layer 240, the capacitor element upper electrode 254 and the connection wiring related to the anode 243 are formed together with the V signal line 229. In Figure 7 the example shown, a plurality of H scan lines 228 are formed in the same wiring layer, but in the present embodiment, the plurality of H scan lines 228 can be formed in such a manner as to be dispersed to different wiring layers.

[0126] Here, for comparison, Figure 10 an example of a layout of a wiring layer different from the wiring layers in the case where the H scan lines 228 and the V signal lines 229 are formed in the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 in the present embodiment is shown. Figure 10 is a figure for comparison with Figure 9 the layout shown, and is a figure showing an example of a layout in the case where the H scan lines 228 and the V signal lines 229 are formed in a wiring layer different from the wiring layers in the case where the H scan lines 228 and the V signal lines 229 are formed in the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240 in the present embodiment. As Figure 10 shown, in contrast to the layout according to the present embodiment shown in Figure 9 , it is assumed that one of the H scan lines 228 and the V signal lines 229 provided for one pixel circuit 220 which is larger in number is formed in a higher level layer. Here, it is assumed that the V signal lines 229 are formed in the first wiring layer 234, and the H scan lines 228 are formed in the third wiring layer 240.

[0127] In this case, as Figure 10As shown, in the first wiring layer 234, connection wirings associated with the anode 243, connection wirings associated with the capacitor element, and connection wirings associated with the H-scan line 228 are formed together with the V signal line 229. Furthermore, in the second wiring layer 237, the connection wirings associated with the anode 243 and the connection wirings associated with the H-scan line 228 are formed together with the lower electrode 251 of the capacitor element. Note that in the first wiring layer 234 and the second wiring layer 237, the number of connection wirings associated with the H-scan line 228 corresponds to the number of H-scan lines 228. Furthermore, in the third wiring layer 240, the upper electrode 254 of the capacitor element and the connection wirings associated with the anode 243 are formed together with an even greater number of H-scan lines 228.

[0128] Will Figure 9 The layout shown according to this embodiment is similar to Figure 10 Comparing the layouts shown, in the layout according to this embodiment, half of the H-scan lines 228, which represent a larger number of wirings, are formed in the first wiring layer 234, which is the lower layer, thus making the wiring pattern of the first wiring layer 234 relatively dense. On the other hand, in Figure 8 In the layout shown, no more H-scan lines 228 are formed in the first wiring layer 234, but a number of connection lines associated with the H-scan lines 228 are required. This number of connection lines corresponds to the number of H-scan lines 228 in the first wiring layer 234. Therefore, it can be said that the area of ​​the connection lines associated with the H-scan lines 228 is smaller than the area of ​​the H-scan lines 228. Consequently, the density of the wiring pattern in the first wiring layer 234 is not significantly lower than the density of the layout according to this embodiment.

[0129] On the other hand, in the layout according to this embodiment, the V signal lines 229, which are a relatively small number of wirings, are formed in the third wiring layer 240, thus the wiring patterns of the second wiring layer 237 and the third wiring layer 240 become relatively sparse. On the other hand, in Figure 8 In the layout shown, since H-scan lines 228, which are a larger number of wirings, are formed in the third wiring layer 240, the number of connection wirings associated with the H-scan lines 228 corresponding to the number of H-scan lines 228 in the second wiring layer 237 needs to be formed. Therefore, the wiring pattern of the second wiring layer 237 becomes relatively dense.

[0130] In this way, according to Figure 9The layout shown, regarding H-scan line 228 and V-signal line 229, can be configured such that the wiring patterns in the higher wiring layers 237 and 240 are sparser, thereby forming H-scan line 228. H-scan line 228 consists of a greater number of wirings provided for a pixel circuit 220 in the lower wiring layers 234 and 237. Therefore, it is possible to obtain [the desired result]. Figure 7 The same effect is achieved in the case of the above-described layout, that is, to realize a display device 1 with high definition and higher reliability.

[0131] Furthermore, according to the current implementation method, the following effects may also be observed.

[0132] For example, by executing such Figure 8 and Figure 10 If the layout shown cannot ensure sufficient area for achieving the desired capacitance in the second wiring layer 237 regarding the lower electrode 251 of the capacitor element, it may be necessary to increase the number of wiring layers to produce a capacitor element with the desired capacitance, and the capacitor element may be formed in the increased wiring layers. In this case, the number of masks and the number of steps increase due to the increase in the number of wiring layers, which may increase manufacturing costs. On the other hand, according to the layout of this embodiment, as described above, since sufficient area for the lower electrode 251 of the capacitor element can be ensured, a capacitor element with the desired capacitance can be formed without causing such an increase in the number of wiring layers. In this way, according to this embodiment, the effect of suppressing the increase in manufacturing costs can also be achieved.

[0133] Furthermore, in this embodiment, compared to the case where a larger number of wirings are formed in the upper wiring layer and isolated connection wirings (such as the connection wirings related to the H scan line 228) are formed in the lower wiring layer, a larger number of wirings are formed in the lower wiring layer, thus making the wiring pattern of the lower wiring layer quite dense. In this way, the wiring pattern in the lower wiring layer near the diffusion layer 231 where the transistor is formed becomes dense, thereby improving the light-shielding effect on the transistor. Therefore, fluctuations in transistor characteristics caused by light exposure can be better suppressed, and the reliability of the display device 1 can be further improved.

[0134] Furthermore, the wiring pattern in the upper wiring layers, especially the highest-level wiring layer, can be relatively sparse, thus improving the flatness of the anode 243 of the organic light-emitting diode 221 formed in the upper layer at a higher position in the highest-level wiring layer. This improves the luminous efficiency of the organic light-emitting diode 221 and further enhances the display quality.

[0135] Further, the wiring pattern of the upper wiring layer can be relatively sparse, and thus the layout freedom of the connection wiring related to the anode 243 formed in the third wiring layer 240 as the highest level wiring layer (i.e., the layout of the third via hole 242 for connecting the connection wiring related to the anode 243 and the anode 243 in the upper layer to each other) is improved. Thus, the design of the pixel layout is easier.

[0136] This will be described in more detail with reference to Figure 11 and 12 Figure 11 is a diagram showing an example of the layout of the third via hole 242 in three sub-pixels in the case where one pixel is formed by the three sub-pixels. Figure 12 is a diagram showing an example of the layout of the third via hole 242 in four sub-pixels in the case where one pixel is formed by the four sub-pixels.

[0137] Figure 11 and Figure 12 all show a top view of a configuration in which the anode 243 and the organic layer 261 (a layer used as a light-emitting layer in the light-emitting organic light-emitting diode 221) corresponding to one pixel are stacked on the left side of the diagram, and the layout of the third via hole 242 for such a configuration is shown schematically. Further, the right side of the diagram shows a plan view of the configuration 262 in which the diffusion layer 231 and the wiring layers (the first wiring layer 234, the second wiring layer 237, and the third wiring layer 240) are similarly stacked corresponding to one pixel, and the layout of the third via hole 242 for such a configuration is shown schematically. Regarding the configuration 262 in which the diffusion layer 231 and the wiring layers are stacked, detailed explanation of the inside of each layer is omitted for convenience. Note that, in Figure 11 and 12 , regarding the organic layer 261 and the configuration 262 in which the diffusion layer 231 and the wiring layers are stacked, a letter indicating the color of the corresponding sub-pixel (R: red, G: green, B: blue, W: white) is attached to the end of the reference sign. Actually, since the color of each sub-pixel is controlled by a color filter (CF) provided at a higher layer than the organic light-emitting diode 221, regarding the organic layer 261 and the configuration 262 in which the diffusion layer 231 and the wiring layers are stacked, there is no difference in structure due to the color.

[0138] As shown in Figure 11 , in the case where one pixel is formed by three sub-pixels, the layout of the third via hole 242 is substantially the same in the sub-pixels. Thus, there is no great advantage due to the improvement in the layout freedom of the third via hole 242.

[0139] On the other hand, as shown in Figure 12 ​As shown, in a case where one pixel is formed of four sub-pixels, the arrangement of the third via holes 242 between the sub-pixels differs. That is, it is also necessary to change the arrangement of the connection wiring related to the anode 243 in the third wiring layer 240 for each sub-pixel. In this case, for example, since the like Figure 10 As shown in the layout, when the wiring pattern in the third wiring layer 240 is dense, the degree of freedom of the arrangement of the connection wiring related to the anode 243 is low. Therefore, in order to make the arrangement of the connection wiring related to the anode 243 different for each sub-pixel, there is a concern that it is necessary to make the entire layout of the third wiring layer 240 different for each sub-pixel. Therefore, in this case, it can also be necessary to make the layout of the second wiring layer 237 and the first wiring layer 234 of the lower layer different for each sub-pixel, which leads to a large amount of work of the layout and a heavy burden on the designer.

[0140] On the other hand, according to the present embodiment, it is possible to make the wiring pattern of the wiring layer of the upper layer relatively sparse, and therefore the degree of freedom of the configuration of the connection wiring related to the anode 243 in the third wiring layer 240 is high. Therefore, it is possible to configure the layout of the third wiring layer 240 so that, for each sub-pixel, only the arrangement of the connection wiring related to the anode 243 is different, and the arrangement of the other wirings is the same for each sub-pixel. In this case, with respect to the layout of the second wiring layer 237 and the first wiring layer 234 of the lower layer, it is sufficient that the arrangement of the connection wiring related to the anode 243 is different for each sub-pixel, thereby reducing the difficulty of designing the layout. In this way, the layout method for the wiring layer according to the present embodiment also has an effect of reducing the difficulty of designing the layout of one pixel in a case where the arrangement of the third via hole 242, that is, the via hole for connecting the highest level wiring layer and the anode 243 to each other, is different for each sub-pixel, as in a case where one pixel is formed of four sub-pixels.

[0141] The layout of the wiring layer according to the present embodiment has been described above. Note that, although only the case where one pixel is formed of four sub-pixels has been taken up above Figure 7 and 9The layout method for wiring layers according to the present embodiment can be applied to various display devices as long as the display devices are display devices driven by the active matrix method. By applying the layout method for wiring layers according to the present embodiment to reduce the number of connection wirings related to the H scan lines 228 or the number of connection wirings related to the V signal lines 229 in the wiring layer of the lower layer regardless of the number of wiring layers and the like, it is possible to make the wiring pattern of the wiring layer of the higher layer relatively sparse. In addition, by providing the electrodes (the lower capacitor electrode 251 and / or the upper capacitor electrode 254) of the capacitor element with a relatively sparse wiring pattern in the wiring layer, it is possible to sufficiently secure the area of the electrodes of the capacitor element. Thus, similarly to the above-described embodiment, it is possible to obtain various effects such as improvement in reliability and the like.

[0142] (5. Specific Configuration Example of Display Device) A more specific configuration example of the display device 1 according to the present embodiment described above will now be described. Figure 13 is a partial cross-sectional view illustrating a specific configuration example of the display device 1 according to the present embodiment. Figure 13 is a partial cross-sectional view illustrating a specific configuration example of the display device 1 according to the present embodiment.

[0143] Referring to Figure 13The display device 1 according to the present embodiment includes a plurality of organic light emitting diodes 211 and a CF layer 33 on the first substrate 11, each of the organic light emitting diodes 211 is a light emitting element that emits white light, and the CF layer 33 is provided on the organic light emitting diodes 211 and in which CFs of some colors are formed to correspond to the organic light emitting diodes 211. Further, a second substrate 34 containing a material that is transparent to light from the organic light emitting diodes 211 is placed on the CF layer 33. Further, on the first substrate 11, thin film transistors 15 (TFTs) for driving the organic light emitting diodes 211 are provided to correspond to each of the organic light emitting diodes 211. The TFTs 15 correspond to each of the transistors (a drive transistor 212, a sampling transistor 213, a light emitting control transistor 214, and a switching transistor 217) included in the above-described pixel circuit 210. The TFTs 15 selectively drive any of the organic light emitting diodes 211; light from the driven organic light emitting diode 211 passes through the corresponding CF, and the color of the light is appropriately converted; and the light is emitted from the upper side via the second substrate 34; thereby, a desired image, a desired character, or the like is displayed.

[0144] Note that, in the following description, the stacking direction of the layers in the display device 1 is also referred to as the up-down direction. In this case, the side on which the first substrate 11 is placed is defined as the lower side, and the side on which the second substrate 34 is placed is defined as the upper side. Further, a plane perpendicular to the up-down direction is also referred to as a horizontal plane.

[0145] Therefore, Figure 13 The display device 1 shown in FIG. 1 is a top emission display device of color display that can be driven by an active matrix system. However, the present embodiment is not limited to this example, and the display device 1 according to the present embodiment can be a bottom emission display device that emits light via the first substrate 11.

[0146] (First substrate and second substrate) In the illustrated configuration example, the first substrate 11 includes a Si substrate. Further, the second substrate 34 contains quartz glass. However, the present embodiment is not limited to this example, and various known materials can be used as the first substrate 11 and the second substrate 34. For example, each of the first substrate 11 and the second substrate 34 can include a high strain point glass substrate, a soda lime glass (a mixture of Na20, CaO, and Si02) substrate, a borosilicate glass (a mixture of Na20, B203, and Si02) substrate, a forsterite (Mg2Si04) substrate, a lead glass (a mixture of Na20, PbO, and Si02) substrate, various glass substrates in which an insulating film is formed on a surface, a quartz substrate, a quartz substrate in which an insulating film is formed on a surface, a Si substrate in which an insulating film is formed on a surface, or an organic polymer substrate (e.g., polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polycarbonate, polyethylene terephthalate (PET), or the like). The materials included in the first substrate 11 and the second substrate 34 can be the same or can be different. However, since the display device 1 is a top emission type as described above, the second substrate 34 preferably contains a material having a high transmittance that is capable of advantageously transmitting light from the organic light emitting diode 211.

[0147] (Light emitting element and second member) The organic light emitting diode 211 includes the first electrode 21, the organic layer 23 provided on the first electrode 21, and the second electrode 22 formed on the organic layer 23. More specifically, the second member 52 having an opening 25 exposing at least a portion of the first electrode 21 is stacked on the first electrode 21, and the organic layer 23 is provided on the portion of the first electrode 21 exposed at the bottom of the opening 25. That is, the organic light emitting diode 211 has a configuration in which the first electrode 21, the organic layer 23, and the second electrode 22 are stacked in the opening 25 of the second member 52 in that order. This stacked structure functions as a light emitting portion 24 of each pixel. That is, a portion of the organic light emitting diode 211 falling below the opening 25 of the second member 52 functions as a light emitting surface. Further, the second member 52 functions as a pixel defining film that is provided between pixels and divides the area of the pixels.

[0148] The organic layer 23 includes a light-emitting layer including an organic light-emitting material, and can emit white light. The specific configuration of the organic layer 23 is not limited, and can be various well-known configurations. For example, the organic layer 23 can have a stacked structure of a hole transport layer, a light-emitting layer, and an electron transport layer, a stacked structure of a hole transport layer and a light-emitting layer also serving as an electron transport layer, a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and the like. Further, in a case where each of these stacked structures and the like serves as a "tandem cell", the organic layer 23 can have a two-stage tandem structure in which a first tandem cell, a connecting layer, and a second tandem cell are stacked. Alternatively, the organic layer 23 can have a three or more stage tandem structure in which three or more tandem cells are stacked. In a case where the organic layer 23 includes a plurality of tandem cells, the organic layer 23 as a whole can emit white light by assigning red, green, and blue to the light-emitting colors of the light-emitting layers of the tandem cells.

[0149] In the illustrated configuration example, the organic layer 23 is formed by depositing an organic material by vacuum vapor deposition. However, the present embodiment is not limited to this example, and the organic layer 23 can be formed by various well-known methods. For example, as a method for forming the organic layer 23, a physical vapor deposition method (PVD method) such as vacuum evaporation, a printing method such as a screen printing method and an inkjet printing method, a laser transfer method of irradiating a stacked structure of a laser absorption layer and an organic layer formed on a transfer substrate with laser light to separate the organic layer on the laser absorption layer and transfer the organic layer, various coating methods, and the like can be used.

[0150] The first electrode 21 functions as an anode. That is, the first electrode 21 corresponds to the above-described Figure 6 Since the display device 1 is a top emission type as described above, the first electrode 21 contains a material capable of reflecting light from the organic layer 23. In the illustrated configuration example, the first electrode 21 contains an alloy of aluminum and neodymium (Al-Nd alloy). Further, the film thickness of the first electrode 21 is about, for example, 0.1 μm to 1 μm. However, the present embodiment is not limited to this example, and the first electrode 21 can contain various well-known materials serving as an electrode on the light-reflecting side of an anode used in a general organic EL display device. Further, the film thickness of the first electrode 21 is also not limited to the above-described example, and the first electrode 21 can be formed at an appropriate film thickness within a range commonly used in organic EL display devices.

[0151] For example, the first electrode 21 can contain a metal having a high work function, such as platinum (Pt), gold (Au), silver (Ag), and the like. Alternatively, the first electrode 21 can contain a metal having a low work function, such as aluminum (Al), magnesium (Mg), and the like. Further, the first electrode 21 can contain a metal having a work function between the above-described high work function and low work function, such as indium (In), titanium (Ti), and the like. Further, the first electrode 21 can contain a metal alloy of the above-described metals, such as an Al-Nd alloy, and the like. g), chromium (Cr), tungsten (W), nickel (Ni), copper (Cu), iron (Fe), cobalt (Co), or tantalum (Ta), or an alloy having a high work function (for example, an Ag-Pd-Cu alloy including silver as a main component and including 0.3 to 1 mass% of palladium (Pd) and 0.3 to 1 mass% of copper, an Al-Nd alloy, or the like). Alternatively, the first electrode 21 can include a conductive material having a small work function value and a high light reflectance, such as aluminum or an aluminum-containing alloy. In this case, it is preferable to improve the hole injection properties by providing a suitable hole injection layer on the first electrode 21 or the like. Alternatively, the first electrode 21 can have a structure in which a transparent conductive material having excellent hole injection properties, such as an oxide of indium and tin (ITO) or an oxide of indium and zinc (IZO), is stacked on a reflective film having a high light reflectance, such as a dielectric multilayer film or aluminum.

[0152] The second electrode 22 functions as a cathode. Since the display device 1 is a top emission type as described above, the second electrode 22 includes a material capable of transmitting light from the organic layer 23. In the illustrated configuration example, the second electrode 22 includes an alloy of magnesium and silver (Mg-Ag alloy). Further, the film thickness of the second electrode 22 is about, for example, 10 nm. However, the present embodiment is not limited to this example, and the second electrode 22 can include various well-known materials used as a material of an electrode on the light-transmitting side of a cathode in a general organic EL display device. Further, the film thickness of the second electrode 22 is also not limited to the above-described example, and the second electrode 22 can be formed at a film thickness range commonly used in organic EL display devices as appropriate.

[0153] For example, the second electrode 22 can include aluminum, silver, magnesium, calcium (Ca), sodium (Na), strontium (Sr), an alloy of an alkali metal and silver, an alloy of an alkaline earth metal and silver (for example, an alloy of magnesium and silver (Mg-Ag alloy)), an alloy of magnesium and calcium (Mg-Ca alloy), an alloy of aluminum and lithium (Al-Li alloy), or the like. In a case where each of these materials is used for a single layer, the film thickness of the second electrode 22 is about, for example, 4 nm to 50 nm. Alternatively, the second electrode 22 can have a structure in which a layer of any of the above-described materials is stacked from the organic layer 23 side and a transparent electrode including, for example, ITO or IZO (thickness of about, for example, 30 nm to 1 μm) is included. In a case where such a stacked structure is used, the thickness of the layer of any of the above-described materials can be as thin as about 1 nm to 4 nm, for example. Alternatively, the second electrode 22 can include only a transparent electrode. Alternatively, a confluence electrode (auxiliary electrode) including a low-resistance material such as aluminum, an aluminum alloy, silver, a silver alloy, copper, a copper alloy, gold, a gold alloy, or the like can be provided on the second electrode 22 to reduce the resistance of the second electrode 22 as a whole.

[0154] In the illustrated configuration example, each of the first electrode 21 and the second electrode 22 is formed by a vacuum vapor deposition method as a film having a prescribed thickness, and then is formed by patterning the film by an etching method. However, the present embodiment is not limited to this example, and the first electrode 21 and the second electrode 22 can be formed by various publicly known methods. Examples of the method for forming the first electrode 21 and the second electrode 22 include a vapor deposition method, including a hot wire vapor deposition method, a vacuum vapor deposition method, a sputtering method, a chemical vapor deposition method (CVD method), a metal organic chemical vapor deposition method (MOCVD method), a combination of an ion plating method and an etching method, various printing methods (for example, a screen printing method, an inkjet printing method, a metal mask printing method, and the like), an electroplating method (electroplating method, chemical plating method, and the like), a peeling method, a laser ablation method, a sol-gel method, and the like.

[0155] The second member 52 is SiO2 that is formed as a film having a prescribed film thickness by a CVD method, and then is formed by patterning the SiO2 film using a photolithography technique and an etching technique. However, the material of the second member 52 is not limited to this example, and various materials having insulating properties can be used as the material of the second member 52. Examples of the material included in the second member 52 include SiO2, MgF, LiF, a polyimide resin, an acrylic resin, a fluorine resin, a silicon resin, a fluorine-based polymer, a siloxane-based polymer, and the like. However, as described later, the second member 52 includes a material having a lower refractive index than the material of the first member 51.

[0156] On the first substrate 11, the first electrode 21 included in the organic light emitting diode 211 is disposed on the interlayer insulating layer 16 containing SiON. Then, the interlayer insulating layer 16 covers the light emitting element drive portion formed on the first substrate 11.

[0157] The light emitting element drive portion includes a plurality of TFTs 15. In other words, the light emitting element drive portion corresponds to a drive circuit of the pixel circuit 210. The TFT 15 includes a gate electrode 12 formed on the first substrate 11, a gate insulating film 13 formed on the first substrate 11 and the gate electrode 12, and a semiconductor layer 14 formed on the gate insulating film 13. A region of the semiconductor layer 14 located directly above the gate electrode 12 serves as a channel region 14A, and a region sandwiching the channel region 14A serves as a source / drain region 14B. Note that, although the TFT 15 is of a bottom gate type in the illustrated example, the present embodiment is not limited to this example, and the TFT 15 can be of a top gate type.

[0158] The interlayer insulating layer 16 including two layers (a lower layer interlayer insulating layer 16A and an upper layer interlayer insulating layer 16B) is stacked on the semiconductor layer 14 by a CVD method. In this case, after the lower layer interlayer insulating layer 16A is stacked, a contact hole 17 is provided in a portion of the lower layer interlayer insulating layer 16A corresponding to the source / drain region 14B to expose the source / drain region 14B, for example, by a photolithography technique and an etching technique, and a wiring 18 containing aluminum is formed to fill the contact hole 17. The wiring 18 is formed, for example, by combining a vacuum vapor deposition method and an etching method. Then, the upper layer interlayer insulating layer 16B is stacked.

[0159] In a portion of the upper layer interlayer insulating layer 16B in which the wiring 18 is provided, a contact hole 19 is provided to expose the wiring 18, for example, by using a photolithography technique and an etching technique. Then, when the first electrode 21 of the organic light emitting diode 211 is formed, the first electrode 21 is formed to be in contact with the wiring 18 via the contact hole 19. Thus, the first electrode 21 of the organic light emitting diode 211 is electrically connected to the source / drain region 14B of the TFT 15 (in the example of the pixel circuit illustrated in FIG. 1, a drain region corresponding to the drive transistor 212) via the wiring 18. Figure 3

[0160] Note that, although the interlayer insulating layer 16 contains SiON in the above-described example, the present embodiment is not limited to this example. The interlayer insulating layer 16 can contain various well-known materials that can be used as an interlayer insulating layer in a general organic EL display device. For example, as a material contained in the interlayer insulating layer 16, a SiO2-based material (for example, SiO2, BPSG, PSG, BSG, AsSG, PbSG, SiON, spin-on glass (SOG), a low-melting glass, a glass paste, or the like), a SiN-based material, and an insulating resin (for example, a polyimide resin, a novolac-based resin, an acrylic-based resin, a polybenzoxazole, or the like) can be used alone or in appropriate combination. Furthermore, a method for forming the interlayer insulating layer 16 is not limited to the above-described example, and the interlayer insulating layer 16 can be formed using a CVD method, a coating method, a sputtering method, and various printing methods and the like that are well known. Furthermore, although aluminum is formed into a film and the film is patterned to form the wiring 18 by a vacuum vapor deposition method and an etching method in the above-described example, the present embodiment is not limited to this example. The wiring 18 can be formed by forming any one of various materials used as a wiring in a general organic EL display device into a film and patterning the film by various methods.

[0161] Furthermore, for the sake of convenience, Figure 13 only one wiring layer is illustrated. Actually, as described above with reference to Figure 6 the drawings, a plurality of wiring layers can be formed on a diffusion layer in which the TFT 15 is formed, and the organic light emitting diode 211 can also be formed on the plurality of wiring layers.​

[0162] (Configuration of the portion above the light-emitting element) The opening 25 in the second component 52 of the organic light-emitting diode 211 is formed into a conical shape, wherein the sidewalls of the opening 25 are inclined such that the opening area increases as it approaches the bottom. Then, the first component 51 is placed in the opening 25. That is, the first component 51 is a layer disposed directly above the light-emitting surface of the organic light-emitting diode 211 and propagating the emitted light from the light-emitting element upward. Furthermore, by forming the opening 25 of the second component 52 in the manner described above, the cross-sectional shape of the first component 51 along the stacking direction (i.e., the cross-sectional shape shown in the figure) has a substantially trapezoidal shape, thus the first component 51 has a truncated cone or pyramidal shape with the bottom facing upward.

[0163] The first component 51 is formed using vacuum evaporation. 1-x N x As a film, the opening 25 is filled, and then the Si is planarized by chemical mechanical polishing (CMP) and other methods. 1-x N x The membrane is formed on its surface. However, the material of the first component 51 is not limited to this example, and various materials with insulating properties can be used as the material of the first component 51. Examples of materials included in the first component 51 include Si. 1-x N x Materials such as ITO, IZO, TiO2, Nb2O5, bromine-containing polymers, sulfur-containing polymers, titanium-containing polymers, and zirconium-containing polymers can be used. The method for forming the first component 51 is not limited to this example, and various known methods can be used as methods for forming the first component 51.

[0164] However, in this embodiment, the materials of the first component 51 and the second component 52 are selected such that the refractive index n1 of the first component 51 and the refractive index n2 of the second component 52 satisfy the relationship n1>n2. By selecting the materials of the first component 51 and the second component 52 such that the refractive indices satisfy the above relationship, at least a portion of the light propagating through the first component 51 is reflected at the surface of the second component 52 facing the first component 51. More specifically, the organic layer 23 and the second electrode 22 of the organic light-emitting diode 211 are formed between the first component 51 and the second component 52, so at least a portion of the light propagating through the first component 51 is reflected at the interface between the second component 52 and the organic layer 23. That is, the surface of the second component 52 facing the first component 51 functions as a light reflector 53.

[0165] In the present embodiment, as described above, the first member 51 is disposed directly above the light-emitting surface of the organic light-emitting diode 211. Then, the first member 51 has a truncated conical or pyramidal shape with the bottom surface facing upward, and thus the light emitted from the light-emitting surface of the organic light-emitting diode 211 is reflected upward (i.e., the light-emitting direction) by the interface between the first member 51 and the second member 52 (i.e., the reflector 53). Therefore, according to the present embodiment, the efficiency of extracting the emitted light from the organic light-emitting diode 211 can be improved by providing the reflector 53, and the luminance of the entire display device 1 can be improved.

[0166] Note that the present inventors' studies have shown that, in order to more advantageously improve the efficiency of extracting the emitted light from the organic light-emitting diode 211, it is preferable that the refractive indices of the first member 51 and the second member 52 satisfy the relationship n1-n2≥0.20. More preferably, the refractive indices of the first member 51 and the second member 52 satisfy the relationship n1-n2≥0.30. Furthermore, in order to further improve the efficiency of extracting the emitted light from the organic light-emitting diode 211, it is preferable that the shape of the first member 51 satisfy the relationships 0.5≤R1 / R2≤0.8 and 0.5≤H / R1≤0.8. Here, R1 represents the diameter of the light-incident surface of the first member 51 (i.e., the surface facing downward in the stacking direction and facing the light-emitting surface of the organic light-emitting diode 211), R2 represents the diameter of the light- exit surface of the first member 51 (i.e., the surface facing upward in the stacking direction), and H represents the distance between the bottom surface and the upper surface (the height in the stacking direction) in the case where the first member 51 is regarded as a truncated cone or a pyramid.

[0167] The protective film 31 and the planarization film 32 are sequentially stacked on the planarized first member 51. The protective film 31 is, for example, stacked with SiO2having a prescribed film thickness (about 3.0 μm) by a vacuum evaporation method, and is planarized by a CMP method or the like. 1-y N y Furthermore, the planarization film 32 is, for example, stacked with SiO2having a prescribed film thickness (about 2.0 μm) by a CVD method and is planarized by a CMP method or the like.

[0168] However, the materials and film thicknesses of the protective film 31 and the planarization film 32 are not limited to these examples, and the protective film 31 and the planarization film 32 can appropriately contain various publicly known materials, be used as a protective film and a planarization film of a general organic EL display device, and thus have a film thickness commonly used in organic EL display devices.

[0169] However, in the present embodiment, the material of the protective film 31 is preferably selected so that the refractive index n3 of the protective film 31 is equal to or less than the refractive index n1 of the first member 51. Further, the materials of the protective film 31 and the planarization film 32 are selected so that the absolute value of the difference between the refractive index n3 of the protective film 31 and the refractive index n4 of the planarization film 32 is preferably less than or equal to 0.30, and more preferably less than or equal to 0.20. By thus selecting the materials of the protective film 31 and the planarization film 32, reflection or scattering of the emission light from the organic light emitting diode 211 at the interface between the first member 51 and the protective film 31 and at the interface between the protective film 31 and the planarization film 32 can be suppressed, and the light extraction efficiency can be further improved.

[0170] The CF layer 33 is formed on the planarization film 32. Thus, the display device 1 is a so-called on-cell color filter (OCCF) system display device in which the CF layer 33 is formed on the first substrate 11 on which the organic light emitting diode 211 is formed. The second substrate 34 is adhered to the upper side of the CF layer 33 via a sealing resin film 35 of, for example, an epoxy resin, thereby manufacturing the display device 1. Note that the material of the sealing resin film 35 is not limited to this example, and the material of the sealing resin film 35 can be appropriately selected on the basis of high transmittance of the emission light from the organic light emitting diode 211, excellent adhesion to the CF layer 33 on the lower side and the second substrate 34 on the upper side, low reflectance of light at the interface with the CF layer 33 on the lower side, and low reflectance of light at the interface with the second substrate 34 on the upper side, and the like. However, the present embodiment is not limited to this example. The display device 1 can be a so-called opposite CF system display device, which is manufactured from the CF layer 33 formed on the second substrate 34, and the first substrate 11 and the second substrate 34 are bonded together so that the CF layer 33 faces the organic light emitting diode 211.

[0171] The CF layer 33 is formed so as to provide each color of CF having a prescribed area for each of the organic light emitting diodes 211. For example, the CF layer 33 can be formed by exposing a resist material in a prescribed configuration and developing by a photolithography technique. Further, for example, the film thickness of the CF layer 33 is about 2 μm. However, the material, the formation method, and the film thickness of the CF layer 33 are not limited to these examples, and the CF layer 33 can be formed to have a film thickness generally used in organic EL display devices by using various well-known materials and various well-known methods appropriately used as a CF layer of a general organic EL display device.

[0172] In the illustrated example, the CF layer 33 is provided so that the red CF 33R, the green CF 33G, and the blue CF 33B each having a prescribed area are continuously distributed in the horizontal plane. Note that, in the following description, in a case where it is not necessary to particularly distinguish the CF 33R, the CF 33G, and the CF 33B, one or more of them can be written as a simple CF 33a. One sub-pixel includes a combination of one organic light emitting diode 211 and one CF 33a.

[0173] In the above, a specific configuration example of the display device 1 is described. Note that, regarding the configuration of the above-described display device 1, particularly the configuration of the reflector 53, for example, reference can be made to the prior application of the present applicant, JP 2013-191533 A. However, the configuration of the display device 1 according to the present embodiment is not limited to this example. As described above, it is sufficient that the aspects described in the above (4, layout of the wiring layer) are reflected in the display device 1 according to the present embodiment, and various known configurations used in ordinary display devices can be used for other aspects.

[0174] (6. Application Examples) Application examples of the display device 1 according to the present embodiment described above will now be described. Here, some examples of electronic equipment in which the display device 1 according to the present embodiment described above can be used are described.

[0175] Figure 14 is a view showing the appearance of a smartphone which is an example of electronic equipment in which the display device 1 according to the present embodiment can be used. As shown in Figure 14 , the smartphone 501 includes an operation section 503 including buttons and accepting operation of user input, and a display section 505 displaying various information. The display device 1 can be applied to the display section 505.

[0176] Figure 15 and Figure 16 is a view showing the appearance of a digital camera which is another example of electronic equipment in which the display device 1 according to the present embodiment can be used. Figure 15 the appearance of the digital camera 511 as viewed from the front (subject side) is shown, Figure 16 the appearance of the digital camera 511 as viewed from the back is shown. As shown in Figure 15 and Figure 16 , the digital camera 511 includes a main body section (camera main body) 513, a replaceable lens unit 515, a grip section 517 which is gripped by a user during photographing, and a monitor 519 displaying various information, and an electronic viewfinder (EVF) 521 displaying a through image which is observed by a user during photographing. The display device 1 can be applied to the monitor 519 and the EVF 521.

[0177] Figure 17 is a drawing illustrating an appearance of a head-mounted display (HMD) which is another example of an electronic device in which the display device 1 according to the present embodiment can be used. As shown in Figure 17 , the HMD 531 includes a glasses-type display portion 533 which displays various information, and an ear fixing portion 535 which is fixed to the ear of a user during wearing. The display device 1 can be applied to the display portion 533.

[0178] In the above, some examples of the electronic device in which the display device 1 according to the present embodiment can be used are described. Note that the electronic device in which the display device 1 can be used is not limited to the above-described examples, and the display device 1 can be used for a display device mounted on an electronic device in all fields in which display is performed based on an image signal inputted from the outside or an image signal generated inside, such as a television device, an electronic book, a smart phone, a personal digital assistant (PDA), a notebook personal computer (PC), a video camera, and a game device.

[0179] (7. Supplement)

[0180] The preferred embodiments of the present disclosure have been described above with reference to the accompanying drawings, and the present disclosure is not limited to the above-described examples. Various changes and modifications can be found by those skilled in the art within the scope of the appended claims, and it should be understood that they will naturally fall within the technical scope of the present disclosure.

[0181] For example, although each transistor (the drive transistor 212, the sampling transistor 213, the light emission control transistor 214, and the switching transistor 217) included in the drive circuit of the pixel circuit 210 is a P-channel type in the above-described embodiment, the technology according to the present disclosure is not limited to this example. For example, each of these transistors can be an N-channel type.

[0182] Further, the effects described in the present specification are merely illustrative or exemplary effects, and are not limited. That is, additional effects can be obtained with or in the place of the above-mentioned effects according to the technology of the present disclosure, which will be clear to those skilled in the art from the description of the present specification.

[0183] Further, the present technology can also be configured as follows.

[0184] (1) A display device comprising:

[0185] a pixel unit configured with a plurality of pixel circuits arranged in a matrix, each pixel circuit including a light emitting element and a drive circuit for driving the light emitting element;

[0186] a scan line, the scan line being a wiring connected to each pixel circuit, and the scan line being provided so as to extend in a first direction and correspond to each row of the plurality of pixel circuits; and

[0187] a signal line, the signal line being a wiring connected to each of the pixel circuits and being provided so as to extend in a second direction orthogonal to the first direction and to correspond to each of columns of the plurality of pixel circuits,

[0188] wherein the larger number of the scan lines and the signal lines provided for one pixel circuit are located in a lower wiring layer, and

[0189] an electrode of a capacitor element included in the drive circuit is located in the wiring layer in which any one of the scan lines and the signal lines is provided.

[0190] (2) The display device according to (1),

[0191] wherein the drive circuit includes a plurality of transistors, and

[0192] a plurality of wiring layers are stacked on a diffusion layer in which the plurality of transistors are formed, and the scan lines, the signal lines, and the capacitor element are formed in each of the wiring layers.

[0193] (3) The display device according to (2),

[0194] wherein the light emitting element is an organic light emitting diode, and

[0195] the organic light emitting diode is located on the uppermost wiring layer.

[0196] (4) The display device according to any one of (1) to (3),

[0197] wherein one sub-pixel includes one pixel circuit, and

[0198] one pixel includes four sub-pixels.

[0199] (5) The display device according to any one of (1) to (4),

[0200] wherein the number of the scan lines is larger than the number of the signal lines.

[0201] (6) The display device according to any one of (1) to (5),

[0202] wherein the scan line is a wiring extending in a horizontal direction, and

[0203] the signal line is a wiring extending in a vertical direction.

[0204] (7) The display device according to any one of (1) to (6),

[0205] wherein all of the plurality of scan lines are located in the same wiring layer, or all of the plurality of signal lines are located in the same wiring layer.

[0206] (8) The display device according to any one of (1) to (7),

[0207] wherein the plurality of scan lines are dispersedly arranged in a plurality of different wiring layers, or the plurality of signal lines are dispersedly arranged in a plurality of different wiring layers.

[0208] (9) An electronic device including:

[0209] a display device that displays based on a video signal,

[0210] wherein the display device includes:

[0211] a pixel unit configured with a plurality of pixel circuits arranged in a matrix, each of the pixel circuits including a light emitting element and a drive circuit for driving the light emitting element,

[0212] a scan line, the scan line being a wiring connected to each of the pixel circuits, and the scan line being provided so as to extend in a first direction and correspond to each of rows of the plurality of pixel circuits, and

[0213] a signal line, the signal line being a wiring connected to each of the pixel circuits, and the signal line being provided so as to extend in a second direction orthogonal to the first direction and correspond to each of columns of the plurality of pixel circuits,

[0214] a larger number of the scan lines and the signal lines provided for one of the pixel circuits are located in a lower wiring layer, and

[0215] an electrode of a capacitor element included in the drive circuit is located in a wiring layer in which any of the scan line or the signal line is provided.

[0216] List of Reference Signs

[0217] 1 Display device

[0218] 10 Display panel

[0219] 20 Pixel unit

[0220] 30 Scan unit

[0221] 40 Selection unit

[0222] 210, 220 Pixel circuit

[0223] 211, 221 Organic light emitting diode

[0224] 212 Drive transistor

[0225] 213 Sampling transistor

[0226] 214 Light emitting control transistor

[0227] 215, 227 holding capacitor

[0228] 216 auxiliary capacitor

[0229] 217 switching transistor

[0230] 222, 223, 224, 225, 226 transistor

[0231] 228 H scan line

[0232] 229 V signal line

[0233] 231 diffusion layer

[0234] 232, 235, 238, 241 insulating layer

[0235] 233 contact

[0236] 236, 239, 242 via hole

[0237] 234, 237, 240 wiring layer

[0238] 243 anode

[0239] 251 lower electrode of capacitor element

[0240] 252, 254 upper electrode of capacitor element

[0241] 261 organic layer

[0242] 301 write scan unit

[0243] 302 write scan line

[0244] 311 first drive scan unit

[0245] 312 first drive line

[0246] 321 second drive scan unit

[0247] 322 second drive line

[0248] 331 common power supply line

[0249] 332 power supply line

[0250] 333 ground line

[0251] 401 signal output unit

[0252] 402 signal line

[0253] 501 smartphone (electronic device)

[0254] 511 digital camera (electronic device)

[0255] 531 HMD (electronic device).

Claims

1. A display device comprising: a substrate; a plurality of pixel circuits each including a sampling transistor, a drive transistor, a first switching transistor, a second switching transistor, a capacitive element, and a light emitting element; a plurality of scan lines including a first scan line, a second scan line, and a third scan line, the first scan line connected to a control terminal of the sampling transistor, the second scan line connected to a control terminal of the first switching transistor, and the third scan line connected to a control terminal of the second switching transistor, wherein a first terminal of the first switching transistor is connected to a first terminal of the drive transistor, and a second terminal of the first switching transistor is connected to a ground line, and a control terminal of the drive transistor is connected to the capacitive element; and a plurality of signal lines, and the signal lines are connected to a first terminal of the sampling transistor, wherein the first scan line and the second scan line are in a first interconnect layer, the signal lines are in a second interconnect layer, the first scan line and the second scan line extend in a first direction, the signal lines extend in a second direction perpendicular to the first direction, and the first interconnect layer is between the substrate and the second interconnect layer.

2. The display device according to claim 1, wherein the third scan line is in a different interconnect layer from the first interconnect layer.

3. The display device according to claim 2, wherein the different interconnect layer is a third interconnect layer between the first interconnect layer and the second interconnect layer.

4. The display device according to claim 3, wherein a first electrode of the capacitive element is in the second interconnect layer.

5. The display device of claim 4, wherein, a second electrode of the capacitive element is in the third interconnect layer.

6. The display device of claim 5, wherein, the light emitting element includes an anode, and the anode is on a fourth interconnect layer.

7. The display device of claim 6, wherein, the third scan line extends in the first direction.

8. The display device according to claim 1, wherein a first electrode of the capacitive element is in the second interconnect layer.

9. The display device of claim 8, wherein, a second electrode of the capacitive element is in a third interconnect layer.

10. The display device of claim 9, wherein, the light emitting element includes an anode, and the anode is on a fourth interconnect layer.

11. An electronic device comprising: a display device that displays based on a video signal, wherein the display device includes: a substrate; a plurality of pixel circuits each including a sampling transistor, a drive transistor, a first switching transistor, a second switching transistor, a capacitive element, and a light emitting element; a plurality of scan lines including a first scan line, a second scan line, and a third scan line, the first scan line connected to a control terminal of the sampling transistor, the second scan line connected to a control terminal of the first switching transistor, and the third scan line connected to a control terminal of the second switching transistor, wherein a first terminal of the first switching transistor is connected to a first terminal of the drive transistor, and a second terminal of the first switching transistor is connected to a ground line, and a control terminal of the drive transistor is connected to the capacitive element; and a plurality of signal lines, and the signal lines are connected to a first terminal of the sampling transistor, wherein the first scan line and the second scan line are in a first interconnect layer, the signal lines are in a second interconnect layer, the first scan line and the second scan line extend in a first direction, The signal line extends in a second direction perpendicular to the first direction, and The first interconnect layer is between the substrate and the second interconnect layer.

12. The electronic device of claim 11, wherein, The third scan line is in a different interconnect layer than the first interconnect layer.

13. The electronic device of claim 12, wherein, The different interconnect layer is a third interconnect layer between the first interconnect layer and the second interconnect layer.

14. The electronic device of claim 13, wherein, A first electrode of the capacitive element is in the second interconnect layer.

15. The electronic device of claim 14, wherein, A second electrode of the capacitive element is in the third interconnect layer.

16. The electronic device of claim 15, wherein, The light emitting element includes an anode, and the anode is on a fourth interconnect layer.

17. The electronic device of claim 16, wherein, The third scan line extends in the first direction.

18. The electronic device of claim 11, wherein, A first electrode of the capacitive element is in the second interconnect layer.

19. The electronic device of claim 18, wherein, A second electrode of the capacitive element is in a third interconnect layer.

20. The electronic device of claim 19, wherein, The light emitting element includes an anode, and the anode is on a fourth interconnect layer.

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